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"HS_STAGE_OFF", "value": 0}, 963 {"name": "HS_STAGE_ON", "value": 1} 964 ] 965 }, 966 "VGT_STAGES_LS_EN": { 967 "entries": [ 968 {"name": "LS_STAGE_OFF", "value": 0}, 969 {"name": "LS_STAGE_ON", "value": 1}, 970 {"name": "CS_STAGE_ON", "value": 2}, 971 {"name": "RESERVED_LS", "value": 3} 972 ] 973 }, 974 "VGT_STAGES_VS_EN": { 975 "entries": [ 976 {"name": "VS_STAGE_REAL", "value": 0}, 977 {"name": "VS_STAGE_DS", "value": 1}, 978 {"name": "VS_STAGE_COPY_SHADER", "value": 2}, 979 {"name": "RESERVED_VS", "value": 3} 980 ] 981 }, 982 "VGT_TESS_PARTITION": { 983 "entries": [ 984 {"name": "PART_INTEGER", "value": 0}, 985 {"name": "PART_POW2", "value": 1}, 986 {"name": "PART_FRAC_ODD", "value": 2}, 987 {"name": "PART_FRAC_EVEN", "value": 3} 988 ] 989 }, 990 "VGT_TESS_TOPOLOGY": { 991 "entries": [ 992 {"name": "OUTPUT_POINT", "value": 0}, 993 {"name": "OUTPUT_LINE", "value": 1}, 994 {"name": "OUTPUT_TRIANGLE_CW", "value": 2}, 995 {"name": "OUTPUT_TRIANGLE_CCW", "value": 3} 996 ] 997 }, 998 "VGT_TESS_TYPE": { 999 "entries": [ 1000 {"name": "TESS_ISOLINE", "value": 0}, 1001 {"name": "TESS_TRIANGLE", "value": 1}, 1002 {"name": "TESS_QUAD", "value": 2} 1003 ] 1004 }, 1005 "ZFormat": { 1006 "entries": [ 1007 {"name": "Z_INVALID", "value": 0}, 1008 {"name": "Z_16", "value": 1}, 1009 {"name": "Z_24", "value": 2}, 1010 {"name": "Z_32_FLOAT", "value": 3} 1011 ] 1012 }, 1013 "ZLimitSumm": { 1014 "entries": [ 1015 {"name": "FORCE_SUMM_OFF", "value": 0}, 1016 {"name": "FORCE_SUMM_MINZ", "value": 1}, 1017 {"name": "FORCE_SUMM_MAXZ", "value": 2}, 1018 {"name": "FORCE_SUMM_BOTH", "value": 3} 1019 ] 1020 }, 1021 "ZOrder": { 1022 "entries": [ 1023 {"name": "LATE_Z", "value": 0}, 1024 {"name": "EARLY_Z_THEN_LATE_Z", "value": 1}, 1025 {"name": "RE_Z", "value": 2}, 1026 {"name": "EARLY_Z_THEN_RE_Z", "value": 3} 1027 ] 1028 } 1029 }, 1030 "register_mappings": [ 1031 { 1032 "chips": ["gfx6"], 1033 "map": {"at": 68, "to": "mm"}, 1034 "name": "SQ_WAVE_MODE", 1035 "type_ref": "SQ_WAVE_MODE" 1036 }, 1037 { 1038 "chips": ["gfx6"], 1039 "map": {"at": 72, "to": "mm"}, 1040 "name": "SQ_WAVE_STATUS", 1041 "type_ref": "SQ_WAVE_STATUS" 1042 }, 1043 { 1044 "chips": ["gfx6"], 1045 "map": {"at": 76, "to": "mm"}, 1046 "name": "SQ_WAVE_TRAPSTS", 1047 "type_ref": "SQ_WAVE_TRAPSTS" 1048 }, 1049 { 1050 "chips": ["gfx6"], 1051 "map": {"at": 80, "to": "mm"}, 1052 "name": "SQ_WAVE_HW_ID", 1053 "type_ref": "SQ_WAVE_HW_ID" 1054 }, 1055 { 1056 "chips": ["gfx6"], 1057 "map": {"at": 84, "to": "mm"}, 1058 "name": "SQ_WAVE_GPR_ALLOC", 1059 "type_ref": "SQ_WAVE_GPR_ALLOC" 1060 }, 1061 { 1062 "chips": ["gfx6"], 1063 "map": {"at": 88, "to": "mm"}, 1064 "name": "SQ_WAVE_LDS_ALLOC", 1065 "type_ref": "SQ_WAVE_LDS_ALLOC" 1066 }, 1067 { 1068 "chips": ["gfx6"], 1069 "map": {"at": 92, "to": "mm"}, 1070 "name": "SQ_WAVE_IB_STS", 1071 "type_ref": "SQ_WAVE_IB_STS" 1072 }, 1073 { 1074 "chips": ["gfx6"], 1075 "map": {"at": 96, "to": "mm"}, 1076 "name": "SQ_WAVE_PC_LO" 1077 }, 1078 { 1079 "chips": ["gfx6"], 1080 "map": {"at": 100, "to": "mm"}, 1081 "name": "SQ_WAVE_PC_HI", 1082 "type_ref": "SQ_WAVE_PC_HI" 1083 }, 1084 { 1085 "chips": ["gfx6"], 1086 "map": {"at": 104, "to": "mm"}, 1087 "name": "SQ_WAVE_INST_DW0" 1088 }, 1089 { 1090 "chips": ["gfx6"], 1091 "map": {"at": 108, "to": "mm"}, 1092 "name": "SQ_WAVE_INST_DW1" 1093 }, 1094 { 1095 "chips": ["gfx6"], 1096 "map": {"at": 112, "to": "mm"}, 1097 "name": "SQ_WAVE_IB_DBG0", 1098 "type_ref": "SQ_WAVE_IB_DBG0" 1099 }, 1100 { 1101 "chips": ["gfx6"], 1102 "map": {"at": 2480, "to": "mm"}, 1103 "name": "SQ_WAVE_TBA_LO" 1104 }, 1105 { 1106 "chips": ["gfx6"], 1107 "map": {"at": 2484, "to": "mm"}, 1108 "name": "SQ_WAVE_TBA_HI", 1109 "type_ref": "SQ_WAVE_TBA_HI" 1110 }, 1111 { 1112 "chips": ["gfx6"], 1113 "map": {"at": 2488, "to": "mm"}, 1114 "name": "SQ_WAVE_TMA_LO" 1115 }, 1116 { 1117 "chips": ["gfx6"], 1118 "map": {"at": 2492, "to": "mm"}, 1119 "name": "SQ_WAVE_TMA_HI", 1120 "type_ref": "SQ_WAVE_TBA_HI" 1121 }, 1122 { 1123 "chips": ["gfx6"], 1124 "map": {"at": 2496, "to": "mm"}, 1125 "name": "SQ_WAVE_TTMP0" 1126 }, 1127 { 1128 "chips": ["gfx6"], 1129 "map": {"at": 2500, "to": "mm"}, 1130 "name": "SQ_WAVE_TTMP1" 1131 }, 1132 { 1133 "chips": ["gfx6"], 1134 "map": {"at": 2504, "to": "mm"}, 1135 "name": "SQ_WAVE_TTMP2" 1136 }, 1137 { 1138 "chips": ["gfx6"], 1139 "map": {"at": 2508, "to": "mm"}, 1140 "name": "SQ_WAVE_TTMP3" 1141 }, 1142 { 1143 "chips": ["gfx6"], 1144 "map": {"at": 2512, "to": "mm"}, 1145 "name": "SQ_WAVE_TTMP4" 1146 }, 1147 { 1148 "chips": ["gfx6"], 1149 "map": {"at": 2516, "to": "mm"}, 1150 "name": "SQ_WAVE_TTMP5" 1151 }, 1152 { 1153 "chips": ["gfx6"], 1154 "map": {"at": 2520, "to": "mm"}, 1155 "name": "SQ_WAVE_TTMP6" 1156 }, 1157 { 1158 "chips": ["gfx6"], 1159 "map": {"at": 2524, "to": "mm"}, 1160 "name": "SQ_WAVE_TTMP7" 1161 }, 1162 { 1163 "chips": ["gfx6"], 1164 "map": {"at": 2528, "to": "mm"}, 1165 "name": "SQ_WAVE_TTMP8" 1166 }, 1167 { 1168 "chips": ["gfx6"], 1169 "map": {"at": 2532, "to": "mm"}, 1170 "name": "SQ_WAVE_TTMP9" 1171 }, 1172 { 1173 "chips": ["gfx6"], 1174 "map": {"at": 2536, "to": "mm"}, 1175 "name": "SQ_WAVE_TTMP10" 1176 }, 1177 { 1178 "chips": ["gfx6"], 1179 "map": {"at": 2540, "to": "mm"}, 1180 "name": "SQ_WAVE_TTMP11" 1181 }, 1182 { 1183 "chips": ["gfx6"], 1184 "map": {"at": 2544, "to": "mm"}, 1185 "name": "SQ_WAVE_M0" 1186 }, 1187 { 1188 "chips": ["gfx6"], 1189 "map": {"at": 2552, "to": "mm"}, 1190 "name": "SQ_WAVE_EXEC_LO" 1191 }, 1192 { 1193 "chips": ["gfx6"], 1194 "map": {"at": 2556, "to": "mm"}, 1195 "name": "SQ_WAVE_EXEC_HI" 1196 }, 1197 { 1198 "chips": ["gfx6"], 1199 "map": {"at": 32768, "to": "mm"}, 1200 "name": "GRBM_CNTL", 1201 "type_ref": "GRBM_CNTL" 1202 }, 1203 { 1204 "chips": ["gfx6"], 1205 "map": {"at": 32772, "to": "mm"}, 1206 "name": "GRBM_SKEW_CNTL", 1207 "type_ref": "GRBM_SKEW_CNTL" 1208 }, 1209 { 1210 "chips": ["gfx6"], 1211 "map": {"at": 32776, "to": "mm"}, 1212 "name": "GRBM_STATUS2", 1213 "type_ref": "GRBM_STATUS2" 1214 }, 1215 { 1216 "chips": ["gfx6"], 1217 "map": {"at": 32780, "to": "mm"}, 1218 "name": "GRBM_PWR_CNTL", 1219 "type_ref": "GRBM_PWR_CNTL" 1220 }, 1221 { 1222 "chips": ["gfx6"], 1223 "map": {"at": 32784, "to": "mm"}, 1224 "name": "GRBM_STATUS", 1225 "type_ref": "GRBM_STATUS" 1226 }, 1227 { 1228 "chips": ["gfx6"], 1229 "map": {"at": 32788, "to": "mm"}, 1230 "name": "GRBM_STATUS_SE0", 1231 "type_ref": "GRBM_STATUS_SE0" 1232 }, 1233 { 1234 "chips": ["gfx6"], 1235 "map": {"at": 32792, "to": "mm"}, 1236 "name": "GRBM_STATUS_SE1", 1237 "type_ref": "GRBM_STATUS_SE0" 1238 }, 1239 { 1240 "chips": ["gfx6"], 1241 "map": {"at": 32800, "to": "mm"}, 1242 "name": "GRBM_SOFT_RESET", 1243 "type_ref": "GRBM_SOFT_RESET" 1244 }, 1245 { 1246 "chips": ["gfx6"], 1247 "map": {"at": 32804, "to": "mm"}, 1248 "name": "GRBM_DEBUG_CNTL", 1249 "type_ref": "GRBM_DEBUG_CNTL" 1250 }, 1251 { 1252 "chips": ["gfx6"], 1253 "map": {"at": 32808, "to": "mm"}, 1254 "name": "GRBM_DEBUG_DATA" 1255 }, 1256 { 1257 "chips": ["gfx6"], 1258 "map": {"at": 32812, "to": "mm"}, 1259 "name": "GRBM_GFX_INDEX", 1260 "type_ref": "GRBM_GFX_INDEX" 1261 }, 1262 { 1263 "chips": ["gfx6"], 1264 "map": {"at": 32816, "to": "mm"}, 1265 "name": "GRBM_GFX_CLKEN_CNTL", 1266 "type_ref": "GRBM_GFX_CLKEN_CNTL" 1267 }, 1268 { 1269 "chips": ["gfx6"], 1270 "map": {"at": 32820, "to": "mm"}, 1271 "name": "GRBM_WAIT_IDLE_CLOCKS", 1272 "type_ref": "GRBM_WAIT_IDLE_CLOCKS" 1273 }, 1274 { 1275 "chips": ["gfx6"], 1276 "map": {"at": 32848, "to": "mm"}, 1277 "name": "GRBM_DEBUG", 1278 "type_ref": "GRBM_DEBUG" 1279 }, 1280 { 1281 "chips": ["gfx6"], 1282 "map": {"at": 32852, "to": "mm"}, 1283 "name": "GRBM_DEBUG_SNAPSHOT", 1284 "type_ref": "GRBM_DEBUG_SNAPSHOT" 1285 }, 1286 { 1287 "chips": ["gfx6"], 1288 "map": {"at": 32856, "to": "mm"}, 1289 "name": "GRBM_READ_ERROR", 1290 "type_ref": "GRBM_READ_ERROR" 1291 }, 1292 { 1293 "chips": ["gfx6"], 1294 "map": {"at": 32864, "to": "mm"}, 1295 "name": "GRBM_INT_CNTL", 1296 "type_ref": "GRBM_INT_CNTL" 1297 }, 1298 { 1299 "chips": ["gfx6"], 1300 "map": {"at": 32880, "to": "mm"}, 1301 "name": "GRBM_PERFCOUNTER0_SELECT", 1302 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 1303 }, 1304 { 1305 "chips": ["gfx6"], 1306 "map": {"at": 32884, "to": "mm"}, 1307 "name": "GRBM_PERFCOUNTER1_SELECT", 1308 "type_ref": "GRBM_PERFCOUNTER0_SELECT" 1309 }, 1310 { 1311 "chips": ["gfx6"], 1312 "map": {"at": 32888, "to": "mm"}, 1313 "name": "GRBM_PERFCOUNTER0_LO" 1314 }, 1315 { 1316 "chips": ["gfx6"], 1317 "map": {"at": 32892, "to": "mm"}, 1318 "name": "GRBM_PERFCOUNTER0_HI" 1319 }, 1320 { 1321 "chips": ["gfx6"], 1322 "map": {"at": 32896, "to": "mm"}, 1323 "name": "GRBM_PERFCOUNTER1_LO" 1324 }, 1325 { 1326 "chips": ["gfx6"], 1327 "map": {"at": 32900, "to": "mm"}, 1328 "name": "GRBM_PERFCOUNTER1_HI" 1329 }, 1330 { 1331 "chips": ["gfx6"], 1332 "map": {"at": 32920, "to": "mm"}, 1333 "name": "GRBM_SE0_PERFCOUNTER_SELECT", 1334 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 1335 }, 1336 { 1337 "chips": ["gfx6"], 1338 "map": {"at": 32924, "to": "mm"}, 1339 "name": "GRBM_SE1_PERFCOUNTER_SELECT", 1340 "type_ref": "GRBM_SE0_PERFCOUNTER_SELECT" 1341 }, 1342 { 1343 "chips": ["gfx6"], 1344 "map": {"at": 32936, "to": "mm"}, 1345 "name": "GRBM_SE0_PERFCOUNTER_LO" 1346 }, 1347 { 1348 "chips": ["gfx6"], 1349 "map": {"at": 32940, "to": "mm"}, 1350 "name": "GRBM_SE0_PERFCOUNTER_HI" 1351 }, 1352 { 1353 "chips": ["gfx6"], 1354 "map": {"at": 32944, "to": "mm"}, 1355 "name": "GRBM_SE1_PERFCOUNTER_LO" 1356 }, 1357 { 1358 "chips": ["gfx6"], 1359 "map": {"at": 32948, "to": "mm"}, 1360 "name": "GRBM_SE1_PERFCOUNTER_HI" 1361 }, 1362 { 1363 "chips": ["gfx6"], 1364 "map": {"at": 33008, "to": "mm"}, 1365 "name": "DEBUG_INDEX", 1366 "type_ref": "DEBUG_INDEX" 1367 }, 1368 { 1369 "chips": ["gfx6"], 1370 "map": {"at": 33012, "to": "mm"}, 1371 "name": "DEBUG_DATA" 1372 }, 1373 { 1374 "chips": ["gfx6"], 1375 "map": {"at": 33020, "to": "mm"}, 1376 "name": "GRBM_NOWHERE" 1377 }, 1378 { 1379 "chips": ["gfx6"], 1380 "map": {"at": 33024, "to": "mm"}, 1381 "name": "GRBM_SCRATCH_REG0" 1382 }, 1383 { 1384 "chips": ["gfx6"], 1385 "map": {"at": 33028, "to": "mm"}, 1386 "name": "GRBM_SCRATCH_REG1" 1387 }, 1388 { 1389 "chips": ["gfx6"], 1390 "map": {"at": 33032, "to": "mm"}, 1391 "name": "GRBM_SCRATCH_REG2" 1392 }, 1393 { 1394 "chips": ["gfx6"], 1395 "map": {"at": 33036, "to": "mm"}, 1396 "name": "GRBM_SCRATCH_REG3" 1397 }, 1398 { 1399 "chips": ["gfx6"], 1400 "map": {"at": 33040, "to": "mm"}, 1401 "name": "GRBM_SCRATCH_REG4" 1402 }, 1403 { 1404 "chips": ["gfx6"], 1405 "map": {"at": 33044, "to": "mm"}, 1406 "name": "GRBM_SCRATCH_REG5" 1407 }, 1408 { 1409 "chips": ["gfx6"], 1410 "map": {"at": 33048, "to": "mm"}, 1411 "name": "GRBM_SCRATCH_REG6" 1412 }, 1413 { 1414 "chips": ["gfx6"], 1415 "map": {"at": 33052, "to": "mm"}, 1416 "name": "GRBM_SCRATCH_REG7" 1417 }, 1418 { 1419 "chips": ["gfx6"], 1420 "map": {"at": 33536, "to": "mm"}, 1421 "name": "SQ_INTERRUPT_WORD_AUTO", 1422 "type_ref": "SQ_INTERRUPT_WORD_AUTO" 1423 }, 1424 { 1425 "chips": ["gfx6"], 1426 "map": {"at": 33792, "to": "mm"}, 1427 "name": "CP_EOP_DONE_ADDR_LO", 1428 "type_ref": "CP_EOP_DONE_ADDR_LO" 1429 }, 1430 { 1431 "chips": ["gfx6"], 1432 "map": {"at": 33796, "to": "mm"}, 1433 "name": "CP_EOP_DONE_ADDR_HI", 1434 "type_ref": "CP_EOP_DONE_ADDR_HI" 1435 }, 1436 { 1437 "chips": ["gfx6"], 1438 "map": {"at": 33800, "to": "mm"}, 1439 "name": "CP_EOP_DONE_DATA_LO" 1440 }, 1441 { 1442 "chips": ["gfx6"], 1443 "map": {"at": 33804, "to": "mm"}, 1444 "name": "CP_EOP_DONE_DATA_HI" 1445 }, 1446 { 1447 "chips": ["gfx6"], 1448 "map": {"at": 33808, "to": "mm"}, 1449 "name": "CP_EOP_LAST_FENCE_LO" 1450 }, 1451 { 1452 "chips": ["gfx6"], 1453 "map": {"at": 33812, "to": "mm"}, 1454 "name": "CP_EOP_LAST_FENCE_HI" 1455 }, 1456 { 1457 "chips": ["gfx6"], 1458 "map": {"at": 33816, "to": "mm"}, 1459 "name": "CP_STREAM_OUT_ADDR_LO", 1460 "type_ref": "CP_STREAM_OUT_ADDR_LO" 1461 }, 1462 { 1463 "chips": ["gfx6"], 1464 "map": {"at": 33820, "to": "mm"}, 1465 "name": "CP_STREAM_OUT_ADDR_HI" 1466 }, 1467 { 1468 "chips": ["gfx6"], 1469 "map": {"at": 33824, "to": "mm"}, 1470 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_LO" 1471 }, 1472 { 1473 "chips": ["gfx6"], 1474 "map": {"at": 33828, "to": "mm"}, 1475 "name": "CP_NUM_PRIM_WRITTEN_COUNT0_HI" 1476 }, 1477 { 1478 "chips": ["gfx6"], 1479 "map": {"at": 33832, "to": "mm"}, 1480 "name": "CP_NUM_PRIM_NEEDED_COUNT0_LO" 1481 }, 1482 { 1483 "chips": ["gfx6"], 1484 "map": {"at": 33836, "to": "mm"}, 1485 "name": "CP_NUM_PRIM_NEEDED_COUNT0_HI" 1486 }, 1487 { 1488 "chips": ["gfx6"], 1489 "map": {"at": 33840, "to": "mm"}, 1490 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_LO" 1491 }, 1492 { 1493 "chips": ["gfx6"], 1494 "map": {"at": 33844, "to": "mm"}, 1495 "name": "CP_NUM_PRIM_WRITTEN_COUNT1_HI" 1496 }, 1497 { 1498 "chips": ["gfx6"], 1499 "map": {"at": 33848, "to": "mm"}, 1500 "name": "CP_NUM_PRIM_NEEDED_COUNT1_LO" 1501 }, 1502 { 1503 "chips": ["gfx6"], 1504 "map": {"at": 33852, "to": "mm"}, 1505 "name": "CP_NUM_PRIM_NEEDED_COUNT1_HI" 1506 }, 1507 { 1508 "chips": ["gfx6"], 1509 "map": {"at": 33856, "to": "mm"}, 1510 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_LO" 1511 }, 1512 { 1513 "chips": ["gfx6"], 1514 "map": {"at": 33860, "to": "mm"}, 1515 "name": "CP_NUM_PRIM_WRITTEN_COUNT2_HI" 1516 }, 1517 { 1518 "chips": ["gfx6"], 1519 "map": {"at": 33864, "to": "mm"}, 1520 "name": "CP_NUM_PRIM_NEEDED_COUNT2_LO" 1521 }, 1522 { 1523 "chips": ["gfx6"], 1524 "map": {"at": 33868, "to": "mm"}, 1525 "name": "CP_NUM_PRIM_NEEDED_COUNT2_HI" 1526 }, 1527 { 1528 "chips": ["gfx6"], 1529 "map": {"at": 33872, "to": "mm"}, 1530 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_LO" 1531 }, 1532 { 1533 "chips": ["gfx6"], 1534 "map": {"at": 33876, "to": "mm"}, 1535 "name": "CP_NUM_PRIM_WRITTEN_COUNT3_HI" 1536 }, 1537 { 1538 "chips": ["gfx6"], 1539 "map": {"at": 33880, "to": "mm"}, 1540 "name": "CP_NUM_PRIM_NEEDED_COUNT3_LO" 1541 }, 1542 { 1543 "chips": ["gfx6"], 1544 "map": {"at": 33884, "to": "mm"}, 1545 "name": "CP_NUM_PRIM_NEEDED_COUNT3_HI" 1546 }, 1547 { 1548 "chips": ["gfx6"], 1549 "map": {"at": 33888, "to": "mm"}, 1550 "name": "CP_PIPE_STATS_ADDR_LO", 1551 "type_ref": "CP_PIPE_STATS_ADDR_LO" 1552 }, 1553 { 1554 "chips": ["gfx6"], 1555 "map": {"at": 33892, "to": "mm"}, 1556 "name": "CP_PIPE_STATS_ADDR_HI" 1557 }, 1558 { 1559 "chips": ["gfx6"], 1560 "map": {"at": 33896, "to": "mm"}, 1561 "name": "CP_VGT_IAVERT_COUNT_LO" 1562 }, 1563 { 1564 "chips": ["gfx6"], 1565 "map": {"at": 33900, "to": "mm"}, 1566 "name": "CP_VGT_IAVERT_COUNT_HI" 1567 }, 1568 { 1569 "chips": ["gfx6"], 1570 "map": {"at": 33904, "to": "mm"}, 1571 "name": "CP_VGT_IAPRIM_COUNT_LO" 1572 }, 1573 { 1574 "chips": ["gfx6"], 1575 "map": {"at": 33908, "to": "mm"}, 1576 "name": "CP_VGT_IAPRIM_COUNT_HI" 1577 }, 1578 { 1579 "chips": ["gfx6"], 1580 "map": {"at": 33912, "to": "mm"}, 1581 "name": "CP_VGT_GSPRIM_COUNT_LO" 1582 }, 1583 { 1584 "chips": ["gfx6"], 1585 "map": {"at": 33916, "to": "mm"}, 1586 "name": "CP_VGT_GSPRIM_COUNT_HI" 1587 }, 1588 { 1589 "chips": ["gfx6"], 1590 "map": {"at": 33920, "to": "mm"}, 1591 "name": "CP_VGT_VSINVOC_COUNT_LO" 1592 }, 1593 { 1594 "chips": ["gfx6"], 1595 "map": {"at": 33924, "to": "mm"}, 1596 "name": "CP_VGT_VSINVOC_COUNT_HI" 1597 }, 1598 { 1599 "chips": ["gfx6"], 1600 "map": {"at": 33928, "to": "mm"}, 1601 "name": "CP_VGT_GSINVOC_COUNT_LO" 1602 }, 1603 { 1604 "chips": ["gfx6"], 1605 "map": {"at": 33932, "to": "mm"}, 1606 "name": "CP_VGT_GSINVOC_COUNT_HI" 1607 }, 1608 { 1609 "chips": ["gfx6"], 1610 "map": {"at": 33936, "to": "mm"}, 1611 "name": "CP_VGT_HSINVOC_COUNT_LO" 1612 }, 1613 { 1614 "chips": ["gfx6"], 1615 "map": {"at": 33940, "to": "mm"}, 1616 "name": "CP_VGT_HSINVOC_COUNT_HI" 1617 }, 1618 { 1619 "chips": ["gfx6"], 1620 "map": {"at": 33944, "to": "mm"}, 1621 "name": "CP_VGT_DSINVOC_COUNT_LO" 1622 }, 1623 { 1624 "chips": ["gfx6"], 1625 "map": {"at": 33948, "to": "mm"}, 1626 "name": "CP_VGT_DSINVOC_COUNT_HI" 1627 }, 1628 { 1629 "chips": ["gfx6"], 1630 "map": {"at": 33952, "to": "mm"}, 1631 "name": "CP_PA_CINVOC_COUNT_LO" 1632 }, 1633 { 1634 "chips": ["gfx6"], 1635 "map": {"at": 33956, "to": "mm"}, 1636 "name": "CP_PA_CINVOC_COUNT_HI" 1637 }, 1638 { 1639 "chips": ["gfx6"], 1640 "map": {"at": 33960, "to": "mm"}, 1641 "name": "CP_PA_CPRIM_COUNT_LO" 1642 }, 1643 { 1644 "chips": ["gfx6"], 1645 "map": {"at": 33964, "to": "mm"}, 1646 "name": "CP_PA_CPRIM_COUNT_HI" 1647 }, 1648 { 1649 "chips": ["gfx6"], 1650 "map": {"at": 33968, "to": "mm"}, 1651 "name": "CP_SC_PSINVOC_COUNT0_LO" 1652 }, 1653 { 1654 "chips": ["gfx6"], 1655 "map": {"at": 33972, "to": "mm"}, 1656 "name": "CP_SC_PSINVOC_COUNT0_HI" 1657 }, 1658 { 1659 "chips": ["gfx6"], 1660 "map": {"at": 33976, "to": "mm"}, 1661 "name": "CP_SC_PSINVOC_COUNT1_LO" 1662 }, 1663 { 1664 "chips": ["gfx6"], 1665 "map": {"at": 33980, "to": "mm"}, 1666 "name": "CP_SC_PSINVOC_COUNT1_HI" 1667 }, 1668 { 1669 "chips": ["gfx6"], 1670 "map": {"at": 33984, "to": "mm"}, 1671 "name": "CP_VGT_CSINVOC_COUNT_LO" 1672 }, 1673 { 1674 "chips": ["gfx6"], 1675 "map": {"at": 33988, "to": "mm"}, 1676 "name": "CP_VGT_CSINVOC_COUNT_HI" 1677 }, 1678 { 1679 "chips": ["gfx6"], 1680 "map": {"at": 34044, "to": "mm"}, 1681 "name": "CP_STRMOUT_CNTL", 1682 "type_ref": "CP_STRMOUT_CNTL" 1683 }, 1684 { 1685 "chips": ["gfx6"], 1686 "map": {"at": 34048, "to": "mm"}, 1687 "name": "SCRATCH_REG0" 1688 }, 1689 { 1690 "chips": ["gfx6"], 1691 "map": {"at": 34052, "to": "mm"}, 1692 "name": "SCRATCH_REG1" 1693 }, 1694 { 1695 "chips": ["gfx6"], 1696 "map": {"at": 34056, "to": "mm"}, 1697 "name": "SCRATCH_REG2" 1698 }, 1699 { 1700 "chips": ["gfx6"], 1701 "map": {"at": 34060, "to": "mm"}, 1702 "name": "SCRATCH_REG3" 1703 }, 1704 { 1705 "chips": ["gfx6"], 1706 "map": {"at": 34064, "to": "mm"}, 1707 "name": "SCRATCH_REG4" 1708 }, 1709 { 1710 "chips": ["gfx6"], 1711 "map": {"at": 34068, "to": "mm"}, 1712 "name": "SCRATCH_REG5" 1713 }, 1714 { 1715 "chips": ["gfx6"], 1716 "map": {"at": 34072, "to": "mm"}, 1717 "name": "SCRATCH_REG6" 1718 }, 1719 { 1720 "chips": ["gfx6"], 1721 "map": {"at": 34076, "to": "mm"}, 1722 "name": "SCRATCH_REG7" 1723 }, 1724 { 1725 "chips": ["gfx6"], 1726 "map": {"at": 34112, "to": "mm"}, 1727 "name": "SCRATCH_UMSK", 1728 "type_ref": "SCRATCH_UMSK" 1729 }, 1730 { 1731 "chips": ["gfx6"], 1732 "map": {"at": 34116, "to": "mm"}, 1733 "name": "SCRATCH_ADDR" 1734 }, 1735 { 1736 "chips": ["gfx6"], 1737 "map": {"at": 34144, "to": "mm"}, 1738 "name": "CP_APPEND_ADDR_LO", 1739 "type_ref": "CP_APPEND_ADDR_LO" 1740 }, 1741 { 1742 "chips": ["gfx6"], 1743 "map": {"at": 34148, "to": "mm"}, 1744 "name": "CP_APPEND_ADDR_HI", 1745 "type_ref": "CP_APPEND_ADDR_HI" 1746 }, 1747 { 1748 "chips": ["gfx6"], 1749 "map": {"at": 34152, "to": "mm"}, 1750 "name": "CP_APPEND_DATA" 1751 }, 1752 { 1753 "chips": ["gfx6"], 1754 "map": {"at": 34156, "to": "mm"}, 1755 "name": "CP_APPEND_LAST_CS_FENCE" 1756 }, 1757 { 1758 "chips": ["gfx6"], 1759 "map": {"at": 34160, "to": "mm"}, 1760 "name": "CP_APPEND_LAST_PS_FENCE" 1761 }, 1762 { 1763 "chips": ["gfx6"], 1764 "map": {"at": 34164, "to": "mm"}, 1765 "name": "CP_ATOMIC_PREOP_LO" 1766 }, 1767 { 1768 "chips": ["gfx6"], 1769 "map": {"at": 34168, "to": "mm"}, 1770 "name": "CP_ATOMIC_PREOP_HI" 1771 }, 1772 { 1773 "chips": ["gfx6"], 1774 "map": {"at": 34172, "to": "mm"}, 1775 "name": "CP_GDS_ATOMIC0_PREOP_LO" 1776 }, 1777 { 1778 "chips": ["gfx6"], 1779 "map": {"at": 34176, "to": "mm"}, 1780 "name": "CP_GDS_ATOMIC0_PREOP_HI" 1781 }, 1782 { 1783 "chips": ["gfx6"], 1784 "map": {"at": 34180, "to": "mm"}, 1785 "name": "CP_GDS_ATOMIC1_PREOP_LO" 1786 }, 1787 { 1788 "chips": ["gfx6"], 1789 "map": {"at": 34184, "to": "mm"}, 1790 "name": "CP_GDS_ATOMIC1_PREOP_HI" 1791 }, 1792 { 1793 "chips": ["gfx6"], 1794 "map": {"at": 34212, "to": "mm"}, 1795 "name": "CP_ME_MC_WADDR_LO", 1796 "type_ref": "CP_ME_MC_WADDR_LO" 1797 }, 1798 { 1799 "chips": ["gfx6"], 1800 "map": {"at": 34216, "to": "mm"}, 1801 "name": "CP_ME_MC_WADDR_HI", 1802 "type_ref": "CP_ME_MC_WADDR_HI" 1803 }, 1804 { 1805 "chips": ["gfx6"], 1806 "map": {"at": 34220, "to": "mm"}, 1807 "name": "CP_ME_MC_WDATA_LO" 1808 }, 1809 { 1810 "chips": ["gfx6"], 1811 "map": {"at": 34224, "to": "mm"}, 1812 "name": "CP_ME_MC_WDATA_HI" 1813 }, 1814 { 1815 "chips": ["gfx6"], 1816 "map": {"at": 34228, "to": "mm"}, 1817 "name": "CP_ME_MC_RADDR_LO", 1818 "type_ref": "CP_ME_MC_RADDR_LO" 1819 }, 1820 { 1821 "chips": ["gfx6"], 1822 "map": {"at": 34232, "to": "mm"}, 1823 "name": "CP_ME_MC_RADDR_HI", 1824 "type_ref": "CP_ME_MC_RADDR_HI" 1825 }, 1826 { 1827 "chips": ["gfx6"], 1828 "map": {"at": 34236, "to": "mm"}, 1829 "name": "CP_SEM_WAIT_TIMER" 1830 }, 1831 { 1832 "chips": ["gfx6"], 1833 "map": {"at": 34240, "to": "mm"}, 1834 "name": "CP_SIG_SEM_ADDR_LO", 1835 "type_ref": "CP_SIG_SEM_ADDR_LO" 1836 }, 1837 { 1838 "chips": ["gfx6"], 1839 "map": {"at": 34244, "to": "mm"}, 1840 "name": "CP_SIG_SEM_ADDR_HI", 1841 "type_ref": "CP_SIG_SEM_ADDR_HI" 1842 }, 1843 { 1844 "chips": ["gfx6"], 1845 "map": {"at": 34256, "to": "mm"}, 1846 "name": "CP_WAIT_REG_MEM_TIMEOUT" 1847 }, 1848 { 1849 "chips": ["gfx6"], 1850 "map": {"at": 34260, "to": "mm"}, 1851 "name": "CP_WAIT_SEM_ADDR_LO", 1852 "type_ref": "CP_SIG_SEM_ADDR_LO" 1853 }, 1854 { 1855 "chips": ["gfx6"], 1856 "map": {"at": 34264, "to": "mm"}, 1857 "name": "CP_WAIT_SEM_ADDR_HI", 1858 "type_ref": "CP_SIG_SEM_ADDR_HI" 1859 }, 1860 { 1861 "chips": ["gfx6"], 1862 "map": {"at": 34284, "to": "mm"}, 1863 "name": "CP_COHER_START_DELAY", 1864 "type_ref": "CP_COHER_START_DELAY" 1865 }, 1866 { 1867 "chips": ["gfx6"], 1868 "map": {"at": 34288, "to": "mm"}, 1869 "name": "CP_COHER_CNTL", 1870 "type_ref": "CP_COHER_CNTL" 1871 }, 1872 { 1873 "chips": ["gfx6"], 1874 "map": {"at": 34292, "to": "mm"}, 1875 "name": "CP_COHER_SIZE" 1876 }, 1877 { 1878 "chips": ["gfx6"], 1879 "map": {"at": 34296, "to": "mm"}, 1880 "name": "CP_COHER_BASE" 1881 }, 1882 { 1883 "chips": ["gfx6"], 1884 "map": {"at": 34300, "to": "mm"}, 1885 "name": "CP_COHER_STATUS", 1886 "type_ref": "CP_COHER_STATUS" 1887 }, 1888 { 1889 "chips": ["gfx6"], 1890 "map": {"at": 34304, "to": "mm"}, 1891 "name": "CP_DMA_ME_SRC_ADDR" 1892 }, 1893 { 1894 "chips": ["gfx6"], 1895 "map": {"at": 34308, "to": "mm"}, 1896 "name": "CP_DMA_ME_SRC_ADDR_HI", 1897 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 1898 }, 1899 { 1900 "chips": ["gfx6"], 1901 "map": {"at": 34312, "to": "mm"}, 1902 "name": "CP_DMA_ME_DST_ADDR" 1903 }, 1904 { 1905 "chips": ["gfx6"], 1906 "map": {"at": 34316, "to": "mm"}, 1907 "name": "CP_DMA_ME_DST_ADDR_HI", 1908 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 1909 }, 1910 { 1911 "chips": ["gfx6"], 1912 "map": {"at": 34320, "to": "mm"}, 1913 "name": "CP_DMA_ME_COMMAND", 1914 "type_ref": "CP_DMA_ME_COMMAND" 1915 }, 1916 { 1917 "chips": ["gfx6"], 1918 "map": {"at": 34324, "to": "mm"}, 1919 "name": "CP_DMA_PFP_SRC_ADDR" 1920 }, 1921 { 1922 "chips": ["gfx6"], 1923 "map": {"at": 34328, "to": "mm"}, 1924 "name": "CP_DMA_PFP_SRC_ADDR_HI", 1925 "type_ref": "CP_DMA_ME_SRC_ADDR_HI" 1926 }, 1927 { 1928 "chips": ["gfx6"], 1929 "map": {"at": 34332, "to": "mm"}, 1930 "name": "CP_DMA_PFP_DST_ADDR" 1931 }, 1932 { 1933 "chips": ["gfx6"], 1934 "map": {"at": 34336, "to": "mm"}, 1935 "name": "CP_DMA_PFP_DST_ADDR_HI", 1936 "type_ref": "CP_DMA_ME_DST_ADDR_HI" 1937 }, 1938 { 1939 "chips": ["gfx6"], 1940 "map": {"at": 34340, "to": "mm"}, 1941 "name": "CP_DMA_PFP_COMMAND", 1942 "type_ref": "CP_DMA_ME_COMMAND" 1943 }, 1944 { 1945 "chips": ["gfx6"], 1946 "map": {"at": 34344, "to": "mm"}, 1947 "name": "CP_DMA_CNTL", 1948 "type_ref": "CP_DMA_CNTL" 1949 }, 1950 { 1951 "chips": ["gfx6"], 1952 "map": {"at": 34348, "to": "mm"}, 1953 "name": "CP_DMA_READ_TAGS", 1954 "type_ref": "CP_DMA_READ_TAGS" 1955 }, 1956 { 1957 "chips": ["gfx6"], 1958 "map": {"at": 34356, "to": "mm"}, 1959 "name": "CP_PFP_IB_CONTROL", 1960 "type_ref": "CP_PFP_IB_CONTROL" 1961 }, 1962 { 1963 "chips": ["gfx6"], 1964 "map": {"at": 34360, "to": "mm"}, 1965 "name": "CP_PFP_LOAD_CONTROL", 1966 "type_ref": "CP_PFP_LOAD_CONTROL" 1967 }, 1968 { 1969 "chips": ["gfx6"], 1970 "map": {"at": 34364, "to": "mm"}, 1971 "name": "CP_SCRATCH_INDEX", 1972 "type_ref": "CP_SCRATCH_INDEX" 1973 }, 1974 { 1975 "chips": ["gfx6"], 1976 "map": {"at": 34368, "to": "mm"}, 1977 "name": "CP_SCRATCH_DATA" 1978 }, 1979 { 1980 "chips": ["gfx6"], 1981 "map": {"at": 34372, "to": "mm"}, 1982 "name": "CP_RB_OFFSET", 1983 "type_ref": "CP_RB_OFFSET" 1984 }, 1985 { 1986 "chips": ["gfx6"], 1987 "map": {"at": 34376, "to": "mm"}, 1988 "name": "CP_IB1_OFFSET", 1989 "type_ref": "CP_IB1_OFFSET" 1990 }, 1991 { 1992 "chips": ["gfx6"], 1993 "map": {"at": 34380, "to": "mm"}, 1994 "name": "CP_IB2_OFFSET", 1995 "type_ref": "CP_IB2_OFFSET" 1996 }, 1997 { 1998 "chips": ["gfx6"], 1999 "map": {"at": 34384, "to": "mm"}, 2000 "name": "CP_IB1_PREAMBLE_BEGIN", 2001 "type_ref": "CP_IB1_PREAMBLE_BEGIN" 2002 }, 2003 { 2004 "chips": ["gfx6"], 2005 "map": {"at": 34388, "to": "mm"}, 2006 "name": "CP_IB1_PREAMBLE_END", 2007 "type_ref": "CP_IB1_PREAMBLE_END" 2008 }, 2009 { 2010 "chips": ["gfx6"], 2011 "map": {"at": 34392, "to": "mm"}, 2012 "name": "CP_IB2_PREAMBLE_BEGIN", 2013 "type_ref": "CP_IB2_PREAMBLE_BEGIN" 2014 }, 2015 { 2016 "chips": ["gfx6"], 2017 "map": {"at": 34396, "to": "mm"}, 2018 "name": "CP_IB2_PREAMBLE_END", 2019 "type_ref": "CP_IB2_PREAMBLE_END" 2020 }, 2021 { 2022 "chips": ["gfx6"], 2023 "map": {"at": 34416, "to": "mm"}, 2024 "name": "CP_STALLED_STAT3", 2025 "type_ref": "CP_STALLED_STAT3" 2026 }, 2027 { 2028 "chips": ["gfx6"], 2029 "map": {"at": 34420, "to": "mm"}, 2030 "name": "CP_STALLED_STAT1", 2031 "type_ref": "CP_STALLED_STAT1" 2032 }, 2033 { 2034 "chips": ["gfx6"], 2035 "map": {"at": 34424, "to": "mm"}, 2036 "name": "CP_STALLED_STAT2", 2037 "type_ref": "CP_STALLED_STAT2" 2038 }, 2039 { 2040 "chips": ["gfx6"], 2041 "map": {"at": 34428, "to": "mm"}, 2042 "name": "CP_BUSY_STAT", 2043 "type_ref": "CP_BUSY_STAT" 2044 }, 2045 { 2046 "chips": ["gfx6"], 2047 "map": {"at": 34432, "to": "mm"}, 2048 "name": "CP_STAT", 2049 "type_ref": "CP_STAT" 2050 }, 2051 { 2052 "chips": ["gfx6"], 2053 "map": {"at": 34436, "to": "mm"}, 2054 "name": "CP_ME_HEADER_DUMP" 2055 }, 2056 { 2057 "chips": ["gfx6"], 2058 "map": {"at": 34440, "to": "mm"}, 2059 "name": "CP_PFP_HEADER_DUMP" 2060 }, 2061 { 2062 "chips": ["gfx6"], 2063 "map": {"at": 34444, "to": "mm"}, 2064 "name": "CP_GRBM_FREE_COUNT", 2065 "type_ref": "CP_GRBM_FREE_COUNT" 2066 }, 2067 { 2068 "chips": ["gfx6"], 2069 "map": {"at": 34448, "to": "mm"}, 2070 "name": "CP_CE_HEADER_DUMP" 2071 }, 2072 { 2073 "chips": ["gfx6"], 2074 "map": {"at": 34460, "to": "mm"}, 2075 "name": "CP_MC_PACK_DELAY_CNT", 2076 "type_ref": "CP_MC_PACK_DELAY_CNT" 2077 }, 2078 { 2079 "chips": ["gfx6"], 2080 "map": {"at": 34512, "to": "mm"}, 2081 "name": "CP_CSF_STAT", 2082 "type_ref": "CP_CSF_STAT" 2083 }, 2084 { 2085 "chips": ["gfx6"], 2086 "map": {"at": 34516, "to": "mm"}, 2087 "name": "CP_CSF_CNTL", 2088 "type_ref": "CP_CSF_CNTL" 2089 }, 2090 { 2091 "chips": ["gfx6"], 2092 "map": {"at": 34520, "to": "mm"}, 2093 "name": "CP_ME_CNTL", 2094 "type_ref": "CP_ME_CNTL" 2095 }, 2096 { 2097 "chips": ["gfx6"], 2098 "map": {"at": 34528, "to": "mm"}, 2099 "name": "CP_CNTX_STAT", 2100 "type_ref": "CP_CNTX_STAT" 2101 }, 2102 { 2103 "chips": ["gfx6"], 2104 "map": {"at": 34532, "to": "mm"}, 2105 "name": "CP_ME_PREEMPTION", 2106 "type_ref": "CP_ME_PREEMPTION" 2107 }, 2108 { 2109 "chips": ["gfx6"], 2110 "map": {"at": 34552, "to": "mm"}, 2111 "name": "CP_RB2_RPTR", 2112 "type_ref": "CP_RB0_RPTR" 2113 }, 2114 { 2115 "chips": ["gfx6"], 2116 "map": {"at": 34556, "to": "mm"}, 2117 "name": "CP_RB1_RPTR", 2118 "type_ref": "CP_RB0_RPTR" 2119 }, 2120 { 2121 "chips": ["gfx6"], 2122 "map": {"at": 34560, "to": "mm"}, 2123 "name": "CP_RB0_RPTR", 2124 "type_ref": "CP_RB0_RPTR" 2125 }, 2126 { 2127 "chips": ["gfx6"], 2128 "map": {"at": 34564, "to": "mm"}, 2129 "name": "CP_RB_WPTR_DELAY", 2130 "type_ref": "CP_RB_WPTR_DELAY" 2131 }, 2132 { 2133 "chips": ["gfx6"], 2134 "map": {"at": 34568, "to": "mm"}, 2135 "name": "CP_RB_WPTR_POLL_CNTL", 2136 "type_ref": "CP_RB_WPTR_POLL_CNTL" 2137 }, 2138 { 2139 "chips": ["gfx6"], 2140 "map": {"at": 34572, "to": "mm"}, 2141 "name": "CP_CE_INIT_BASE_LO", 2142 "type_ref": "CP_CE_INIT_BASE_LO" 2143 }, 2144 { 2145 "chips": ["gfx6"], 2146 "map": {"at": 34576, "to": "mm"}, 2147 "name": "CP_CE_INIT_BASE_HI", 2148 "type_ref": "CP_CE_INIT_BASE_HI" 2149 }, 2150 { 2151 "chips": ["gfx6"], 2152 "map": {"at": 34580, "to": "mm"}, 2153 "name": "CP_CE_INIT_BUFSZ", 2154 "type_ref": "CP_CE_INIT_BUFSZ" 2155 }, 2156 { 2157 "chips": ["gfx6"], 2158 "map": {"at": 34584, "to": "mm"}, 2159 "name": "CP_CE_IB1_BASE_LO", 2160 "type_ref": "CP_CE_IB1_BASE_LO" 2161 }, 2162 { 2163 "chips": ["gfx6"], 2164 "map": {"at": 34588, "to": "mm"}, 2165 "name": "CP_CE_IB1_BASE_HI", 2166 "type_ref": "CP_CE_IB1_BASE_HI" 2167 }, 2168 { 2169 "chips": ["gfx6"], 2170 "map": {"at": 34592, "to": "mm"}, 2171 "name": "CP_CE_IB1_BUFSZ", 2172 "type_ref": "CP_CE_IB1_BUFSZ" 2173 }, 2174 { 2175 "chips": ["gfx6"], 2176 "map": {"at": 34596, "to": "mm"}, 2177 "name": "CP_CE_IB2_BASE_LO", 2178 "type_ref": "CP_CE_IB2_BASE_LO" 2179 }, 2180 { 2181 "chips": ["gfx6"], 2182 "map": {"at": 34600, "to": "mm"}, 2183 "name": "CP_CE_IB2_BASE_HI", 2184 "type_ref": "CP_CE_IB2_BASE_HI" 2185 }, 2186 { 2187 "chips": ["gfx6"], 2188 "map": {"at": 34604, "to": "mm"}, 2189 "name": "CP_CE_IB2_BUFSZ", 2190 "type_ref": "CP_CE_IB2_BUFSZ" 2191 }, 2192 { 2193 "chips": ["gfx6"], 2194 "map": {"at": 34608, "to": "mm"}, 2195 "name": "CP_IB1_BASE_LO", 2196 "type_ref": "CP_CE_IB1_BASE_LO" 2197 }, 2198 { 2199 "chips": ["gfx6"], 2200 "map": {"at": 34612, "to": "mm"}, 2201 "name": "CP_IB1_BASE_HI", 2202 "type_ref": "CP_CE_IB1_BASE_HI" 2203 }, 2204 { 2205 "chips": ["gfx6"], 2206 "map": {"at": 34616, "to": "mm"}, 2207 "name": "CP_IB1_BUFSZ", 2208 "type_ref": "CP_CE_IB1_BUFSZ" 2209 }, 2210 { 2211 "chips": ["gfx6"], 2212 "map": {"at": 34620, "to": "mm"}, 2213 "name": "CP_IB2_BASE_LO", 2214 "type_ref": "CP_CE_IB2_BASE_LO" 2215 }, 2216 { 2217 "chips": ["gfx6"], 2218 "map": {"at": 34624, "to": "mm"}, 2219 "name": "CP_IB2_BASE_HI", 2220 "type_ref": "CP_CE_IB2_BASE_HI" 2221 }, 2222 { 2223 "chips": ["gfx6"], 2224 "map": {"at": 34628, "to": "mm"}, 2225 "name": "CP_IB2_BUFSZ", 2226 "type_ref": "CP_CE_IB2_BUFSZ" 2227 }, 2228 { 2229 "chips": ["gfx6"], 2230 "map": {"at": 34632, "to": "mm"}, 2231 "name": "CP_ST_BASE_LO", 2232 "type_ref": "CP_ST_BASE_LO" 2233 }, 2234 { 2235 "chips": ["gfx6"], 2236 "map": {"at": 34636, "to": "mm"}, 2237 "name": "CP_ST_BASE_HI", 2238 "type_ref": "CP_ST_BASE_HI" 2239 }, 2240 { 2241 "chips": ["gfx6"], 2242 "map": {"at": 34640, "to": "mm"}, 2243 "name": "CP_ST_BUFSZ", 2244 "type_ref": "CP_ST_BUFSZ" 2245 }, 2246 { 2247 "chips": ["gfx6"], 2248 "map": {"at": 34644, "to": "mm"}, 2249 "name": "CP_ROQ1_THRESHOLDS", 2250 "type_ref": "CP_ROQ1_THRESHOLDS" 2251 }, 2252 { 2253 "chips": ["gfx6"], 2254 "map": {"at": 34648, "to": "mm"}, 2255 "name": "CP_ROQ2_THRESHOLDS", 2256 "type_ref": "CP_ROQ2_THRESHOLDS" 2257 }, 2258 { 2259 "chips": ["gfx6"], 2260 "map": {"at": 34652, "to": "mm"}, 2261 "name": "CP_STQ_THRESHOLDS", 2262 "type_ref": "CP_STQ_THRESHOLDS" 2263 }, 2264 { 2265 "chips": ["gfx6"], 2266 "map": {"at": 34656, "to": "mm"}, 2267 "name": "CP_QUEUE_THRESHOLDS", 2268 "type_ref": "CP_QUEUE_THRESHOLDS" 2269 }, 2270 { 2271 "chips": ["gfx6"], 2272 "map": {"at": 34660, "to": "mm"}, 2273 "name": "CP_MEQ_THRESHOLDS", 2274 "type_ref": "CP_MEQ_THRESHOLDS" 2275 }, 2276 { 2277 "chips": ["gfx6"], 2278 "map": {"at": 34664, "to": "mm"}, 2279 "name": "CP_ROQ_AVAIL", 2280 "type_ref": "CP_ROQ_AVAIL" 2281 }, 2282 { 2283 "chips": ["gfx6"], 2284 "map": {"at": 34668, "to": "mm"}, 2285 "name": "CP_STQ_AVAIL", 2286 "type_ref": "CP_STQ_AVAIL" 2287 }, 2288 { 2289 "chips": ["gfx6"], 2290 "map": {"at": 34672, "to": "mm"}, 2291 "name": "CP_ROQ2_AVAIL", 2292 "type_ref": "CP_ROQ2_AVAIL" 2293 }, 2294 { 2295 "chips": ["gfx6"], 2296 "map": {"at": 34676, "to": "mm"}, 2297 "name": "CP_MEQ_AVAIL", 2298 "type_ref": "CP_MEQ_AVAIL" 2299 }, 2300 { 2301 "chips": ["gfx6"], 2302 "map": {"at": 34680, "to": "mm"}, 2303 "name": "CP_CMD_INDEX", 2304 "type_ref": "CP_CMD_INDEX" 2305 }, 2306 { 2307 "chips": ["gfx6"], 2308 "map": {"at": 34684, "to": "mm"}, 2309 "name": "CP_CMD_DATA" 2310 }, 2311 { 2312 "chips": ["gfx6"], 2313 "map": {"at": 34688, "to": "mm"}, 2314 "name": "CP_ROQ_RB_STAT", 2315 "type_ref": "CP_ROQ_RB_STAT" 2316 }, 2317 { 2318 "chips": ["gfx6"], 2319 "map": {"at": 34692, "to": "mm"}, 2320 "name": "CP_ROQ_IB1_STAT", 2321 "type_ref": "CP_ROQ_IB1_STAT" 2322 }, 2323 { 2324 "chips": ["gfx6"], 2325 "map": {"at": 34696, "to": "mm"}, 2326 "name": "CP_ROQ_IB2_STAT", 2327 "type_ref": "CP_ROQ_IB2_STAT" 2328 }, 2329 { 2330 "chips": ["gfx6"], 2331 "map": {"at": 34700, "to": "mm"}, 2332 "name": "CP_STQ_STAT", 2333 "type_ref": "CP_STQ_STAT" 2334 }, 2335 { 2336 "chips": ["gfx6"], 2337 "map": {"at": 34708, "to": "mm"}, 2338 "name": "CP_MEQ_STAT", 2339 "type_ref": "CP_MEQ_STAT" 2340 }, 2341 { 2342 "chips": ["gfx6"], 2343 "map": {"at": 34712, "to": "mm"}, 2344 "name": "CP_CEQ1_AVAIL", 2345 "type_ref": "CP_CEQ1_AVAIL" 2346 }, 2347 { 2348 "chips": ["gfx6"], 2349 "map": {"at": 34716, "to": "mm"}, 2350 "name": "CP_CEQ2_AVAIL", 2351 "type_ref": "CP_CEQ2_AVAIL" 2352 }, 2353 { 2354 "chips": ["gfx6"], 2355 "map": {"at": 34720, "to": "mm"}, 2356 "name": "CP_CE_ROQ_RB_STAT", 2357 "type_ref": "CP_CE_ROQ_RB_STAT" 2358 }, 2359 { 2360 "chips": ["gfx6"], 2361 "map": {"at": 34724, "to": "mm"}, 2362 "name": "CP_CE_ROQ_IB1_STAT", 2363 "type_ref": "CP_CE_ROQ_IB1_STAT" 2364 }, 2365 { 2366 "chips": ["gfx6"], 2367 "map": {"at": 34728, "to": "mm"}, 2368 "name": "CP_CE_ROQ_IB2_STAT", 2369 "type_ref": "CP_CE_ROQ_IB2_STAT" 2370 }, 2371 { 2372 "chips": ["gfx6"], 2373 "map": {"at": 34780, "to": "mm"}, 2374 "name": "CP_INT_STAT_DEBUG", 2375 "type_ref": "CP_INT_STAT_DEBUG" 2376 }, 2377 { 2378 "chips": ["gfx6"], 2379 "map": {"at": 34812, "to": "mm"}, 2380 "name": "CP_PERFMON_CNTL", 2381 "type_ref": "CP_PERFMON_CNTL" 2382 }, 2383 { 2384 "chips": ["gfx6"], 2385 "map": {"at": 34944, "to": "mm"}, 2386 "name": "IA_PERFCOUNTER0_SELECT", 2387 "type_ref": "IA_PERFCOUNTER0_SELECT" 2388 }, 2389 { 2390 "chips": ["gfx6"], 2391 "map": {"at": 34948, "to": "mm"}, 2392 "name": "IA_PERFCOUNTER1_SELECT", 2393 "type_ref": "IA_PERFCOUNTER1_SELECT" 2394 }, 2395 { 2396 "chips": ["gfx6"], 2397 "map": {"at": 34952, "to": "mm"}, 2398 "name": "IA_PERFCOUNTER2_SELECT", 2399 "type_ref": "IA_PERFCOUNTER1_SELECT" 2400 }, 2401 { 2402 "chips": ["gfx6"], 2403 "map": {"at": 34956, "to": "mm"}, 2404 "name": "IA_PERFCOUNTER3_SELECT", 2405 "type_ref": "IA_PERFCOUNTER1_SELECT" 2406 }, 2407 { 2408 "chips": ["gfx6"], 2409 "map": {"at": 34960, "to": "mm"}, 2410 "name": "IA_PERFCOUNTER0_LO" 2411 }, 2412 { 2413 "chips": ["gfx6"], 2414 "map": {"at": 34964, "to": "mm"}, 2415 "name": "IA_PERFCOUNTER0_HI" 2416 }, 2417 { 2418 "chips": ["gfx6"], 2419 "map": {"at": 34968, "to": "mm"}, 2420 "name": "IA_PERFCOUNTER1_LO" 2421 }, 2422 { 2423 "chips": ["gfx6"], 2424 "map": {"at": 34972, "to": "mm"}, 2425 "name": "IA_PERFCOUNTER1_HI" 2426 }, 2427 { 2428 "chips": ["gfx6"], 2429 "map": {"at": 34976, "to": "mm"}, 2430 "name": "IA_PERFCOUNTER2_LO" 2431 }, 2432 { 2433 "chips": ["gfx6"], 2434 "map": {"at": 34980, "to": "mm"}, 2435 "name": "IA_PERFCOUNTER2_HI" 2436 }, 2437 { 2438 "chips": ["gfx6"], 2439 "map": {"at": 34984, "to": "mm"}, 2440 "name": "IA_PERFCOUNTER3_LO" 2441 }, 2442 { 2443 "chips": ["gfx6"], 2444 "map": {"at": 34988, "to": "mm"}, 2445 "name": "IA_PERFCOUNTER3_HI" 2446 }, 2447 { 2448 "chips": ["gfx6"], 2449 "map": {"at": 34992, "to": "mm"}, 2450 "name": "VGT_VTX_VECT_EJECT_REG", 2451 "type_ref": "VGT_VTX_VECT_EJECT_REG" 2452 }, 2453 { 2454 "chips": ["gfx6"], 2455 "map": {"at": 34996, "to": "mm"}, 2456 "name": "VGT_DMA_DATA_FIFO_DEPTH", 2457 "type_ref": "VGT_DMA_DATA_FIFO_DEPTH" 2458 }, 2459 { 2460 "chips": ["gfx6"], 2461 "map": {"at": 35000, "to": "mm"}, 2462 "name": "VGT_DMA_REQ_FIFO_DEPTH", 2463 "type_ref": "VGT_DMA_REQ_FIFO_DEPTH" 2464 }, 2465 { 2466 "chips": ["gfx6"], 2467 "map": {"at": 35004, "to": "mm"}, 2468 "name": "VGT_DRAW_INIT_FIFO_DEPTH", 2469 "type_ref": "VGT_DRAW_INIT_FIFO_DEPTH" 2470 }, 2471 { 2472 "chips": ["gfx6"], 2473 "map": {"at": 35008, "to": "mm"}, 2474 "name": "VGT_LAST_COPY_STATE", 2475 "type_ref": "VGT_LAST_COPY_STATE" 2476 }, 2477 { 2478 "chips": ["gfx6"], 2479 "map": {"at": 35012, "to": "mm"}, 2480 "name": "VGT_CACHE_INVALIDATION", 2481 "type_ref": "VGT_CACHE_INVALIDATION" 2482 }, 2483 { 2484 "chips": ["gfx6"], 2485 "map": {"at": 35016, "to": "mm"}, 2486 "name": "VGT_ESGS_RING_SIZE" 2487 }, 2488 { 2489 "chips": ["gfx6"], 2490 "map": {"at": 35020, "to": "mm"}, 2491 "name": "VGT_GSVS_RING_SIZE" 2492 }, 2493 { 2494 "chips": ["gfx6"], 2495 "map": {"at": 35024, "to": "mm"}, 2496 "name": "VGT_FIFO_DEPTHS", 2497 "type_ref": "VGT_FIFO_DEPTHS" 2498 }, 2499 { 2500 "chips": ["gfx6"], 2501 "map": {"at": 35028, "to": "mm"}, 2502 "name": "VGT_GS_VERTEX_REUSE", 2503 "type_ref": "VGT_GS_VERTEX_REUSE" 2504 }, 2505 { 2506 "chips": ["gfx6"], 2507 "map": {"at": 35032, "to": "mm"}, 2508 "name": "VGT_MC_LAT_CNTL", 2509 "type_ref": "VGT_MC_LAT_CNTL" 2510 }, 2511 { 2512 "chips": ["gfx6"], 2513 "map": {"at": 35036, "to": "mm"}, 2514 "name": "IA_CNTL_STATUS", 2515 "type_ref": "IA_CNTL_STATUS" 2516 }, 2517 { 2518 "chips": ["gfx6"], 2519 "map": {"at": 35040, "to": "mm"}, 2520 "name": "VGT_DEBUG_CNTL", 2521 "type_ref": "VGT_DEBUG_CNTL" 2522 }, 2523 { 2524 "chips": ["gfx6"], 2525 "map": {"at": 35044, "to": "mm"}, 2526 "name": "VGT_DEBUG_DATA" 2527 }, 2528 { 2529 "chips": ["gfx6"], 2530 "map": {"at": 35048, "to": "mm"}, 2531 "name": "IA_DEBUG_CNTL", 2532 "type_ref": "IA_DEBUG_CNTL" 2533 }, 2534 { 2535 "chips": ["gfx6"], 2536 "map": {"at": 35052, "to": "mm"}, 2537 "name": "IA_DEBUG_DATA" 2538 }, 2539 { 2540 "chips": ["gfx6"], 2541 "map": {"at": 35056, "to": "mm"}, 2542 "name": "VGT_CNTL_STATUS", 2543 "type_ref": "VGT_CNTL_STATUS" 2544 }, 2545 { 2546 "chips": ["gfx6"], 2547 "map": {"at": 35100, "to": "mm"}, 2548 "name": "VGT_PERFCOUNTER_SEID_MASK", 2549 "type_ref": "VGT_PERFCOUNTER_SEID_MASK" 2550 }, 2551 { 2552 "chips": ["gfx6"], 2553 "map": {"at": 35104, "to": "mm"}, 2554 "name": "VGT_PERFCOUNTER0_SELECT", 2555 "type_ref": "IA_PERFCOUNTER0_SELECT" 2556 }, 2557 { 2558 "chips": ["gfx6"], 2559 "map": {"at": 35108, "to": "mm"}, 2560 "name": "VGT_PERFCOUNTER1_SELECT", 2561 "type_ref": "IA_PERFCOUNTER0_SELECT" 2562 }, 2563 { 2564 "chips": ["gfx6"], 2565 "map": {"at": 35112, "to": "mm"}, 2566 "name": "VGT_PERFCOUNTER2_SELECT", 2567 "type_ref": "IA_PERFCOUNTER1_SELECT" 2568 }, 2569 { 2570 "chips": ["gfx6"], 2571 "map": {"at": 35116, "to": "mm"}, 2572 "name": "VGT_PERFCOUNTER3_SELECT", 2573 "type_ref": "IA_PERFCOUNTER1_SELECT" 2574 }, 2575 { 2576 "chips": ["gfx6"], 2577 "map": {"at": 35120, "to": "mm"}, 2578 "name": "VGT_PERFCOUNTER0_LO" 2579 }, 2580 { 2581 "chips": ["gfx6"], 2582 "map": {"at": 35124, "to": "mm"}, 2583 "name": "VGT_PERFCOUNTER0_HI" 2584 }, 2585 { 2586 "chips": ["gfx6"], 2587 "map": {"at": 35128, "to": "mm"}, 2588 "name": "VGT_PERFCOUNTER1_LO" 2589 }, 2590 { 2591 "chips": ["gfx6"], 2592 "map": {"at": 35132, "to": "mm"}, 2593 "name": "VGT_PERFCOUNTER1_HI" 2594 }, 2595 { 2596 "chips": ["gfx6"], 2597 "map": {"at": 35136, "to": "mm"}, 2598 "name": "VGT_PERFCOUNTER2_LO" 2599 }, 2600 { 2601 "chips": ["gfx6"], 2602 "map": {"at": 35140, "to": "mm"}, 2603 "name": "VGT_PERFCOUNTER2_HI" 2604 }, 2605 { 2606 "chips": ["gfx6"], 2607 "map": {"at": 35144, "to": "mm"}, 2608 "name": "VGT_PERFCOUNTER3_LO" 2609 }, 2610 { 2611 "chips": ["gfx6"], 2612 "map": {"at": 35148, "to": "mm"}, 2613 "name": "VGT_PERFCOUNTER3_HI" 2614 }, 2615 { 2616 "chips": ["gfx6"], 2617 "map": {"at": 35160, "to": "mm"}, 2618 "name": "VGT_PRIMITIVE_TYPE", 2619 "type_ref": "VGT_PRIMITIVE_TYPE" 2620 }, 2621 { 2622 "chips": ["gfx6"], 2623 "map": {"at": 35164, "to": "mm"}, 2624 "name": "VGT_INDEX_TYPE", 2625 "type_ref": "VGT_INDEX_TYPE" 2626 }, 2627 { 2628 "chips": ["gfx6"], 2629 "map": {"at": 35168, "to": "mm"}, 2630 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_0" 2631 }, 2632 { 2633 "chips": ["gfx6"], 2634 "map": {"at": 35172, "to": "mm"}, 2635 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_1" 2636 }, 2637 { 2638 "chips": ["gfx6"], 2639 "map": {"at": 35176, "to": "mm"}, 2640 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_2" 2641 }, 2642 { 2643 "chips": ["gfx6"], 2644 "map": {"at": 35180, "to": "mm"}, 2645 "name": "VGT_STRMOUT_BUFFER_FILLED_SIZE_3" 2646 }, 2647 { 2648 "chips": ["gfx6"], 2649 "map": {"at": 35184, "to": "mm"}, 2650 "name": "VGT_NUM_INDICES" 2651 }, 2652 { 2653 "chips": ["gfx6"], 2654 "map": {"at": 35188, "to": "mm"}, 2655 "name": "VGT_NUM_INSTANCES" 2656 }, 2657 { 2658 "chips": ["gfx6"], 2659 "map": {"at": 35196, "to": "mm"}, 2660 "name": "CGTT_VGT_CLK_CTRL", 2661 "type_ref": "CGTT_VGT_CLK_CTRL" 2662 }, 2663 { 2664 "chips": ["gfx6"], 2665 "map": {"at": 35200, "to": "mm"}, 2666 "name": "IA_VMID_OVERRIDE", 2667 "type_ref": "IA_VMID_OVERRIDE" 2668 }, 2669 { 2670 "chips": ["gfx6"], 2671 "map": {"at": 35204, "to": "mm"}, 2672 "name": "CGTT_IA_CLK_CTRL", 2673 "type_ref": "CGTT_IA_CLK_CTRL" 2674 }, 2675 { 2676 "chips": ["gfx6"], 2677 "map": {"at": 35208, "to": "mm"}, 2678 "name": "VGT_TF_RING_SIZE", 2679 "type_ref": "VGT_TF_RING_SIZE" 2680 }, 2681 { 2682 "chips": ["gfx6"], 2683 "map": {"at": 35212, "to": "mm"}, 2684 "name": "VGT_SYS_CONFIG", 2685 "type_ref": "VGT_SYS_CONFIG" 2686 }, 2687 { 2688 "chips": ["gfx6"], 2689 "map": {"at": 35248, "to": "mm"}, 2690 "name": "VGT_HS_OFFCHIP_PARAM", 2691 "type_ref": "VGT_HS_OFFCHIP_PARAM" 2692 }, 2693 { 2694 "chips": ["gfx6"], 2695 "map": {"at": 35256, "to": "mm"}, 2696 "name": "VGT_TF_MEMORY_BASE" 2697 }, 2698 { 2699 "chips": ["gfx6"], 2700 "map": {"at": 35260, "to": "mm"}, 2701 "name": "CC_GC_SHADER_ARRAY_CONFIG", 2702 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG" 2703 }, 2704 { 2705 "chips": ["gfx6"], 2706 "map": {"at": 35264, "to": "mm"}, 2707 "name": "GC_USER_SHADER_ARRAY_CONFIG", 2708 "type_ref": "CC_GC_SHADER_ARRAY_CONFIG" 2709 }, 2710 { 2711 "chips": ["gfx6"], 2712 "map": {"at": 35328, "to": "mm"}, 2713 "name": "PA_SU_DEBUG_CNTL", 2714 "type_ref": "PA_SU_DEBUG_CNTL" 2715 }, 2716 { 2717 "chips": ["gfx6"], 2718 "map": {"at": 35332, "to": "mm"}, 2719 "name": "PA_SU_DEBUG_DATA" 2720 }, 2721 { 2722 "chips": ["gfx6"], 2723 "map": {"at": 35344, "to": "mm"}, 2724 "name": "PA_CL_CNTL_STATUS", 2725 "type_ref": "PA_CL_CNTL_STATUS" 2726 }, 2727 { 2728 "chips": ["gfx6"], 2729 "map": {"at": 35348, "to": "mm"}, 2730 "name": "PA_CL_ENHANCE", 2731 "type_ref": "PA_CL_ENHANCE" 2732 }, 2733 { 2734 "chips": ["gfx6"], 2735 "map": {"at": 35352, "to": "mm"}, 2736 "name": "CGTT_PA_CLK_CTRL", 2737 "type_ref": "CGTT_PA_CLK_CTRL" 2738 }, 2739 { 2740 "chips": ["gfx6"], 2741 "map": {"at": 35360, "to": "mm"}, 2742 "name": "PA_SU_PERFCOUNTER0_SELECT", 2743 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 2744 }, 2745 { 2746 "chips": ["gfx6"], 2747 "map": {"at": 35364, "to": "mm"}, 2748 "name": "PA_SU_PERFCOUNTER1_SELECT", 2749 "type_ref": "PA_SU_PERFCOUNTER0_SELECT" 2750 }, 2751 { 2752 "chips": ["gfx6"], 2753 "map": {"at": 35368, "to": "mm"}, 2754 "name": "PA_SU_PERFCOUNTER2_SELECT", 2755 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 2756 }, 2757 { 2758 "chips": ["gfx6"], 2759 "map": {"at": 35372, "to": "mm"}, 2760 "name": "PA_SU_PERFCOUNTER3_SELECT", 2761 "type_ref": "PA_SU_PERFCOUNTER2_SELECT" 2762 }, 2763 { 2764 "chips": ["gfx6"], 2765 "map": {"at": 35376, "to": "mm"}, 2766 "name": "PA_SU_PERFCOUNTER0_LO" 2767 }, 2768 { 2769 "chips": ["gfx6"], 2770 "map": {"at": 35380, "to": "mm"}, 2771 "name": "PA_SU_PERFCOUNTER0_HI", 2772 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2773 }, 2774 { 2775 "chips": ["gfx6"], 2776 "map": {"at": 35384, "to": "mm"}, 2777 "name": "PA_SU_PERFCOUNTER1_LO" 2778 }, 2779 { 2780 "chips": ["gfx6"], 2781 "map": {"at": 35388, "to": "mm"}, 2782 "name": "PA_SU_PERFCOUNTER1_HI", 2783 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2784 }, 2785 { 2786 "chips": ["gfx6"], 2787 "map": {"at": 35392, "to": "mm"}, 2788 "name": "PA_SU_PERFCOUNTER2_LO" 2789 }, 2790 { 2791 "chips": ["gfx6"], 2792 "map": {"at": 35396, "to": "mm"}, 2793 "name": "PA_SU_PERFCOUNTER2_HI", 2794 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2795 }, 2796 { 2797 "chips": ["gfx6"], 2798 "map": {"at": 35400, "to": "mm"}, 2799 "name": "PA_SU_PERFCOUNTER3_LO" 2800 }, 2801 { 2802 "chips": ["gfx6"], 2803 "map": {"at": 35404, "to": "mm"}, 2804 "name": "PA_SU_PERFCOUNTER3_HI", 2805 "type_ref": "PA_SU_PERFCOUNTER0_HI" 2806 }, 2807 { 2808 "chips": ["gfx6"], 2809 "map": {"at": 35408, "to": "mm"}, 2810 "name": "PA_SU_CNTL_STATUS", 2811 "type_ref": "PA_SU_CNTL_STATUS" 2812 }, 2813 { 2814 "chips": ["gfx6"], 2815 "map": {"at": 35412, "to": "mm"}, 2816 "name": "PA_SC_FIFO_DEPTH_CNTL", 2817 "type_ref": "PA_SC_FIFO_DEPTH_CNTL" 2818 }, 2819 { 2820 "chips": ["gfx6"], 2821 "map": {"at": 35424, "to": "mm"}, 2822 "name": "PA_SU_LINE_STIPPLE_VALUE", 2823 "type_ref": "PA_SU_LINE_STIPPLE_VALUE" 2824 }, 2825 { 2826 "chips": ["gfx6"], 2827 "map": {"at": 35456, "to": "mm"}, 2828 "name": "PA_SC_PERFCOUNTER0_SELECT", 2829 "type_ref": "PA_SC_PERFCOUNTER0_SELECT" 2830 }, 2831 { 2832 "chips": ["gfx6"], 2833 "map": {"at": 35460, "to": "mm"}, 2834 "name": "PA_SC_PERFCOUNTER1_SELECT", 2835 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2836 }, 2837 { 2838 "chips": ["gfx6"], 2839 "map": {"at": 35464, "to": "mm"}, 2840 "name": "PA_SC_PERFCOUNTER2_SELECT", 2841 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2842 }, 2843 { 2844 "chips": ["gfx6"], 2845 "map": {"at": 35468, "to": "mm"}, 2846 "name": "PA_SC_PERFCOUNTER3_SELECT", 2847 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2848 }, 2849 { 2850 "chips": ["gfx6"], 2851 "map": {"at": 35472, "to": "mm"}, 2852 "name": "PA_SC_PERFCOUNTER4_SELECT", 2853 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2854 }, 2855 { 2856 "chips": ["gfx6"], 2857 "map": {"at": 35476, "to": "mm"}, 2858 "name": "PA_SC_PERFCOUNTER5_SELECT", 2859 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2860 }, 2861 { 2862 "chips": ["gfx6"], 2863 "map": {"at": 35480, "to": "mm"}, 2864 "name": "PA_SC_PERFCOUNTER6_SELECT", 2865 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2866 }, 2867 { 2868 "chips": ["gfx6"], 2869 "map": {"at": 35484, "to": "mm"}, 2870 "name": "PA_SC_PERFCOUNTER7_SELECT", 2871 "type_ref": "PA_SC_PERFCOUNTER1_SELECT" 2872 }, 2873 { 2874 "chips": ["gfx6"], 2875 "map": {"at": 35488, "to": "mm"}, 2876 "name": "PA_SC_PERFCOUNTER0_LO" 2877 }, 2878 { 2879 "chips": ["gfx6"], 2880 "map": {"at": 35492, "to": "mm"}, 2881 "name": "PA_SC_PERFCOUNTER0_HI" 2882 }, 2883 { 2884 "chips": ["gfx6"], 2885 "map": {"at": 35496, "to": "mm"}, 2886 "name": "PA_SC_PERFCOUNTER1_LO" 2887 }, 2888 { 2889 "chips": ["gfx6"], 2890 "map": {"at": 35500, "to": "mm"}, 2891 "name": "PA_SC_PERFCOUNTER1_HI" 2892 }, 2893 { 2894 "chips": ["gfx6"], 2895 "map": {"at": 35504, "to": "mm"}, 2896 "name": "PA_SC_PERFCOUNTER2_LO" 2897 }, 2898 { 2899 "chips": ["gfx6"], 2900 "map": {"at": 35508, "to": "mm"}, 2901 "name": "PA_SC_PERFCOUNTER2_HI" 2902 }, 2903 { 2904 "chips": ["gfx6"], 2905 "map": {"at": 35512, "to": "mm"}, 2906 "name": "PA_SC_PERFCOUNTER3_LO" 2907 }, 2908 { 2909 "chips": ["gfx6"], 2910 "map": {"at": 35516, "to": "mm"}, 2911 "name": "PA_SC_PERFCOUNTER3_HI" 2912 }, 2913 { 2914 "chips": ["gfx6"], 2915 "map": {"at": 35520, "to": "mm"}, 2916 "name": "PA_SC_PERFCOUNTER4_LO" 2917 }, 2918 { 2919 "chips": ["gfx6"], 2920 "map": {"at": 35524, "to": "mm"}, 2921 "name": "PA_SC_PERFCOUNTER4_HI" 2922 }, 2923 { 2924 "chips": ["gfx6"], 2925 "map": {"at": 35528, "to": "mm"}, 2926 "name": "PA_SC_PERFCOUNTER5_LO" 2927 }, 2928 { 2929 "chips": ["gfx6"], 2930 "map": {"at": 35532, "to": "mm"}, 2931 "name": "PA_SC_PERFCOUNTER5_HI" 2932 }, 2933 { 2934 "chips": ["gfx6"], 2935 "map": {"at": 35536, "to": "mm"}, 2936 "name": "PA_SC_PERFCOUNTER6_LO" 2937 }, 2938 { 2939 "chips": ["gfx6"], 2940 "map": {"at": 35540, "to": "mm"}, 2941 "name": "PA_SC_PERFCOUNTER6_HI" 2942 }, 2943 { 2944 "chips": ["gfx6"], 2945 "map": {"at": 35544, "to": "mm"}, 2946 "name": "PA_SC_PERFCOUNTER7_LO" 2947 }, 2948 { 2949 "chips": ["gfx6"], 2950 "map": {"at": 35548, "to": "mm"}, 2951 "name": "PA_SC_PERFCOUNTER7_HI" 2952 }, 2953 { 2954 "chips": ["gfx6"], 2955 "map": {"at": 35600, "to": "mm"}, 2956 "name": "PA_SC_LINE_STIPPLE_STATE", 2957 "type_ref": "PA_SC_LINE_STIPPLE_STATE" 2958 }, 2959 { 2960 "chips": ["gfx6"], 2961 "map": {"at": 35620, "to": "mm"}, 2962 "name": "PA_SC_FORCE_EOV_MAX_CNTS", 2963 "type_ref": "PA_SC_FORCE_EOV_MAX_CNTS" 2964 }, 2965 { 2966 "chips": ["gfx6"], 2967 "map": {"at": 35624, "to": "mm"}, 2968 "name": "CGTT_SC_CLK_CTRL", 2969 "type_ref": "CGTT_SC_CLK_CTRL" 2970 }, 2971 { 2972 "chips": ["gfx6"], 2973 "map": {"at": 35788, "to": "mm"}, 2974 "name": "PA_SC_FIFO_SIZE", 2975 "type_ref": "PA_SC_FIFO_SIZE" 2976 }, 2977 { 2978 "chips": ["gfx6"], 2979 "map": {"at": 35796, "to": "mm"}, 2980 "name": "PA_SC_IF_FIFO_SIZE", 2981 "type_ref": "PA_SC_IF_FIFO_SIZE" 2982 }, 2983 { 2984 "chips": ["gfx6"], 2985 "map": {"at": 35800, "to": "mm"}, 2986 "name": "PA_SC_DEBUG_CNTL", 2987 "type_ref": "PA_SC_DEBUG_CNTL" 2988 }, 2989 { 2990 "chips": ["gfx6"], 2991 "map": {"at": 35804, "to": "mm"}, 2992 "name": "PA_SC_DEBUG_DATA" 2993 }, 2994 { 2995 "chips": ["gfx6"], 2996 "map": {"at": 35824, "to": "mm"}, 2997 "name": "PA_SC_ENHANCE", 2998 "type_ref": "PA_SC_ENHANCE" 2999 }, 3000 { 3001 "chips": ["gfx6"], 3002 "map": {"at": 35840, "to": "mm"}, 3003 "name": "SQ_CONFIG", 3004 "type_ref": "SQ_CONFIG" 3005 }, 3006 { 3007 "chips": ["gfx6"], 3008 "map": {"at": 35844, "to": "mm"}, 3009 "name": "SQC_CONFIG", 3010 "type_ref": "SQC_CONFIG" 3011 }, 3012 { 3013 "chips": ["gfx6"], 3014 "map": {"at": 35848, "to": "mm"}, 3015 "name": "SQC_CACHES", 3016 "type_ref": "SQC_CACHES" 3017 }, 3018 { 3019 "chips": ["gfx6"], 3020 "map": {"at": 35852, "to": "mm"}, 3021 "name": "SQ_RANDOM_WAVE_PRI", 3022 "type_ref": "SQ_RANDOM_WAVE_PRI" 3023 }, 3024 { 3025 "chips": ["gfx6"], 3026 "map": {"at": 35856, "to": "mm"}, 3027 "name": "SQ_REG_CREDITS", 3028 "type_ref": "SQ_REG_CREDITS" 3029 }, 3030 { 3031 "chips": ["gfx6"], 3032 "map": {"at": 35860, "to": "mm"}, 3033 "name": "SQ_FIFO_SIZES", 3034 "type_ref": "SQ_FIFO_SIZES" 3035 }, 3036 { 3037 "chips": ["gfx6"], 3038 "map": {"at": 35864, "to": "mm"}, 3039 "name": "SQ_PERFCOUNTER_CTRL", 3040 "type_ref": "SQ_PERFCOUNTER_CTRL" 3041 }, 3042 { 3043 "chips": ["gfx6"], 3044 "map": {"at": 35868, "to": "mm"}, 3045 "name": "CC_SQC_BANK_DISABLE", 3046 "type_ref": "CC_SQC_BANK_DISABLE" 3047 }, 3048 { 3049 "chips": ["gfx6"], 3050 "map": {"at": 35872, "to": "mm"}, 3051 "name": "USER_SQC_BANK_DISABLE", 3052 "type_ref": "CC_SQC_BANK_DISABLE" 3053 }, 3054 { 3055 "chips": ["gfx6"], 3056 "map": {"at": 35876, "to": "mm"}, 3057 "name": "SQ_DEBUG_STS_GLOBAL", 3058 "type_ref": "SQ_DEBUG_STS_GLOBAL" 3059 }, 3060 { 3061 "chips": ["gfx6"], 3062 "map": {"at": 35968, "to": "mm"}, 3063 "name": "SQ_PERFCOUNTER0_LO" 3064 }, 3065 { 3066 "chips": ["gfx6"], 3067 "map": {"at": 35972, "to": "mm"}, 3068 "name": "SQ_PERFCOUNTER0_HI" 3069 }, 3070 { 3071 "chips": ["gfx6"], 3072 "map": {"at": 35976, "to": "mm"}, 3073 "name": "SQ_PERFCOUNTER1_LO" 3074 }, 3075 { 3076 "chips": ["gfx6"], 3077 "map": {"at": 35980, "to": "mm"}, 3078 "name": "SQ_PERFCOUNTER1_HI" 3079 }, 3080 { 3081 "chips": ["gfx6"], 3082 "map": {"at": 35984, "to": "mm"}, 3083 "name": "SQ_PERFCOUNTER2_LO" 3084 }, 3085 { 3086 "chips": ["gfx6"], 3087 "map": {"at": 35988, "to": "mm"}, 3088 "name": "SQ_PERFCOUNTER2_HI" 3089 }, 3090 { 3091 "chips": ["gfx6"], 3092 "map": {"at": 35992, "to": "mm"}, 3093 "name": "SQ_PERFCOUNTER3_LO" 3094 }, 3095 { 3096 "chips": ["gfx6"], 3097 "map": {"at": 35996, "to": "mm"}, 3098 "name": "SQ_PERFCOUNTER3_HI" 3099 }, 3100 { 3101 "chips": ["gfx6"], 3102 "map": {"at": 36000, "to": "mm"}, 3103 "name": "SQ_PERFCOUNTER4_LO" 3104 }, 3105 { 3106 "chips": ["gfx6"], 3107 "map": {"at": 36004, "to": "mm"}, 3108 "name": "SQ_PERFCOUNTER4_HI" 3109 }, 3110 { 3111 "chips": ["gfx6"], 3112 "map": {"at": 36008, "to": "mm"}, 3113 "name": "SQ_PERFCOUNTER5_LO" 3114 }, 3115 { 3116 "chips": ["gfx6"], 3117 "map": {"at": 36012, "to": "mm"}, 3118 "name": "SQ_PERFCOUNTER5_HI" 3119 }, 3120 { 3121 "chips": ["gfx6"], 3122 "map": {"at": 36016, "to": "mm"}, 3123 "name": "SQ_PERFCOUNTER6_LO" 3124 }, 3125 { 3126 "chips": ["gfx6"], 3127 "map": {"at": 36020, "to": "mm"}, 3128 "name": "SQ_PERFCOUNTER6_HI" 3129 }, 3130 { 3131 "chips": ["gfx6"], 3132 "map": {"at": 36024, "to": "mm"}, 3133 "name": "SQ_PERFCOUNTER7_LO" 3134 }, 3135 { 3136 "chips": ["gfx6"], 3137 "map": {"at": 36028, "to": "mm"}, 3138 "name": "SQ_PERFCOUNTER7_HI" 3139 }, 3140 { 3141 "chips": ["gfx6"], 3142 "map": {"at": 36032, "to": "mm"}, 3143 "name": "SQ_PERFCOUNTER8_LO" 3144 }, 3145 { 3146 "chips": ["gfx6"], 3147 "map": {"at": 36036, "to": "mm"}, 3148 "name": "SQ_PERFCOUNTER8_HI" 3149 }, 3150 { 3151 "chips": ["gfx6"], 3152 "map": {"at": 36040, "to": "mm"}, 3153 "name": "SQ_PERFCOUNTER9_LO" 3154 }, 3155 { 3156 "chips": ["gfx6"], 3157 "map": {"at": 36044, "to": "mm"}, 3158 "name": "SQ_PERFCOUNTER9_HI" 3159 }, 3160 { 3161 "chips": ["gfx6"], 3162 "map": {"at": 36048, "to": "mm"}, 3163 "name": "SQ_PERFCOUNTER10_LO" 3164 }, 3165 { 3166 "chips": ["gfx6"], 3167 "map": {"at": 36052, "to": "mm"}, 3168 "name": "SQ_PERFCOUNTER10_HI" 3169 }, 3170 { 3171 "chips": ["gfx6"], 3172 "map": {"at": 36056, "to": "mm"}, 3173 "name": "SQ_PERFCOUNTER11_LO" 3174 }, 3175 { 3176 "chips": ["gfx6"], 3177 "map": {"at": 36060, "to": "mm"}, 3178 "name": "SQ_PERFCOUNTER11_HI" 3179 }, 3180 { 3181 "chips": ["gfx6"], 3182 "map": {"at": 36064, "to": "mm"}, 3183 "name": "SQ_PERFCOUNTER12_LO" 3184 }, 3185 { 3186 "chips": ["gfx6"], 3187 "map": {"at": 36068, "to": "mm"}, 3188 "name": "SQ_PERFCOUNTER12_HI" 3189 }, 3190 { 3191 "chips": ["gfx6"], 3192 "map": {"at": 36072, "to": "mm"}, 3193 "name": "SQ_PERFCOUNTER13_LO" 3194 }, 3195 { 3196 "chips": ["gfx6"], 3197 "map": {"at": 36076, "to": "mm"}, 3198 "name": "SQ_PERFCOUNTER13_HI" 3199 }, 3200 { 3201 "chips": ["gfx6"], 3202 "map": {"at": 36080, "to": "mm"}, 3203 "name": "SQ_PERFCOUNTER14_LO" 3204 }, 3205 { 3206 "chips": ["gfx6"], 3207 "map": {"at": 36084, "to": "mm"}, 3208 "name": "SQ_PERFCOUNTER14_HI" 3209 }, 3210 { 3211 "chips": ["gfx6"], 3212 "map": {"at": 36088, "to": "mm"}, 3213 "name": "SQ_PERFCOUNTER15_LO" 3214 }, 3215 { 3216 "chips": ["gfx6"], 3217 "map": {"at": 36092, "to": "mm"}, 3218 "name": "SQ_PERFCOUNTER15_HI" 3219 }, 3220 { 3221 "chips": ["gfx6"], 3222 "map": {"at": 36096, "to": "mm"}, 3223 "name": "SQ_PERFCOUNTER0_SELECT", 3224 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3225 }, 3226 { 3227 "chips": ["gfx6"], 3228 "map": {"at": 36100, "to": "mm"}, 3229 "name": "SQ_PERFCOUNTER1_SELECT", 3230 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3231 }, 3232 { 3233 "chips": ["gfx6"], 3234 "map": {"at": 36104, "to": "mm"}, 3235 "name": "SQ_PERFCOUNTER2_SELECT", 3236 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3237 }, 3238 { 3239 "chips": ["gfx6"], 3240 "map": {"at": 36108, "to": "mm"}, 3241 "name": "SQ_PERFCOUNTER3_SELECT", 3242 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3243 }, 3244 { 3245 "chips": ["gfx6"], 3246 "map": {"at": 36112, "to": "mm"}, 3247 "name": "SQ_PERFCOUNTER4_SELECT", 3248 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3249 }, 3250 { 3251 "chips": ["gfx6"], 3252 "map": {"at": 36116, "to": "mm"}, 3253 "name": "SQ_PERFCOUNTER5_SELECT", 3254 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3255 }, 3256 { 3257 "chips": ["gfx6"], 3258 "map": {"at": 36120, "to": "mm"}, 3259 "name": "SQ_PERFCOUNTER6_SELECT", 3260 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3261 }, 3262 { 3263 "chips": ["gfx6"], 3264 "map": {"at": 36124, "to": "mm"}, 3265 "name": "SQ_PERFCOUNTER7_SELECT", 3266 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3267 }, 3268 { 3269 "chips": ["gfx6"], 3270 "map": {"at": 36128, "to": "mm"}, 3271 "name": "SQ_PERFCOUNTER8_SELECT", 3272 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3273 }, 3274 { 3275 "chips": ["gfx6"], 3276 "map": {"at": 36132, "to": "mm"}, 3277 "name": "SQ_PERFCOUNTER9_SELECT", 3278 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3279 }, 3280 { 3281 "chips": ["gfx6"], 3282 "map": {"at": 36136, "to": "mm"}, 3283 "name": "SQ_PERFCOUNTER10_SELECT", 3284 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3285 }, 3286 { 3287 "chips": ["gfx6"], 3288 "map": {"at": 36140, "to": "mm"}, 3289 "name": "SQ_PERFCOUNTER11_SELECT", 3290 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3291 }, 3292 { 3293 "chips": ["gfx6"], 3294 "map": {"at": 36144, "to": "mm"}, 3295 "name": "SQ_PERFCOUNTER12_SELECT", 3296 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3297 }, 3298 { 3299 "chips": ["gfx6"], 3300 "map": {"at": 36148, "to": "mm"}, 3301 "name": "SQ_PERFCOUNTER13_SELECT", 3302 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3303 }, 3304 { 3305 "chips": ["gfx6"], 3306 "map": {"at": 36152, "to": "mm"}, 3307 "name": "SQ_PERFCOUNTER14_SELECT", 3308 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3309 }, 3310 { 3311 "chips": ["gfx6"], 3312 "map": {"at": 36156, "to": "mm"}, 3313 "name": "SQ_PERFCOUNTER15_SELECT", 3314 "type_ref": "SQ_PERFCOUNTER0_SELECT" 3315 }, 3316 { 3317 "chips": ["gfx6"], 3318 "map": {"at": 36224, "to": "mm"}, 3319 "name": "SQ_ALU_CLK_CTRL", 3320 "type_ref": "SQ_ALU_CLK_CTRL" 3321 }, 3322 { 3323 "chips": ["gfx6"], 3324 "map": {"at": 36228, "to": "mm"}, 3325 "name": "SQ_TEX_CLK_CTRL", 3326 "type_ref": "SQ_ALU_CLK_CTRL" 3327 }, 3328 { 3329 "chips": ["gfx6"], 3330 "map": {"at": 36232, "to": "mm"}, 3331 "name": "CGTT_SQ_CLK_CTRL", 3332 "type_ref": "CGTT_SQ_CLK_CTRL" 3333 }, 3334 { 3335 "chips": ["gfx6"], 3336 "map": {"at": 36236, "to": "mm"}, 3337 "name": "CGTT_SQG_CLK_CTRL", 3338 "type_ref": "CGTT_SQ_CLK_CTRL" 3339 }, 3340 { 3341 "chips": ["gfx6"], 3342 "map": {"at": 36320, "to": "mm"}, 3343 "name": "SQ_IND_INDEX", 3344 "type_ref": "SQ_IND_INDEX" 3345 }, 3346 { 3347 "chips": ["gfx6"], 3348 "map": {"at": 36324, "to": "mm"}, 3349 "name": "SQ_IND_DATA" 3350 }, 3351 { 3352 "chips": ["gfx6"], 3353 "map": {"at": 36336, "to": "mm"}, 3354 "name": "SQ_TIME_HI" 3355 }, 3356 { 3357 "chips": ["gfx6"], 3358 "map": {"at": 36340, "to": "mm"}, 3359 "name": "SQ_TIME_LO" 3360 }, 3361 { 3362 "chips": ["gfx6"], 3363 "map": {"at": 36352, "to": "mm"}, 3364 "name": "SQ_THREAD_TRACE_BASE" 3365 }, 3366 { 3367 "chips": ["gfx6"], 3368 "map": {"at": 36356, "to": "mm"}, 3369 "name": "SQ_THREAD_TRACE_SIZE", 3370 "type_ref": "SQ_THREAD_TRACE_SIZE" 3371 }, 3372 { 3373 "chips": ["gfx6"], 3374 "map": {"at": 36360, "to": "mm"}, 3375 "name": "SQ_THREAD_TRACE_MASK", 3376 "type_ref": "SQ_THREAD_TRACE_MASK" 3377 }, 3378 { 3379 "chips": ["gfx6"], 3380 "map": {"at": 36364, "to": "mm"}, 3381 "name": "SQ_THREAD_TRACE_TOKEN_MASK", 3382 "type_ref": "SQ_THREAD_TRACE_TOKEN_MASK" 3383 }, 3384 { 3385 "chips": ["gfx6"], 3386 "map": {"at": 36368, "to": "mm"}, 3387 "name": "SQ_THREAD_TRACE_PERF_MASK", 3388 "type_ref": "SQ_THREAD_TRACE_PERF_MASK" 3389 }, 3390 { 3391 "chips": ["gfx6"], 3392 "map": {"at": 36384, "to": "mm"}, 3393 "name": "SQ_THREAD_TRACE_USERDATA_0" 3394 }, 3395 { 3396 "chips": ["gfx6"], 3397 "map": {"at": 36388, "to": "mm"}, 3398 "name": "SQ_THREAD_TRACE_USERDATA_1" 3399 }, 3400 { 3401 "chips": ["gfx6"], 3402 "map": {"at": 36392, "to": "mm"}, 3403 "name": "SQ_THREAD_TRACE_USERDATA_2" 3404 }, 3405 { 3406 "chips": ["gfx6"], 3407 "map": {"at": 36396, "to": "mm"}, 3408 "name": "SQ_THREAD_TRACE_USERDATA_3" 3409 }, 3410 { 3411 "chips": ["gfx6"], 3412 "map": {"at": 36400, "to": "mm"}, 3413 "name": "SQ_THREAD_TRACE_WPTR", 3414 "type_ref": "SQ_THREAD_TRACE_WPTR" 3415 }, 3416 { 3417 "chips": ["gfx6"], 3418 "map": {"at": 36404, "to": "mm"}, 3419 "name": "SQ_THREAD_TRACE_STATUS", 3420 "type_ref": "SQ_THREAD_TRACE_STATUS" 3421 }, 3422 { 3423 "chips": ["gfx6"], 3424 "map": {"at": 36408, "to": "mm"}, 3425 "name": "SQ_THREAD_TRACE_MODE", 3426 "type_ref": "SQ_THREAD_TRACE_MODE" 3427 }, 3428 { 3429 "chips": ["gfx6"], 3430 "map": {"at": 36412, "to": "mm"}, 3431 "name": "SQ_THREAD_TRACE_CTRL", 3432 "type_ref": "SQ_THREAD_TRACE_CTRL" 3433 }, 3434 { 3435 "chips": ["gfx6"], 3436 "map": {"at": 36416, "to": "mm"}, 3437 "name": "SQ_THREAD_TRACE_CNTR" 3438 }, 3439 { 3440 "chips": ["gfx6"], 3441 "map": {"at": 36424, "to": "mm"}, 3442 "name": "SQ_THREAD_TRACE_HIWATER", 3443 "type_ref": "SQ_THREAD_TRACE_HIWATER" 3444 }, 3445 { 3446 "chips": ["gfx6"], 3447 "map": {"at": 36440, "to": "mm"}, 3448 "name": "SQ_POWER_THROTTLE", 3449 "type_ref": "SQ_POWER_THROTTLE" 3450 }, 3451 { 3452 "chips": ["gfx6"], 3453 "map": {"at": 36444, "to": "mm"}, 3454 "name": "SQ_POWER_THROTTLE2", 3455 "type_ref": "SQ_POWER_THROTTLE2" 3456 }, 3457 { 3458 "chips": ["gfx6"], 3459 "map": {"at": 36448, "to": "mm"}, 3460 "name": "SQ_LB_CTR_CTRL", 3461 "type_ref": "SQ_LB_CTR_CTRL" 3462 }, 3463 { 3464 "chips": ["gfx6"], 3465 "map": {"at": 36452, "to": "mm"}, 3466 "name": "SQ_LB_DATA_ALU_CYCLES" 3467 }, 3468 { 3469 "chips": ["gfx6"], 3470 "map": {"at": 36456, "to": "mm"}, 3471 "name": "SQ_LB_DATA_TEX_CYCLES" 3472 }, 3473 { 3474 "chips": ["gfx6"], 3475 "map": {"at": 36460, "to": "mm"}, 3476 "name": "SQ_LB_DATA_ALU_STALLS" 3477 }, 3478 { 3479 "chips": ["gfx6"], 3480 "map": {"at": 36464, "to": "mm"}, 3481 "name": "SQ_LB_DATA_TEX_STALLS" 3482 }, 3483 { 3484 "chips": ["gfx6"], 3485 "map": {"at": 36480, "to": "mm"}, 3486 "name": "SQC_SECDED_CNT", 3487 "type_ref": "SQC_SECDED_CNT" 3488 }, 3489 { 3490 "chips": ["gfx6"], 3491 "map": {"at": 36484, "to": "mm"}, 3492 "name": "SQ_SEC_CNT", 3493 "type_ref": "SQ_SEC_CNT" 3494 }, 3495 { 3496 "chips": ["gfx6"], 3497 "map": {"at": 36488, "to": "mm"}, 3498 "name": "SQ_DED_CNT", 3499 "type_ref": "SQ_DED_CNT" 3500 }, 3501 { 3502 "chips": ["gfx6"], 3503 "map": {"at": 36492, "to": "mm"}, 3504 "name": "SQ_DED_INFO", 3505 "type_ref": "SQ_DED_INFO" 3506 }, 3507 { 3508 "chips": ["gfx6"], 3509 "map": {"at": 36608, "to": "mm"}, 3510 "name": "SQ_BUF_RSRC_WORD0" 3511 }, 3512 { 3513 "chips": ["gfx6"], 3514 "map": {"at": 36612, "to": "mm"}, 3515 "name": "SQ_BUF_RSRC_WORD1", 3516 "type_ref": "SQ_BUF_RSRC_WORD1" 3517 }, 3518 { 3519 "chips": ["gfx6"], 3520 "map": {"at": 36616, "to": "mm"}, 3521 "name": "SQ_BUF_RSRC_WORD2" 3522 }, 3523 { 3524 "chips": ["gfx6"], 3525 "map": {"at": 36620, "to": "mm"}, 3526 "name": "SQ_BUF_RSRC_WORD3", 3527 "type_ref": "SQ_BUF_RSRC_WORD3" 3528 }, 3529 { 3530 "chips": ["gfx6"], 3531 "map": {"at": 36624, "to": "mm"}, 3532 "name": "SQ_IMG_RSRC_WORD0" 3533 }, 3534 { 3535 "chips": ["gfx6"], 3536 "map": {"at": 36628, "to": "mm"}, 3537 "name": "SQ_IMG_RSRC_WORD1", 3538 "type_ref": "SQ_IMG_RSRC_WORD1" 3539 }, 3540 { 3541 "chips": ["gfx6"], 3542 "map": {"at": 36632, "to": "mm"}, 3543 "name": "SQ_IMG_RSRC_WORD2", 3544 "type_ref": "SQ_IMG_RSRC_WORD2" 3545 }, 3546 { 3547 "chips": ["gfx6"], 3548 "map": {"at": 36636, "to": "mm"}, 3549 "name": "SQ_IMG_RSRC_WORD3", 3550 "type_ref": "SQ_IMG_RSRC_WORD3" 3551 }, 3552 { 3553 "chips": ["gfx6"], 3554 "map": {"at": 36640, "to": "mm"}, 3555 "name": "SQ_IMG_RSRC_WORD4", 3556 "type_ref": "SQ_IMG_RSRC_WORD4" 3557 }, 3558 { 3559 "chips": ["gfx6"], 3560 "map": {"at": 36644, "to": "mm"}, 3561 "name": "SQ_IMG_RSRC_WORD5", 3562 "type_ref": "SQ_IMG_RSRC_WORD5" 3563 }, 3564 { 3565 "chips": ["gfx6"], 3566 "map": {"at": 36648, "to": "mm"}, 3567 "name": "SQ_IMG_RSRC_WORD6", 3568 "type_ref": "SQ_IMG_RSRC_WORD6" 3569 }, 3570 { 3571 "chips": ["gfx6"], 3572 "map": {"at": 36652, "to": "mm"}, 3573 "name": "SQ_IMG_RSRC_WORD7" 3574 }, 3575 { 3576 "chips": ["gfx6"], 3577 "map": {"at": 36656, "to": "mm"}, 3578 "name": "SQ_IMG_SAMP_WORD0", 3579 "type_ref": "SQ_IMG_SAMP_WORD0" 3580 }, 3581 { 3582 "chips": ["gfx6"], 3583 "map": {"at": 36660, "to": "mm"}, 3584 "name": "SQ_IMG_SAMP_WORD1", 3585 "type_ref": "SQ_IMG_SAMP_WORD1" 3586 }, 3587 { 3588 "chips": ["gfx6"], 3589 "map": {"at": 36664, "to": "mm"}, 3590 "name": "SQ_IMG_SAMP_WORD2", 3591 "type_ref": "SQ_IMG_SAMP_WORD2" 3592 }, 3593 { 3594 "chips": ["gfx6"], 3595 "map": {"at": 36668, "to": "mm"}, 3596 "name": "SQ_IMG_SAMP_WORD3", 3597 "type_ref": "SQ_IMG_SAMP_WORD3" 3598 }, 3599 { 3600 "chips": ["gfx6"], 3601 "map": {"at": 37120, "to": "mm"}, 3602 "name": "SPI_CONFIG_CNTL", 3603 "type_ref": "SPI_CONFIG_CNTL" 3604 }, 3605 { 3606 "chips": ["gfx6"], 3607 "map": {"at": 38156, "to": "mm"}, 3608 "name": "TA_CS_BC_BASE_ADDR" 3609 }, 3610 { 3611 "chips": ["gfx6"], 3612 "map": {"at": 39160, "to": "mm"}, 3613 "name": "GB_ADDR_CONFIG", 3614 "type_ref": "GB_ADDR_CONFIG" 3615 }, 3616 { 3617 "chips": ["gfx6"], 3618 "map": {"at": 39184, "to": "mm"}, 3619 "name": "GB_TILE_MODE0", 3620 "type_ref": "GB_TILE_MODE0" 3621 }, 3622 { 3623 "chips": ["gfx6"], 3624 "map": {"at": 39188, "to": "mm"}, 3625 "name": "GB_TILE_MODE1", 3626 "type_ref": "GB_TILE_MODE10" 3627 }, 3628 { 3629 "chips": ["gfx6"], 3630 "map": {"at": 39192, "to": "mm"}, 3631 "name": "GB_TILE_MODE2", 3632 "type_ref": "GB_TILE_MODE10" 3633 }, 3634 { 3635 "chips": ["gfx6"], 3636 "map": {"at": 39196, "to": "mm"}, 3637 "name": "GB_TILE_MODE3", 3638 "type_ref": "GB_TILE_MODE10" 3639 }, 3640 { 3641 "chips": ["gfx6"], 3642 "map": {"at": 39200, "to": "mm"}, 3643 "name": "GB_TILE_MODE4", 3644 "type_ref": "GB_TILE_MODE10" 3645 }, 3646 { 3647 "chips": ["gfx6"], 3648 "map": {"at": 39204, "to": "mm"}, 3649 "name": "GB_TILE_MODE5", 3650 "type_ref": "GB_TILE_MODE10" 3651 }, 3652 { 3653 "chips": ["gfx6"], 3654 "map": {"at": 39208, "to": "mm"}, 3655 "name": "GB_TILE_MODE6", 3656 "type_ref": "GB_TILE_MODE10" 3657 }, 3658 { 3659 "chips": ["gfx6"], 3660 "map": {"at": 39212, "to": "mm"}, 3661 "name": "GB_TILE_MODE7", 3662 "type_ref": "GB_TILE_MODE10" 3663 }, 3664 { 3665 "chips": ["gfx6"], 3666 "map": {"at": 39216, "to": "mm"}, 3667 "name": "GB_TILE_MODE8", 3668 "type_ref": "GB_TILE_MODE10" 3669 }, 3670 { 3671 "chips": ["gfx6"], 3672 "map": {"at": 39220, "to": "mm"}, 3673 "name": "GB_TILE_MODE9", 3674 "type_ref": "GB_TILE_MODE10" 3675 }, 3676 { 3677 "chips": ["gfx6"], 3678 "map": {"at": 39224, "to": "mm"}, 3679 "name": "GB_TILE_MODE10", 3680 "type_ref": "GB_TILE_MODE10" 3681 }, 3682 { 3683 "chips": ["gfx6"], 3684 "map": {"at": 39228, "to": "mm"}, 3685 "name": "GB_TILE_MODE11", 3686 "type_ref": "GB_TILE_MODE10" 3687 }, 3688 { 3689 "chips": ["gfx6"], 3690 "map": {"at": 39232, "to": "mm"}, 3691 "name": "GB_TILE_MODE12", 3692 "type_ref": "GB_TILE_MODE10" 3693 }, 3694 { 3695 "chips": ["gfx6"], 3696 "map": {"at": 39236, "to": "mm"}, 3697 "name": "GB_TILE_MODE13", 3698 "type_ref": "GB_TILE_MODE10" 3699 }, 3700 { 3701 "chips": ["gfx6"], 3702 "map": {"at": 39240, "to": "mm"}, 3703 "name": "GB_TILE_MODE14", 3704 "type_ref": "GB_TILE_MODE10" 3705 }, 3706 { 3707 "chips": ["gfx6"], 3708 "map": {"at": 39244, "to": "mm"}, 3709 "name": "GB_TILE_MODE15", 3710 "type_ref": "GB_TILE_MODE10" 3711 }, 3712 { 3713 "chips": ["gfx6"], 3714 "map": {"at": 39248, "to": "mm"}, 3715 "name": "GB_TILE_MODE16", 3716 "type_ref": "GB_TILE_MODE10" 3717 }, 3718 { 3719 "chips": ["gfx6"], 3720 "map": {"at": 39252, "to": "mm"}, 3721 "name": "GB_TILE_MODE17", 3722 "type_ref": "GB_TILE_MODE10" 3723 }, 3724 { 3725 "chips": ["gfx6"], 3726 "map": {"at": 39256, "to": "mm"}, 3727 "name": "GB_TILE_MODE18", 3728 "type_ref": "GB_TILE_MODE10" 3729 }, 3730 { 3731 "chips": ["gfx6"], 3732 "map": {"at": 39260, "to": "mm"}, 3733 "name": "GB_TILE_MODE19", 3734 "type_ref": "GB_TILE_MODE10" 3735 }, 3736 { 3737 "chips": ["gfx6"], 3738 "map": {"at": 39264, "to": "mm"}, 3739 "name": "GB_TILE_MODE20", 3740 "type_ref": "GB_TILE_MODE10" 3741 }, 3742 { 3743 "chips": ["gfx6"], 3744 "map": {"at": 39268, "to": "mm"}, 3745 "name": "GB_TILE_MODE21", 3746 "type_ref": "GB_TILE_MODE10" 3747 }, 3748 { 3749 "chips": ["gfx6"], 3750 "map": {"at": 39272, "to": "mm"}, 3751 "name": "GB_TILE_MODE22", 3752 "type_ref": "GB_TILE_MODE10" 3753 }, 3754 { 3755 "chips": ["gfx6"], 3756 "map": {"at": 39276, "to": "mm"}, 3757 "name": "GB_TILE_MODE23", 3758 "type_ref": "GB_TILE_MODE10" 3759 }, 3760 { 3761 "chips": ["gfx6"], 3762 "map": {"at": 39280, "to": "mm"}, 3763 "name": "GB_TILE_MODE24", 3764 "type_ref": "GB_TILE_MODE10" 3765 }, 3766 { 3767 "chips": ["gfx6"], 3768 "map": {"at": 39284, "to": "mm"}, 3769 "name": "GB_TILE_MODE25", 3770 "type_ref": "GB_TILE_MODE10" 3771 }, 3772 { 3773 "chips": ["gfx6"], 3774 "map": {"at": 39288, "to": "mm"}, 3775 "name": "GB_TILE_MODE26", 3776 "type_ref": "GB_TILE_MODE10" 3777 }, 3778 { 3779 "chips": ["gfx6"], 3780 "map": {"at": 39292, "to": "mm"}, 3781 "name": "GB_TILE_MODE27", 3782 "type_ref": "GB_TILE_MODE10" 3783 }, 3784 { 3785 "chips": ["gfx6"], 3786 "map": {"at": 39296, "to": "mm"}, 3787 "name": "GB_TILE_MODE28", 3788 "type_ref": "GB_TILE_MODE10" 3789 }, 3790 { 3791 "chips": ["gfx6"], 3792 "map": {"at": 39300, "to": "mm"}, 3793 "name": "GB_TILE_MODE29", 3794 "type_ref": "GB_TILE_MODE10" 3795 }, 3796 { 3797 "chips": ["gfx6"], 3798 "map": {"at": 39304, "to": "mm"}, 3799 "name": "GB_TILE_MODE30", 3800 "type_ref": "GB_TILE_MODE10" 3801 }, 3802 { 3803 "chips": ["gfx6"], 3804 "map": {"at": 39308, "to": "mm"}, 3805 "name": "GB_TILE_MODE31", 3806 "type_ref": "GB_TILE_MODE10" 3807 }, 3808 { 3809 "chips": ["gfx6"], 3810 "map": {"at": 45056, "to": "mm"}, 3811 "name": "SPI_SHADER_TBA_LO_PS" 3812 }, 3813 { 3814 "chips": ["gfx6"], 3815 "map": {"at": 45060, "to": "mm"}, 3816 "name": "SPI_SHADER_TBA_HI_PS", 3817 "type_ref": "SPI_SHADER_PGM_HI_ES" 3818 }, 3819 { 3820 "chips": ["gfx6"], 3821 "map": {"at": 45064, "to": "mm"}, 3822 "name": "SPI_SHADER_TMA_LO_PS" 3823 }, 3824 { 3825 "chips": ["gfx6"], 3826 "map": {"at": 45068, "to": "mm"}, 3827 "name": "SPI_SHADER_TMA_HI_PS", 3828 "type_ref": "SPI_SHADER_PGM_HI_ES" 3829 }, 3830 { 3831 "chips": ["gfx6"], 3832 "map": {"at": 45088, "to": "mm"}, 3833 "name": "SPI_SHADER_PGM_LO_PS" 3834 }, 3835 { 3836 "chips": ["gfx6"], 3837 "map": {"at": 45092, "to": "mm"}, 3838 "name": "SPI_SHADER_PGM_HI_PS", 3839 "type_ref": "SPI_SHADER_PGM_HI_ES" 3840 }, 3841 { 3842 "chips": ["gfx6"], 3843 "map": {"at": 45096, "to": "mm"}, 3844 "name": "SPI_SHADER_PGM_RSRC1_PS", 3845 "type_ref": "SPI_SHADER_PGM_RSRC1_PS" 3846 }, 3847 { 3848 "chips": ["gfx6"], 3849 "map": {"at": 45100, "to": "mm"}, 3850 "name": "SPI_SHADER_PGM_RSRC2_PS", 3851 "type_ref": "SPI_SHADER_PGM_RSRC2_PS" 3852 }, 3853 { 3854 "chips": ["gfx6"], 3855 "map": {"at": 45104, "to": "mm"}, 3856 "name": "SPI_SHADER_USER_DATA_PS_0" 3857 }, 3858 { 3859 "chips": ["gfx6"], 3860 "map": {"at": 45108, "to": "mm"}, 3861 "name": "SPI_SHADER_USER_DATA_PS_1" 3862 }, 3863 { 3864 "chips": ["gfx6"], 3865 "map": {"at": 45112, "to": "mm"}, 3866 "name": "SPI_SHADER_USER_DATA_PS_2" 3867 }, 3868 { 3869 "chips": ["gfx6"], 3870 "map": {"at": 45116, "to": "mm"}, 3871 "name": "SPI_SHADER_USER_DATA_PS_3" 3872 }, 3873 { 3874 "chips": ["gfx6"], 3875 "map": {"at": 45120, "to": "mm"}, 3876 "name": "SPI_SHADER_USER_DATA_PS_4" 3877 }, 3878 { 3879 "chips": ["gfx6"], 3880 "map": {"at": 45124, "to": "mm"}, 3881 "name": "SPI_SHADER_USER_DATA_PS_5" 3882 }, 3883 { 3884 "chips": ["gfx6"], 3885 "map": {"at": 45128, "to": "mm"}, 3886 "name": "SPI_SHADER_USER_DATA_PS_6" 3887 }, 3888 { 3889 "chips": ["gfx6"], 3890 "map": {"at": 45132, "to": "mm"}, 3891 "name": "SPI_SHADER_USER_DATA_PS_7" 3892 }, 3893 { 3894 "chips": ["gfx6"], 3895 "map": {"at": 45136, "to": "mm"}, 3896 "name": "SPI_SHADER_USER_DATA_PS_8" 3897 }, 3898 { 3899 "chips": ["gfx6"], 3900 "map": {"at": 45140, "to": "mm"}, 3901 "name": "SPI_SHADER_USER_DATA_PS_9" 3902 }, 3903 { 3904 "chips": ["gfx6"], 3905 "map": {"at": 45144, "to": "mm"}, 3906 "name": "SPI_SHADER_USER_DATA_PS_10" 3907 }, 3908 { 3909 "chips": ["gfx6"], 3910 "map": {"at": 45148, "to": "mm"}, 3911 "name": "SPI_SHADER_USER_DATA_PS_11" 3912 }, 3913 { 3914 "chips": ["gfx6"], 3915 "map": {"at": 45152, "to": "mm"}, 3916 "name": "SPI_SHADER_USER_DATA_PS_12" 3917 }, 3918 { 3919 "chips": ["gfx6"], 3920 "map": {"at": 45156, "to": "mm"}, 3921 "name": "SPI_SHADER_USER_DATA_PS_13" 3922 }, 3923 { 3924 "chips": ["gfx6"], 3925 "map": {"at": 45160, "to": "mm"}, 3926 "name": "SPI_SHADER_USER_DATA_PS_14" 3927 }, 3928 { 3929 "chips": ["gfx6"], 3930 "map": {"at": 45164, "to": "mm"}, 3931 "name": "SPI_SHADER_USER_DATA_PS_15" 3932 }, 3933 { 3934 "chips": ["gfx6"], 3935 "map": {"at": 45312, "to": "mm"}, 3936 "name": "SPI_SHADER_TBA_LO_VS" 3937 }, 3938 { 3939 "chips": ["gfx6"], 3940 "map": {"at": 45316, "to": "mm"}, 3941 "name": "SPI_SHADER_TBA_HI_VS", 3942 "type_ref": "SPI_SHADER_PGM_HI_ES" 3943 }, 3944 { 3945 "chips": ["gfx6"], 3946 "map": {"at": 45320, "to": "mm"}, 3947 "name": "SPI_SHADER_TMA_LO_VS" 3948 }, 3949 { 3950 "chips": ["gfx6"], 3951 "map": {"at": 45324, "to": "mm"}, 3952 "name": "SPI_SHADER_TMA_HI_VS", 3953 "type_ref": "SPI_SHADER_PGM_HI_ES" 3954 }, 3955 { 3956 "chips": ["gfx6"], 3957 "map": {"at": 45344, "to": "mm"}, 3958 "name": "SPI_SHADER_PGM_LO_VS" 3959 }, 3960 { 3961 "chips": ["gfx6"], 3962 "map": {"at": 45348, "to": "mm"}, 3963 "name": "SPI_SHADER_PGM_HI_VS", 3964 "type_ref": "SPI_SHADER_PGM_HI_ES" 3965 }, 3966 { 3967 "chips": ["gfx6"], 3968 "map": {"at": 45352, "to": "mm"}, 3969 "name": "SPI_SHADER_PGM_RSRC1_VS", 3970 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 3971 }, 3972 { 3973 "chips": ["gfx6"], 3974 "map": {"at": 45356, "to": "mm"}, 3975 "name": "SPI_SHADER_PGM_RSRC2_VS", 3976 "type_ref": "SPI_SHADER_PGM_RSRC2_VS" 3977 }, 3978 { 3979 "chips": ["gfx6"], 3980 "map": {"at": 45360, "to": "mm"}, 3981 "name": "SPI_SHADER_USER_DATA_VS_0" 3982 }, 3983 { 3984 "chips": ["gfx6"], 3985 "map": {"at": 45364, "to": "mm"}, 3986 "name": "SPI_SHADER_USER_DATA_VS_1" 3987 }, 3988 { 3989 "chips": ["gfx6"], 3990 "map": {"at": 45368, "to": "mm"}, 3991 "name": "SPI_SHADER_USER_DATA_VS_2" 3992 }, 3993 { 3994 "chips": ["gfx6"], 3995 "map": {"at": 45372, "to": "mm"}, 3996 "name": "SPI_SHADER_USER_DATA_VS_3" 3997 }, 3998 { 3999 "chips": ["gfx6"], 4000 "map": {"at": 45376, "to": "mm"}, 4001 "name": "SPI_SHADER_USER_DATA_VS_4" 4002 }, 4003 { 4004 "chips": ["gfx6"], 4005 "map": {"at": 45380, "to": "mm"}, 4006 "name": "SPI_SHADER_USER_DATA_VS_5" 4007 }, 4008 { 4009 "chips": ["gfx6"], 4010 "map": {"at": 45384, "to": "mm"}, 4011 "name": "SPI_SHADER_USER_DATA_VS_6" 4012 }, 4013 { 4014 "chips": ["gfx6"], 4015 "map": {"at": 45388, "to": "mm"}, 4016 "name": "SPI_SHADER_USER_DATA_VS_7" 4017 }, 4018 { 4019 "chips": ["gfx6"], 4020 "map": {"at": 45392, "to": "mm"}, 4021 "name": "SPI_SHADER_USER_DATA_VS_8" 4022 }, 4023 { 4024 "chips": ["gfx6"], 4025 "map": {"at": 45396, "to": "mm"}, 4026 "name": "SPI_SHADER_USER_DATA_VS_9" 4027 }, 4028 { 4029 "chips": ["gfx6"], 4030 "map": {"at": 45400, "to": "mm"}, 4031 "name": "SPI_SHADER_USER_DATA_VS_10" 4032 }, 4033 { 4034 "chips": ["gfx6"], 4035 "map": {"at": 45404, "to": "mm"}, 4036 "name": "SPI_SHADER_USER_DATA_VS_11" 4037 }, 4038 { 4039 "chips": ["gfx6"], 4040 "map": {"at": 45408, "to": "mm"}, 4041 "name": "SPI_SHADER_USER_DATA_VS_12" 4042 }, 4043 { 4044 "chips": ["gfx6"], 4045 "map": {"at": 45412, "to": "mm"}, 4046 "name": "SPI_SHADER_USER_DATA_VS_13" 4047 }, 4048 { 4049 "chips": ["gfx6"], 4050 "map": {"at": 45416, "to": "mm"}, 4051 "name": "SPI_SHADER_USER_DATA_VS_14" 4052 }, 4053 { 4054 "chips": ["gfx6"], 4055 "map": {"at": 45420, "to": "mm"}, 4056 "name": "SPI_SHADER_USER_DATA_VS_15" 4057 }, 4058 { 4059 "chips": ["gfx6"], 4060 "map": {"at": 45568, "to": "mm"}, 4061 "name": "SPI_SHADER_TBA_LO_GS" 4062 }, 4063 { 4064 "chips": ["gfx6"], 4065 "map": {"at": 45572, "to": "mm"}, 4066 "name": "SPI_SHADER_TBA_HI_GS", 4067 "type_ref": "SPI_SHADER_PGM_HI_ES" 4068 }, 4069 { 4070 "chips": ["gfx6"], 4071 "map": {"at": 45576, "to": "mm"}, 4072 "name": "SPI_SHADER_TMA_LO_GS" 4073 }, 4074 { 4075 "chips": ["gfx6"], 4076 "map": {"at": 45580, "to": "mm"}, 4077 "name": "SPI_SHADER_TMA_HI_GS", 4078 "type_ref": "SPI_SHADER_PGM_HI_ES" 4079 }, 4080 { 4081 "chips": ["gfx6"], 4082 "map": {"at": 45600, "to": "mm"}, 4083 "name": "SPI_SHADER_PGM_LO_GS" 4084 }, 4085 { 4086 "chips": ["gfx6"], 4087 "map": {"at": 45604, "to": "mm"}, 4088 "name": "SPI_SHADER_PGM_HI_GS", 4089 "type_ref": "SPI_SHADER_PGM_HI_ES" 4090 }, 4091 { 4092 "chips": ["gfx6"], 4093 "map": {"at": 45608, "to": "mm"}, 4094 "name": "SPI_SHADER_PGM_RSRC1_GS", 4095 "type_ref": "SPI_SHADER_PGM_RSRC1_GS" 4096 }, 4097 { 4098 "chips": ["gfx6"], 4099 "map": {"at": 45612, "to": "mm"}, 4100 "name": "SPI_SHADER_PGM_RSRC2_GS", 4101 "type_ref": "SPI_SHADER_PGM_RSRC2_GS" 4102 }, 4103 { 4104 "chips": ["gfx6"], 4105 "map": {"at": 45616, "to": "mm"}, 4106 "name": "SPI_SHADER_USER_DATA_GS_0" 4107 }, 4108 { 4109 "chips": ["gfx6"], 4110 "map": {"at": 45620, "to": "mm"}, 4111 "name": "SPI_SHADER_USER_DATA_GS_1" 4112 }, 4113 { 4114 "chips": ["gfx6"], 4115 "map": {"at": 45624, "to": "mm"}, 4116 "name": "SPI_SHADER_USER_DATA_GS_2" 4117 }, 4118 { 4119 "chips": ["gfx6"], 4120 "map": {"at": 45628, "to": "mm"}, 4121 "name": "SPI_SHADER_USER_DATA_GS_3" 4122 }, 4123 { 4124 "chips": ["gfx6"], 4125 "map": {"at": 45632, "to": "mm"}, 4126 "name": "SPI_SHADER_USER_DATA_GS_4" 4127 }, 4128 { 4129 "chips": ["gfx6"], 4130 "map": {"at": 45636, "to": "mm"}, 4131 "name": "SPI_SHADER_USER_DATA_GS_5" 4132 }, 4133 { 4134 "chips": ["gfx6"], 4135 "map": {"at": 45640, "to": "mm"}, 4136 "name": "SPI_SHADER_USER_DATA_GS_6" 4137 }, 4138 { 4139 "chips": ["gfx6"], 4140 "map": {"at": 45644, "to": "mm"}, 4141 "name": "SPI_SHADER_USER_DATA_GS_7" 4142 }, 4143 { 4144 "chips": ["gfx6"], 4145 "map": {"at": 45648, "to": "mm"}, 4146 "name": "SPI_SHADER_USER_DATA_GS_8" 4147 }, 4148 { 4149 "chips": ["gfx6"], 4150 "map": {"at": 45652, "to": "mm"}, 4151 "name": "SPI_SHADER_USER_DATA_GS_9" 4152 }, 4153 { 4154 "chips": ["gfx6"], 4155 "map": {"at": 45656, "to": "mm"}, 4156 "name": "SPI_SHADER_USER_DATA_GS_10" 4157 }, 4158 { 4159 "chips": ["gfx6"], 4160 "map": {"at": 45660, "to": "mm"}, 4161 "name": "SPI_SHADER_USER_DATA_GS_11" 4162 }, 4163 { 4164 "chips": ["gfx6"], 4165 "map": {"at": 45664, "to": "mm"}, 4166 "name": "SPI_SHADER_USER_DATA_GS_12" 4167 }, 4168 { 4169 "chips": ["gfx6"], 4170 "map": {"at": 45668, "to": "mm"}, 4171 "name": "SPI_SHADER_USER_DATA_GS_13" 4172 }, 4173 { 4174 "chips": ["gfx6"], 4175 "map": {"at": 45672, "to": "mm"}, 4176 "name": "SPI_SHADER_USER_DATA_GS_14" 4177 }, 4178 { 4179 "chips": ["gfx6"], 4180 "map": {"at": 45676, "to": "mm"}, 4181 "name": "SPI_SHADER_USER_DATA_GS_15" 4182 }, 4183 { 4184 "chips": ["gfx6"], 4185 "map": {"at": 45824, "to": "mm"}, 4186 "name": "SPI_SHADER_TBA_LO_ES" 4187 }, 4188 { 4189 "chips": ["gfx6"], 4190 "map": {"at": 45828, "to": "mm"}, 4191 "name": "SPI_SHADER_TBA_HI_ES", 4192 "type_ref": "SPI_SHADER_PGM_HI_ES" 4193 }, 4194 { 4195 "chips": ["gfx6"], 4196 "map": {"at": 45832, "to": "mm"}, 4197 "name": "SPI_SHADER_TMA_LO_ES" 4198 }, 4199 { 4200 "chips": ["gfx6"], 4201 "map": {"at": 45836, "to": "mm"}, 4202 "name": "SPI_SHADER_TMA_HI_ES", 4203 "type_ref": "SPI_SHADER_PGM_HI_ES" 4204 }, 4205 { 4206 "chips": ["gfx6"], 4207 "map": {"at": 45856, "to": "mm"}, 4208 "name": "SPI_SHADER_PGM_LO_ES" 4209 }, 4210 { 4211 "chips": ["gfx6"], 4212 "map": {"at": 45860, "to": "mm"}, 4213 "name": "SPI_SHADER_PGM_HI_ES", 4214 "type_ref": "SPI_SHADER_PGM_HI_ES" 4215 }, 4216 { 4217 "chips": ["gfx6"], 4218 "map": {"at": 45864, "to": "mm"}, 4219 "name": "SPI_SHADER_PGM_RSRC1_ES", 4220 "type_ref": "SPI_SHADER_PGM_RSRC1_ES" 4221 }, 4222 { 4223 "chips": ["gfx6"], 4224 "map": {"at": 45868, "to": "mm"}, 4225 "name": "SPI_SHADER_PGM_RSRC2_ES", 4226 "type_ref": "SPI_SHADER_PGM_RSRC2_ES" 4227 }, 4228 { 4229 "chips": ["gfx6"], 4230 "map": {"at": 45872, "to": "mm"}, 4231 "name": "SPI_SHADER_USER_DATA_ES_0" 4232 }, 4233 { 4234 "chips": ["gfx6"], 4235 "map": {"at": 45876, "to": "mm"}, 4236 "name": "SPI_SHADER_USER_DATA_ES_1" 4237 }, 4238 { 4239 "chips": ["gfx6"], 4240 "map": {"at": 45880, "to": "mm"}, 4241 "name": "SPI_SHADER_USER_DATA_ES_2" 4242 }, 4243 { 4244 "chips": ["gfx6"], 4245 "map": {"at": 45884, "to": "mm"}, 4246 "name": "SPI_SHADER_USER_DATA_ES_3" 4247 }, 4248 { 4249 "chips": ["gfx6"], 4250 "map": {"at": 45888, "to": "mm"}, 4251 "name": "SPI_SHADER_USER_DATA_ES_4" 4252 }, 4253 { 4254 "chips": ["gfx6"], 4255 "map": {"at": 45892, "to": "mm"}, 4256 "name": "SPI_SHADER_USER_DATA_ES_5" 4257 }, 4258 { 4259 "chips": ["gfx6"], 4260 "map": {"at": 45896, "to": "mm"}, 4261 "name": "SPI_SHADER_USER_DATA_ES_6" 4262 }, 4263 { 4264 "chips": ["gfx6"], 4265 "map": {"at": 45900, "to": "mm"}, 4266 "name": "SPI_SHADER_USER_DATA_ES_7" 4267 }, 4268 { 4269 "chips": ["gfx6"], 4270 "map": {"at": 45904, "to": "mm"}, 4271 "name": "SPI_SHADER_USER_DATA_ES_8" 4272 }, 4273 { 4274 "chips": ["gfx6"], 4275 "map": {"at": 45908, "to": "mm"}, 4276 "name": "SPI_SHADER_USER_DATA_ES_9" 4277 }, 4278 { 4279 "chips": ["gfx6"], 4280 "map": {"at": 45912, "to": "mm"}, 4281 "name": "SPI_SHADER_USER_DATA_ES_10" 4282 }, 4283 { 4284 "chips": ["gfx6"], 4285 "map": {"at": 45916, "to": "mm"}, 4286 "name": "SPI_SHADER_USER_DATA_ES_11" 4287 }, 4288 { 4289 "chips": ["gfx6"], 4290 "map": {"at": 45920, "to": "mm"}, 4291 "name": "SPI_SHADER_USER_DATA_ES_12" 4292 }, 4293 { 4294 "chips": ["gfx6"], 4295 "map": {"at": 45924, "to": "mm"}, 4296 "name": "SPI_SHADER_USER_DATA_ES_13" 4297 }, 4298 { 4299 "chips": ["gfx6"], 4300 "map": {"at": 45928, "to": "mm"}, 4301 "name": "SPI_SHADER_USER_DATA_ES_14" 4302 }, 4303 { 4304 "chips": ["gfx6"], 4305 "map": {"at": 45932, "to": "mm"}, 4306 "name": "SPI_SHADER_USER_DATA_ES_15" 4307 }, 4308 { 4309 "chips": ["gfx6"], 4310 "map": {"at": 46080, "to": "mm"}, 4311 "name": "SPI_SHADER_TBA_LO_HS" 4312 }, 4313 { 4314 "chips": ["gfx6"], 4315 "map": {"at": 46084, "to": "mm"}, 4316 "name": "SPI_SHADER_TBA_HI_HS", 4317 "type_ref": "SPI_SHADER_PGM_HI_ES" 4318 }, 4319 { 4320 "chips": ["gfx6"], 4321 "map": {"at": 46088, "to": "mm"}, 4322 "name": "SPI_SHADER_TMA_LO_HS" 4323 }, 4324 { 4325 "chips": ["gfx6"], 4326 "map": {"at": 46092, "to": "mm"}, 4327 "name": "SPI_SHADER_TMA_HI_HS", 4328 "type_ref": "SPI_SHADER_PGM_HI_ES" 4329 }, 4330 { 4331 "chips": ["gfx6"], 4332 "map": {"at": 46112, "to": "mm"}, 4333 "name": "SPI_SHADER_PGM_LO_HS" 4334 }, 4335 { 4336 "chips": ["gfx6"], 4337 "map": {"at": 46116, "to": "mm"}, 4338 "name": "SPI_SHADER_PGM_HI_HS", 4339 "type_ref": "SPI_SHADER_PGM_HI_ES" 4340 }, 4341 { 4342 "chips": ["gfx6"], 4343 "map": {"at": 46120, "to": "mm"}, 4344 "name": "SPI_SHADER_PGM_RSRC1_HS", 4345 "type_ref": "SPI_SHADER_PGM_RSRC1_HS" 4346 }, 4347 { 4348 "chips": ["gfx6"], 4349 "map": {"at": 46124, "to": "mm"}, 4350 "name": "SPI_SHADER_PGM_RSRC2_HS", 4351 "type_ref": "SPI_SHADER_PGM_RSRC2_HS" 4352 }, 4353 { 4354 "chips": ["gfx6"], 4355 "map": {"at": 46128, "to": "mm"}, 4356 "name": "SPI_SHADER_USER_DATA_HS_0" 4357 }, 4358 { 4359 "chips": ["gfx6"], 4360 "map": {"at": 46132, "to": "mm"}, 4361 "name": "SPI_SHADER_USER_DATA_HS_1" 4362 }, 4363 { 4364 "chips": ["gfx6"], 4365 "map": {"at": 46136, "to": "mm"}, 4366 "name": "SPI_SHADER_USER_DATA_HS_2" 4367 }, 4368 { 4369 "chips": ["gfx6"], 4370 "map": {"at": 46140, "to": "mm"}, 4371 "name": "SPI_SHADER_USER_DATA_HS_3" 4372 }, 4373 { 4374 "chips": ["gfx6"], 4375 "map": {"at": 46144, "to": "mm"}, 4376 "name": "SPI_SHADER_USER_DATA_HS_4" 4377 }, 4378 { 4379 "chips": ["gfx6"], 4380 "map": {"at": 46148, "to": "mm"}, 4381 "name": "SPI_SHADER_USER_DATA_HS_5" 4382 }, 4383 { 4384 "chips": ["gfx6"], 4385 "map": {"at": 46152, "to": "mm"}, 4386 "name": "SPI_SHADER_USER_DATA_HS_6" 4387 }, 4388 { 4389 "chips": ["gfx6"], 4390 "map": {"at": 46156, "to": "mm"}, 4391 "name": "SPI_SHADER_USER_DATA_HS_7" 4392 }, 4393 { 4394 "chips": ["gfx6"], 4395 "map": {"at": 46160, "to": "mm"}, 4396 "name": "SPI_SHADER_USER_DATA_HS_8" 4397 }, 4398 { 4399 "chips": ["gfx6"], 4400 "map": {"at": 46164, "to": "mm"}, 4401 "name": "SPI_SHADER_USER_DATA_HS_9" 4402 }, 4403 { 4404 "chips": ["gfx6"], 4405 "map": {"at": 46168, "to": "mm"}, 4406 "name": "SPI_SHADER_USER_DATA_HS_10" 4407 }, 4408 { 4409 "chips": ["gfx6"], 4410 "map": {"at": 46172, "to": "mm"}, 4411 "name": "SPI_SHADER_USER_DATA_HS_11" 4412 }, 4413 { 4414 "chips": ["gfx6"], 4415 "map": {"at": 46176, "to": "mm"}, 4416 "name": "SPI_SHADER_USER_DATA_HS_12" 4417 }, 4418 { 4419 "chips": ["gfx6"], 4420 "map": {"at": 46180, "to": "mm"}, 4421 "name": "SPI_SHADER_USER_DATA_HS_13" 4422 }, 4423 { 4424 "chips": ["gfx6"], 4425 "map": {"at": 46184, "to": "mm"}, 4426 "name": "SPI_SHADER_USER_DATA_HS_14" 4427 }, 4428 { 4429 "chips": ["gfx6"], 4430 "map": {"at": 46188, "to": "mm"}, 4431 "name": "SPI_SHADER_USER_DATA_HS_15" 4432 }, 4433 { 4434 "chips": ["gfx6"], 4435 "map": {"at": 46336, "to": "mm"}, 4436 "name": "SPI_SHADER_TBA_LO_LS" 4437 }, 4438 { 4439 "chips": ["gfx6"], 4440 "map": {"at": 46340, "to": "mm"}, 4441 "name": "SPI_SHADER_TBA_HI_LS", 4442 "type_ref": "SPI_SHADER_PGM_HI_ES" 4443 }, 4444 { 4445 "chips": ["gfx6"], 4446 "map": {"at": 46344, "to": "mm"}, 4447 "name": "SPI_SHADER_TMA_LO_LS" 4448 }, 4449 { 4450 "chips": ["gfx6"], 4451 "map": {"at": 46348, "to": "mm"}, 4452 "name": "SPI_SHADER_TMA_HI_LS", 4453 "type_ref": "SPI_SHADER_PGM_HI_ES" 4454 }, 4455 { 4456 "chips": ["gfx6"], 4457 "map": {"at": 46368, "to": "mm"}, 4458 "name": "SPI_SHADER_PGM_LO_LS" 4459 }, 4460 { 4461 "chips": ["gfx6"], 4462 "map": {"at": 46372, "to": "mm"}, 4463 "name": "SPI_SHADER_PGM_HI_LS", 4464 "type_ref": "SPI_SHADER_PGM_HI_ES" 4465 }, 4466 { 4467 "chips": ["gfx6"], 4468 "map": {"at": 46376, "to": "mm"}, 4469 "name": "SPI_SHADER_PGM_RSRC1_LS", 4470 "type_ref": "SPI_SHADER_PGM_RSRC1_LS" 4471 }, 4472 { 4473 "chips": ["gfx6"], 4474 "map": {"at": 46380, "to": "mm"}, 4475 "name": "SPI_SHADER_PGM_RSRC2_LS", 4476 "type_ref": "SPI_SHADER_PGM_RSRC2_LS" 4477 }, 4478 { 4479 "chips": ["gfx6"], 4480 "map": {"at": 46384, "to": "mm"}, 4481 "name": "SPI_SHADER_USER_DATA_LS_0" 4482 }, 4483 { 4484 "chips": ["gfx6"], 4485 "map": {"at": 46388, "to": "mm"}, 4486 "name": "SPI_SHADER_USER_DATA_LS_1" 4487 }, 4488 { 4489 "chips": ["gfx6"], 4490 "map": {"at": 46392, "to": "mm"}, 4491 "name": "SPI_SHADER_USER_DATA_LS_2" 4492 }, 4493 { 4494 "chips": ["gfx6"], 4495 "map": {"at": 46396, "to": "mm"}, 4496 "name": "SPI_SHADER_USER_DATA_LS_3" 4497 }, 4498 { 4499 "chips": ["gfx6"], 4500 "map": {"at": 46400, "to": "mm"}, 4501 "name": "SPI_SHADER_USER_DATA_LS_4" 4502 }, 4503 { 4504 "chips": ["gfx6"], 4505 "map": {"at": 46404, "to": "mm"}, 4506 "name": "SPI_SHADER_USER_DATA_LS_5" 4507 }, 4508 { 4509 "chips": ["gfx6"], 4510 "map": {"at": 46408, "to": "mm"}, 4511 "name": "SPI_SHADER_USER_DATA_LS_6" 4512 }, 4513 { 4514 "chips": ["gfx6"], 4515 "map": {"at": 46412, "to": "mm"}, 4516 "name": "SPI_SHADER_USER_DATA_LS_7" 4517 }, 4518 { 4519 "chips": ["gfx6"], 4520 "map": {"at": 46416, "to": "mm"}, 4521 "name": "SPI_SHADER_USER_DATA_LS_8" 4522 }, 4523 { 4524 "chips": ["gfx6"], 4525 "map": {"at": 46420, "to": "mm"}, 4526 "name": "SPI_SHADER_USER_DATA_LS_9" 4527 }, 4528 { 4529 "chips": ["gfx6"], 4530 "map": {"at": 46424, "to": "mm"}, 4531 "name": "SPI_SHADER_USER_DATA_LS_10" 4532 }, 4533 { 4534 "chips": ["gfx6"], 4535 "map": {"at": 46428, "to": "mm"}, 4536 "name": "SPI_SHADER_USER_DATA_LS_11" 4537 }, 4538 { 4539 "chips": ["gfx6"], 4540 "map": {"at": 46432, "to": "mm"}, 4541 "name": "SPI_SHADER_USER_DATA_LS_12" 4542 }, 4543 { 4544 "chips": ["gfx6"], 4545 "map": {"at": 46436, "to": "mm"}, 4546 "name": "SPI_SHADER_USER_DATA_LS_13" 4547 }, 4548 { 4549 "chips": ["gfx6"], 4550 "map": {"at": 46440, "to": "mm"}, 4551 "name": "SPI_SHADER_USER_DATA_LS_14" 4552 }, 4553 { 4554 "chips": ["gfx6"], 4555 "map": {"at": 46444, "to": "mm"}, 4556 "name": "SPI_SHADER_USER_DATA_LS_15" 4557 }, 4558 { 4559 "chips": ["gfx6"], 4560 "map": {"at": 47104, "to": "mm"}, 4561 "name": "COMPUTE_DISPATCH_INITIATOR", 4562 "type_ref": "COMPUTE_DISPATCH_INITIATOR" 4563 }, 4564 { 4565 "chips": ["gfx6"], 4566 "map": {"at": 47108, "to": "mm"}, 4567 "name": "COMPUTE_DIM_X" 4568 }, 4569 { 4570 "chips": ["gfx6"], 4571 "map": {"at": 47112, "to": "mm"}, 4572 "name": "COMPUTE_DIM_Y" 4573 }, 4574 { 4575 "chips": ["gfx6"], 4576 "map": {"at": 47116, "to": "mm"}, 4577 "name": "COMPUTE_DIM_Z" 4578 }, 4579 { 4580 "chips": ["gfx6"], 4581 "map": {"at": 47120, "to": "mm"}, 4582 "name": "COMPUTE_START_X" 4583 }, 4584 { 4585 "chips": ["gfx6"], 4586 "map": {"at": 47124, "to": "mm"}, 4587 "name": "COMPUTE_START_Y" 4588 }, 4589 { 4590 "chips": ["gfx6"], 4591 "map": {"at": 47128, "to": "mm"}, 4592 "name": "COMPUTE_START_Z" 4593 }, 4594 { 4595 "chips": ["gfx6"], 4596 "map": {"at": 47132, "to": "mm"}, 4597 "name": "COMPUTE_NUM_THREAD_X", 4598 "type_ref": "COMPUTE_NUM_THREAD_X" 4599 }, 4600 { 4601 "chips": ["gfx6"], 4602 "map": {"at": 47136, "to": "mm"}, 4603 "name": "COMPUTE_NUM_THREAD_Y", 4604 "type_ref": "COMPUTE_NUM_THREAD_X" 4605 }, 4606 { 4607 "chips": ["gfx6"], 4608 "map": {"at": 47140, "to": "mm"}, 4609 "name": "COMPUTE_NUM_THREAD_Z", 4610 "type_ref": "COMPUTE_NUM_THREAD_X" 4611 }, 4612 { 4613 "chips": ["gfx6"], 4614 "map": {"at": 47152, "to": "mm"}, 4615 "name": "COMPUTE_PGM_LO" 4616 }, 4617 { 4618 "chips": ["gfx6"], 4619 "map": {"at": 47156, "to": "mm"}, 4620 "name": "COMPUTE_PGM_HI", 4621 "type_ref": "COMPUTE_PGM_HI" 4622 }, 4623 { 4624 "chips": ["gfx6"], 4625 "map": {"at": 47160, "to": "mm"}, 4626 "name": "COMPUTE_TBA_LO" 4627 }, 4628 { 4629 "chips": ["gfx6"], 4630 "map": {"at": 47164, "to": "mm"}, 4631 "name": "COMPUTE_TBA_HI", 4632 "type_ref": "COMPUTE_TBA_HI" 4633 }, 4634 { 4635 "chips": ["gfx6"], 4636 "map": {"at": 47168, "to": "mm"}, 4637 "name": "COMPUTE_TMA_LO" 4638 }, 4639 { 4640 "chips": ["gfx6"], 4641 "map": {"at": 47172, "to": "mm"}, 4642 "name": "COMPUTE_TMA_HI", 4643 "type_ref": "COMPUTE_TBA_HI" 4644 }, 4645 { 4646 "chips": ["gfx6"], 4647 "map": {"at": 47176, "to": "mm"}, 4648 "name": "COMPUTE_PGM_RSRC1", 4649 "type_ref": "COMPUTE_PGM_RSRC1" 4650 }, 4651 { 4652 "chips": ["gfx6"], 4653 "map": {"at": 47180, "to": "mm"}, 4654 "name": "COMPUTE_PGM_RSRC2", 4655 "type_ref": "COMPUTE_PGM_RSRC2" 4656 }, 4657 { 4658 "chips": ["gfx6"], 4659 "map": {"at": 47184, "to": "mm"}, 4660 "name": "COMPUTE_VMID", 4661 "type_ref": "COMPUTE_VMID" 4662 }, 4663 { 4664 "chips": ["gfx6"], 4665 "map": {"at": 47188, "to": "mm"}, 4666 "name": "COMPUTE_RESOURCE_LIMITS", 4667 "type_ref": "COMPUTE_RESOURCE_LIMITS" 4668 }, 4669 { 4670 "chips": ["gfx6"], 4671 "map": {"at": 47192, "to": "mm"}, 4672 "name": "COMPUTE_STATIC_THREAD_MGMT_SE0", 4673 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 4674 }, 4675 { 4676 "chips": ["gfx6"], 4677 "map": {"at": 47196, "to": "mm"}, 4678 "name": "COMPUTE_STATIC_THREAD_MGMT_SE1", 4679 "type_ref": "COMPUTE_STATIC_THREAD_MGMT_SE0" 4680 }, 4681 { 4682 "chips": ["gfx6"], 4683 "map": {"at": 47200, "to": "mm"}, 4684 "name": "COMPUTE_TMPRING_SIZE", 4685 "type_ref": "COMPUTE_TMPRING_SIZE" 4686 }, 4687 { 4688 "chips": ["gfx6"], 4689 "map": {"at": 47360, "to": "mm"}, 4690 "name": "COMPUTE_USER_DATA_0" 4691 }, 4692 { 4693 "chips": ["gfx6"], 4694 "map": {"at": 47364, "to": "mm"}, 4695 "name": "COMPUTE_USER_DATA_1" 4696 }, 4697 { 4698 "chips": ["gfx6"], 4699 "map": {"at": 47368, "to": "mm"}, 4700 "name": "COMPUTE_USER_DATA_2" 4701 }, 4702 { 4703 "chips": ["gfx6"], 4704 "map": {"at": 47372, "to": "mm"}, 4705 "name": "COMPUTE_USER_DATA_3" 4706 }, 4707 { 4708 "chips": ["gfx6"], 4709 "map": {"at": 47376, "to": "mm"}, 4710 "name": "COMPUTE_USER_DATA_4" 4711 }, 4712 { 4713 "chips": ["gfx6"], 4714 "map": {"at": 47380, "to": "mm"}, 4715 "name": "COMPUTE_USER_DATA_5" 4716 }, 4717 { 4718 "chips": ["gfx6"], 4719 "map": {"at": 47384, "to": "mm"}, 4720 "name": "COMPUTE_USER_DATA_6" 4721 }, 4722 { 4723 "chips": ["gfx6"], 4724 "map": {"at": 47388, "to": "mm"}, 4725 "name": "COMPUTE_USER_DATA_7" 4726 }, 4727 { 4728 "chips": ["gfx6"], 4729 "map": {"at": 47392, "to": "mm"}, 4730 "name": "COMPUTE_USER_DATA_8" 4731 }, 4732 { 4733 "chips": ["gfx6"], 4734 "map": {"at": 47396, "to": "mm"}, 4735 "name": "COMPUTE_USER_DATA_9" 4736 }, 4737 { 4738 "chips": ["gfx6"], 4739 "map": {"at": 47400, "to": "mm"}, 4740 "name": "COMPUTE_USER_DATA_10" 4741 }, 4742 { 4743 "chips": ["gfx6"], 4744 "map": {"at": 47404, "to": "mm"}, 4745 "name": "COMPUTE_USER_DATA_11" 4746 }, 4747 { 4748 "chips": ["gfx6"], 4749 "map": {"at": 47408, "to": "mm"}, 4750 "name": "COMPUTE_USER_DATA_12" 4751 }, 4752 { 4753 "chips": ["gfx6"], 4754 "map": {"at": 47412, "to": "mm"}, 4755 "name": "COMPUTE_USER_DATA_13" 4756 }, 4757 { 4758 "chips": ["gfx6"], 4759 "map": {"at": 47416, "to": "mm"}, 4760 "name": "COMPUTE_USER_DATA_14" 4761 }, 4762 { 4763 "chips": ["gfx6"], 4764 "map": {"at": 47420, "to": "mm"}, 4765 "name": "COMPUTE_USER_DATA_15" 4766 }, 4767 { 4768 "chips": ["gfx6"], 4769 "map": {"at": 163840, "to": "mm"}, 4770 "name": "DB_RENDER_CONTROL", 4771 "type_ref": "DB_RENDER_CONTROL" 4772 }, 4773 { 4774 "chips": ["gfx6"], 4775 "map": {"at": 163844, "to": "mm"}, 4776 "name": "DB_COUNT_CONTROL", 4777 "type_ref": "DB_COUNT_CONTROL" 4778 }, 4779 { 4780 "chips": ["gfx6"], 4781 "map": {"at": 163848, "to": "mm"}, 4782 "name": "DB_DEPTH_VIEW", 4783 "type_ref": "DB_DEPTH_VIEW" 4784 }, 4785 { 4786 "chips": ["gfx6"], 4787 "map": {"at": 163852, "to": "mm"}, 4788 "name": "DB_RENDER_OVERRIDE", 4789 "type_ref": "DB_RENDER_OVERRIDE" 4790 }, 4791 { 4792 "chips": ["gfx6"], 4793 "map": {"at": 163856, "to": "mm"}, 4794 "name": "DB_RENDER_OVERRIDE2", 4795 "type_ref": "DB_RENDER_OVERRIDE2" 4796 }, 4797 { 4798 "chips": ["gfx6"], 4799 "map": {"at": 163860, "to": "mm"}, 4800 "name": "DB_HTILE_DATA_BASE" 4801 }, 4802 { 4803 "chips": ["gfx6"], 4804 "map": {"at": 163872, "to": "mm"}, 4805 "name": "DB_DEPTH_BOUNDS_MIN" 4806 }, 4807 { 4808 "chips": ["gfx6"], 4809 "map": {"at": 163876, "to": "mm"}, 4810 "name": "DB_DEPTH_BOUNDS_MAX" 4811 }, 4812 { 4813 "chips": ["gfx6"], 4814 "map": {"at": 163880, "to": "mm"}, 4815 "name": "DB_STENCIL_CLEAR", 4816 "type_ref": "DB_STENCIL_CLEAR" 4817 }, 4818 { 4819 "chips": ["gfx6"], 4820 "map": {"at": 163884, "to": "mm"}, 4821 "name": "DB_DEPTH_CLEAR" 4822 }, 4823 { 4824 "chips": ["gfx6"], 4825 "map": {"at": 163888, "to": "mm"}, 4826 "name": "PA_SC_SCREEN_SCISSOR_TL", 4827 "type_ref": "PA_SC_SCREEN_SCISSOR_TL" 4828 }, 4829 { 4830 "chips": ["gfx6"], 4831 "map": {"at": 163892, "to": "mm"}, 4832 "name": "PA_SC_SCREEN_SCISSOR_BR", 4833 "type_ref": "PA_SC_SCREEN_SCISSOR_BR" 4834 }, 4835 { 4836 "chips": ["gfx6"], 4837 "map": {"at": 163900, "to": "mm"}, 4838 "name": "DB_DEPTH_INFO", 4839 "type_ref": "DB_DEPTH_INFO" 4840 }, 4841 { 4842 "chips": ["gfx6"], 4843 "map": {"at": 163904, "to": "mm"}, 4844 "name": "DB_Z_INFO", 4845 "type_ref": "DB_Z_INFO" 4846 }, 4847 { 4848 "chips": ["gfx6"], 4849 "map": {"at": 163908, "to": "mm"}, 4850 "name": "DB_STENCIL_INFO", 4851 "type_ref": "DB_STENCIL_INFO" 4852 }, 4853 { 4854 "chips": ["gfx6"], 4855 "map": {"at": 163912, "to": "mm"}, 4856 "name": "DB_Z_READ_BASE" 4857 }, 4858 { 4859 "chips": ["gfx6"], 4860 "map": {"at": 163916, "to": "mm"}, 4861 "name": "DB_STENCIL_READ_BASE" 4862 }, 4863 { 4864 "chips": ["gfx6"], 4865 "map": {"at": 163920, "to": "mm"}, 4866 "name": "DB_Z_WRITE_BASE" 4867 }, 4868 { 4869 "chips": ["gfx6"], 4870 "map": {"at": 163924, "to": "mm"}, 4871 "name": "DB_STENCIL_WRITE_BASE" 4872 }, 4873 { 4874 "chips": ["gfx6"], 4875 "map": {"at": 163928, "to": "mm"}, 4876 "name": "DB_DEPTH_SIZE", 4877 "type_ref": "DB_DEPTH_SIZE" 4878 }, 4879 { 4880 "chips": ["gfx6"], 4881 "map": {"at": 163932, "to": "mm"}, 4882 "name": "DB_DEPTH_SLICE", 4883 "type_ref": "DB_DEPTH_SLICE" 4884 }, 4885 { 4886 "chips": ["gfx6"], 4887 "map": {"at": 163968, "to": "mm"}, 4888 "name": "TA_BC_BASE_ADDR" 4889 }, 4890 { 4891 "chips": ["gfx6"], 4892 "map": {"at": 164344, "to": "mm"}, 4893 "name": "COHER_DEST_BASE_2" 4894 }, 4895 { 4896 "chips": ["gfx6"], 4897 "map": {"at": 164348, "to": "mm"}, 4898 "name": "COHER_DEST_BASE_3" 4899 }, 4900 { 4901 "chips": ["gfx6"], 4902 "map": {"at": 164352, "to": "mm"}, 4903 "name": "PA_SC_WINDOW_OFFSET", 4904 "type_ref": "PA_SC_WINDOW_OFFSET" 4905 }, 4906 { 4907 "chips": ["gfx6"], 4908 "map": {"at": 164356, "to": "mm"}, 4909 "name": "PA_SC_WINDOW_SCISSOR_TL", 4910 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 4911 }, 4912 { 4913 "chips": ["gfx6"], 4914 "map": {"at": 164360, "to": "mm"}, 4915 "name": "PA_SC_WINDOW_SCISSOR_BR", 4916 "type_ref": "PA_SC_CLIPRECT_0_BR" 4917 }, 4918 { 4919 "chips": ["gfx6"], 4920 "map": {"at": 164364, "to": "mm"}, 4921 "name": "PA_SC_CLIPRECT_RULE", 4922 "type_ref": "PA_SC_CLIPRECT_RULE" 4923 }, 4924 { 4925 "chips": ["gfx6"], 4926 "map": {"at": 164368, "to": "mm"}, 4927 "name": "PA_SC_CLIPRECT_0_TL", 4928 "type_ref": "PA_SC_CLIPRECT_0_TL" 4929 }, 4930 { 4931 "chips": ["gfx6"], 4932 "map": {"at": 164372, "to": "mm"}, 4933 "name": "PA_SC_CLIPRECT_0_BR", 4934 "type_ref": "PA_SC_CLIPRECT_0_BR" 4935 }, 4936 { 4937 "chips": ["gfx6"], 4938 "map": {"at": 164376, "to": "mm"}, 4939 "name": "PA_SC_CLIPRECT_1_TL", 4940 "type_ref": "PA_SC_CLIPRECT_0_TL" 4941 }, 4942 { 4943 "chips": ["gfx6"], 4944 "map": {"at": 164380, "to": "mm"}, 4945 "name": "PA_SC_CLIPRECT_1_BR", 4946 "type_ref": "PA_SC_CLIPRECT_0_BR" 4947 }, 4948 { 4949 "chips": ["gfx6"], 4950 "map": {"at": 164384, "to": "mm"}, 4951 "name": "PA_SC_CLIPRECT_2_TL", 4952 "type_ref": "PA_SC_CLIPRECT_0_TL" 4953 }, 4954 { 4955 "chips": ["gfx6"], 4956 "map": {"at": 164388, "to": "mm"}, 4957 "name": "PA_SC_CLIPRECT_2_BR", 4958 "type_ref": "PA_SC_CLIPRECT_0_BR" 4959 }, 4960 { 4961 "chips": ["gfx6"], 4962 "map": {"at": 164392, "to": "mm"}, 4963 "name": "PA_SC_CLIPRECT_3_TL", 4964 "type_ref": "PA_SC_CLIPRECT_0_TL" 4965 }, 4966 { 4967 "chips": ["gfx6"], 4968 "map": {"at": 164396, "to": "mm"}, 4969 "name": "PA_SC_CLIPRECT_3_BR", 4970 "type_ref": "PA_SC_CLIPRECT_0_BR" 4971 }, 4972 { 4973 "chips": ["gfx6"], 4974 "map": {"at": 164400, "to": "mm"}, 4975 "name": "PA_SC_EDGERULE", 4976 "type_ref": "PA_SC_EDGERULE" 4977 }, 4978 { 4979 "chips": ["gfx6"], 4980 "map": {"at": 164404, "to": "mm"}, 4981 "name": "PA_SU_HARDWARE_SCREEN_OFFSET", 4982 "type_ref": "PA_SU_HARDWARE_SCREEN_OFFSET" 4983 }, 4984 { 4985 "chips": ["gfx6"], 4986 "map": {"at": 164408, "to": "mm"}, 4987 "name": "CB_TARGET_MASK", 4988 "type_ref": "CB_TARGET_MASK" 4989 }, 4990 { 4991 "chips": ["gfx6"], 4992 "map": {"at": 164412, "to": "mm"}, 4993 "name": "CB_SHADER_MASK", 4994 "type_ref": "CB_SHADER_MASK" 4995 }, 4996 { 4997 "chips": ["gfx6"], 4998 "map": {"at": 164416, "to": "mm"}, 4999 "name": "PA_SC_GENERIC_SCISSOR_TL", 5000 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5001 }, 5002 { 5003 "chips": ["gfx6"], 5004 "map": {"at": 164420, "to": "mm"}, 5005 "name": "PA_SC_GENERIC_SCISSOR_BR", 5006 "type_ref": "PA_SC_CLIPRECT_0_BR" 5007 }, 5008 { 5009 "chips": ["gfx6"], 5010 "map": {"at": 164424, "to": "mm"}, 5011 "name": "COHER_DEST_BASE_0" 5012 }, 5013 { 5014 "chips": ["gfx6"], 5015 "map": {"at": 164428, "to": "mm"}, 5016 "name": "COHER_DEST_BASE_1" 5017 }, 5018 { 5019 "chips": ["gfx6"], 5020 "map": {"at": 164432, "to": "mm"}, 5021 "name": "PA_SC_VPORT_SCISSOR_0_TL", 5022 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5023 }, 5024 { 5025 "chips": ["gfx6"], 5026 "map": {"at": 164436, "to": "mm"}, 5027 "name": "PA_SC_VPORT_SCISSOR_0_BR", 5028 "type_ref": "PA_SC_CLIPRECT_0_BR" 5029 }, 5030 { 5031 "chips": ["gfx6"], 5032 "map": {"at": 164440, "to": "mm"}, 5033 "name": "PA_SC_VPORT_SCISSOR_1_TL", 5034 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5035 }, 5036 { 5037 "chips": ["gfx6"], 5038 "map": {"at": 164444, "to": "mm"}, 5039 "name": "PA_SC_VPORT_SCISSOR_1_BR", 5040 "type_ref": "PA_SC_CLIPRECT_0_BR" 5041 }, 5042 { 5043 "chips": ["gfx6"], 5044 "map": {"at": 164448, "to": "mm"}, 5045 "name": "PA_SC_VPORT_SCISSOR_2_TL", 5046 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5047 }, 5048 { 5049 "chips": ["gfx6"], 5050 "map": {"at": 164452, "to": "mm"}, 5051 "name": "PA_SC_VPORT_SCISSOR_2_BR", 5052 "type_ref": "PA_SC_CLIPRECT_0_BR" 5053 }, 5054 { 5055 "chips": ["gfx6"], 5056 "map": {"at": 164456, "to": "mm"}, 5057 "name": "PA_SC_VPORT_SCISSOR_3_TL", 5058 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5059 }, 5060 { 5061 "chips": ["gfx6"], 5062 "map": {"at": 164460, "to": "mm"}, 5063 "name": "PA_SC_VPORT_SCISSOR_3_BR", 5064 "type_ref": "PA_SC_CLIPRECT_0_BR" 5065 }, 5066 { 5067 "chips": ["gfx6"], 5068 "map": {"at": 164464, "to": "mm"}, 5069 "name": "PA_SC_VPORT_SCISSOR_4_TL", 5070 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5071 }, 5072 { 5073 "chips": ["gfx6"], 5074 "map": {"at": 164468, "to": "mm"}, 5075 "name": "PA_SC_VPORT_SCISSOR_4_BR", 5076 "type_ref": "PA_SC_CLIPRECT_0_BR" 5077 }, 5078 { 5079 "chips": ["gfx6"], 5080 "map": {"at": 164472, "to": "mm"}, 5081 "name": "PA_SC_VPORT_SCISSOR_5_TL", 5082 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5083 }, 5084 { 5085 "chips": ["gfx6"], 5086 "map": {"at": 164476, "to": "mm"}, 5087 "name": "PA_SC_VPORT_SCISSOR_5_BR", 5088 "type_ref": "PA_SC_CLIPRECT_0_BR" 5089 }, 5090 { 5091 "chips": ["gfx6"], 5092 "map": {"at": 164480, "to": "mm"}, 5093 "name": "PA_SC_VPORT_SCISSOR_6_TL", 5094 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5095 }, 5096 { 5097 "chips": ["gfx6"], 5098 "map": {"at": 164484, "to": "mm"}, 5099 "name": "PA_SC_VPORT_SCISSOR_6_BR", 5100 "type_ref": "PA_SC_CLIPRECT_0_BR" 5101 }, 5102 { 5103 "chips": ["gfx6"], 5104 "map": {"at": 164488, "to": "mm"}, 5105 "name": "PA_SC_VPORT_SCISSOR_7_TL", 5106 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5107 }, 5108 { 5109 "chips": ["gfx6"], 5110 "map": {"at": 164492, "to": "mm"}, 5111 "name": "PA_SC_VPORT_SCISSOR_7_BR", 5112 "type_ref": "PA_SC_CLIPRECT_0_BR" 5113 }, 5114 { 5115 "chips": ["gfx6"], 5116 "map": {"at": 164496, "to": "mm"}, 5117 "name": "PA_SC_VPORT_SCISSOR_8_TL", 5118 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5119 }, 5120 { 5121 "chips": ["gfx6"], 5122 "map": {"at": 164500, "to": "mm"}, 5123 "name": "PA_SC_VPORT_SCISSOR_8_BR", 5124 "type_ref": "PA_SC_CLIPRECT_0_BR" 5125 }, 5126 { 5127 "chips": ["gfx6"], 5128 "map": {"at": 164504, "to": "mm"}, 5129 "name": "PA_SC_VPORT_SCISSOR_9_TL", 5130 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5131 }, 5132 { 5133 "chips": ["gfx6"], 5134 "map": {"at": 164508, "to": "mm"}, 5135 "name": "PA_SC_VPORT_SCISSOR_9_BR", 5136 "type_ref": "PA_SC_CLIPRECT_0_BR" 5137 }, 5138 { 5139 "chips": ["gfx6"], 5140 "map": {"at": 164512, "to": "mm"}, 5141 "name": "PA_SC_VPORT_SCISSOR_10_TL", 5142 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5143 }, 5144 { 5145 "chips": ["gfx6"], 5146 "map": {"at": 164516, "to": "mm"}, 5147 "name": "PA_SC_VPORT_SCISSOR_10_BR", 5148 "type_ref": "PA_SC_CLIPRECT_0_BR" 5149 }, 5150 { 5151 "chips": ["gfx6"], 5152 "map": {"at": 164520, "to": "mm"}, 5153 "name": "PA_SC_VPORT_SCISSOR_11_TL", 5154 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5155 }, 5156 { 5157 "chips": ["gfx6"], 5158 "map": {"at": 164524, "to": "mm"}, 5159 "name": "PA_SC_VPORT_SCISSOR_11_BR", 5160 "type_ref": "PA_SC_CLIPRECT_0_BR" 5161 }, 5162 { 5163 "chips": ["gfx6"], 5164 "map": {"at": 164528, "to": "mm"}, 5165 "name": "PA_SC_VPORT_SCISSOR_12_TL", 5166 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5167 }, 5168 { 5169 "chips": ["gfx6"], 5170 "map": {"at": 164532, "to": "mm"}, 5171 "name": "PA_SC_VPORT_SCISSOR_12_BR", 5172 "type_ref": "PA_SC_CLIPRECT_0_BR" 5173 }, 5174 { 5175 "chips": ["gfx6"], 5176 "map": {"at": 164536, "to": "mm"}, 5177 "name": "PA_SC_VPORT_SCISSOR_13_TL", 5178 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5179 }, 5180 { 5181 "chips": ["gfx6"], 5182 "map": {"at": 164540, "to": "mm"}, 5183 "name": "PA_SC_VPORT_SCISSOR_13_BR", 5184 "type_ref": "PA_SC_CLIPRECT_0_BR" 5185 }, 5186 { 5187 "chips": ["gfx6"], 5188 "map": {"at": 164544, "to": "mm"}, 5189 "name": "PA_SC_VPORT_SCISSOR_14_TL", 5190 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5191 }, 5192 { 5193 "chips": ["gfx6"], 5194 "map": {"at": 164548, "to": "mm"}, 5195 "name": "PA_SC_VPORT_SCISSOR_14_BR", 5196 "type_ref": "PA_SC_CLIPRECT_0_BR" 5197 }, 5198 { 5199 "chips": ["gfx6"], 5200 "map": {"at": 164552, "to": "mm"}, 5201 "name": "PA_SC_VPORT_SCISSOR_15_TL", 5202 "type_ref": "PA_SC_GENERIC_SCISSOR_TL" 5203 }, 5204 { 5205 "chips": ["gfx6"], 5206 "map": {"at": 164556, "to": "mm"}, 5207 "name": "PA_SC_VPORT_SCISSOR_15_BR", 5208 "type_ref": "PA_SC_CLIPRECT_0_BR" 5209 }, 5210 { 5211 "chips": ["gfx6"], 5212 "map": {"at": 164560, "to": "mm"}, 5213 "name": "PA_SC_VPORT_ZMIN_0" 5214 }, 5215 { 5216 "chips": ["gfx6"], 5217 "map": {"at": 164564, "to": "mm"}, 5218 "name": "PA_SC_VPORT_ZMAX_0" 5219 }, 5220 { 5221 "chips": ["gfx6"], 5222 "map": {"at": 164568, "to": "mm"}, 5223 "name": "PA_SC_VPORT_ZMIN_1" 5224 }, 5225 { 5226 "chips": ["gfx6"], 5227 "map": {"at": 164572, "to": "mm"}, 5228 "name": "PA_SC_VPORT_ZMAX_1" 5229 }, 5230 { 5231 "chips": ["gfx6"], 5232 "map": {"at": 164576, "to": "mm"}, 5233 "name": "PA_SC_VPORT_ZMIN_2" 5234 }, 5235 { 5236 "chips": ["gfx6"], 5237 "map": {"at": 164580, "to": "mm"}, 5238 "name": "PA_SC_VPORT_ZMAX_2" 5239 }, 5240 { 5241 "chips": ["gfx6"], 5242 "map": {"at": 164584, "to": "mm"}, 5243 "name": "PA_SC_VPORT_ZMIN_3" 5244 }, 5245 { 5246 "chips": ["gfx6"], 5247 "map": {"at": 164588, "to": "mm"}, 5248 "name": "PA_SC_VPORT_ZMAX_3" 5249 }, 5250 { 5251 "chips": ["gfx6"], 5252 "map": {"at": 164592, "to": "mm"}, 5253 "name": "PA_SC_VPORT_ZMIN_4" 5254 }, 5255 { 5256 "chips": ["gfx6"], 5257 "map": {"at": 164596, "to": "mm"}, 5258 "name": "PA_SC_VPORT_ZMAX_4" 5259 }, 5260 { 5261 "chips": ["gfx6"], 5262 "map": {"at": 164600, "to": "mm"}, 5263 "name": "PA_SC_VPORT_ZMIN_5" 5264 }, 5265 { 5266 "chips": ["gfx6"], 5267 "map": {"at": 164604, "to": "mm"}, 5268 "name": "PA_SC_VPORT_ZMAX_5" 5269 }, 5270 { 5271 "chips": ["gfx6"], 5272 "map": {"at": 164608, "to": "mm"}, 5273 "name": "PA_SC_VPORT_ZMIN_6" 5274 }, 5275 { 5276 "chips": ["gfx6"], 5277 "map": {"at": 164612, "to": "mm"}, 5278 "name": "PA_SC_VPORT_ZMAX_6" 5279 }, 5280 { 5281 "chips": ["gfx6"], 5282 "map": {"at": 164616, "to": "mm"}, 5283 "name": "PA_SC_VPORT_ZMIN_7" 5284 }, 5285 { 5286 "chips": ["gfx6"], 5287 "map": {"at": 164620, "to": "mm"}, 5288 "name": "PA_SC_VPORT_ZMAX_7" 5289 }, 5290 { 5291 "chips": ["gfx6"], 5292 "map": {"at": 164624, "to": "mm"}, 5293 "name": "PA_SC_VPORT_ZMIN_8" 5294 }, 5295 { 5296 "chips": ["gfx6"], 5297 "map": {"at": 164628, "to": "mm"}, 5298 "name": "PA_SC_VPORT_ZMAX_8" 5299 }, 5300 { 5301 "chips": ["gfx6"], 5302 "map": {"at": 164632, "to": "mm"}, 5303 "name": "PA_SC_VPORT_ZMIN_9" 5304 }, 5305 { 5306 "chips": ["gfx6"], 5307 "map": {"at": 164636, "to": "mm"}, 5308 "name": "PA_SC_VPORT_ZMAX_9" 5309 }, 5310 { 5311 "chips": ["gfx6"], 5312 "map": {"at": 164640, "to": "mm"}, 5313 "name": "PA_SC_VPORT_ZMIN_10" 5314 }, 5315 { 5316 "chips": ["gfx6"], 5317 "map": {"at": 164644, "to": "mm"}, 5318 "name": "PA_SC_VPORT_ZMAX_10" 5319 }, 5320 { 5321 "chips": ["gfx6"], 5322 "map": {"at": 164648, "to": "mm"}, 5323 "name": "PA_SC_VPORT_ZMIN_11" 5324 }, 5325 { 5326 "chips": ["gfx6"], 5327 "map": {"at": 164652, "to": "mm"}, 5328 "name": "PA_SC_VPORT_ZMAX_11" 5329 }, 5330 { 5331 "chips": ["gfx6"], 5332 "map": {"at": 164656, "to": "mm"}, 5333 "name": "PA_SC_VPORT_ZMIN_12" 5334 }, 5335 { 5336 "chips": ["gfx6"], 5337 "map": {"at": 164660, "to": "mm"}, 5338 "name": "PA_SC_VPORT_ZMAX_12" 5339 }, 5340 { 5341 "chips": ["gfx6"], 5342 "map": {"at": 164664, "to": "mm"}, 5343 "name": "PA_SC_VPORT_ZMIN_13" 5344 }, 5345 { 5346 "chips": ["gfx6"], 5347 "map": {"at": 164668, "to": "mm"}, 5348 "name": "PA_SC_VPORT_ZMAX_13" 5349 }, 5350 { 5351 "chips": ["gfx6"], 5352 "map": {"at": 164672, "to": "mm"}, 5353 "name": "PA_SC_VPORT_ZMIN_14" 5354 }, 5355 { 5356 "chips": ["gfx6"], 5357 "map": {"at": 164676, "to": "mm"}, 5358 "name": "PA_SC_VPORT_ZMAX_14" 5359 }, 5360 { 5361 "chips": ["gfx6"], 5362 "map": {"at": 164680, "to": "mm"}, 5363 "name": "PA_SC_VPORT_ZMIN_15" 5364 }, 5365 { 5366 "chips": ["gfx6"], 5367 "map": {"at": 164684, "to": "mm"}, 5368 "name": "PA_SC_VPORT_ZMAX_15" 5369 }, 5370 { 5371 "chips": ["gfx6"], 5372 "map": {"at": 164688, "to": "mm"}, 5373 "name": "PA_SC_RASTER_CONFIG", 5374 "type_ref": "PA_SC_RASTER_CONFIG" 5375 }, 5376 { 5377 "chips": ["gfx6"], 5378 "map": {"at": 164704, "to": "mm"}, 5379 "name": "CP_PERFMON_CNTX_CNTL", 5380 "type_ref": "CP_PERFMON_CNTX_CNTL" 5381 }, 5382 { 5383 "chips": ["gfx6"], 5384 "map": {"at": 164708, "to": "mm"}, 5385 "name": "CP_RINGID", 5386 "type_ref": "CP_RINGID" 5387 }, 5388 { 5389 "chips": ["gfx6"], 5390 "map": {"at": 164712, "to": "mm"}, 5391 "name": "CP_VMID", 5392 "type_ref": "CP_VMID" 5393 }, 5394 { 5395 "chips": ["gfx6"], 5396 "map": {"at": 164864, "to": "mm"}, 5397 "name": "VGT_MAX_VTX_INDX" 5398 }, 5399 { 5400 "chips": ["gfx6"], 5401 "map": {"at": 164868, "to": "mm"}, 5402 "name": "VGT_MIN_VTX_INDX" 5403 }, 5404 { 5405 "chips": ["gfx6"], 5406 "map": {"at": 164872, "to": "mm"}, 5407 "name": "VGT_INDX_OFFSET" 5408 }, 5409 { 5410 "chips": ["gfx6"], 5411 "map": {"at": 164876, "to": "mm"}, 5412 "name": "VGT_MULTI_PRIM_IB_RESET_INDX" 5413 }, 5414 { 5415 "chips": ["gfx6"], 5416 "map": {"at": 164884, "to": "mm"}, 5417 "name": "CB_BLEND_RED" 5418 }, 5419 { 5420 "chips": ["gfx6"], 5421 "map": {"at": 164888, "to": "mm"}, 5422 "name": "CB_BLEND_GREEN" 5423 }, 5424 { 5425 "chips": ["gfx6"], 5426 "map": {"at": 164892, "to": "mm"}, 5427 "name": "CB_BLEND_BLUE" 5428 }, 5429 { 5430 "chips": ["gfx6"], 5431 "map": {"at": 164896, "to": "mm"}, 5432 "name": "CB_BLEND_ALPHA" 5433 }, 5434 { 5435 "chips": ["gfx6"], 5436 "map": {"at": 164908, "to": "mm"}, 5437 "name": "DB_STENCIL_CONTROL", 5438 "type_ref": "DB_STENCIL_CONTROL" 5439 }, 5440 { 5441 "chips": ["gfx6"], 5442 "map": {"at": 164912, "to": "mm"}, 5443 "name": "DB_STENCILREFMASK", 5444 "type_ref": "DB_STENCILREFMASK" 5445 }, 5446 { 5447 "chips": ["gfx6"], 5448 "map": {"at": 164916, "to": "mm"}, 5449 "name": "DB_STENCILREFMASK_BF", 5450 "type_ref": "DB_STENCILREFMASK_BF" 5451 }, 5452 { 5453 "chips": ["gfx6"], 5454 "map": {"at": 164924, "to": "mm"}, 5455 "name": "PA_CL_VPORT_XSCALE" 5456 }, 5457 { 5458 "chips": ["gfx6"], 5459 "map": {"at": 164928, "to": "mm"}, 5460 "name": "PA_CL_VPORT_XOFFSET" 5461 }, 5462 { 5463 "chips": ["gfx6"], 5464 "map": {"at": 164932, "to": "mm"}, 5465 "name": "PA_CL_VPORT_YSCALE" 5466 }, 5467 { 5468 "chips": ["gfx6"], 5469 "map": {"at": 164936, "to": "mm"}, 5470 "name": "PA_CL_VPORT_YOFFSET" 5471 }, 5472 { 5473 "chips": ["gfx6"], 5474 "map": {"at": 164940, "to": "mm"}, 5475 "name": "PA_CL_VPORT_ZSCALE" 5476 }, 5477 { 5478 "chips": ["gfx6"], 5479 "map": {"at": 164944, "to": "mm"}, 5480 "name": "PA_CL_VPORT_ZOFFSET" 5481 }, 5482 { 5483 "chips": ["gfx6"], 5484 "map": {"at": 164948, "to": "mm"}, 5485 "name": "PA_CL_VPORT_XSCALE_1" 5486 }, 5487 { 5488 "chips": ["gfx6"], 5489 "map": {"at": 164952, "to": "mm"}, 5490 "name": "PA_CL_VPORT_XOFFSET_1" 5491 }, 5492 { 5493 "chips": ["gfx6"], 5494 "map": {"at": 164956, "to": "mm"}, 5495 "name": "PA_CL_VPORT_YSCALE_1" 5496 }, 5497 { 5498 "chips": ["gfx6"], 5499 "map": {"at": 164960, "to": "mm"}, 5500 "name": "PA_CL_VPORT_YOFFSET_1" 5501 }, 5502 { 5503 "chips": ["gfx6"], 5504 "map": {"at": 164964, "to": "mm"}, 5505 "name": "PA_CL_VPORT_ZSCALE_1" 5506 }, 5507 { 5508 "chips": ["gfx6"], 5509 "map": {"at": 164968, "to": "mm"}, 5510 "name": "PA_CL_VPORT_ZOFFSET_1" 5511 }, 5512 { 5513 "chips": ["gfx6"], 5514 "map": {"at": 164972, "to": "mm"}, 5515 "name": "PA_CL_VPORT_XSCALE_2" 5516 }, 5517 { 5518 "chips": ["gfx6"], 5519 "map": {"at": 164976, "to": "mm"}, 5520 "name": "PA_CL_VPORT_XOFFSET_2" 5521 }, 5522 { 5523 "chips": ["gfx6"], 5524 "map": {"at": 164980, "to": "mm"}, 5525 "name": "PA_CL_VPORT_YSCALE_2" 5526 }, 5527 { 5528 "chips": ["gfx6"], 5529 "map": {"at": 164984, "to": "mm"}, 5530 "name": "PA_CL_VPORT_YOFFSET_2" 5531 }, 5532 { 5533 "chips": ["gfx6"], 5534 "map": {"at": 164988, "to": "mm"}, 5535 "name": "PA_CL_VPORT_ZSCALE_2" 5536 }, 5537 { 5538 "chips": ["gfx6"], 5539 "map": {"at": 164992, "to": "mm"}, 5540 "name": "PA_CL_VPORT_ZOFFSET_2" 5541 }, 5542 { 5543 "chips": ["gfx6"], 5544 "map": {"at": 164996, "to": "mm"}, 5545 "name": "PA_CL_VPORT_XSCALE_3" 5546 }, 5547 { 5548 "chips": ["gfx6"], 5549 "map": {"at": 165000, "to": "mm"}, 5550 "name": "PA_CL_VPORT_XOFFSET_3" 5551 }, 5552 { 5553 "chips": ["gfx6"], 5554 "map": {"at": 165004, "to": "mm"}, 5555 "name": "PA_CL_VPORT_YSCALE_3" 5556 }, 5557 { 5558 "chips": ["gfx6"], 5559 "map": {"at": 165008, "to": "mm"}, 5560 "name": "PA_CL_VPORT_YOFFSET_3" 5561 }, 5562 { 5563 "chips": ["gfx6"], 5564 "map": {"at": 165012, "to": "mm"}, 5565 "name": "PA_CL_VPORT_ZSCALE_3" 5566 }, 5567 { 5568 "chips": ["gfx6"], 5569 "map": {"at": 165016, "to": "mm"}, 5570 "name": "PA_CL_VPORT_ZOFFSET_3" 5571 }, 5572 { 5573 "chips": ["gfx6"], 5574 "map": {"at": 165020, "to": "mm"}, 5575 "name": "PA_CL_VPORT_XSCALE_4" 5576 }, 5577 { 5578 "chips": ["gfx6"], 5579 "map": {"at": 165024, "to": "mm"}, 5580 "name": "PA_CL_VPORT_XOFFSET_4" 5581 }, 5582 { 5583 "chips": ["gfx6"], 5584 "map": {"at": 165028, "to": "mm"}, 5585 "name": "PA_CL_VPORT_YSCALE_4" 5586 }, 5587 { 5588 "chips": ["gfx6"], 5589 "map": {"at": 165032, "to": "mm"}, 5590 "name": "PA_CL_VPORT_YOFFSET_4" 5591 }, 5592 { 5593 "chips": ["gfx6"], 5594 "map": {"at": 165036, "to": "mm"}, 5595 "name": "PA_CL_VPORT_ZSCALE_4" 5596 }, 5597 { 5598 "chips": ["gfx6"], 5599 "map": {"at": 165040, "to": "mm"}, 5600 "name": "PA_CL_VPORT_ZOFFSET_4" 5601 }, 5602 { 5603 "chips": ["gfx6"], 5604 "map": {"at": 165044, "to": "mm"}, 5605 "name": "PA_CL_VPORT_XSCALE_5" 5606 }, 5607 { 5608 "chips": ["gfx6"], 5609 "map": {"at": 165048, "to": "mm"}, 5610 "name": "PA_CL_VPORT_XOFFSET_5" 5611 }, 5612 { 5613 "chips": ["gfx6"], 5614 "map": {"at": 165052, "to": "mm"}, 5615 "name": "PA_CL_VPORT_YSCALE_5" 5616 }, 5617 { 5618 "chips": ["gfx6"], 5619 "map": {"at": 165056, "to": "mm"}, 5620 "name": "PA_CL_VPORT_YOFFSET_5" 5621 }, 5622 { 5623 "chips": ["gfx6"], 5624 "map": {"at": 165060, "to": "mm"}, 5625 "name": "PA_CL_VPORT_ZSCALE_5" 5626 }, 5627 { 5628 "chips": ["gfx6"], 5629 "map": {"at": 165064, "to": "mm"}, 5630 "name": "PA_CL_VPORT_ZOFFSET_5" 5631 }, 5632 { 5633 "chips": ["gfx6"], 5634 "map": {"at": 165068, "to": "mm"}, 5635 "name": "PA_CL_VPORT_XSCALE_6" 5636 }, 5637 { 5638 "chips": ["gfx6"], 5639 "map": {"at": 165072, "to": "mm"}, 5640 "name": "PA_CL_VPORT_XOFFSET_6" 5641 }, 5642 { 5643 "chips": ["gfx6"], 5644 "map": {"at": 165076, "to": "mm"}, 5645 "name": "PA_CL_VPORT_YSCALE_6" 5646 }, 5647 { 5648 "chips": ["gfx6"], 5649 "map": {"at": 165080, "to": "mm"}, 5650 "name": "PA_CL_VPORT_YOFFSET_6" 5651 }, 5652 { 5653 "chips": ["gfx6"], 5654 "map": {"at": 165084, "to": "mm"}, 5655 "name": "PA_CL_VPORT_ZSCALE_6" 5656 }, 5657 { 5658 "chips": ["gfx6"], 5659 "map": {"at": 165088, "to": "mm"}, 5660 "name": "PA_CL_VPORT_ZOFFSET_6" 5661 }, 5662 { 5663 "chips": ["gfx6"], 5664 "map": {"at": 165092, "to": "mm"}, 5665 "name": "PA_CL_VPORT_XSCALE_7" 5666 }, 5667 { 5668 "chips": ["gfx6"], 5669 "map": {"at": 165096, "to": "mm"}, 5670 "name": "PA_CL_VPORT_XOFFSET_7" 5671 }, 5672 { 5673 "chips": ["gfx6"], 5674 "map": {"at": 165100, "to": "mm"}, 5675 "name": "PA_CL_VPORT_YSCALE_7" 5676 }, 5677 { 5678 "chips": ["gfx6"], 5679 "map": {"at": 165104, "to": "mm"}, 5680 "name": "PA_CL_VPORT_YOFFSET_7" 5681 }, 5682 { 5683 "chips": ["gfx6"], 5684 "map": {"at": 165108, "to": "mm"}, 5685 "name": "PA_CL_VPORT_ZSCALE_7" 5686 }, 5687 { 5688 "chips": ["gfx6"], 5689 "map": {"at": 165112, "to": "mm"}, 5690 "name": "PA_CL_VPORT_ZOFFSET_7" 5691 }, 5692 { 5693 "chips": ["gfx6"], 5694 "map": {"at": 165116, "to": "mm"}, 5695 "name": "PA_CL_VPORT_XSCALE_8" 5696 }, 5697 { 5698 "chips": ["gfx6"], 5699 "map": {"at": 165120, "to": "mm"}, 5700 "name": "PA_CL_VPORT_XOFFSET_8" 5701 }, 5702 { 5703 "chips": ["gfx6"], 5704 "map": {"at": 165124, "to": "mm"}, 5705 "name": "PA_CL_VPORT_YSCALE_8" 5706 }, 5707 { 5708 "chips": ["gfx6"], 5709 "map": {"at": 165128, "to": "mm"}, 5710 "name": "PA_CL_VPORT_YOFFSET_8" 5711 }, 5712 { 5713 "chips": ["gfx6"], 5714 "map": {"at": 165132, "to": "mm"}, 5715 "name": "PA_CL_VPORT_ZSCALE_8" 5716 }, 5717 { 5718 "chips": ["gfx6"], 5719 "map": {"at": 165136, "to": "mm"}, 5720 "name": "PA_CL_VPORT_ZOFFSET_8" 5721 }, 5722 { 5723 "chips": ["gfx6"], 5724 "map": {"at": 165140, "to": "mm"}, 5725 "name": "PA_CL_VPORT_XSCALE_9" 5726 }, 5727 { 5728 "chips": ["gfx6"], 5729 "map": {"at": 165144, "to": "mm"}, 5730 "name": "PA_CL_VPORT_XOFFSET_9" 5731 }, 5732 { 5733 "chips": ["gfx6"], 5734 "map": {"at": 165148, "to": "mm"}, 5735 "name": "PA_CL_VPORT_YSCALE_9" 5736 }, 5737 { 5738 "chips": ["gfx6"], 5739 "map": {"at": 165152, "to": "mm"}, 5740 "name": "PA_CL_VPORT_YOFFSET_9" 5741 }, 5742 { 5743 "chips": ["gfx6"], 5744 "map": {"at": 165156, "to": "mm"}, 5745 "name": "PA_CL_VPORT_ZSCALE_9" 5746 }, 5747 { 5748 "chips": ["gfx6"], 5749 "map": {"at": 165160, "to": "mm"}, 5750 "name": "PA_CL_VPORT_ZOFFSET_9" 5751 }, 5752 { 5753 "chips": ["gfx6"], 5754 "map": {"at": 165164, "to": "mm"}, 5755 "name": "PA_CL_VPORT_XSCALE_10" 5756 }, 5757 { 5758 "chips": ["gfx6"], 5759 "map": {"at": 165168, "to": "mm"}, 5760 "name": "PA_CL_VPORT_XOFFSET_10" 5761 }, 5762 { 5763 "chips": ["gfx6"], 5764 "map": {"at": 165172, "to": "mm"}, 5765 "name": "PA_CL_VPORT_YSCALE_10" 5766 }, 5767 { 5768 "chips": ["gfx6"], 5769 "map": {"at": 165176, "to": "mm"}, 5770 "name": "PA_CL_VPORT_YOFFSET_10" 5771 }, 5772 { 5773 "chips": ["gfx6"], 5774 "map": {"at": 165180, "to": "mm"}, 5775 "name": "PA_CL_VPORT_ZSCALE_10" 5776 }, 5777 { 5778 "chips": ["gfx6"], 5779 "map": {"at": 165184, "to": "mm"}, 5780 "name": "PA_CL_VPORT_ZOFFSET_10" 5781 }, 5782 { 5783 "chips": ["gfx6"], 5784 "map": {"at": 165188, "to": "mm"}, 5785 "name": "PA_CL_VPORT_XSCALE_11" 5786 }, 5787 { 5788 "chips": ["gfx6"], 5789 "map": {"at": 165192, "to": "mm"}, 5790 "name": "PA_CL_VPORT_XOFFSET_11" 5791 }, 5792 { 5793 "chips": ["gfx6"], 5794 "map": {"at": 165196, "to": "mm"}, 5795 "name": "PA_CL_VPORT_YSCALE_11" 5796 }, 5797 { 5798 "chips": ["gfx6"], 5799 "map": {"at": 165200, "to": "mm"}, 5800 "name": "PA_CL_VPORT_YOFFSET_11" 5801 }, 5802 { 5803 "chips": ["gfx6"], 5804 "map": {"at": 165204, "to": "mm"}, 5805 "name": "PA_CL_VPORT_ZSCALE_11" 5806 }, 5807 { 5808 "chips": ["gfx6"], 5809 "map": {"at": 165208, "to": "mm"}, 5810 "name": "PA_CL_VPORT_ZOFFSET_11" 5811 }, 5812 { 5813 "chips": ["gfx6"], 5814 "map": {"at": 165212, "to": "mm"}, 5815 "name": "PA_CL_VPORT_XSCALE_12" 5816 }, 5817 { 5818 "chips": ["gfx6"], 5819 "map": {"at": 165216, "to": "mm"}, 5820 "name": "PA_CL_VPORT_XOFFSET_12" 5821 }, 5822 { 5823 "chips": ["gfx6"], 5824 "map": {"at": 165220, "to": "mm"}, 5825 "name": "PA_CL_VPORT_YSCALE_12" 5826 }, 5827 { 5828 "chips": ["gfx6"], 5829 "map": {"at": 165224, "to": "mm"}, 5830 "name": "PA_CL_VPORT_YOFFSET_12" 5831 }, 5832 { 5833 "chips": ["gfx6"], 5834 "map": {"at": 165228, "to": "mm"}, 5835 "name": "PA_CL_VPORT_ZSCALE_12" 5836 }, 5837 { 5838 "chips": ["gfx6"], 5839 "map": {"at": 165232, "to": "mm"}, 5840 "name": "PA_CL_VPORT_ZOFFSET_12" 5841 }, 5842 { 5843 "chips": ["gfx6"], 5844 "map": {"at": 165236, "to": "mm"}, 5845 "name": "PA_CL_VPORT_XSCALE_13" 5846 }, 5847 { 5848 "chips": ["gfx6"], 5849 "map": {"at": 165240, "to": "mm"}, 5850 "name": "PA_CL_VPORT_XOFFSET_13" 5851 }, 5852 { 5853 "chips": ["gfx6"], 5854 "map": {"at": 165244, "to": "mm"}, 5855 "name": "PA_CL_VPORT_YSCALE_13" 5856 }, 5857 { 5858 "chips": ["gfx6"], 5859 "map": {"at": 165248, "to": "mm"}, 5860 "name": "PA_CL_VPORT_YOFFSET_13" 5861 }, 5862 { 5863 "chips": ["gfx6"], 5864 "map": {"at": 165252, "to": "mm"}, 5865 "name": "PA_CL_VPORT_ZSCALE_13" 5866 }, 5867 { 5868 "chips": ["gfx6"], 5869 "map": {"at": 165256, "to": "mm"}, 5870 "name": "PA_CL_VPORT_ZOFFSET_13" 5871 }, 5872 { 5873 "chips": ["gfx6"], 5874 "map": {"at": 165260, "to": "mm"}, 5875 "name": "PA_CL_VPORT_XSCALE_14" 5876 }, 5877 { 5878 "chips": ["gfx6"], 5879 "map": {"at": 165264, "to": "mm"}, 5880 "name": "PA_CL_VPORT_XOFFSET_14" 5881 }, 5882 { 5883 "chips": ["gfx6"], 5884 "map": {"at": 165268, "to": "mm"}, 5885 "name": "PA_CL_VPORT_YSCALE_14" 5886 }, 5887 { 5888 "chips": ["gfx6"], 5889 "map": {"at": 165272, "to": "mm"}, 5890 "name": "PA_CL_VPORT_YOFFSET_14" 5891 }, 5892 { 5893 "chips": ["gfx6"], 5894 "map": {"at": 165276, "to": "mm"}, 5895 "name": "PA_CL_VPORT_ZSCALE_14" 5896 }, 5897 { 5898 "chips": ["gfx6"], 5899 "map": {"at": 165280, "to": "mm"}, 5900 "name": "PA_CL_VPORT_ZOFFSET_14" 5901 }, 5902 { 5903 "chips": ["gfx6"], 5904 "map": {"at": 165284, "to": "mm"}, 5905 "name": "PA_CL_VPORT_XSCALE_15" 5906 }, 5907 { 5908 "chips": ["gfx6"], 5909 "map": {"at": 165288, "to": "mm"}, 5910 "name": "PA_CL_VPORT_XOFFSET_15" 5911 }, 5912 { 5913 "chips": ["gfx6"], 5914 "map": {"at": 165292, "to": "mm"}, 5915 "name": "PA_CL_VPORT_YSCALE_15" 5916 }, 5917 { 5918 "chips": ["gfx6"], 5919 "map": {"at": 165296, "to": "mm"}, 5920 "name": "PA_CL_VPORT_YOFFSET_15" 5921 }, 5922 { 5923 "chips": ["gfx6"], 5924 "map": {"at": 165300, "to": "mm"}, 5925 "name": "PA_CL_VPORT_ZSCALE_15" 5926 }, 5927 { 5928 "chips": ["gfx6"], 5929 "map": {"at": 165304, "to": "mm"}, 5930 "name": "PA_CL_VPORT_ZOFFSET_15" 5931 }, 5932 { 5933 "chips": ["gfx6"], 5934 "map": {"at": 165308, "to": "mm"}, 5935 "name": "PA_CL_UCP_0_X" 5936 }, 5937 { 5938 "chips": ["gfx6"], 5939 "map": {"at": 165312, "to": "mm"}, 5940 "name": "PA_CL_UCP_0_Y" 5941 }, 5942 { 5943 "chips": ["gfx6"], 5944 "map": {"at": 165316, "to": "mm"}, 5945 "name": "PA_CL_UCP_0_Z" 5946 }, 5947 { 5948 "chips": ["gfx6"], 5949 "map": {"at": 165320, "to": "mm"}, 5950 "name": "PA_CL_UCP_0_W" 5951 }, 5952 { 5953 "chips": ["gfx6"], 5954 "map": {"at": 165324, "to": "mm"}, 5955 "name": "PA_CL_UCP_1_X" 5956 }, 5957 { 5958 "chips": ["gfx6"], 5959 "map": {"at": 165328, "to": "mm"}, 5960 "name": "PA_CL_UCP_1_Y" 5961 }, 5962 { 5963 "chips": ["gfx6"], 5964 "map": {"at": 165332, "to": "mm"}, 5965 "name": "PA_CL_UCP_1_Z" 5966 }, 5967 { 5968 "chips": ["gfx6"], 5969 "map": {"at": 165336, "to": "mm"}, 5970 "name": "PA_CL_UCP_1_W" 5971 }, 5972 { 5973 "chips": ["gfx6"], 5974 "map": {"at": 165340, "to": "mm"}, 5975 "name": "PA_CL_UCP_2_X" 5976 }, 5977 { 5978 "chips": ["gfx6"], 5979 "map": {"at": 165344, "to": "mm"}, 5980 "name": "PA_CL_UCP_2_Y" 5981 }, 5982 { 5983 "chips": ["gfx6"], 5984 "map": {"at": 165348, "to": "mm"}, 5985 "name": "PA_CL_UCP_2_Z" 5986 }, 5987 { 5988 "chips": ["gfx6"], 5989 "map": {"at": 165352, "to": "mm"}, 5990 "name": "PA_CL_UCP_2_W" 5991 }, 5992 { 5993 "chips": ["gfx6"], 5994 "map": {"at": 165356, "to": "mm"}, 5995 "name": "PA_CL_UCP_3_X" 5996 }, 5997 { 5998 "chips": ["gfx6"], 5999 "map": {"at": 165360, "to": "mm"}, 6000 "name": "PA_CL_UCP_3_Y" 6001 }, 6002 { 6003 "chips": ["gfx6"], 6004 "map": {"at": 165364, "to": "mm"}, 6005 "name": "PA_CL_UCP_3_Z" 6006 }, 6007 { 6008 "chips": ["gfx6"], 6009 "map": {"at": 165368, "to": "mm"}, 6010 "name": "PA_CL_UCP_3_W" 6011 }, 6012 { 6013 "chips": ["gfx6"], 6014 "map": {"at": 165372, "to": "mm"}, 6015 "name": "PA_CL_UCP_4_X" 6016 }, 6017 { 6018 "chips": ["gfx6"], 6019 "map": {"at": 165376, "to": "mm"}, 6020 "name": "PA_CL_UCP_4_Y" 6021 }, 6022 { 6023 "chips": ["gfx6"], 6024 "map": {"at": 165380, "to": "mm"}, 6025 "name": "PA_CL_UCP_4_Z" 6026 }, 6027 { 6028 "chips": ["gfx6"], 6029 "map": {"at": 165384, "to": "mm"}, 6030 "name": "PA_CL_UCP_4_W" 6031 }, 6032 { 6033 "chips": ["gfx6"], 6034 "map": {"at": 165388, "to": "mm"}, 6035 "name": "PA_CL_UCP_5_X" 6036 }, 6037 { 6038 "chips": ["gfx6"], 6039 "map": {"at": 165392, "to": "mm"}, 6040 "name": "PA_CL_UCP_5_Y" 6041 }, 6042 { 6043 "chips": ["gfx6"], 6044 "map": {"at": 165396, "to": "mm"}, 6045 "name": "PA_CL_UCP_5_Z" 6046 }, 6047 { 6048 "chips": ["gfx6"], 6049 "map": {"at": 165400, "to": "mm"}, 6050 "name": "PA_CL_UCP_5_W" 6051 }, 6052 { 6053 "chips": ["gfx6"], 6054 "map": {"at": 165444, "to": "mm"}, 6055 "name": "SPI_PS_INPUT_CNTL_0", 6056 "type_ref": "SPI_PS_INPUT_CNTL_0" 6057 }, 6058 { 6059 "chips": ["gfx6"], 6060 "map": {"at": 165448, "to": "mm"}, 6061 "name": "SPI_PS_INPUT_CNTL_1", 6062 "type_ref": "SPI_PS_INPUT_CNTL_0" 6063 }, 6064 { 6065 "chips": ["gfx6"], 6066 "map": {"at": 165452, "to": "mm"}, 6067 "name": "SPI_PS_INPUT_CNTL_2", 6068 "type_ref": "SPI_PS_INPUT_CNTL_0" 6069 }, 6070 { 6071 "chips": ["gfx6"], 6072 "map": {"at": 165456, "to": "mm"}, 6073 "name": "SPI_PS_INPUT_CNTL_3", 6074 "type_ref": "SPI_PS_INPUT_CNTL_0" 6075 }, 6076 { 6077 "chips": ["gfx6"], 6078 "map": {"at": 165460, "to": "mm"}, 6079 "name": "SPI_PS_INPUT_CNTL_4", 6080 "type_ref": "SPI_PS_INPUT_CNTL_0" 6081 }, 6082 { 6083 "chips": ["gfx6"], 6084 "map": {"at": 165464, "to": "mm"}, 6085 "name": "SPI_PS_INPUT_CNTL_5", 6086 "type_ref": "SPI_PS_INPUT_CNTL_0" 6087 }, 6088 { 6089 "chips": ["gfx6"], 6090 "map": {"at": 165468, "to": "mm"}, 6091 "name": "SPI_PS_INPUT_CNTL_6", 6092 "type_ref": "SPI_PS_INPUT_CNTL_0" 6093 }, 6094 { 6095 "chips": ["gfx6"], 6096 "map": {"at": 165472, "to": "mm"}, 6097 "name": "SPI_PS_INPUT_CNTL_7", 6098 "type_ref": "SPI_PS_INPUT_CNTL_0" 6099 }, 6100 { 6101 "chips": ["gfx6"], 6102 "map": {"at": 165476, "to": "mm"}, 6103 "name": "SPI_PS_INPUT_CNTL_8", 6104 "type_ref": "SPI_PS_INPUT_CNTL_0" 6105 }, 6106 { 6107 "chips": ["gfx6"], 6108 "map": {"at": 165480, "to": "mm"}, 6109 "name": "SPI_PS_INPUT_CNTL_9", 6110 "type_ref": "SPI_PS_INPUT_CNTL_0" 6111 }, 6112 { 6113 "chips": ["gfx6"], 6114 "map": {"at": 165484, "to": "mm"}, 6115 "name": "SPI_PS_INPUT_CNTL_10", 6116 "type_ref": "SPI_PS_INPUT_CNTL_0" 6117 }, 6118 { 6119 "chips": ["gfx6"], 6120 "map": {"at": 165488, "to": "mm"}, 6121 "name": "SPI_PS_INPUT_CNTL_11", 6122 "type_ref": "SPI_PS_INPUT_CNTL_0" 6123 }, 6124 { 6125 "chips": ["gfx6"], 6126 "map": {"at": 165492, "to": "mm"}, 6127 "name": "SPI_PS_INPUT_CNTL_12", 6128 "type_ref": "SPI_PS_INPUT_CNTL_0" 6129 }, 6130 { 6131 "chips": ["gfx6"], 6132 "map": {"at": 165496, "to": "mm"}, 6133 "name": "SPI_PS_INPUT_CNTL_13", 6134 "type_ref": "SPI_PS_INPUT_CNTL_0" 6135 }, 6136 { 6137 "chips": ["gfx6"], 6138 "map": {"at": 165500, "to": "mm"}, 6139 "name": "SPI_PS_INPUT_CNTL_14", 6140 "type_ref": "SPI_PS_INPUT_CNTL_0" 6141 }, 6142 { 6143 "chips": ["gfx6"], 6144 "map": {"at": 165504, "to": "mm"}, 6145 "name": "SPI_PS_INPUT_CNTL_15", 6146 "type_ref": "SPI_PS_INPUT_CNTL_0" 6147 }, 6148 { 6149 "chips": ["gfx6"], 6150 "map": {"at": 165508, "to": "mm"}, 6151 "name": "SPI_PS_INPUT_CNTL_16", 6152 "type_ref": "SPI_PS_INPUT_CNTL_0" 6153 }, 6154 { 6155 "chips": ["gfx6"], 6156 "map": {"at": 165512, "to": "mm"}, 6157 "name": "SPI_PS_INPUT_CNTL_17", 6158 "type_ref": "SPI_PS_INPUT_CNTL_0" 6159 }, 6160 { 6161 "chips": ["gfx6"], 6162 "map": {"at": 165516, "to": "mm"}, 6163 "name": "SPI_PS_INPUT_CNTL_18", 6164 "type_ref": "SPI_PS_INPUT_CNTL_0" 6165 }, 6166 { 6167 "chips": ["gfx6"], 6168 "map": {"at": 165520, "to": "mm"}, 6169 "name": "SPI_PS_INPUT_CNTL_19", 6170 "type_ref": "SPI_PS_INPUT_CNTL_0" 6171 }, 6172 { 6173 "chips": ["gfx6"], 6174 "map": {"at": 165524, "to": "mm"}, 6175 "name": "SPI_PS_INPUT_CNTL_20", 6176 "type_ref": "SPI_PS_INPUT_CNTL_20" 6177 }, 6178 { 6179 "chips": ["gfx6"], 6180 "map": {"at": 165528, "to": "mm"}, 6181 "name": "SPI_PS_INPUT_CNTL_21", 6182 "type_ref": "SPI_PS_INPUT_CNTL_20" 6183 }, 6184 { 6185 "chips": ["gfx6"], 6186 "map": {"at": 165532, "to": "mm"}, 6187 "name": "SPI_PS_INPUT_CNTL_22", 6188 "type_ref": "SPI_PS_INPUT_CNTL_20" 6189 }, 6190 { 6191 "chips": ["gfx6"], 6192 "map": {"at": 165536, "to": "mm"}, 6193 "name": "SPI_PS_INPUT_CNTL_23", 6194 "type_ref": "SPI_PS_INPUT_CNTL_20" 6195 }, 6196 { 6197 "chips": ["gfx6"], 6198 "map": {"at": 165540, "to": "mm"}, 6199 "name": "SPI_PS_INPUT_CNTL_24", 6200 "type_ref": "SPI_PS_INPUT_CNTL_20" 6201 }, 6202 { 6203 "chips": ["gfx6"], 6204 "map": {"at": 165544, "to": "mm"}, 6205 "name": "SPI_PS_INPUT_CNTL_25", 6206 "type_ref": "SPI_PS_INPUT_CNTL_20" 6207 }, 6208 { 6209 "chips": ["gfx6"], 6210 "map": {"at": 165548, "to": "mm"}, 6211 "name": "SPI_PS_INPUT_CNTL_26", 6212 "type_ref": "SPI_PS_INPUT_CNTL_20" 6213 }, 6214 { 6215 "chips": ["gfx6"], 6216 "map": {"at": 165552, "to": "mm"}, 6217 "name": "SPI_PS_INPUT_CNTL_27", 6218 "type_ref": "SPI_PS_INPUT_CNTL_20" 6219 }, 6220 { 6221 "chips": ["gfx6"], 6222 "map": {"at": 165556, "to": "mm"}, 6223 "name": "SPI_PS_INPUT_CNTL_28", 6224 "type_ref": "SPI_PS_INPUT_CNTL_20" 6225 }, 6226 { 6227 "chips": ["gfx6"], 6228 "map": {"at": 165560, "to": "mm"}, 6229 "name": "SPI_PS_INPUT_CNTL_29", 6230 "type_ref": "SPI_PS_INPUT_CNTL_20" 6231 }, 6232 { 6233 "chips": ["gfx6"], 6234 "map": {"at": 165564, "to": "mm"}, 6235 "name": "SPI_PS_INPUT_CNTL_30", 6236 "type_ref": "SPI_PS_INPUT_CNTL_20" 6237 }, 6238 { 6239 "chips": ["gfx6"], 6240 "map": {"at": 165568, "to": "mm"}, 6241 "name": "SPI_PS_INPUT_CNTL_31", 6242 "type_ref": "SPI_PS_INPUT_CNTL_20" 6243 }, 6244 { 6245 "chips": ["gfx6"], 6246 "map": {"at": 165572, "to": "mm"}, 6247 "name": "SPI_VS_OUT_CONFIG", 6248 "type_ref": "SPI_VS_OUT_CONFIG" 6249 }, 6250 { 6251 "chips": ["gfx6"], 6252 "map": {"at": 165580, "to": "mm"}, 6253 "name": "SPI_PS_INPUT_ENA", 6254 "type_ref": "SPI_PS_INPUT_ADDR" 6255 }, 6256 { 6257 "chips": ["gfx6"], 6258 "map": {"at": 165584, "to": "mm"}, 6259 "name": "SPI_PS_INPUT_ADDR", 6260 "type_ref": "SPI_PS_INPUT_ADDR" 6261 }, 6262 { 6263 "chips": ["gfx6"], 6264 "map": {"at": 165588, "to": "mm"}, 6265 "name": "SPI_INTERP_CONTROL_0", 6266 "type_ref": "SPI_INTERP_CONTROL_0" 6267 }, 6268 { 6269 "chips": ["gfx6"], 6270 "map": {"at": 165592, "to": "mm"}, 6271 "name": "SPI_PS_IN_CONTROL", 6272 "type_ref": "SPI_PS_IN_CONTROL" 6273 }, 6274 { 6275 "chips": ["gfx6"], 6276 "map": {"at": 165600, "to": "mm"}, 6277 "name": "SPI_BARYC_CNTL", 6278 "type_ref": "SPI_BARYC_CNTL" 6279 }, 6280 { 6281 "chips": ["gfx6"], 6282 "map": {"at": 165608, "to": "mm"}, 6283 "name": "SPI_TMPRING_SIZE", 6284 "type_ref": "COMPUTE_TMPRING_SIZE" 6285 }, 6286 { 6287 "chips": ["gfx6"], 6288 "map": {"at": 165644, "to": "mm"}, 6289 "name": "SPI_SHADER_POS_FORMAT", 6290 "type_ref": "SPI_SHADER_POS_FORMAT" 6291 }, 6292 { 6293 "chips": ["gfx6"], 6294 "map": {"at": 165648, "to": "mm"}, 6295 "name": "SPI_SHADER_Z_FORMAT", 6296 "type_ref": "SPI_SHADER_Z_FORMAT" 6297 }, 6298 { 6299 "chips": ["gfx6"], 6300 "map": {"at": 165652, "to": "mm"}, 6301 "name": "SPI_SHADER_COL_FORMAT", 6302 "type_ref": "SPI_SHADER_COL_FORMAT" 6303 }, 6304 { 6305 "chips": ["gfx6"], 6306 "map": {"at": 165760, "to": "mm"}, 6307 "name": "CB_BLEND0_CONTROL", 6308 "type_ref": "CB_BLEND0_CONTROL" 6309 }, 6310 { 6311 "chips": ["gfx6"], 6312 "map": {"at": 165764, "to": "mm"}, 6313 "name": "CB_BLEND1_CONTROL", 6314 "type_ref": "CB_BLEND0_CONTROL" 6315 }, 6316 { 6317 "chips": ["gfx6"], 6318 "map": {"at": 165768, "to": "mm"}, 6319 "name": "CB_BLEND2_CONTROL", 6320 "type_ref": "CB_BLEND0_CONTROL" 6321 }, 6322 { 6323 "chips": ["gfx6"], 6324 "map": {"at": 165772, "to": "mm"}, 6325 "name": "CB_BLEND3_CONTROL", 6326 "type_ref": "CB_BLEND0_CONTROL" 6327 }, 6328 { 6329 "chips": ["gfx6"], 6330 "map": {"at": 165776, "to": "mm"}, 6331 "name": "CB_BLEND4_CONTROL", 6332 "type_ref": "CB_BLEND0_CONTROL" 6333 }, 6334 { 6335 "chips": ["gfx6"], 6336 "map": {"at": 165780, "to": "mm"}, 6337 "name": "CB_BLEND5_CONTROL", 6338 "type_ref": "CB_BLEND0_CONTROL" 6339 }, 6340 { 6341 "chips": ["gfx6"], 6342 "map": {"at": 165784, "to": "mm"}, 6343 "name": "CB_BLEND6_CONTROL", 6344 "type_ref": "CB_BLEND0_CONTROL" 6345 }, 6346 { 6347 "chips": ["gfx6"], 6348 "map": {"at": 165788, "to": "mm"}, 6349 "name": "CB_BLEND7_CONTROL", 6350 "type_ref": "CB_BLEND0_CONTROL" 6351 }, 6352 { 6353 "chips": ["gfx6"], 6354 "map": {"at": 165836, "to": "mm"}, 6355 "name": "CS_COPY_STATE", 6356 "type_ref": "CS_COPY_STATE" 6357 }, 6358 { 6359 "chips": ["gfx6"], 6360 "map": {"at": 165840, "to": "mm"}, 6361 "name": "GFX_COPY_STATE", 6362 "type_ref": "CS_COPY_STATE" 6363 }, 6364 { 6365 "chips": ["gfx6"], 6366 "map": {"at": 165844, "to": "mm"}, 6367 "name": "PA_CL_POINT_X_RAD" 6368 }, 6369 { 6370 "chips": ["gfx6"], 6371 "map": {"at": 165848, "to": "mm"}, 6372 "name": "PA_CL_POINT_Y_RAD" 6373 }, 6374 { 6375 "chips": ["gfx6"], 6376 "map": {"at": 165852, "to": "mm"}, 6377 "name": "PA_CL_POINT_SIZE" 6378 }, 6379 { 6380 "chips": ["gfx6"], 6381 "map": {"at": 165856, "to": "mm"}, 6382 "name": "PA_CL_POINT_CULL_RAD" 6383 }, 6384 { 6385 "chips": ["gfx6"], 6386 "map": {"at": 165860, "to": "mm"}, 6387 "name": "VGT_DMA_BASE_HI", 6388 "type_ref": "VGT_DMA_BASE_HI" 6389 }, 6390 { 6391 "chips": ["gfx6"], 6392 "map": {"at": 165864, "to": "mm"}, 6393 "name": "VGT_DMA_BASE" 6394 }, 6395 { 6396 "chips": ["gfx6"], 6397 "map": {"at": 165872, "to": "mm"}, 6398 "name": "VGT_DRAW_INITIATOR", 6399 "type_ref": "VGT_DRAW_INITIATOR" 6400 }, 6401 { 6402 "chips": ["gfx6"], 6403 "map": {"at": 165876, "to": "mm"}, 6404 "name": "VGT_IMMED_DATA" 6405 }, 6406 { 6407 "chips": ["gfx6"], 6408 "map": {"at": 165880, "to": "mm"}, 6409 "name": "VGT_EVENT_ADDRESS_REG", 6410 "type_ref": "VGT_EVENT_ADDRESS_REG" 6411 }, 6412 { 6413 "chips": ["gfx6"], 6414 "map": {"at": 165888, "to": "mm"}, 6415 "name": "DB_DEPTH_CONTROL", 6416 "type_ref": "DB_DEPTH_CONTROL" 6417 }, 6418 { 6419 "chips": ["gfx6"], 6420 "map": {"at": 165892, "to": "mm"}, 6421 "name": "DB_EQAA", 6422 "type_ref": "DB_EQAA" 6423 }, 6424 { 6425 "chips": ["gfx6"], 6426 "map": {"at": 165896, "to": "mm"}, 6427 "name": "CB_COLOR_CONTROL", 6428 "type_ref": "CB_COLOR_CONTROL" 6429 }, 6430 { 6431 "chips": ["gfx6"], 6432 "map": {"at": 165900, "to": "mm"}, 6433 "name": "DB_SHADER_CONTROL", 6434 "type_ref": "DB_SHADER_CONTROL" 6435 }, 6436 { 6437 "chips": ["gfx6"], 6438 "map": {"at": 165904, "to": "mm"}, 6439 "name": "PA_CL_CLIP_CNTL", 6440 "type_ref": "PA_CL_CLIP_CNTL" 6441 }, 6442 { 6443 "chips": ["gfx6"], 6444 "map": {"at": 165908, "to": "mm"}, 6445 "name": "PA_SU_SC_MODE_CNTL", 6446 "type_ref": "PA_SU_SC_MODE_CNTL" 6447 }, 6448 { 6449 "chips": ["gfx6"], 6450 "map": {"at": 165912, "to": "mm"}, 6451 "name": "PA_CL_VTE_CNTL", 6452 "type_ref": "PA_CL_VTE_CNTL" 6453 }, 6454 { 6455 "chips": ["gfx6"], 6456 "map": {"at": 165916, "to": "mm"}, 6457 "name": "PA_CL_VS_OUT_CNTL", 6458 "type_ref": "PA_CL_VS_OUT_CNTL" 6459 }, 6460 { 6461 "chips": ["gfx6"], 6462 "map": {"at": 165920, "to": "mm"}, 6463 "name": "PA_CL_NANINF_CNTL", 6464 "type_ref": "PA_CL_NANINF_CNTL" 6465 }, 6466 { 6467 "chips": ["gfx6"], 6468 "map": {"at": 165924, "to": "mm"}, 6469 "name": "PA_SU_LINE_STIPPLE_CNTL", 6470 "type_ref": "PA_SU_LINE_STIPPLE_CNTL" 6471 }, 6472 { 6473 "chips": ["gfx6"], 6474 "map": {"at": 165928, "to": "mm"}, 6475 "name": "PA_SU_LINE_STIPPLE_SCALE" 6476 }, 6477 { 6478 "chips": ["gfx6"], 6479 "map": {"at": 165932, "to": "mm"}, 6480 "name": "PA_SU_PRIM_FILTER_CNTL", 6481 "type_ref": "PA_SU_PRIM_FILTER_CNTL" 6482 }, 6483 { 6484 "chips": ["gfx6"], 6485 "map": {"at": 166400, "to": "mm"}, 6486 "name": "PA_SU_POINT_SIZE", 6487 "type_ref": "PA_SU_POINT_SIZE" 6488 }, 6489 { 6490 "chips": ["gfx6"], 6491 "map": {"at": 166404, "to": "mm"}, 6492 "name": "PA_SU_POINT_MINMAX", 6493 "type_ref": "PA_SU_POINT_MINMAX" 6494 }, 6495 { 6496 "chips": ["gfx6"], 6497 "map": {"at": 166408, "to": "mm"}, 6498 "name": "PA_SU_LINE_CNTL", 6499 "type_ref": "PA_SU_LINE_CNTL" 6500 }, 6501 { 6502 "chips": ["gfx6"], 6503 "map": {"at": 166412, "to": "mm"}, 6504 "name": "PA_SC_LINE_STIPPLE", 6505 "type_ref": "PA_SC_LINE_STIPPLE" 6506 }, 6507 { 6508 "chips": ["gfx6"], 6509 "map": {"at": 166416, "to": "mm"}, 6510 "name": "VGT_OUTPUT_PATH_CNTL", 6511 "type_ref": "VGT_OUTPUT_PATH_CNTL" 6512 }, 6513 { 6514 "chips": ["gfx6"], 6515 "map": {"at": 166420, "to": "mm"}, 6516 "name": "VGT_HOS_CNTL", 6517 "type_ref": "VGT_HOS_CNTL" 6518 }, 6519 { 6520 "chips": ["gfx6"], 6521 "map": {"at": 166424, "to": "mm"}, 6522 "name": "VGT_HOS_MAX_TESS_LEVEL" 6523 }, 6524 { 6525 "chips": ["gfx6"], 6526 "map": {"at": 166428, "to": "mm"}, 6527 "name": "VGT_HOS_MIN_TESS_LEVEL" 6528 }, 6529 { 6530 "chips": ["gfx6"], 6531 "map": {"at": 166432, "to": "mm"}, 6532 "name": "VGT_HOS_REUSE_DEPTH", 6533 "type_ref": "VGT_HOS_REUSE_DEPTH" 6534 }, 6535 { 6536 "chips": ["gfx6"], 6537 "map": {"at": 166436, "to": "mm"}, 6538 "name": "VGT_GROUP_PRIM_TYPE", 6539 "type_ref": "VGT_GROUP_PRIM_TYPE" 6540 }, 6541 { 6542 "chips": ["gfx6"], 6543 "map": {"at": 166440, "to": "mm"}, 6544 "name": "VGT_GROUP_FIRST_DECR", 6545 "type_ref": "VGT_GROUP_FIRST_DECR" 6546 }, 6547 { 6548 "chips": ["gfx6"], 6549 "map": {"at": 166444, "to": "mm"}, 6550 "name": "VGT_GROUP_DECR", 6551 "type_ref": "VGT_GROUP_DECR" 6552 }, 6553 { 6554 "chips": ["gfx6"], 6555 "map": {"at": 166448, "to": "mm"}, 6556 "name": "VGT_GROUP_VECT_0_CNTL", 6557 "type_ref": "VGT_GROUP_VECT_0_CNTL" 6558 }, 6559 { 6560 "chips": ["gfx6"], 6561 "map": {"at": 166452, "to": "mm"}, 6562 "name": "VGT_GROUP_VECT_1_CNTL", 6563 "type_ref": "VGT_GROUP_VECT_0_CNTL" 6564 }, 6565 { 6566 "chips": ["gfx6"], 6567 "map": {"at": 166456, "to": "mm"}, 6568 "name": "VGT_GROUP_VECT_0_FMT_CNTL", 6569 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 6570 }, 6571 { 6572 "chips": ["gfx6"], 6573 "map": {"at": 166460, "to": "mm"}, 6574 "name": "VGT_GROUP_VECT_1_FMT_CNTL", 6575 "type_ref": "VGT_GROUP_VECT_0_FMT_CNTL" 6576 }, 6577 { 6578 "chips": ["gfx6"], 6579 "map": {"at": 166464, "to": "mm"}, 6580 "name": "VGT_GS_MODE", 6581 "type_ref": "VGT_GS_MODE" 6582 }, 6583 { 6584 "chips": ["gfx6"], 6585 "map": {"at": 166472, "to": "mm"}, 6586 "name": "PA_SC_MODE_CNTL_0", 6587 "type_ref": "PA_SC_MODE_CNTL_0" 6588 }, 6589 { 6590 "chips": ["gfx6"], 6591 "map": {"at": 166476, "to": "mm"}, 6592 "name": "PA_SC_MODE_CNTL_1", 6593 "type_ref": "PA_SC_MODE_CNTL_1" 6594 }, 6595 { 6596 "chips": ["gfx6"], 6597 "map": {"at": 166480, "to": "mm"}, 6598 "name": "VGT_ENHANCE" 6599 }, 6600 { 6601 "chips": ["gfx6"], 6602 "map": {"at": 166484, "to": "mm"}, 6603 "name": "VGT_GS_PER_ES", 6604 "type_ref": "VGT_GS_PER_ES" 6605 }, 6606 { 6607 "chips": ["gfx6"], 6608 "map": {"at": 166488, "to": "mm"}, 6609 "name": "VGT_ES_PER_GS", 6610 "type_ref": "VGT_ES_PER_GS" 6611 }, 6612 { 6613 "chips": ["gfx6"], 6614 "map": {"at": 166492, "to": "mm"}, 6615 "name": "VGT_GS_PER_VS", 6616 "type_ref": "VGT_GS_PER_VS" 6617 }, 6618 { 6619 "chips": ["gfx6"], 6620 "map": {"at": 166496, "to": "mm"}, 6621 "name": "VGT_GSVS_RING_OFFSET_1", 6622 "type_ref": "VGT_GSVS_RING_OFFSET_1" 6623 }, 6624 { 6625 "chips": ["gfx6"], 6626 "map": {"at": 166500, "to": "mm"}, 6627 "name": "VGT_GSVS_RING_OFFSET_2", 6628 "type_ref": "VGT_GSVS_RING_OFFSET_1" 6629 }, 6630 { 6631 "chips": ["gfx6"], 6632 "map": {"at": 166504, "to": "mm"}, 6633 "name": "VGT_GSVS_RING_OFFSET_3", 6634 "type_ref": "VGT_GSVS_RING_OFFSET_1" 6635 }, 6636 { 6637 "chips": ["gfx6"], 6638 "map": {"at": 166508, "to": "mm"}, 6639 "name": "VGT_GS_OUT_PRIM_TYPE", 6640 "type_ref": "VGT_GS_OUT_PRIM_TYPE" 6641 }, 6642 { 6643 "chips": ["gfx6"], 6644 "map": {"at": 166512, "to": "mm"}, 6645 "name": "IA_ENHANCE" 6646 }, 6647 { 6648 "chips": ["gfx6"], 6649 "map": {"at": 166516, "to": "mm"}, 6650 "name": "VGT_DMA_SIZE" 6651 }, 6652 { 6653 "chips": ["gfx6"], 6654 "map": {"at": 166520, "to": "mm"}, 6655 "name": "VGT_DMA_MAX_SIZE" 6656 }, 6657 { 6658 "chips": ["gfx6"], 6659 "map": {"at": 166524, "to": "mm"}, 6660 "name": "VGT_DMA_INDEX_TYPE", 6661 "type_ref": "VGT_DMA_INDEX_TYPE" 6662 }, 6663 { 6664 "chips": ["gfx6"], 6665 "map": {"at": 166532, "to": "mm"}, 6666 "name": "VGT_PRIMITIVEID_EN", 6667 "type_ref": "VGT_PRIMITIVEID_EN" 6668 }, 6669 { 6670 "chips": ["gfx6"], 6671 "map": {"at": 166536, "to": "mm"}, 6672 "name": "VGT_DMA_NUM_INSTANCES" 6673 }, 6674 { 6675 "chips": ["gfx6"], 6676 "map": {"at": 166540, "to": "mm"}, 6677 "name": "VGT_PRIMITIVEID_RESET" 6678 }, 6679 { 6680 "chips": ["gfx6"], 6681 "map": {"at": 166544, "to": "mm"}, 6682 "name": "VGT_EVENT_INITIATOR", 6683 "type_ref": "VGT_EVENT_INITIATOR" 6684 }, 6685 { 6686 "chips": ["gfx6"], 6687 "map": {"at": 166548, "to": "mm"}, 6688 "name": "VGT_MULTI_PRIM_IB_RESET_EN", 6689 "type_ref": "VGT_MULTI_PRIM_IB_RESET_EN" 6690 }, 6691 { 6692 "chips": ["gfx6"], 6693 "map": {"at": 166560, "to": "mm"}, 6694 "name": "VGT_INSTANCE_STEP_RATE_0" 6695 }, 6696 { 6697 "chips": ["gfx6"], 6698 "map": {"at": 166564, "to": "mm"}, 6699 "name": "VGT_INSTANCE_STEP_RATE_1" 6700 }, 6701 { 6702 "chips": ["gfx6"], 6703 "map": {"at": 166568, "to": "mm"}, 6704 "name": "IA_MULTI_VGT_PARAM", 6705 "type_ref": "IA_MULTI_VGT_PARAM" 6706 }, 6707 { 6708 "chips": ["gfx6"], 6709 "map": {"at": 166572, "to": "mm"}, 6710 "name": "VGT_ESGS_RING_ITEMSIZE", 6711 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6712 }, 6713 { 6714 "chips": ["gfx6"], 6715 "map": {"at": 166576, "to": "mm"}, 6716 "name": "VGT_GSVS_RING_ITEMSIZE", 6717 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6718 }, 6719 { 6720 "chips": ["gfx6"], 6721 "map": {"at": 166580, "to": "mm"}, 6722 "name": "VGT_REUSE_OFF", 6723 "type_ref": "VGT_REUSE_OFF" 6724 }, 6725 { 6726 "chips": ["gfx6"], 6727 "map": {"at": 166584, "to": "mm"}, 6728 "name": "VGT_VTX_CNT_EN", 6729 "type_ref": "VGT_VTX_CNT_EN" 6730 }, 6731 { 6732 "chips": ["gfx6"], 6733 "map": {"at": 166588, "to": "mm"}, 6734 "name": "DB_HTILE_SURFACE", 6735 "type_ref": "DB_HTILE_SURFACE" 6736 }, 6737 { 6738 "chips": ["gfx6"], 6739 "map": {"at": 166592, "to": "mm"}, 6740 "name": "DB_SRESULTS_COMPARE_STATE0", 6741 "type_ref": "DB_SRESULTS_COMPARE_STATE0" 6742 }, 6743 { 6744 "chips": ["gfx6"], 6745 "map": {"at": 166596, "to": "mm"}, 6746 "name": "DB_SRESULTS_COMPARE_STATE1", 6747 "type_ref": "DB_SRESULTS_COMPARE_STATE1" 6748 }, 6749 { 6750 "chips": ["gfx6"], 6751 "map": {"at": 166600, "to": "mm"}, 6752 "name": "DB_PRELOAD_CONTROL", 6753 "type_ref": "DB_PRELOAD_CONTROL" 6754 }, 6755 { 6756 "chips": ["gfx6"], 6757 "map": {"at": 166608, "to": "mm"}, 6758 "name": "VGT_STRMOUT_BUFFER_SIZE_0" 6759 }, 6760 { 6761 "chips": ["gfx6"], 6762 "map": {"at": 166612, "to": "mm"}, 6763 "name": "VGT_STRMOUT_VTX_STRIDE_0", 6764 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6765 }, 6766 { 6767 "chips": ["gfx6"], 6768 "map": {"at": 166620, "to": "mm"}, 6769 "name": "VGT_STRMOUT_BUFFER_OFFSET_0" 6770 }, 6771 { 6772 "chips": ["gfx6"], 6773 "map": {"at": 166624, "to": "mm"}, 6774 "name": "VGT_STRMOUT_BUFFER_SIZE_1" 6775 }, 6776 { 6777 "chips": ["gfx6"], 6778 "map": {"at": 166628, "to": "mm"}, 6779 "name": "VGT_STRMOUT_VTX_STRIDE_1", 6780 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6781 }, 6782 { 6783 "chips": ["gfx6"], 6784 "map": {"at": 166636, "to": "mm"}, 6785 "name": "VGT_STRMOUT_BUFFER_OFFSET_1" 6786 }, 6787 { 6788 "chips": ["gfx6"], 6789 "map": {"at": 166640, "to": "mm"}, 6790 "name": "VGT_STRMOUT_BUFFER_SIZE_2" 6791 }, 6792 { 6793 "chips": ["gfx6"], 6794 "map": {"at": 166644, "to": "mm"}, 6795 "name": "VGT_STRMOUT_VTX_STRIDE_2", 6796 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6797 }, 6798 { 6799 "chips": ["gfx6"], 6800 "map": {"at": 166652, "to": "mm"}, 6801 "name": "VGT_STRMOUT_BUFFER_OFFSET_2" 6802 }, 6803 { 6804 "chips": ["gfx6"], 6805 "map": {"at": 166656, "to": "mm"}, 6806 "name": "VGT_STRMOUT_BUFFER_SIZE_3" 6807 }, 6808 { 6809 "chips": ["gfx6"], 6810 "map": {"at": 166660, "to": "mm"}, 6811 "name": "VGT_STRMOUT_VTX_STRIDE_3", 6812 "type_ref": "VGT_STRMOUT_VTX_STRIDE_0" 6813 }, 6814 { 6815 "chips": ["gfx6"], 6816 "map": {"at": 166668, "to": "mm"}, 6817 "name": "VGT_STRMOUT_BUFFER_OFFSET_3" 6818 }, 6819 { 6820 "chips": ["gfx6"], 6821 "map": {"at": 166696, "to": "mm"}, 6822 "name": "VGT_STRMOUT_DRAW_OPAQUE_OFFSET" 6823 }, 6824 { 6825 "chips": ["gfx6"], 6826 "map": {"at": 166700, "to": "mm"}, 6827 "name": "VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE" 6828 }, 6829 { 6830 "chips": ["gfx6"], 6831 "map": {"at": 166704, "to": "mm"}, 6832 "name": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", 6833 "type_ref": "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE" 6834 }, 6835 { 6836 "chips": ["gfx6"], 6837 "map": {"at": 166712, "to": "mm"}, 6838 "name": "VGT_GS_MAX_VERT_OUT", 6839 "type_ref": "VGT_GS_MAX_VERT_OUT" 6840 }, 6841 { 6842 "chips": ["gfx6"], 6843 "map": {"at": 166740, "to": "mm"}, 6844 "name": "VGT_SHADER_STAGES_EN", 6845 "type_ref": "VGT_SHADER_STAGES_EN" 6846 }, 6847 { 6848 "chips": ["gfx6"], 6849 "map": {"at": 166744, "to": "mm"}, 6850 "name": "VGT_LS_HS_CONFIG", 6851 "type_ref": "VGT_LS_HS_CONFIG" 6852 }, 6853 { 6854 "chips": ["gfx6"], 6855 "map": {"at": 166748, "to": "mm"}, 6856 "name": "VGT_GS_VERT_ITEMSIZE", 6857 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6858 }, 6859 { 6860 "chips": ["gfx6"], 6861 "map": {"at": 166752, "to": "mm"}, 6862 "name": "VGT_GS_VERT_ITEMSIZE_1", 6863 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6864 }, 6865 { 6866 "chips": ["gfx6"], 6867 "map": {"at": 166756, "to": "mm"}, 6868 "name": "VGT_GS_VERT_ITEMSIZE_2", 6869 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6870 }, 6871 { 6872 "chips": ["gfx6"], 6873 "map": {"at": 166760, "to": "mm"}, 6874 "name": "VGT_GS_VERT_ITEMSIZE_3", 6875 "type_ref": "VGT_ESGS_RING_ITEMSIZE" 6876 }, 6877 { 6878 "chips": ["gfx6"], 6879 "map": {"at": 166764, "to": "mm"}, 6880 "name": "VGT_TF_PARAM", 6881 "type_ref": "VGT_TF_PARAM" 6882 }, 6883 { 6884 "chips": ["gfx6"], 6885 "map": {"at": 166768, "to": "mm"}, 6886 "name": "DB_ALPHA_TO_MASK", 6887 "type_ref": "DB_ALPHA_TO_MASK" 6888 }, 6889 { 6890 "chips": ["gfx6"], 6891 "map": {"at": 166776, "to": "mm"}, 6892 "name": "PA_SU_POLY_OFFSET_DB_FMT_CNTL", 6893 "type_ref": "PA_SU_POLY_OFFSET_DB_FMT_CNTL" 6894 }, 6895 { 6896 "chips": ["gfx6"], 6897 "map": {"at": 166780, "to": "mm"}, 6898 "name": "PA_SU_POLY_OFFSET_CLAMP" 6899 }, 6900 { 6901 "chips": ["gfx6"], 6902 "map": {"at": 166784, "to": "mm"}, 6903 "name": "PA_SU_POLY_OFFSET_FRONT_SCALE" 6904 }, 6905 { 6906 "chips": ["gfx6"], 6907 "map": {"at": 166788, "to": "mm"}, 6908 "name": "PA_SU_POLY_OFFSET_FRONT_OFFSET" 6909 }, 6910 { 6911 "chips": ["gfx6"], 6912 "map": {"at": 166792, "to": "mm"}, 6913 "name": "PA_SU_POLY_OFFSET_BACK_SCALE" 6914 }, 6915 { 6916 "chips": ["gfx6"], 6917 "map": {"at": 166796, "to": "mm"}, 6918 "name": "PA_SU_POLY_OFFSET_BACK_OFFSET" 6919 }, 6920 { 6921 "chips": ["gfx6"], 6922 "map": {"at": 166800, "to": "mm"}, 6923 "name": "VGT_GS_INSTANCE_CNT", 6924 "type_ref": "VGT_GS_INSTANCE_CNT" 6925 }, 6926 { 6927 "chips": ["gfx6"], 6928 "map": {"at": 166804, "to": "mm"}, 6929 "name": "VGT_STRMOUT_CONFIG", 6930 "type_ref": "VGT_STRMOUT_CONFIG" 6931 }, 6932 { 6933 "chips": ["gfx6"], 6934 "map": {"at": 166808, "to": "mm"}, 6935 "name": "VGT_STRMOUT_BUFFER_CONFIG", 6936 "type_ref": "VGT_STRMOUT_BUFFER_CONFIG" 6937 }, 6938 { 6939 "chips": ["gfx6"], 6940 "map": {"at": 166868, "to": "mm"}, 6941 "name": "PA_SC_CENTROID_PRIORITY_0", 6942 "type_ref": "PA_SC_CENTROID_PRIORITY_0" 6943 }, 6944 { 6945 "chips": ["gfx6"], 6946 "map": {"at": 166872, "to": "mm"}, 6947 "name": "PA_SC_CENTROID_PRIORITY_1", 6948 "type_ref": "PA_SC_CENTROID_PRIORITY_1" 6949 }, 6950 { 6951 "chips": ["gfx6"], 6952 "map": {"at": 166876, "to": "mm"}, 6953 "name": "PA_SC_LINE_CNTL", 6954 "type_ref": "PA_SC_LINE_CNTL" 6955 }, 6956 { 6957 "chips": ["gfx6"], 6958 "map": {"at": 166880, "to": "mm"}, 6959 "name": "PA_SC_AA_CONFIG", 6960 "type_ref": "PA_SC_AA_CONFIG" 6961 }, 6962 { 6963 "chips": ["gfx6"], 6964 "map": {"at": 166884, "to": "mm"}, 6965 "name": "PA_SU_VTX_CNTL", 6966 "type_ref": "PA_SU_VTX_CNTL" 6967 }, 6968 { 6969 "chips": ["gfx6"], 6970 "map": {"at": 166888, "to": "mm"}, 6971 "name": "PA_CL_GB_VERT_CLIP_ADJ" 6972 }, 6973 { 6974 "chips": ["gfx6"], 6975 "map": {"at": 166892, "to": "mm"}, 6976 "name": "PA_CL_GB_VERT_DISC_ADJ" 6977 }, 6978 { 6979 "chips": ["gfx6"], 6980 "map": {"at": 166896, "to": "mm"}, 6981 "name": "PA_CL_GB_HORZ_CLIP_ADJ" 6982 }, 6983 { 6984 "chips": ["gfx6"], 6985 "map": {"at": 166900, "to": "mm"}, 6986 "name": "PA_CL_GB_HORZ_DISC_ADJ" 6987 }, 6988 { 6989 "chips": ["gfx6"], 6990 "map": {"at": 166904, "to": "mm"}, 6991 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", 6992 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 6993 }, 6994 { 6995 "chips": ["gfx6"], 6996 "map": {"at": 166908, "to": "mm"}, 6997 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", 6998 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 6999 }, 7000 { 7001 "chips": ["gfx6"], 7002 "map": {"at": 166912, "to": "mm"}, 7003 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", 7004 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7005 }, 7006 { 7007 "chips": ["gfx6"], 7008 "map": {"at": 166916, "to": "mm"}, 7009 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", 7010 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7011 }, 7012 { 7013 "chips": ["gfx6"], 7014 "map": {"at": 166920, "to": "mm"}, 7015 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", 7016 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7017 }, 7018 { 7019 "chips": ["gfx6"], 7020 "map": {"at": 166924, "to": "mm"}, 7021 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", 7022 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7023 }, 7024 { 7025 "chips": ["gfx6"], 7026 "map": {"at": 166928, "to": "mm"}, 7027 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", 7028 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7029 }, 7030 { 7031 "chips": ["gfx6"], 7032 "map": {"at": 166932, "to": "mm"}, 7033 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", 7034 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7035 }, 7036 { 7037 "chips": ["gfx6"], 7038 "map": {"at": 166936, "to": "mm"}, 7039 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", 7040 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7041 }, 7042 { 7043 "chips": ["gfx6"], 7044 "map": {"at": 166940, "to": "mm"}, 7045 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", 7046 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7047 }, 7048 { 7049 "chips": ["gfx6"], 7050 "map": {"at": 166944, "to": "mm"}, 7051 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", 7052 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7053 }, 7054 { 7055 "chips": ["gfx6"], 7056 "map": {"at": 166948, "to": "mm"}, 7057 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", 7058 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7059 }, 7060 { 7061 "chips": ["gfx6"], 7062 "map": {"at": 166952, "to": "mm"}, 7063 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", 7064 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0" 7065 }, 7066 { 7067 "chips": ["gfx6"], 7068 "map": {"at": 166956, "to": "mm"}, 7069 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", 7070 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1" 7071 }, 7072 { 7073 "chips": ["gfx6"], 7074 "map": {"at": 166960, "to": "mm"}, 7075 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", 7076 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2" 7077 }, 7078 { 7079 "chips": ["gfx6"], 7080 "map": {"at": 166964, "to": "mm"}, 7081 "name": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", 7082 "type_ref": "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3" 7083 }, 7084 { 7085 "chips": ["gfx6"], 7086 "map": {"at": 166968, "to": "mm"}, 7087 "name": "PA_SC_AA_MASK_X0Y0_X1Y0", 7088 "type_ref": "PA_SC_AA_MASK_X0Y0_X1Y0" 7089 }, 7090 { 7091 "chips": ["gfx6"], 7092 "map": {"at": 166972, "to": "mm"}, 7093 "name": "PA_SC_AA_MASK_X0Y1_X1Y1", 7094 "type_ref": "PA_SC_AA_MASK_X0Y1_X1Y1" 7095 }, 7096 { 7097 "chips": ["gfx6"], 7098 "map": {"at": 167000, "to": "mm"}, 7099 "name": "VGT_VERTEX_REUSE_BLOCK_CNTL", 7100 "type_ref": "VGT_VERTEX_REUSE_BLOCK_CNTL" 7101 }, 7102 { 7103 "chips": ["gfx6"], 7104 "map": {"at": 167004, "to": "mm"}, 7105 "name": "VGT_OUT_DEALLOC_CNTL", 7106 "type_ref": "VGT_OUT_DEALLOC_CNTL" 7107 }, 7108 { 7109 "chips": ["gfx6"], 7110 "map": {"at": 167008, "to": "mm"}, 7111 "name": "CB_COLOR0_BASE" 7112 }, 7113 { 7114 "chips": ["gfx6"], 7115 "map": {"at": 167012, "to": "mm"}, 7116 "name": "CB_COLOR0_PITCH", 7117 "type_ref": "CB_COLOR0_PITCH" 7118 }, 7119 { 7120 "chips": ["gfx6"], 7121 "map": {"at": 167016, "to": "mm"}, 7122 "name": "CB_COLOR0_SLICE", 7123 "type_ref": "CB_COLOR0_FMASK_SLICE" 7124 }, 7125 { 7126 "chips": ["gfx6"], 7127 "map": {"at": 167020, "to": "mm"}, 7128 "name": "CB_COLOR0_VIEW", 7129 "type_ref": "CB_COLOR0_VIEW" 7130 }, 7131 { 7132 "chips": ["gfx6"], 7133 "map": {"at": 167024, "to": "mm"}, 7134 "name": "CB_COLOR0_INFO", 7135 "type_ref": "CB_COLOR0_INFO" 7136 }, 7137 { 7138 "chips": ["gfx6"], 7139 "map": {"at": 167028, "to": "mm"}, 7140 "name": "CB_COLOR0_ATTRIB", 7141 "type_ref": "CB_COLOR0_ATTRIB" 7142 }, 7143 { 7144 "chips": ["gfx6"], 7145 "map": {"at": 167036, "to": "mm"}, 7146 "name": "CB_COLOR0_CMASK" 7147 }, 7148 { 7149 "chips": ["gfx6"], 7150 "map": {"at": 167040, "to": "mm"}, 7151 "name": "CB_COLOR0_CMASK_SLICE", 7152 "type_ref": "CB_COLOR0_CMASK_SLICE" 7153 }, 7154 { 7155 "chips": ["gfx6"], 7156 "map": {"at": 167044, "to": "mm"}, 7157 "name": "CB_COLOR0_FMASK" 7158 }, 7159 { 7160 "chips": ["gfx6"], 7161 "map": {"at": 167048, "to": "mm"}, 7162 "name": "CB_COLOR0_FMASK_SLICE", 7163 "type_ref": "CB_COLOR0_FMASK_SLICE" 7164 }, 7165 { 7166 "chips": ["gfx6"], 7167 "map": {"at": 167052, "to": "mm"}, 7168 "name": "CB_COLOR0_CLEAR_WORD0" 7169 }, 7170 { 7171 "chips": ["gfx6"], 7172 "map": {"at": 167056, "to": "mm"}, 7173 "name": "CB_COLOR0_CLEAR_WORD1" 7174 }, 7175 { 7176 "chips": ["gfx6"], 7177 "map": {"at": 167068, "to": "mm"}, 7178 "name": "CB_COLOR1_BASE" 7179 }, 7180 { 7181 "chips": ["gfx6"], 7182 "map": {"at": 167072, "to": "mm"}, 7183 "name": "CB_COLOR1_PITCH", 7184 "type_ref": "CB_COLOR0_PITCH" 7185 }, 7186 { 7187 "chips": ["gfx6"], 7188 "map": {"at": 167076, "to": "mm"}, 7189 "name": "CB_COLOR1_SLICE", 7190 "type_ref": "CB_COLOR0_FMASK_SLICE" 7191 }, 7192 { 7193 "chips": ["gfx6"], 7194 "map": {"at": 167080, "to": "mm"}, 7195 "name": "CB_COLOR1_VIEW", 7196 "type_ref": "CB_COLOR0_VIEW" 7197 }, 7198 { 7199 "chips": ["gfx6"], 7200 "map": {"at": 167084, "to": "mm"}, 7201 "name": "CB_COLOR1_INFO", 7202 "type_ref": "CB_COLOR0_INFO" 7203 }, 7204 { 7205 "chips": ["gfx6"], 7206 "map": {"at": 167088, "to": "mm"}, 7207 "name": "CB_COLOR1_ATTRIB", 7208 "type_ref": "CB_COLOR0_ATTRIB" 7209 }, 7210 { 7211 "chips": ["gfx6"], 7212 "map": {"at": 167096, "to": "mm"}, 7213 "name": "CB_COLOR1_CMASK" 7214 }, 7215 { 7216 "chips": ["gfx6"], 7217 "map": {"at": 167100, "to": "mm"}, 7218 "name": "CB_COLOR1_CMASK_SLICE", 7219 "type_ref": "CB_COLOR0_CMASK_SLICE" 7220 }, 7221 { 7222 "chips": ["gfx6"], 7223 "map": {"at": 167104, "to": "mm"}, 7224 "name": "CB_COLOR1_FMASK" 7225 }, 7226 { 7227 "chips": ["gfx6"], 7228 "map": {"at": 167108, "to": "mm"}, 7229 "name": "CB_COLOR1_FMASK_SLICE", 7230 "type_ref": "CB_COLOR0_FMASK_SLICE" 7231 }, 7232 { 7233 "chips": ["gfx6"], 7234 "map": {"at": 167112, "to": "mm"}, 7235 "name": "CB_COLOR1_CLEAR_WORD0" 7236 }, 7237 { 7238 "chips": ["gfx6"], 7239 "map": {"at": 167116, "to": "mm"}, 7240 "name": "CB_COLOR1_CLEAR_WORD1" 7241 }, 7242 { 7243 "chips": ["gfx6"], 7244 "map": {"at": 167128, "to": "mm"}, 7245 "name": "CB_COLOR2_BASE" 7246 }, 7247 { 7248 "chips": ["gfx6"], 7249 "map": {"at": 167132, "to": "mm"}, 7250 "name": "CB_COLOR2_PITCH", 7251 "type_ref": "CB_COLOR0_PITCH" 7252 }, 7253 { 7254 "chips": ["gfx6"], 7255 "map": {"at": 167136, "to": "mm"}, 7256 "name": "CB_COLOR2_SLICE", 7257 "type_ref": "CB_COLOR0_FMASK_SLICE" 7258 }, 7259 { 7260 "chips": ["gfx6"], 7261 "map": {"at": 167140, "to": "mm"}, 7262 "name": "CB_COLOR2_VIEW", 7263 "type_ref": "CB_COLOR0_VIEW" 7264 }, 7265 { 7266 "chips": ["gfx6"], 7267 "map": {"at": 167144, "to": "mm"}, 7268 "name": "CB_COLOR2_INFO", 7269 "type_ref": "CB_COLOR0_INFO" 7270 }, 7271 { 7272 "chips": ["gfx6"], 7273 "map": {"at": 167148, "to": "mm"}, 7274 "name": "CB_COLOR2_ATTRIB", 7275 "type_ref": "CB_COLOR0_ATTRIB" 7276 }, 7277 { 7278 "chips": ["gfx6"], 7279 "map": {"at": 167156, "to": "mm"}, 7280 "name": "CB_COLOR2_CMASK" 7281 }, 7282 { 7283 "chips": ["gfx6"], 7284 "map": {"at": 167160, "to": "mm"}, 7285 "name": "CB_COLOR2_CMASK_SLICE", 7286 "type_ref": "CB_COLOR0_CMASK_SLICE" 7287 }, 7288 { 7289 "chips": ["gfx6"], 7290 "map": {"at": 167164, "to": "mm"}, 7291 "name": "CB_COLOR2_FMASK" 7292 }, 7293 { 7294 "chips": ["gfx6"], 7295 "map": {"at": 167168, "to": "mm"}, 7296 "name": "CB_COLOR2_FMASK_SLICE", 7297 "type_ref": "CB_COLOR0_FMASK_SLICE" 7298 }, 7299 { 7300 "chips": ["gfx6"], 7301 "map": {"at": 167172, "to": "mm"}, 7302 "name": "CB_COLOR2_CLEAR_WORD0" 7303 }, 7304 { 7305 "chips": ["gfx6"], 7306 "map": {"at": 167176, "to": "mm"}, 7307 "name": "CB_COLOR2_CLEAR_WORD1" 7308 }, 7309 { 7310 "chips": ["gfx6"], 7311 "map": {"at": 167188, "to": "mm"}, 7312 "name": "CB_COLOR3_BASE" 7313 }, 7314 { 7315 "chips": ["gfx6"], 7316 "map": {"at": 167192, "to": "mm"}, 7317 "name": "CB_COLOR3_PITCH", 7318 "type_ref": "CB_COLOR0_PITCH" 7319 }, 7320 { 7321 "chips": ["gfx6"], 7322 "map": {"at": 167196, "to": "mm"}, 7323 "name": "CB_COLOR3_SLICE", 7324 "type_ref": "CB_COLOR0_FMASK_SLICE" 7325 }, 7326 { 7327 "chips": ["gfx6"], 7328 "map": {"at": 167200, "to": "mm"}, 7329 "name": "CB_COLOR3_VIEW", 7330 "type_ref": "CB_COLOR0_VIEW" 7331 }, 7332 { 7333 "chips": ["gfx6"], 7334 "map": {"at": 167204, "to": "mm"}, 7335 "name": "CB_COLOR3_INFO", 7336 "type_ref": "CB_COLOR0_INFO" 7337 }, 7338 { 7339 "chips": ["gfx6"], 7340 "map": {"at": 167208, "to": "mm"}, 7341 "name": "CB_COLOR3_ATTRIB", 7342 "type_ref": "CB_COLOR0_ATTRIB" 7343 }, 7344 { 7345 "chips": ["gfx6"], 7346 "map": {"at": 167216, "to": "mm"}, 7347 "name": "CB_COLOR3_CMASK" 7348 }, 7349 { 7350 "chips": ["gfx6"], 7351 "map": {"at": 167220, "to": "mm"}, 7352 "name": "CB_COLOR3_CMASK_SLICE", 7353 "type_ref": "CB_COLOR0_CMASK_SLICE" 7354 }, 7355 { 7356 "chips": ["gfx6"], 7357 "map": {"at": 167224, "to": "mm"}, 7358 "name": "CB_COLOR3_FMASK" 7359 }, 7360 { 7361 "chips": ["gfx6"], 7362 "map": {"at": 167228, "to": "mm"}, 7363 "name": "CB_COLOR3_FMASK_SLICE", 7364 "type_ref": "CB_COLOR0_FMASK_SLICE" 7365 }, 7366 { 7367 "chips": ["gfx6"], 7368 "map": {"at": 167232, "to": "mm"}, 7369 "name": "CB_COLOR3_CLEAR_WORD0" 7370 }, 7371 { 7372 "chips": ["gfx6"], 7373 "map": {"at": 167236, "to": "mm"}, 7374 "name": "CB_COLOR3_CLEAR_WORD1" 7375 }, 7376 { 7377 "chips": ["gfx6"], 7378 "map": {"at": 167248, "to": "mm"}, 7379 "name": "CB_COLOR4_BASE" 7380 }, 7381 { 7382 "chips": ["gfx6"], 7383 "map": {"at": 167252, "to": "mm"}, 7384 "name": "CB_COLOR4_PITCH", 7385 "type_ref": "CB_COLOR0_PITCH" 7386 }, 7387 { 7388 "chips": ["gfx6"], 7389 "map": {"at": 167256, "to": "mm"}, 7390 "name": "CB_COLOR4_SLICE", 7391 "type_ref": "CB_COLOR0_FMASK_SLICE" 7392 }, 7393 { 7394 "chips": ["gfx6"], 7395 "map": {"at": 167260, "to": "mm"}, 7396 "name": "CB_COLOR4_VIEW", 7397 "type_ref": "CB_COLOR0_VIEW" 7398 }, 7399 { 7400 "chips": ["gfx6"], 7401 "map": {"at": 167264, "to": "mm"}, 7402 "name": "CB_COLOR4_INFO", 7403 "type_ref": "CB_COLOR0_INFO" 7404 }, 7405 { 7406 "chips": ["gfx6"], 7407 "map": {"at": 167268, "to": "mm"}, 7408 "name": "CB_COLOR4_ATTRIB", 7409 "type_ref": "CB_COLOR0_ATTRIB" 7410 }, 7411 { 7412 "chips": ["gfx6"], 7413 "map": {"at": 167276, "to": "mm"}, 7414 "name": "CB_COLOR4_CMASK" 7415 }, 7416 { 7417 "chips": ["gfx6"], 7418 "map": {"at": 167280, "to": "mm"}, 7419 "name": "CB_COLOR4_CMASK_SLICE", 7420 "type_ref": "CB_COLOR0_CMASK_SLICE" 7421 }, 7422 { 7423 "chips": ["gfx6"], 7424 "map": {"at": 167284, "to": "mm"}, 7425 "name": "CB_COLOR4_FMASK" 7426 }, 7427 { 7428 "chips": ["gfx6"], 7429 "map": {"at": 167288, "to": "mm"}, 7430 "name": "CB_COLOR4_FMASK_SLICE", 7431 "type_ref": "CB_COLOR0_FMASK_SLICE" 7432 }, 7433 { 7434 "chips": ["gfx6"], 7435 "map": {"at": 167292, "to": "mm"}, 7436 "name": "CB_COLOR4_CLEAR_WORD0" 7437 }, 7438 { 7439 "chips": ["gfx6"], 7440 "map": {"at": 167296, "to": "mm"}, 7441 "name": "CB_COLOR4_CLEAR_WORD1" 7442 }, 7443 { 7444 "chips": ["gfx6"], 7445 "map": {"at": 167308, "to": "mm"}, 7446 "name": "CB_COLOR5_BASE" 7447 }, 7448 { 7449 "chips": ["gfx6"], 7450 "map": {"at": 167312, "to": "mm"}, 7451 "name": "CB_COLOR5_PITCH", 7452 "type_ref": "CB_COLOR0_PITCH" 7453 }, 7454 { 7455 "chips": ["gfx6"], 7456 "map": {"at": 167316, "to": "mm"}, 7457 "name": "CB_COLOR5_SLICE", 7458 "type_ref": "CB_COLOR0_FMASK_SLICE" 7459 }, 7460 { 7461 "chips": ["gfx6"], 7462 "map": {"at": 167320, "to": "mm"}, 7463 "name": "CB_COLOR5_VIEW", 7464 "type_ref": "CB_COLOR0_VIEW" 7465 }, 7466 { 7467 "chips": ["gfx6"], 7468 "map": {"at": 167324, "to": "mm"}, 7469 "name": "CB_COLOR5_INFO", 7470 "type_ref": "CB_COLOR0_INFO" 7471 }, 7472 { 7473 "chips": ["gfx6"], 7474 "map": {"at": 167328, "to": "mm"}, 7475 "name": "CB_COLOR5_ATTRIB", 7476 "type_ref": "CB_COLOR0_ATTRIB" 7477 }, 7478 { 7479 "chips": ["gfx6"], 7480 "map": {"at": 167336, "to": "mm"}, 7481 "name": "CB_COLOR5_CMASK" 7482 }, 7483 { 7484 "chips": ["gfx6"], 7485 "map": {"at": 167340, "to": "mm"}, 7486 "name": "CB_COLOR5_CMASK_SLICE", 7487 "type_ref": "CB_COLOR0_CMASK_SLICE" 7488 }, 7489 { 7490 "chips": ["gfx6"], 7491 "map": {"at": 167344, "to": "mm"}, 7492 "name": "CB_COLOR5_FMASK" 7493 }, 7494 { 7495 "chips": ["gfx6"], 7496 "map": {"at": 167348, "to": "mm"}, 7497 "name": "CB_COLOR5_FMASK_SLICE", 7498 "type_ref": "CB_COLOR0_FMASK_SLICE" 7499 }, 7500 { 7501 "chips": ["gfx6"], 7502 "map": {"at": 167352, "to": "mm"}, 7503 "name": "CB_COLOR5_CLEAR_WORD0" 7504 }, 7505 { 7506 "chips": ["gfx6"], 7507 "map": {"at": 167356, "to": "mm"}, 7508 "name": "CB_COLOR5_CLEAR_WORD1" 7509 }, 7510 { 7511 "chips": ["gfx6"], 7512 "map": {"at": 167368, "to": "mm"}, 7513 "name": "CB_COLOR6_BASE" 7514 }, 7515 { 7516 "chips": ["gfx6"], 7517 "map": {"at": 167372, "to": "mm"}, 7518 "name": "CB_COLOR6_PITCH", 7519 "type_ref": "CB_COLOR0_PITCH" 7520 }, 7521 { 7522 "chips": ["gfx6"], 7523 "map": {"at": 167376, "to": "mm"}, 7524 "name": "CB_COLOR6_SLICE", 7525 "type_ref": "CB_COLOR0_FMASK_SLICE" 7526 }, 7527 { 7528 "chips": ["gfx6"], 7529 "map": {"at": 167380, "to": "mm"}, 7530 "name": "CB_COLOR6_VIEW", 7531 "type_ref": "CB_COLOR0_VIEW" 7532 }, 7533 { 7534 "chips": ["gfx6"], 7535 "map": {"at": 167384, "to": "mm"}, 7536 "name": "CB_COLOR6_INFO", 7537 "type_ref": "CB_COLOR0_INFO" 7538 }, 7539 { 7540 "chips": ["gfx6"], 7541 "map": {"at": 167388, "to": "mm"}, 7542 "name": "CB_COLOR6_ATTRIB", 7543 "type_ref": "CB_COLOR0_ATTRIB" 7544 }, 7545 { 7546 "chips": ["gfx6"], 7547 "map": {"at": 167396, "to": "mm"}, 7548 "name": "CB_COLOR6_CMASK" 7549 }, 7550 { 7551 "chips": ["gfx6"], 7552 "map": {"at": 167400, "to": "mm"}, 7553 "name": "CB_COLOR6_CMASK_SLICE", 7554 "type_ref": "CB_COLOR0_CMASK_SLICE" 7555 }, 7556 { 7557 "chips": ["gfx6"], 7558 "map": {"at": 167404, "to": "mm"}, 7559 "name": "CB_COLOR6_FMASK" 7560 }, 7561 { 7562 "chips": ["gfx6"], 7563 "map": {"at": 167408, "to": "mm"}, 7564 "name": "CB_COLOR6_FMASK_SLICE", 7565 "type_ref": "CB_COLOR0_FMASK_SLICE" 7566 }, 7567 { 7568 "chips": ["gfx6"], 7569 "map": {"at": 167412, "to": "mm"}, 7570 "name": "CB_COLOR6_CLEAR_WORD0" 7571 }, 7572 { 7573 "chips": ["gfx6"], 7574 "map": {"at": 167416, "to": "mm"}, 7575 "name": "CB_COLOR6_CLEAR_WORD1" 7576 }, 7577 { 7578 "chips": ["gfx6"], 7579 "map": {"at": 167428, "to": "mm"}, 7580 "name": "CB_COLOR7_BASE" 7581 }, 7582 { 7583 "chips": ["gfx6"], 7584 "map": {"at": 167432, "to": "mm"}, 7585 "name": "CB_COLOR7_PITCH", 7586 "type_ref": "CB_COLOR0_PITCH" 7587 }, 7588 { 7589 "chips": ["gfx6"], 7590 "map": {"at": 167436, "to": "mm"}, 7591 "name": "CB_COLOR7_SLICE", 7592 "type_ref": "CB_COLOR0_FMASK_SLICE" 7593 }, 7594 { 7595 "chips": ["gfx6"], 7596 "map": {"at": 167440, "to": "mm"}, 7597 "name": "CB_COLOR7_VIEW", 7598 "type_ref": "CB_COLOR0_VIEW" 7599 }, 7600 { 7601 "chips": ["gfx6"], 7602 "map": {"at": 167444, "to": "mm"}, 7603 "name": "CB_COLOR7_INFO", 7604 "type_ref": "CB_COLOR0_INFO" 7605 }, 7606 { 7607 "chips": ["gfx6"], 7608 "map": {"at": 167448, "to": "mm"}, 7609 "name": "CB_COLOR7_ATTRIB", 7610 "type_ref": "CB_COLOR0_ATTRIB" 7611 }, 7612 { 7613 "chips": ["gfx6"], 7614 "map": {"at": 167456, "to": "mm"}, 7615 "name": "CB_COLOR7_CMASK" 7616 }, 7617 { 7618 "chips": ["gfx6"], 7619 "map": {"at": 167460, "to": "mm"}, 7620 "name": "CB_COLOR7_CMASK_SLICE", 7621 "type_ref": "CB_COLOR0_CMASK_SLICE" 7622 }, 7623 { 7624 "chips": ["gfx6"], 7625 "map": {"at": 167464, "to": "mm"}, 7626 "name": "CB_COLOR7_FMASK" 7627 }, 7628 { 7629 "chips": ["gfx6"], 7630 "map": {"at": 167468, "to": "mm"}, 7631 "name": "CB_COLOR7_FMASK_SLICE", 7632 "type_ref": "CB_COLOR0_FMASK_SLICE" 7633 }, 7634 { 7635 "chips": ["gfx6"], 7636 "map": {"at": 167472, "to": "mm"}, 7637 "name": "CB_COLOR7_CLEAR_WORD0" 7638 }, 7639 { 7640 "chips": ["gfx6"], 7641 "map": {"at": 167476, "to": "mm"}, 7642 "name": "CB_COLOR7_CLEAR_WORD1" 7643 } 7644 ], 7645 "register_types": { 7646 "CB_BLEND0_CONTROL": { 7647 "fields": [ 7648 {"bits": [0, 4], "enum_ref": "BlendOp", "name": "COLOR_SRCBLEND"}, 7649 {"bits": [5, 7], "enum_ref": "CombFunc", "name": "COLOR_COMB_FCN"}, 7650 {"bits": [8, 12], "enum_ref": "BlendOp", "name": "COLOR_DESTBLEND"}, 7651 {"bits": [16, 20], "enum_ref": "BlendOp", "name": "ALPHA_SRCBLEND"}, 7652 {"bits": [21, 23], "enum_ref": "CombFunc", "name": "ALPHA_COMB_FCN"}, 7653 {"bits": [24, 28], "enum_ref": "BlendOp", "name": "ALPHA_DESTBLEND"}, 7654 {"bits": [29, 29], "name": "SEPARATE_ALPHA_BLEND"}, 7655 {"bits": [30, 30], "name": "ENABLE"}, 7656 {"bits": [31, 31], "name": "DISABLE_ROP3"} 7657 ] 7658 }, 7659 "CB_COLOR0_ATTRIB": { 7660 "fields": [ 7661 {"bits": [0, 4], "name": "TILE_MODE_INDEX"}, 7662 {"bits": [5, 9], "name": "FMASK_TILE_MODE_INDEX"}, 7663 {"bits": [10, 11], "name": "FMASK_BANK_HEIGHT"}, 7664 {"bits": [12, 14], "name": "NUM_SAMPLES"}, 7665 {"bits": [15, 16], "name": "NUM_FRAGMENTS"}, 7666 {"bits": [17, 17], "name": "FORCE_DST_ALPHA_1"} 7667 ] 7668 }, 7669 "CB_COLOR0_CMASK_SLICE": { 7670 "fields": [ 7671 {"bits": [0, 13], "name": "TILE_MAX"} 7672 ] 7673 }, 7674 "CB_COLOR0_FMASK_SLICE": { 7675 "fields": [ 7676 {"bits": [0, 21], "name": "TILE_MAX"} 7677 ] 7678 }, 7679 "CB_COLOR0_INFO": { 7680 "fields": [ 7681 {"bits": [0, 1], "enum_ref": "SurfaceEndian", "name": "ENDIAN"}, 7682 {"bits": [2, 6], "enum_ref": "ColorFormat", "name": "FORMAT"}, 7683 {"bits": [7, 7], "name": "LINEAR_GENERAL"}, 7684 {"bits": [8, 10], "enum_ref": "SurfaceNumber", "name": "NUMBER_TYPE"}, 7685 {"bits": [11, 12], "enum_ref": "SurfaceSwap", "name": "COMP_SWAP"}, 7686 {"bits": [13, 13], "name": "FAST_CLEAR"}, 7687 {"bits": [14, 14], "name": "COMPRESSION"}, 7688 {"bits": [15, 15], "name": "BLEND_CLAMP"}, 7689 {"bits": [16, 16], "name": "BLEND_BYPASS"}, 7690 {"bits": [17, 17], "name": "SIMPLE_FLOAT"}, 7691 {"bits": [18, 18], "name": "ROUND_MODE"}, 7692 {"bits": [19, 19], "name": "CMASK_IS_LINEAR"}, 7693 {"bits": [20, 22], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DONT_RD_DST"}, 7694 {"bits": [23, 25], "enum_ref": "BlendOpt", "name": "BLEND_OPT_DISCARD_PIXEL"}, 7695 {"bits": [26, 26], "name": "FMASK_COMPRESSION_DISABLE"} 7696 ] 7697 }, 7698 "CB_COLOR0_PITCH": { 7699 "fields": [ 7700 {"bits": [0, 10], "name": "TILE_MAX"}, 7701 {"bits": [20, 30], "name": "FMASK_TILE_MAX"} 7702 ] 7703 }, 7704 "CB_COLOR0_VIEW": { 7705 "fields": [ 7706 {"bits": [0, 10], "name": "SLICE_START"}, 7707 {"bits": [13, 23], "name": "SLICE_MAX"} 7708 ] 7709 }, 7710 "CB_COLOR_CONTROL": { 7711 "fields": [ 7712 {"bits": [3, 3], "name": "DEGAMMA_ENABLE"}, 7713 {"bits": [4, 6], "enum_ref": "CBMode", "name": "MODE"}, 7714 {"bits": [16, 23], "enum_ref": "ROP3", "name": "ROP3"} 7715 ] 7716 }, 7717 "CB_SHADER_MASK": { 7718 "fields": [ 7719 {"bits": [0, 3], "name": "OUTPUT0_ENABLE"}, 7720 {"bits": [4, 7], "name": "OUTPUT1_ENABLE"}, 7721 {"bits": [8, 11], "name": "OUTPUT2_ENABLE"}, 7722 {"bits": [12, 15], "name": "OUTPUT3_ENABLE"}, 7723 {"bits": [16, 19], "name": "OUTPUT4_ENABLE"}, 7724 {"bits": [20, 23], "name": "OUTPUT5_ENABLE"}, 7725 {"bits": [24, 27], "name": "OUTPUT6_ENABLE"}, 7726 {"bits": [28, 31], "name": "OUTPUT7_ENABLE"} 7727 ] 7728 }, 7729 "CB_TARGET_MASK": { 7730 "fields": [ 7731 {"bits": [0, 3], "name": "TARGET0_ENABLE"}, 7732 {"bits": [4, 7], "name": "TARGET1_ENABLE"}, 7733 {"bits": [8, 11], "name": "TARGET2_ENABLE"}, 7734 {"bits": [12, 15], "name": "TARGET3_ENABLE"}, 7735 {"bits": [16, 19], "name": "TARGET4_ENABLE"}, 7736 {"bits": [20, 23], "name": "TARGET5_ENABLE"}, 7737 {"bits": [24, 27], "name": "TARGET6_ENABLE"}, 7738 {"bits": [28, 31], "name": "TARGET7_ENABLE"} 7739 ] 7740 }, 7741 "CC_GC_SHADER_ARRAY_CONFIG": { 7742 "fields": [ 7743 {"bits": [1, 2], "name": "DPFP_RATE"}, 7744 {"bits": [3, 3], "name": "SQC_BALANCE_DISABLE"}, 7745 {"bits": [4, 4], "name": "HALF_LDS"}, 7746 {"bits": [16, 31], "name": "INACTIVE_CUS"} 7747 ] 7748 }, 7749 "CC_SQC_BANK_DISABLE": { 7750 "fields": [ 7751 {"bits": [16, 19], "name": "SQC0_BANK_DISABLE"}, 7752 {"bits": [20, 23], "name": "SQC1_BANK_DISABLE"}, 7753 {"bits": [24, 27], "name": "SQC2_BANK_DISABLE"}, 7754 {"bits": [28, 31], "name": "SQC3_BANK_DISABLE"} 7755 ] 7756 }, 7757 "CGTT_IA_CLK_CTRL": { 7758 "fields": [ 7759 {"bits": [0, 3], "name": "ON_DELAY"}, 7760 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7761 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7762 {"bits": [25, 25], "name": "PERF_ENABLE"}, 7763 {"bits": [26, 26], "name": "DBG_ENABLE"}, 7764 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7765 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7766 {"bits": [29, 29], "name": "CORE_OVERRIDE"}, 7767 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, 7768 {"bits": [31, 31], "name": "REG_OVERRIDE"} 7769 ] 7770 }, 7771 "CGTT_PA_CLK_CTRL": { 7772 "fields": [ 7773 {"bits": [0, 3], "name": "ON_DELAY"}, 7774 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7775 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7776 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, 7777 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, 7778 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7779 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7780 {"bits": [29, 29], "name": "SU_CLK_OVERRIDE"}, 7781 {"bits": [30, 30], "name": "CL_CLK_OVERRIDE"}, 7782 {"bits": [31, 31], "name": "REG_CLK_OVERRIDE"} 7783 ] 7784 }, 7785 "CGTT_SC_CLK_CTRL": { 7786 "fields": [ 7787 {"bits": [0, 3], "name": "ON_DELAY"}, 7788 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7789 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7790 {"bits": [25, 25], "name": "SOFT_OVERRIDE6"}, 7791 {"bits": [26, 26], "name": "SOFT_OVERRIDE5"}, 7792 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7793 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7794 {"bits": [29, 29], "name": "SOFT_OVERRIDE2"}, 7795 {"bits": [30, 30], "name": "SOFT_OVERRIDE1"}, 7796 {"bits": [31, 31], "name": "SOFT_OVERRIDE0"} 7797 ] 7798 }, 7799 "CGTT_SQ_CLK_CTRL": { 7800 "fields": [ 7801 {"bits": [0, 3], "name": "ON_DELAY"}, 7802 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7803 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, 7804 {"bits": [31, 31], "name": "REG_OVERRIDE"} 7805 ] 7806 }, 7807 "CGTT_VGT_CLK_CTRL": { 7808 "fields": [ 7809 {"bits": [0, 3], "name": "ON_DELAY"}, 7810 {"bits": [4, 11], "name": "OFF_HYSTERESIS"}, 7811 {"bits": [24, 24], "name": "SOFT_OVERRIDE7"}, 7812 {"bits": [25, 25], "name": "PERF_ENABLE"}, 7813 {"bits": [26, 26], "name": "DBG_ENABLE"}, 7814 {"bits": [27, 27], "name": "SOFT_OVERRIDE4"}, 7815 {"bits": [28, 28], "name": "SOFT_OVERRIDE3"}, 7816 {"bits": [29, 29], "name": "GS_OVERRIDE"}, 7817 {"bits": [30, 30], "name": "CORE_OVERRIDE"}, 7818 {"bits": [31, 31], "name": "REG_OVERRIDE"} 7819 ] 7820 }, 7821 "COMPUTE_DISPATCH_INITIATOR": { 7822 "fields": [ 7823 {"bits": [0, 0], "name": "COMPUTE_SHADER_EN"}, 7824 {"bits": [1, 1], "name": "PARTIAL_TG_EN"}, 7825 {"bits": [2, 2], "name": "FORCE_START_AT_000"}, 7826 {"bits": [3, 3], "name": "ORDERED_APPEND_ENBL"}, 7827 {"bits": [4, 4], "name": "ORDERED_APPEND_MODE"}, 7828 {"bits": [5, 5], "name": "USE_THREAD_DIMENSIONS"}, 7829 {"bits": [6, 6], "name": "ORDER_MODE"}, 7830 {"bits": [7, 9], "name": "DISPATCH_CACHE_CNTL"}, 7831 {"bits": [10, 10], "name": "SCALAR_L1_INV_VOL"}, 7832 {"bits": [11, 11], "name": "VECTOR_L1_INV_VOL"}, 7833 {"bits": [12, 12], "name": "DATA_ATC"}, 7834 {"bits": [14, 14], "name": "RESTORE"} 7835 ] 7836 }, 7837 "COMPUTE_NUM_THREAD_X": { 7838 "fields": [ 7839 {"bits": [0, 15], "name": "NUM_THREAD_FULL"}, 7840 {"bits": [16, 31], "name": "NUM_THREAD_PARTIAL"} 7841 ] 7842 }, 7843 "COMPUTE_PGM_HI": { 7844 "fields": [ 7845 {"bits": [0, 7], "name": "DATA"}, 7846 {"bits": [8, 8], "name": "INST_ATC"} 7847 ] 7848 }, 7849 "COMPUTE_PGM_RSRC1": { 7850 "fields": [ 7851 {"bits": [0, 5], "name": "VGPRS"}, 7852 {"bits": [6, 9], "name": "SGPRS"}, 7853 {"bits": [10, 11], "name": "PRIORITY"}, 7854 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 7855 {"bits": [20, 20], "name": "PRIV"}, 7856 {"bits": [21, 21], "name": "DX10_CLAMP"}, 7857 {"bits": [22, 22], "name": "DEBUG_MODE"}, 7858 {"bits": [23, 23], "name": "IEEE_MODE"}, 7859 {"bits": [24, 24], "name": "BULKY"}, 7860 {"bits": [25, 25], "name": "CDBG_USER"} 7861 ] 7862 }, 7863 "COMPUTE_PGM_RSRC2": { 7864 "fields": [ 7865 {"bits": [0, 0], "name": "SCRATCH_EN"}, 7866 {"bits": [1, 5], "name": "USER_SGPR"}, 7867 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 7868 {"bits": [7, 7], "name": "TGID_X_EN"}, 7869 {"bits": [8, 8], "name": "TGID_Y_EN"}, 7870 {"bits": [9, 9], "name": "TGID_Z_EN"}, 7871 {"bits": [10, 10], "name": "TG_SIZE_EN"}, 7872 {"bits": [11, 12], "name": "TIDIG_COMP_CNT"}, 7873 {"bits": [13, 14], "name": "EXCP_EN_MSB"}, 7874 {"bits": [15, 23], "name": "LDS_SIZE"}, 7875 {"bits": [24, 30], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 7876 ] 7877 }, 7878 "COMPUTE_RESOURCE_LIMITS": { 7879 "fields": [ 7880 {"bits": [0, 5], "name": "WAVES_PER_SH"}, 7881 {"bits": [0, 5], "name": "WAVES_PER_SH_GFX6"}, 7882 {"bits": [12, 15], "name": "TG_PER_CU"}, 7883 {"bits": [16, 21], "name": "LOCK_THRESHOLD"}, 7884 {"bits": [22, 22], "name": "SIMD_DEST_CNTL"}, 7885 {"bits": [23, 23], "name": "FORCE_SIMD_DIST"}, 7886 {"bits": [24, 26], "name": "CU_GROUP_COUNT"} 7887 ] 7888 }, 7889 "COMPUTE_STATIC_THREAD_MGMT_SE0": { 7890 "fields": [ 7891 {"bits": [0, 15], "name": "SH0_CU_EN"}, 7892 {"bits": [16, 31], "name": "SH1_CU_EN"} 7893 ] 7894 }, 7895 "COMPUTE_TBA_HI": { 7896 "fields": [ 7897 {"bits": [0, 7], "name": "DATA"} 7898 ] 7899 }, 7900 "COMPUTE_TMPRING_SIZE": { 7901 "fields": [ 7902 {"bits": [0, 11], "name": "WAVES"}, 7903 {"bits": [12, 24], "name": "WAVESIZE"} 7904 ] 7905 }, 7906 "COMPUTE_VMID": { 7907 "fields": [ 7908 {"bits": [0, 3], "name": "DATA"} 7909 ] 7910 }, 7911 "CP_APPEND_ADDR_HI": { 7912 "fields": [ 7913 {"bits": [0, 7], "name": "MEM_ADDR_HI"}, 7914 {"bits": [16, 17], "name": "CS_PS_SEL"}, 7915 {"bits": [29, 31], "name": "COMMAND"} 7916 ] 7917 }, 7918 "CP_APPEND_ADDR_LO": { 7919 "fields": [ 7920 {"bits": [2, 31], "name": "MEM_ADDR_LO"} 7921 ] 7922 }, 7923 "CP_BUSY_STAT": { 7924 "fields": [ 7925 {"bits": [0, 0], "name": "REG_BUS_FIFO_BUSY"}, 7926 {"bits": [6, 6], "name": "COHER_CNT_NEQ_ZERO"}, 7927 {"bits": [7, 7], "name": "PFP_PARSING_PACKETS"}, 7928 {"bits": [8, 8], "name": "ME_PARSING_PACKETS"}, 7929 {"bits": [9, 9], "name": "RCIU_PFP_BUSY"}, 7930 {"bits": [10, 10], "name": "RCIU_ME_BUSY"}, 7931 {"bits": [12, 12], "name": "SEM_CMDFIFO_NOT_EMPTY"}, 7932 {"bits": [13, 13], "name": "SEM_FAILED_AND_HOLDING"}, 7933 {"bits": [14, 14], "name": "SEM_POLLING_FOR_PASS"}, 7934 {"bits": [15, 15], "name": "GFX_CONTEXT_BUSY"}, 7935 {"bits": [17, 17], "name": "ME_PARSER_BUSY"}, 7936 {"bits": [18, 18], "name": "EOP_DONE_BUSY"}, 7937 {"bits": [19, 19], "name": "STRM_OUT_BUSY"}, 7938 {"bits": [20, 20], "name": "PIPE_STATS_BUSY"}, 7939 {"bits": [21, 21], "name": "RCIU_CE_BUSY"}, 7940 {"bits": [22, 22], "name": "CE_PARSING_PACKETS"} 7941 ] 7942 }, 7943 "CP_CEQ1_AVAIL": { 7944 "fields": [ 7945 {"bits": [0, 10], "name": "CEQ_CNT_RING"}, 7946 {"bits": [16, 26], "name": "CEQ_CNT_IB1"} 7947 ] 7948 }, 7949 "CP_CEQ2_AVAIL": { 7950 "fields": [ 7951 {"bits": [0, 10], "name": "CEQ_CNT_IB2"} 7952 ] 7953 }, 7954 "CP_CE_IB1_BASE_HI": { 7955 "fields": [ 7956 {"bits": [0, 7], "name": "IB1_BASE_HI"} 7957 ] 7958 }, 7959 "CP_CE_IB1_BASE_LO": { 7960 "fields": [ 7961 {"bits": [2, 31], "name": "IB1_BASE_LO"} 7962 ] 7963 }, 7964 "CP_CE_IB1_BUFSZ": { 7965 "fields": [ 7966 {"bits": [0, 19], "name": "IB1_BUFSZ"} 7967 ] 7968 }, 7969 "CP_CE_IB2_BASE_HI": { 7970 "fields": [ 7971 {"bits": [0, 7], "name": "IB2_BASE_HI"} 7972 ] 7973 }, 7974 "CP_CE_IB2_BASE_LO": { 7975 "fields": [ 7976 {"bits": [2, 31], "name": "IB2_BASE_LO"} 7977 ] 7978 }, 7979 "CP_CE_IB2_BUFSZ": { 7980 "fields": [ 7981 {"bits": [0, 19], "name": "IB2_BUFSZ"} 7982 ] 7983 }, 7984 "CP_CE_INIT_BASE_HI": { 7985 "fields": [ 7986 {"bits": [0, 7], "name": "INIT_BASE_HI"} 7987 ] 7988 }, 7989 "CP_CE_INIT_BASE_LO": { 7990 "fields": [ 7991 {"bits": [5, 31], "name": "INIT_BASE_LO"} 7992 ] 7993 }, 7994 "CP_CE_INIT_BUFSZ": { 7995 "fields": [ 7996 {"bits": [0, 11], "name": "INIT_BUFSZ"} 7997 ] 7998 }, 7999 "CP_CE_ROQ_IB1_STAT": { 8000 "fields": [ 8001 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT1"}, 8002 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT1"} 8003 ] 8004 }, 8005 "CP_CE_ROQ_IB2_STAT": { 8006 "fields": [ 8007 {"bits": [0, 9], "name": "CEQ_RPTR_INDIRECT2"}, 8008 {"bits": [16, 25], "name": "CEQ_WPTR_INDIRECT2"} 8009 ] 8010 }, 8011 "CP_CE_ROQ_RB_STAT": { 8012 "fields": [ 8013 {"bits": [0, 9], "name": "CEQ_RPTR_PRIMARY"}, 8014 {"bits": [16, 25], "name": "CEQ_WPTR_PRIMARY"} 8015 ] 8016 }, 8017 "CP_CMD_INDEX": { 8018 "fields": [ 8019 {"bits": [0, 10], "name": "CMD_INDEX"}, 8020 {"bits": [12, 13], "name": "CMD_ME_SEL"}, 8021 {"bits": [16, 17], "name": "CMD_QUEUE_SEL"} 8022 ] 8023 }, 8024 "CP_CNTX_STAT": { 8025 "fields": [ 8026 {"bits": [0, 7], "name": "ACTIVE_HP3D_CONTEXTS"}, 8027 {"bits": [8, 10], "name": "CURRENT_HP3D_CONTEXT"}, 8028 {"bits": [20, 27], "name": "ACTIVE_GFX_CONTEXTS"}, 8029 {"bits": [28, 30], "name": "CURRENT_GFX_CONTEXT"} 8030 ] 8031 }, 8032 "CP_COHER_CNTL": { 8033 "fields": [ 8034 {"bits": [0, 0], "name": "DEST_BASE_0_ENA"}, 8035 {"bits": [1, 1], "name": "DEST_BASE_1_ENA"}, 8036 {"bits": [6, 6], "name": "CB0_DEST_BASE_ENA"}, 8037 {"bits": [7, 7], "name": "CB1_DEST_BASE_ENA"}, 8038 {"bits": [8, 8], "name": "CB2_DEST_BASE_ENA"}, 8039 {"bits": [9, 9], "name": "CB3_DEST_BASE_ENA"}, 8040 {"bits": [10, 10], "name": "CB4_DEST_BASE_ENA"}, 8041 {"bits": [11, 11], "name": "CB5_DEST_BASE_ENA"}, 8042 {"bits": [12, 12], "name": "CB6_DEST_BASE_ENA"}, 8043 {"bits": [13, 13], "name": "CB7_DEST_BASE_ENA"}, 8044 {"bits": [14, 14], "name": "DB_DEST_BASE_ENA"}, 8045 {"bits": [15, 15], "name": "TCL1_VOL_ACTION_ENA"}, 8046 {"bits": [16, 16], "name": "TC_VOL_ACTION_ENA"}, 8047 {"bits": [18, 18], "name": "TC_WB_ACTION_ENA"}, 8048 {"bits": [19, 19], "name": "DEST_BASE_2_ENA"}, 8049 {"bits": [21, 21], "name": "DEST_BASE_3_ENA"}, 8050 {"bits": [22, 22], "name": "TCL1_ACTION_ENA"}, 8051 {"bits": [23, 23], "name": "TC_ACTION_ENA"}, 8052 {"bits": [25, 25], "name": "CB_ACTION_ENA"}, 8053 {"bits": [26, 26], "name": "DB_ACTION_ENA"}, 8054 {"bits": [27, 27], "name": "SH_KCACHE_ACTION_ENA"}, 8055 {"bits": [28, 28], "name": "SH_KCACHE_VOL_ACTION_ENA"}, 8056 {"bits": [29, 29], "name": "SH_ICACHE_ACTION_ENA"} 8057 ] 8058 }, 8059 "CP_COHER_START_DELAY": { 8060 "fields": [ 8061 {"bits": [0, 5], "name": "START_DELAY_COUNT"} 8062 ] 8063 }, 8064 "CP_COHER_STATUS": { 8065 "fields": [ 8066 {"bits": [0, 7], "name": "MATCHING_GFX_CNTX"}, 8067 {"bits": [24, 25], "name": "MEID"}, 8068 {"bits": [30, 30], "name": "PHASE1_STATUS"}, 8069 {"bits": [31, 31], "name": "STATUS"} 8070 ] 8071 }, 8072 "CP_CSF_CNTL": { 8073 "fields": [ 8074 {"bits": [0, 3], "name": "FETCH_BUFFER_DEPTH"} 8075 ] 8076 }, 8077 "CP_CSF_STAT": { 8078 "fields": [ 8079 {"bits": [0, 3], "name": "BUFFER_SLOTS_ALLOCATED"}, 8080 {"bits": [8, 13], "name": "BUFFER_REQUEST_COUNT"} 8081 ] 8082 }, 8083 "CP_DMA_CNTL": { 8084 "fields": [ 8085 {"bits": [4, 5], "name": "MIN_AVAILSZ"}, 8086 {"bits": [16, 19], "name": "BUFFER_DEPTH"}, 8087 {"bits": [28, 28], "name": "PIO_FIFO_EMPTY"}, 8088 {"bits": [29, 29], "name": "PIO_FIFO_FULL"}, 8089 {"bits": [30, 31], "name": "PIO_COUNT"} 8090 ] 8091 }, 8092 "CP_DMA_ME_COMMAND": { 8093 "fields": [ 8094 {"bits": [0, 20], "name": "BYTE_COUNT"}, 8095 {"bits": [21, 21], "name": "DIS_WC"}, 8096 {"bits": [22, 23], "name": "SRC_SWAP"}, 8097 {"bits": [24, 25], "name": "DST_SWAP"}, 8098 {"bits": [26, 26], "name": "SAS"}, 8099 {"bits": [27, 27], "name": "DAS"}, 8100 {"bits": [28, 28], "name": "SAIC"}, 8101 {"bits": [29, 29], "name": "DAIC"}, 8102 {"bits": [30, 30], "name": "RAW_WAIT"} 8103 ] 8104 }, 8105 "CP_DMA_ME_DST_ADDR_HI": { 8106 "fields": [ 8107 {"bits": [0, 7], "name": "DST_ADDR_HI"} 8108 ] 8109 }, 8110 "CP_DMA_ME_SRC_ADDR_HI": { 8111 "fields": [ 8112 {"bits": [0, 7], "name": "SRC_ADDR_HI"} 8113 ] 8114 }, 8115 "CP_DMA_READ_TAGS": { 8116 "fields": [ 8117 {"bits": [0, 25], "name": "DMA_READ_TAG"}, 8118 {"bits": [28, 28], "name": "DMA_READ_TAG_VALID"} 8119 ] 8120 }, 8121 "CP_EOP_DONE_ADDR_HI": { 8122 "fields": [ 8123 {"bits": [0, 15], "name": "ADDR_HI"} 8124 ] 8125 }, 8126 "CP_EOP_DONE_ADDR_LO": { 8127 "fields": [ 8128 {"bits": [0, 1], "name": "ADDR_SWAP"}, 8129 {"bits": [2, 31], "name": "ADDR_LO"} 8130 ] 8131 }, 8132 "CP_GRBM_FREE_COUNT": { 8133 "fields": [ 8134 {"bits": [0, 5], "name": "FREE_COUNT"}, 8135 {"bits": [8, 13], "name": "FREE_COUNT_GDS"}, 8136 {"bits": [16, 21], "name": "FREE_COUNT_PFP"} 8137 ] 8138 }, 8139 "CP_IB1_OFFSET": { 8140 "fields": [ 8141 {"bits": [0, 19], "name": "IB1_OFFSET"} 8142 ] 8143 }, 8144 "CP_IB1_PREAMBLE_BEGIN": { 8145 "fields": [ 8146 {"bits": [0, 19], "name": "IB1_PREAMBLE_BEGIN"} 8147 ] 8148 }, 8149 "CP_IB1_PREAMBLE_END": { 8150 "fields": [ 8151 {"bits": [0, 19], "name": "IB1_PREAMBLE_END"} 8152 ] 8153 }, 8154 "CP_IB2_OFFSET": { 8155 "fields": [ 8156 {"bits": [0, 19], "name": "IB2_OFFSET"} 8157 ] 8158 }, 8159 "CP_IB2_PREAMBLE_BEGIN": { 8160 "fields": [ 8161 {"bits": [0, 19], "name": "IB2_PREAMBLE_BEGIN"} 8162 ] 8163 }, 8164 "CP_IB2_PREAMBLE_END": { 8165 "fields": [ 8166 {"bits": [0, 19], "name": "IB2_PREAMBLE_END"} 8167 ] 8168 }, 8169 "CP_INT_STAT_DEBUG": { 8170 "fields": [ 8171 {"bits": [14, 14], "name": "CP_ECC_ERROR_INT_ASSERTED"}, 8172 {"bits": [17, 17], "name": "WRM_POLL_TIMEOUT_INT_ASSERTED"}, 8173 {"bits": [19, 19], "name": "CNTX_BUSY_INT_ASSERTED"}, 8174 {"bits": [20, 20], "name": "CNTX_EMPTY_INT_ASSERTED"}, 8175 {"bits": [22, 22], "name": "PRIV_INSTR_INT_ASSERTED"}, 8176 {"bits": [23, 23], "name": "PRIV_REG_INT_ASSERTED"}, 8177 {"bits": [24, 24], "name": "OPCODE_ERROR_INT_ASSERTED"}, 8178 {"bits": [26, 26], "name": "TIME_STAMP_INT_ASSERTED"}, 8179 {"bits": [27, 27], "name": "RESERVED_BIT_ERROR_INT_ASSERTED"}, 8180 {"bits": [29, 29], "name": "GENERIC2_INT_ASSERTED"}, 8181 {"bits": [30, 30], "name": "GENERIC1_INT_ASSERTED"}, 8182 {"bits": [31, 31], "name": "GENERIC0_INT_ASSERTED"} 8183 ] 8184 }, 8185 "CP_MC_PACK_DELAY_CNT": { 8186 "fields": [ 8187 {"bits": [0, 4], "name": "PACK_DELAY_CNT"} 8188 ] 8189 }, 8190 "CP_MEQ_AVAIL": { 8191 "fields": [ 8192 {"bits": [0, 9], "name": "MEQ_CNT"} 8193 ] 8194 }, 8195 "CP_MEQ_STAT": { 8196 "fields": [ 8197 {"bits": [0, 9], "name": "MEQ_RPTR"}, 8198 {"bits": [16, 25], "name": "MEQ_WPTR"} 8199 ] 8200 }, 8201 "CP_MEQ_THRESHOLDS": { 8202 "fields": [ 8203 {"bits": [0, 7], "name": "MEQ1_START"}, 8204 {"bits": [8, 15], "name": "MEQ2_START"} 8205 ] 8206 }, 8207 "CP_ME_CNTL": { 8208 "fields": [ 8209 {"bits": [4, 4], "name": "CE_INVALIDATE_ICACHE"}, 8210 {"bits": [6, 6], "name": "PFP_INVALIDATE_ICACHE"}, 8211 {"bits": [8, 8], "name": "ME_INVALIDATE_ICACHE"}, 8212 {"bits": [24, 24], "name": "CE_HALT"}, 8213 {"bits": [25, 25], "name": "CE_STEP"}, 8214 {"bits": [26, 26], "name": "PFP_HALT"}, 8215 {"bits": [27, 27], "name": "PFP_STEP"}, 8216 {"bits": [28, 28], "name": "ME_HALT"}, 8217 {"bits": [29, 29], "name": "ME_STEP"} 8218 ] 8219 }, 8220 "CP_ME_MC_RADDR_HI": { 8221 "fields": [ 8222 {"bits": [0, 7], "name": "ME_MC_RADDR_HI"} 8223 ] 8224 }, 8225 "CP_ME_MC_RADDR_LO": { 8226 "fields": [ 8227 {"bits": [0, 1], "name": "ME_MC_RADDR_SWAP"}, 8228 {"bits": [2, 31], "name": "ME_MC_RADDR_LO"} 8229 ] 8230 }, 8231 "CP_ME_MC_WADDR_HI": { 8232 "fields": [ 8233 {"bits": [0, 7], "name": "ME_MC_WADDR_HI"} 8234 ] 8235 }, 8236 "CP_ME_MC_WADDR_LO": { 8237 "fields": [ 8238 {"bits": [0, 1], "name": "ME_MC_WADDR_SWAP"}, 8239 {"bits": [2, 31], "name": "ME_MC_WADDR_LO"} 8240 ] 8241 }, 8242 "CP_ME_PREEMPTION": { 8243 "fields": [ 8244 {"bits": [0, 0], "name": "ME_CNTXSW_PREEMPTION"} 8245 ] 8246 }, 8247 "CP_PERFMON_CNTL": { 8248 "fields": [ 8249 {"bits": [0, 3], "enum_ref": "CP_PERFMON_STATE", "name": "PERFMON_STATE"}, 8250 {"bits": [4, 7], "enum_ref": "SPM_PERFMON_STATE", "name": "SPM_PERFMON_STATE"}, 8251 {"bits": [8, 9], "enum_ref": "CP_PERFMON_ENABLE_MODE", "name": "PERFMON_ENABLE_MODE"}, 8252 {"bits": [10, 10], "name": "PERFMON_SAMPLE_ENABLE"} 8253 ] 8254 }, 8255 "CP_PERFMON_CNTX_CNTL": { 8256 "fields": [ 8257 {"bits": [31, 31], "name": "PERFMON_ENABLE"} 8258 ] 8259 }, 8260 "CP_PFP_IB_CONTROL": { 8261 "fields": [ 8262 {"bits": [0, 0], "name": "IB_EN"} 8263 ] 8264 }, 8265 "CP_PFP_LOAD_CONTROL": { 8266 "fields": [ 8267 {"bits": [0, 0], "name": "CONFIG_REG_EN"}, 8268 {"bits": [1, 1], "name": "CNTX_REG_EN"}, 8269 {"bits": [15, 15], "name": "UCONFIG_REG_EN"}, 8270 {"bits": [16, 16], "name": "SH_GFX_REG_EN"}, 8271 {"bits": [24, 24], "name": "SH_CS_REG_EN"} 8272 ] 8273 }, 8274 "CP_PIPE_STATS_ADDR_LO": { 8275 "fields": [ 8276 {"bits": [0, 1], "name": "PIPE_STATS_ADDR_SWAP"}, 8277 {"bits": [2, 31], "name": "PIPE_STATS_ADDR_LO"} 8278 ] 8279 }, 8280 "CP_QUEUE_THRESHOLDS": { 8281 "fields": [ 8282 {"bits": [0, 5], "name": "ROQ_IB1_START"}, 8283 {"bits": [8, 13], "name": "ROQ_IB2_START"} 8284 ] 8285 }, 8286 "CP_RB0_RPTR": { 8287 "fields": [ 8288 {"bits": [0, 19], "name": "RB_RPTR"} 8289 ] 8290 }, 8291 "CP_RB_OFFSET": { 8292 "fields": [ 8293 {"bits": [0, 19], "name": "RB_OFFSET"} 8294 ] 8295 }, 8296 "CP_RB_WPTR_DELAY": { 8297 "fields": [ 8298 {"bits": [0, 27], "name": "PRE_WRITE_TIMER"}, 8299 {"bits": [28, 31], "name": "PRE_WRITE_LIMIT"} 8300 ] 8301 }, 8302 "CP_RB_WPTR_POLL_CNTL": { 8303 "fields": [ 8304 {"bits": [0, 15], "name": "POLL_FREQUENCY"}, 8305 {"bits": [16, 31], "name": "IDLE_POLL_COUNT"} 8306 ] 8307 }, 8308 "CP_RINGID": { 8309 "fields": [ 8310 {"bits": [0, 1], "name": "RINGID"} 8311 ] 8312 }, 8313 "CP_ROQ1_THRESHOLDS": { 8314 "fields": [ 8315 {"bits": [0, 7], "name": "RB1_START"}, 8316 {"bits": [8, 15], "name": "RB2_START"}, 8317 {"bits": [16, 23], "name": "R0_IB1_START"}, 8318 {"bits": [24, 31], "name": "R1_IB1_START"} 8319 ] 8320 }, 8321 "CP_ROQ2_AVAIL": { 8322 "fields": [ 8323 {"bits": [0, 10], "name": "ROQ_CNT_IB2"} 8324 ] 8325 }, 8326 "CP_ROQ2_THRESHOLDS": { 8327 "fields": [ 8328 {"bits": [0, 7], "name": "R2_IB1_START"}, 8329 {"bits": [8, 15], "name": "R0_IB2_START"}, 8330 {"bits": [16, 23], "name": "R1_IB2_START"}, 8331 {"bits": [24, 31], "name": "R2_IB2_START"} 8332 ] 8333 }, 8334 "CP_ROQ_AVAIL": { 8335 "fields": [ 8336 {"bits": [0, 10], "name": "ROQ_CNT_RING"}, 8337 {"bits": [16, 26], "name": "ROQ_CNT_IB1"} 8338 ] 8339 }, 8340 "CP_ROQ_IB1_STAT": { 8341 "fields": [ 8342 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT1"}, 8343 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT1"} 8344 ] 8345 }, 8346 "CP_ROQ_IB2_STAT": { 8347 "fields": [ 8348 {"bits": [0, 9], "name": "ROQ_RPTR_INDIRECT2"}, 8349 {"bits": [16, 25], "name": "ROQ_WPTR_INDIRECT2"} 8350 ] 8351 }, 8352 "CP_ROQ_RB_STAT": { 8353 "fields": [ 8354 {"bits": [0, 9], "name": "ROQ_RPTR_PRIMARY"}, 8355 {"bits": [16, 25], "name": "ROQ_WPTR_PRIMARY"} 8356 ] 8357 }, 8358 "CP_SCRATCH_INDEX": { 8359 "fields": [ 8360 {"bits": [0, 7], "name": "SCRATCH_INDEX"} 8361 ] 8362 }, 8363 "CP_SIG_SEM_ADDR_HI": { 8364 "fields": [ 8365 {"bits": [0, 7], "name": "SEM_ADDR_HI"}, 8366 {"bits": [16, 16], "name": "SEM_USE_MAILBOX"}, 8367 {"bits": [20, 20], "name": "SEM_SIGNAL_TYPE"}, 8368 {"bits": [24, 25], "name": "SEM_CLIENT_CODE"}, 8369 {"bits": [29, 31], "name": "SEM_SELECT"} 8370 ] 8371 }, 8372 "CP_SIG_SEM_ADDR_LO": { 8373 "fields": [ 8374 {"bits": [0, 1], "name": "SEM_ADDR_SWAP"}, 8375 {"bits": [3, 31], "name": "SEM_ADDR_LO"} 8376 ] 8377 }, 8378 "CP_STALLED_STAT1": { 8379 "fields": [ 8380 {"bits": [0, 0], "name": "RBIU_TO_DMA_NOT_RDY_TO_RCV"}, 8381 {"bits": [2, 2], "name": "RBIU_TO_SEM_NOT_RDY_TO_RCV"}, 8382 {"bits": [4, 4], "name": "RBIU_TO_MEMWR_NOT_RDY_TO_RCV"}, 8383 {"bits": [10, 10], "name": "ME_HAS_ACTIVE_CE_BUFFER_FLAG"}, 8384 {"bits": [11, 11], "name": "ME_HAS_ACTIVE_DE_BUFFER_FLAG"}, 8385 {"bits": [12, 12], "name": "ME_STALLED_ON_TC_WR_CONFIRM"}, 8386 {"bits": [13, 13], "name": "ME_STALLED_ON_ATOMIC_RTN_DATA"}, 8387 {"bits": [14, 14], "name": "ME_WAITING_ON_MC_READ_DATA"}, 8388 {"bits": [15, 15], "name": "ME_WAITING_ON_REG_READ_DATA"}, 8389 {"bits": [16, 16], "name": "MIU_WAITING_ON_RDREQ_FREE"}, 8390 {"bits": [17, 17], "name": "MIU_WAITING_ON_WRREQ_FREE"}, 8391 {"bits": [23, 23], "name": "RCIU_WAITING_ON_GDS_FREE"}, 8392 {"bits": [24, 24], "name": "RCIU_WAITING_ON_GRBM_FREE"}, 8393 {"bits": [25, 25], "name": "RCIU_WAITING_ON_VGT_FREE"}, 8394 {"bits": [26, 26], "name": "RCIU_STALLED_ON_ME_READ"}, 8395 {"bits": [27, 27], "name": "RCIU_STALLED_ON_DMA_READ"}, 8396 {"bits": [28, 28], "name": "RCIU_HALTED_BY_REG_VIOLATION"}, 8397 {"bits": [28, 28], "name": "RCIU_STALLED_ON_APPEND_READ"} 8398 ] 8399 }, 8400 "CP_STALLED_STAT2": { 8401 "fields": [ 8402 {"bits": [0, 0], "name": "PFP_TO_CSF_NOT_RDY_TO_RCV"}, 8403 {"bits": [1, 1], "name": "PFP_TO_MEQ_NOT_RDY_TO_RCV"}, 8404 {"bits": [2, 2], "name": "PFP_TO_RCIU_NOT_RDY_TO_RCV"}, 8405 {"bits": [4, 4], "name": "PFP_TO_VGT_WRITES_PENDING"}, 8406 {"bits": [5, 5], "name": "PFP_RCIU_READ_PENDING"}, 8407 {"bits": [6, 6], "name": "PFP_MIU_READ_PENDING"}, 8408 {"bits": [7, 7], "name": "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, 8409 {"bits": [8, 8], "name": "PFP_WAITING_ON_BUFFER_DATA"}, 8410 {"bits": [9, 9], "name": "ME_WAIT_ON_CE_COUNTER"}, 8411 {"bits": [10, 10], "name": "ME_WAIT_ON_AVAIL_BUFFER"}, 8412 {"bits": [11, 11], "name": "GFX_CNTX_NOT_AVAIL_TO_ME"}, 8413 {"bits": [12, 12], "name": "ME_RCIU_NOT_RDY_TO_RCV"}, 8414 {"bits": [13, 13], "name": "ME_TO_CONST_NOT_RDY_TO_RCV"}, 8415 {"bits": [14, 14], "name": "ME_WAITING_DATA_FROM_PFP"}, 8416 {"bits": [15, 15], "name": "ME_WAITING_ON_PARTIAL_FLUSH"}, 8417 {"bits": [16, 16], "name": "MEQ_TO_ME_NOT_RDY_TO_RCV"}, 8418 {"bits": [17, 17], "name": "STQ_TO_ME_NOT_RDY_TO_RCV"}, 8419 {"bits": [18, 18], "name": "ME_WAITING_DATA_FROM_STQ"}, 8420 {"bits": [19, 19], "name": "PFP_STALLED_ON_TC_WR_CONFIRM"}, 8421 {"bits": [20, 20], "name": "PFP_STALLED_ON_ATOMIC_RTN_DATA"}, 8422 {"bits": [21, 21], "name": "EOPD_FIFO_NEEDS_SC_EOP_DONE"}, 8423 {"bits": [22, 22], "name": "EOPD_FIFO_NEEDS_WR_CONFIRM"}, 8424 {"bits": [23, 23], "name": "STRMO_WR_OF_PRIM_DATA_PENDING"}, 8425 {"bits": [24, 24], "name": "PIPE_STATS_WR_DATA_PENDING"}, 8426 {"bits": [25, 25], "name": "APPEND_RDY_WAIT_ON_CS_DONE"}, 8427 {"bits": [26, 26], "name": "APPEND_RDY_WAIT_ON_PS_DONE"}, 8428 {"bits": [27, 27], "name": "APPEND_WAIT_ON_WR_CONFIRM"}, 8429 {"bits": [28, 28], "name": "APPEND_ACTIVE_PARTITION"}, 8430 {"bits": [29, 29], "name": "APPEND_WAITING_TO_SEND_MEMWRITE"}, 8431 {"bits": [30, 30], "name": "SURF_SYNC_NEEDS_IDLE_CNTXS"}, 8432 {"bits": [31, 31], "name": "SURF_SYNC_NEEDS_ALL_CLEAN"} 8433 ] 8434 }, 8435 "CP_STALLED_STAT3": { 8436 "fields": [ 8437 {"bits": [0, 0], "name": "CE_TO_CSF_NOT_RDY_TO_RCV"}, 8438 {"bits": [1, 1], "name": "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV"}, 8439 {"bits": [2, 2], "name": "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER"}, 8440 {"bits": [3, 3], "name": "CE_TO_RAM_INIT_NOT_RDY"}, 8441 {"bits": [4, 4], "name": "CE_TO_RAM_DUMP_NOT_RDY"}, 8442 {"bits": [5, 5], "name": "CE_TO_RAM_WRITE_NOT_RDY"}, 8443 {"bits": [6, 6], "name": "CE_TO_INC_FIFO_NOT_RDY_TO_RCV"}, 8444 {"bits": [7, 7], "name": "CE_TO_WR_FIFO_NOT_RDY_TO_RCV"}, 8445 {"bits": [8, 8], "name": "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV"}, 8446 {"bits": [10, 10], "name": "CE_WAITING_ON_BUFFER_DATA"}, 8447 {"bits": [11, 11], "name": "CE_WAITING_ON_CE_BUFFER_FLAG"}, 8448 {"bits": [12, 12], "name": "CE_WAITING_ON_DE_COUNTER"}, 8449 {"bits": [13, 13], "name": "CE_WAITING_ON_DE_COUNTER_UNDERFLOW"}, 8450 {"bits": [14, 14], "name": "TCIU_WAITING_ON_FREE"}, 8451 {"bits": [15, 15], "name": "TCIU_WAITING_ON_TAGS"} 8452 ] 8453 }, 8454 "CP_STAT": { 8455 "fields": [ 8456 {"bits": [7, 7], "name": "MIU_RDREQ_BUSY"}, 8457 {"bits": [8, 8], "name": "MIU_WRREQ_BUSY"}, 8458 {"bits": [9, 9], "name": "ROQ_RING_BUSY"}, 8459 {"bits": [10, 10], "name": "ROQ_INDIRECT1_BUSY"}, 8460 {"bits": [11, 11], "name": "ROQ_INDIRECT2_BUSY"}, 8461 {"bits": [12, 12], "name": "ROQ_STATE_BUSY"}, 8462 {"bits": [13, 13], "name": "DC_BUSY"}, 8463 {"bits": [15, 15], "name": "PFP_BUSY"}, 8464 {"bits": [16, 16], "name": "MEQ_BUSY"}, 8465 {"bits": [17, 17], "name": "ME_BUSY"}, 8466 {"bits": [18, 18], "name": "QUERY_BUSY"}, 8467 {"bits": [19, 19], "name": "SEMAPHORE_BUSY"}, 8468 {"bits": [20, 20], "name": "INTERRUPT_BUSY"}, 8469 {"bits": [21, 21], "name": "SURFACE_SYNC_BUSY"}, 8470 {"bits": [22, 22], "name": "DMA_BUSY"}, 8471 {"bits": [23, 23], "name": "RCIU_BUSY"}, 8472 {"bits": [24, 24], "name": "SCRATCH_RAM_BUSY"}, 8473 {"bits": [25, 25], "name": "CPC_CPG_BUSY"}, 8474 {"bits": [26, 26], "name": "CE_BUSY"}, 8475 {"bits": [27, 27], "name": "TCIU_BUSY"}, 8476 {"bits": [28, 28], "name": "ROQ_CE_RING_BUSY"}, 8477 {"bits": [29, 29], "name": "ROQ_CE_INDIRECT1_BUSY"}, 8478 {"bits": [30, 30], "name": "ROQ_CE_INDIRECT2_BUSY"}, 8479 {"bits": [31, 31], "name": "CP_BUSY"} 8480 ] 8481 }, 8482 "CP_STQ_AVAIL": { 8483 "fields": [ 8484 {"bits": [0, 8], "name": "STQ_CNT"} 8485 ] 8486 }, 8487 "CP_STQ_STAT": { 8488 "fields": [ 8489 {"bits": [0, 9], "name": "STQ_RPTR"} 8490 ] 8491 }, 8492 "CP_STQ_THRESHOLDS": { 8493 "fields": [ 8494 {"bits": [0, 7], "name": "STQ0_START"}, 8495 {"bits": [8, 15], "name": "STQ1_START"}, 8496 {"bits": [16, 23], "name": "STQ2_START"} 8497 ] 8498 }, 8499 "CP_STREAM_OUT_ADDR_LO": { 8500 "fields": [ 8501 {"bits": [0, 1], "name": "STREAM_OUT_ADDR_SWAP"}, 8502 {"bits": [2, 31], "name": "STREAM_OUT_ADDR_LO"} 8503 ] 8504 }, 8505 "CP_STRMOUT_CNTL": { 8506 "fields": [ 8507 {"bits": [0, 0], "name": "OFFSET_UPDATE_DONE"} 8508 ] 8509 }, 8510 "CP_ST_BASE_HI": { 8511 "fields": [ 8512 {"bits": [0, 7], "name": "ST_BASE_HI"} 8513 ] 8514 }, 8515 "CP_ST_BASE_LO": { 8516 "fields": [ 8517 {"bits": [2, 31], "name": "ST_BASE_LO"} 8518 ] 8519 }, 8520 "CP_ST_BUFSZ": { 8521 "fields": [ 8522 {"bits": [0, 19], "name": "ST_BUFSZ"} 8523 ] 8524 }, 8525 "CP_VMID": { 8526 "fields": [ 8527 {"bits": [0, 3], "name": "VMID"} 8528 ] 8529 }, 8530 "CS_COPY_STATE": { 8531 "fields": [ 8532 {"bits": [0, 2], "name": "SRC_STATE_ID"} 8533 ] 8534 }, 8535 "DB_ALPHA_TO_MASK": { 8536 "fields": [ 8537 {"bits": [0, 0], "name": "ALPHA_TO_MASK_ENABLE"}, 8538 {"bits": [8, 9], "name": "ALPHA_TO_MASK_OFFSET0"}, 8539 {"bits": [10, 11], "name": "ALPHA_TO_MASK_OFFSET1"}, 8540 {"bits": [12, 13], "name": "ALPHA_TO_MASK_OFFSET2"}, 8541 {"bits": [14, 15], "name": "ALPHA_TO_MASK_OFFSET3"}, 8542 {"bits": [16, 16], "name": "OFFSET_ROUND"} 8543 ] 8544 }, 8545 "DB_COUNT_CONTROL": { 8546 "fields": [ 8547 {"bits": [0, 0], "name": "ZPASS_INCREMENT_DISABLE"}, 8548 {"bits": [1, 1], "name": "PERFECT_ZPASS_COUNTS"}, 8549 {"bits": [4, 6], "name": "SAMPLE_RATE"}, 8550 {"bits": [8, 11], "name": "ZPASS_ENABLE"}, 8551 {"bits": [12, 15], "name": "ZFAIL_ENABLE"}, 8552 {"bits": [16, 19], "name": "SFAIL_ENABLE"}, 8553 {"bits": [20, 23], "name": "DBFAIL_ENABLE"}, 8554 {"bits": [24, 27], "name": "SLICE_EVEN_ENABLE"}, 8555 {"bits": [28, 31], "name": "SLICE_ODD_ENABLE"} 8556 ] 8557 }, 8558 "DB_DEPTH_CONTROL": { 8559 "fields": [ 8560 {"bits": [0, 0], "name": "STENCIL_ENABLE"}, 8561 {"bits": [1, 1], "name": "Z_ENABLE"}, 8562 {"bits": [2, 2], "name": "Z_WRITE_ENABLE"}, 8563 {"bits": [3, 3], "name": "DEPTH_BOUNDS_ENABLE"}, 8564 {"bits": [4, 6], "enum_ref": "CompareFrag", "name": "ZFUNC"}, 8565 {"bits": [7, 7], "name": "BACKFACE_ENABLE"}, 8566 {"bits": [8, 10], "enum_ref": "CompareFrag", "name": "STENCILFUNC"}, 8567 {"bits": [20, 22], "enum_ref": "CompareFrag", "name": "STENCILFUNC_BF"}, 8568 {"bits": [30, 30], "name": "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL"}, 8569 {"bits": [31, 31], "name": "DISABLE_COLOR_WRITES_ON_DEPTH_PASS"} 8570 ] 8571 }, 8572 "DB_DEPTH_INFO": { 8573 "fields": [ 8574 {"bits": [0, 3], "name": "ADDR5_SWIZZLE_MASK"}, 8575 {"bits": [4, 7], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 8576 {"bits": [8, 12], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 8577 {"bits": [13, 14], "enum_ref": "BankWidth", "name": "BANK_WIDTH"}, 8578 {"bits": [15, 16], "enum_ref": "BankHeight", "name": "BANK_HEIGHT"}, 8579 {"bits": [17, 18], "enum_ref": "MacroTileAspect", "name": "MACRO_TILE_ASPECT"}, 8580 {"bits": [19, 20], "enum_ref": "NumBanks", "name": "NUM_BANKS"} 8581 ] 8582 }, 8583 "DB_DEPTH_SIZE": { 8584 "fields": [ 8585 {"bits": [0, 10], "name": "PITCH_TILE_MAX"}, 8586 {"bits": [11, 21], "name": "HEIGHT_TILE_MAX"} 8587 ] 8588 }, 8589 "DB_DEPTH_SLICE": { 8590 "fields": [ 8591 {"bits": [0, 21], "name": "SLICE_TILE_MAX"} 8592 ] 8593 }, 8594 "DB_DEPTH_VIEW": { 8595 "fields": [ 8596 {"bits": [0, 10], "name": "SLICE_START"}, 8597 {"bits": [13, 23], "name": "SLICE_MAX"}, 8598 {"bits": [24, 24], "name": "Z_READ_ONLY"}, 8599 {"bits": [25, 25], "name": "STENCIL_READ_ONLY"} 8600 ] 8601 }, 8602 "DB_EQAA": { 8603 "fields": [ 8604 {"bits": [0, 2], "name": "MAX_ANCHOR_SAMPLES"}, 8605 {"bits": [4, 6], "name": "PS_ITER_SAMPLES"}, 8606 {"bits": [8, 10], "name": "MASK_EXPORT_NUM_SAMPLES"}, 8607 {"bits": [12, 14], "name": "ALPHA_TO_MASK_NUM_SAMPLES"}, 8608 {"bits": [16, 16], "name": "HIGH_QUALITY_INTERSECTIONS"}, 8609 {"bits": [17, 17], "name": "INCOHERENT_EQAA_READS"}, 8610 {"bits": [18, 18], "name": "INTERPOLATE_COMP_Z"}, 8611 {"bits": [19, 19], "name": "INTERPOLATE_SRC_Z"}, 8612 {"bits": [20, 20], "name": "STATIC_ANCHOR_ASSOCIATIONS"}, 8613 {"bits": [21, 21], "name": "ALPHA_TO_MASK_EQAA_DISABLE"}, 8614 {"bits": [24, 26], "name": "OVERRASTERIZATION_AMOUNT"}, 8615 {"bits": [27, 27], "name": "ENABLE_POSTZ_OVERRASTERIZATION"} 8616 ] 8617 }, 8618 "DB_HTILE_SURFACE": { 8619 "fields": [ 8620 {"bits": [0, 0], "name": "LINEAR"}, 8621 {"bits": [1, 1], "name": "FULL_CACHE"}, 8622 {"bits": [2, 2], "name": "HTILE_USES_PRELOAD_WIN"}, 8623 {"bits": [3, 3], "name": "PRELOAD"}, 8624 {"bits": [4, 9], "name": "PREFETCH_WIDTH"}, 8625 {"bits": [10, 15], "name": "PREFETCH_HEIGHT"}, 8626 {"bits": [16, 16], "name": "DST_OUTSIDE_ZERO_TO_ONE"} 8627 ] 8628 }, 8629 "DB_PRELOAD_CONTROL": { 8630 "fields": [ 8631 {"bits": [0, 7], "name": "START_X"}, 8632 {"bits": [8, 15], "name": "START_Y"}, 8633 {"bits": [16, 23], "name": "MAX_X"}, 8634 {"bits": [24, 31], "name": "MAX_Y"} 8635 ] 8636 }, 8637 "DB_RENDER_CONTROL": { 8638 "fields": [ 8639 {"bits": [0, 0], "name": "DEPTH_CLEAR_ENABLE"}, 8640 {"bits": [1, 1], "name": "STENCIL_CLEAR_ENABLE"}, 8641 {"bits": [2, 2], "name": "DEPTH_COPY"}, 8642 {"bits": [3, 3], "name": "STENCIL_COPY"}, 8643 {"bits": [4, 4], "name": "RESUMMARIZE_ENABLE"}, 8644 {"bits": [5, 5], "name": "STENCIL_COMPRESS_DISABLE"}, 8645 {"bits": [6, 6], "name": "DEPTH_COMPRESS_DISABLE"}, 8646 {"bits": [7, 7], "name": "COPY_CENTROID"}, 8647 {"bits": [8, 11], "name": "COPY_SAMPLE"} 8648 ] 8649 }, 8650 "DB_RENDER_OVERRIDE": { 8651 "fields": [ 8652 {"bits": [0, 1], "enum_ref": "ForceControl", "name": "FORCE_HIZ_ENABLE"}, 8653 {"bits": [2, 3], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE0"}, 8654 {"bits": [4, 5], "enum_ref": "ForceControl", "name": "FORCE_HIS_ENABLE1"}, 8655 {"bits": [6, 6], "name": "FORCE_SHADER_Z_ORDER"}, 8656 {"bits": [7, 7], "name": "FAST_Z_DISABLE"}, 8657 {"bits": [8, 8], "name": "FAST_STENCIL_DISABLE"}, 8658 {"bits": [9, 9], "name": "NOOP_CULL_DISABLE"}, 8659 {"bits": [10, 10], "name": "FORCE_COLOR_KILL"}, 8660 {"bits": [11, 11], "name": "FORCE_Z_READ"}, 8661 {"bits": [12, 12], "name": "FORCE_STENCIL_READ"}, 8662 {"bits": [13, 14], "enum_ref": "ForceControl", "name": "FORCE_FULL_Z_RANGE"}, 8663 {"bits": [15, 15], "name": "FORCE_QC_SMASK_CONFLICT"}, 8664 {"bits": [16, 16], "name": "DISABLE_VIEWPORT_CLAMP"}, 8665 {"bits": [17, 17], "name": "IGNORE_SC_ZRANGE"}, 8666 {"bits": [18, 18], "name": "DISABLE_FULLY_COVERED"}, 8667 {"bits": [19, 20], "enum_ref": "ZLimitSumm", "name": "FORCE_Z_LIMIT_SUMM"}, 8668 {"bits": [21, 25], "name": "MAX_TILES_IN_DTT"}, 8669 {"bits": [26, 26], "name": "DISABLE_TILE_RATE_TILES"}, 8670 {"bits": [27, 27], "name": "FORCE_Z_DIRTY"}, 8671 {"bits": [28, 28], "name": "FORCE_STENCIL_DIRTY"}, 8672 {"bits": [29, 29], "name": "FORCE_Z_VALID"}, 8673 {"bits": [30, 30], "name": "FORCE_STENCIL_VALID"}, 8674 {"bits": [31, 31], "name": "PRESERVE_COMPRESSION"} 8675 ] 8676 }, 8677 "DB_RENDER_OVERRIDE2": { 8678 "fields": [ 8679 {"bits": [0, 1], "enum_ref": "DbPSLControl", "name": "PARTIAL_SQUAD_LAUNCH_CONTROL"}, 8680 {"bits": [2, 4], "name": "PARTIAL_SQUAD_LAUNCH_COUNTDOWN"}, 8681 {"bits": [5, 5], "name": "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION"}, 8682 {"bits": [6, 6], "name": "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION"}, 8683 {"bits": [7, 7], "name": "DISABLE_COLOR_ON_VALIDATION"}, 8684 {"bits": [8, 8], "name": "DECOMPRESS_Z_ON_FLUSH"}, 8685 {"bits": [9, 9], "name": "DISABLE_REG_SNOOP"}, 8686 {"bits": [10, 10], "name": "DEPTH_BOUNDS_HIER_DEPTH_DISABLE"}, 8687 {"bits": [11, 11], "name": "SEPARATE_HIZS_FUNC_ENABLE"}, 8688 {"bits": [12, 14], "enum_ref": "CompareFrag", "name": "HIZ_ZFUNC"}, 8689 {"bits": [15, 17], "name": "HIS_SFUNC_FF"}, 8690 {"bits": [18, 20], "name": "HIS_SFUNC_BF"}, 8691 {"bits": [21, 21], "name": "PRESERVE_ZRANGE"}, 8692 {"bits": [22, 22], "name": "PRESERVE_SRESULTS"}, 8693 {"bits": [23, 23], "name": "DISABLE_FAST_PASS"} 8694 ] 8695 }, 8696 "DB_SHADER_CONTROL": { 8697 "fields": [ 8698 {"bits": [0, 0], "name": "Z_EXPORT_ENABLE"}, 8699 {"bits": [1, 1], "name": "STENCIL_TEST_VAL_EXPORT_ENABLE"}, 8700 {"bits": [2, 2], "name": "STENCIL_OP_VAL_EXPORT_ENABLE"}, 8701 {"bits": [4, 5], "enum_ref": "ZOrder", "name": "Z_ORDER"}, 8702 {"bits": [6, 6], "name": "KILL_ENABLE"}, 8703 {"bits": [7, 7], "name": "COVERAGE_TO_MASK_ENABLE"}, 8704 {"bits": [8, 8], "name": "MASK_EXPORT_ENABLE"}, 8705 {"bits": [9, 9], "name": "EXEC_ON_HIER_FAIL"}, 8706 {"bits": [10, 10], "name": "EXEC_ON_NOOP"}, 8707 {"bits": [11, 11], "name": "ALPHA_TO_MASK_DISABLE"}, 8708 {"bits": [12, 12], "name": "DEPTH_BEFORE_SHADER"}, 8709 {"bits": [13, 14], "enum_ref": "ConservativeZExport", "name": "CONSERVATIVE_Z_EXPORT"} 8710 ] 8711 }, 8712 "DB_SRESULTS_COMPARE_STATE0": { 8713 "fields": [ 8714 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC0"}, 8715 {"bits": [4, 11], "name": "COMPAREVALUE0"}, 8716 {"bits": [12, 19], "name": "COMPAREMASK0"}, 8717 {"bits": [24, 24], "name": "ENABLE0"} 8718 ] 8719 }, 8720 "DB_SRESULTS_COMPARE_STATE1": { 8721 "fields": [ 8722 {"bits": [0, 2], "enum_ref": "CompareFrag", "name": "COMPAREFUNC1"}, 8723 {"bits": [4, 11], "name": "COMPAREVALUE1"}, 8724 {"bits": [12, 19], "name": "COMPAREMASK1"}, 8725 {"bits": [24, 24], "name": "ENABLE1"} 8726 ] 8727 }, 8728 "DB_STENCILREFMASK": { 8729 "fields": [ 8730 {"bits": [0, 7], "name": "STENCILTESTVAL"}, 8731 {"bits": [8, 15], "name": "STENCILMASK"}, 8732 {"bits": [16, 23], "name": "STENCILWRITEMASK"}, 8733 {"bits": [24, 31], "name": "STENCILOPVAL"} 8734 ] 8735 }, 8736 "DB_STENCILREFMASK_BF": { 8737 "fields": [ 8738 {"bits": [0, 7], "name": "STENCILTESTVAL_BF"}, 8739 {"bits": [8, 15], "name": "STENCILMASK_BF"}, 8740 {"bits": [16, 23], "name": "STENCILWRITEMASK_BF"}, 8741 {"bits": [24, 31], "name": "STENCILOPVAL_BF"} 8742 ] 8743 }, 8744 "DB_STENCIL_CLEAR": { 8745 "fields": [ 8746 {"bits": [0, 7], "name": "CLEAR"} 8747 ] 8748 }, 8749 "DB_STENCIL_CONTROL": { 8750 "fields": [ 8751 {"bits": [0, 3], "enum_ref": "StencilOp", "name": "STENCILFAIL"}, 8752 {"bits": [4, 7], "enum_ref": "StencilOp", "name": "STENCILZPASS"}, 8753 {"bits": [8, 11], "enum_ref": "StencilOp", "name": "STENCILZFAIL"}, 8754 {"bits": [12, 15], "enum_ref": "StencilOp", "name": "STENCILFAIL_BF"}, 8755 {"bits": [16, 19], "enum_ref": "StencilOp", "name": "STENCILZPASS_BF"}, 8756 {"bits": [20, 23], "enum_ref": "StencilOp", "name": "STENCILZFAIL_BF"} 8757 ] 8758 }, 8759 "DB_STENCIL_INFO": { 8760 "fields": [ 8761 {"bits": [0, 0], "enum_ref": "StencilFormat", "name": "FORMAT"}, 8762 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8763 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, 8764 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 8765 {"bits": [29, 29], "name": "TILE_STENCIL_DISABLE"} 8766 ] 8767 }, 8768 "DB_Z_INFO": { 8769 "fields": [ 8770 {"bits": [0, 1], "enum_ref": "ZFormat", "name": "FORMAT"}, 8771 {"bits": [2, 3], "name": "NUM_SAMPLES"}, 8772 {"bits": [13, 15], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8773 {"bits": [20, 22], "name": "TILE_MODE_INDEX"}, 8774 {"bits": [27, 27], "name": "ALLOW_EXPCLEAR"}, 8775 {"bits": [28, 28], "name": "READ_SIZE"}, 8776 {"bits": [29, 29], "name": "TILE_SURFACE_ENABLE"}, 8777 {"bits": [31, 31], "name": "ZRANGE_PRECISION"} 8778 ] 8779 }, 8780 "DEBUG_INDEX": { 8781 "fields": [ 8782 {"bits": [0, 17], "name": "DEBUG_INDEX"} 8783 ] 8784 }, 8785 "GB_ADDR_CONFIG": { 8786 "fields": [ 8787 {"bits": [0, 2], "name": "NUM_PIPES"}, 8788 {"bits": [4, 6], "name": "PIPE_INTERLEAVE_SIZE"}, 8789 {"bits": [8, 10], "name": "BANK_INTERLEAVE_SIZE"}, 8790 {"bits": [12, 13], "name": "NUM_SHADER_ENGINES"}, 8791 {"bits": [16, 18], "name": "SHADER_ENGINE_TILE_SIZE"}, 8792 {"bits": [20, 22], "name": "NUM_GPUS"}, 8793 {"bits": [24, 25], "name": "MULTI_GPU_TILE_SIZE"}, 8794 {"bits": [28, 29], "name": "ROW_SIZE"}, 8795 {"bits": [30, 30], "name": "NUM_LOWER_PIPES"} 8796 ] 8797 }, 8798 "GB_TILE_MODE0": { 8799 "fields": [ 8800 {"bits": [0, 1], "enum_ref": "GB_TILE_MODE0__MICRO_TILE_MODE", "name": "MICRO_TILE_MODE"}, 8801 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 8802 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 8803 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8804 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 8805 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 8806 ] 8807 }, 8808 "GB_TILE_MODE10": { 8809 "fields": [ 8810 {"bits": [2, 5], "enum_ref": "ArrayMode", "name": "ARRAY_MODE"}, 8811 {"bits": [6, 10], "enum_ref": "PipeConfig", "name": "PIPE_CONFIG"}, 8812 {"bits": [11, 13], "enum_ref": "TileSplit", "name": "TILE_SPLIT"}, 8813 {"bits": [22, 24], "enum_ref": "MicroTileMode", "name": "MICRO_TILE_MODE_NEW"}, 8814 {"bits": [25, 26], "name": "SAMPLE_SPLIT"} 8815 ] 8816 }, 8817 "GRBM_CNTL": { 8818 "fields": [ 8819 {"bits": [0, 7], "name": "READ_TIMEOUT"} 8820 ] 8821 }, 8822 "GRBM_DEBUG": { 8823 "fields": [ 8824 {"bits": [1, 1], "name": "IGNORE_RDY"}, 8825 {"bits": [5, 5], "name": "IGNORE_FAO"}, 8826 {"bits": [6, 6], "name": "DISABLE_READ_TIMEOUT"}, 8827 {"bits": [7, 7], "name": "SNAPSHOT_FREE_CNTRS"}, 8828 {"bits": [8, 11], "name": "HYSTERESIS_GUI_ACTIVE"}, 8829 {"bits": [12, 12], "name": "GFX_CLOCK_DOMAIN_OVERRIDE"} 8830 ] 8831 }, 8832 "GRBM_DEBUG_CNTL": { 8833 "fields": [ 8834 {"bits": [0, 5], "name": "GRBM_DEBUG_INDEX"} 8835 ] 8836 }, 8837 "GRBM_DEBUG_SNAPSHOT": { 8838 "fields": [ 8839 {"bits": [0, 0], "name": "CPF_RDY"}, 8840 {"bits": [1, 1], "name": "CPG_RDY"}, 8841 {"bits": [1, 1], "name": "SRBM_RDY"}, 8842 {"bits": [3, 3], "name": "WD_ME0PIPE0_RDY"}, 8843 {"bits": [4, 4], "name": "WD_ME0PIPE1_RDY"}, 8844 {"bits": [6, 6], "name": "SE0SPI_ME0PIPE0_RDY0"}, 8845 {"bits": [7, 7], "name": "SE0SPI_ME0PIPE1_RDY0"}, 8846 {"bits": [8, 8], "name": "SE1SPI_ME0PIPE0_RDY0"}, 8847 {"bits": [9, 9], "name": "GDS_RDY"}, 8848 {"bits": [9, 9], "name": "SE1SPI_ME0PIPE1_RDY0"}, 8849 {"bits": [10, 10], "name": "SE2SPI_ME0PIPE0_RDY0"}, 8850 {"bits": [11, 11], "name": "SE2SPI_ME0PIPE1_RDY0"}, 8851 {"bits": [12, 12], "name": "SE3SPI_ME0PIPE0_RDY0"}, 8852 {"bits": [13, 13], "name": "SE3SPI_ME0PIPE1_RDY0"}, 8853 {"bits": [14, 14], "name": "SE0SPI_ME0PIPE0_RDY1"}, 8854 {"bits": [15, 15], "name": "SE0SPI_ME0PIPE1_RDY1"}, 8855 {"bits": [16, 16], "name": "SE1SPI_ME0PIPE0_RDY1"}, 8856 {"bits": [17, 17], "name": "SE1SPI_ME0PIPE1_RDY1"}, 8857 {"bits": [18, 18], "name": "SE2SPI_ME0PIPE0_RDY1"}, 8858 {"bits": [19, 19], "name": "SE2SPI_ME0PIPE1_RDY1"}, 8859 {"bits": [20, 20], "name": "SE3SPI_ME0PIPE0_RDY1"}, 8860 {"bits": [21, 21], "name": "SE3SPI_ME0PIPE1_RDY1"} 8861 ] 8862 }, 8863 "GRBM_GFX_CLKEN_CNTL": { 8864 "fields": [ 8865 {"bits": [0, 3], "name": "PREFIX_DELAY_CNT"}, 8866 {"bits": [8, 12], "name": "POST_DELAY_CNT"} 8867 ] 8868 }, 8869 "GRBM_GFX_INDEX": { 8870 "fields": [ 8871 {"bits": [0, 7], "name": "INSTANCE_INDEX"}, 8872 {"bits": [8, 15], "name": "SH_INDEX"}, 8873 {"bits": [16, 23], "name": "SE_INDEX"}, 8874 {"bits": [29, 29], "name": "SH_BROADCAST_WRITES"}, 8875 {"bits": [30, 30], "name": "INSTANCE_BROADCAST_WRITES"}, 8876 {"bits": [31, 31], "name": "SE_BROADCAST_WRITES"} 8877 ] 8878 }, 8879 "GRBM_INT_CNTL": { 8880 "fields": [ 8881 {"bits": [0, 0], "name": "RDERR_INT_ENABLE"}, 8882 {"bits": [19, 19], "name": "GUI_IDLE_INT_ENABLE"} 8883 ] 8884 }, 8885 "GRBM_PERFCOUNTER0_SELECT": { 8886 "fields": [ 8887 {"bits": [0, 5], "name": "PERF_SEL"}, 8888 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 8889 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 8890 {"bits": [12, 12], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 8891 {"bits": [13, 13], "name": "TA_BUSY_USER_DEFINED_MASK"}, 8892 {"bits": [14, 14], "name": "SX_BUSY_USER_DEFINED_MASK"}, 8893 {"bits": [16, 16], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 8894 {"bits": [17, 17], "name": "SC_BUSY_USER_DEFINED_MASK"}, 8895 {"bits": [18, 18], "name": "PA_BUSY_USER_DEFINED_MASK"}, 8896 {"bits": [19, 19], "name": "GRBM_BUSY_USER_DEFINED_MASK"}, 8897 {"bits": [20, 20], "name": "DB_BUSY_USER_DEFINED_MASK"}, 8898 {"bits": [21, 21], "name": "CB_BUSY_USER_DEFINED_MASK"}, 8899 {"bits": [22, 22], "name": "CP_BUSY_USER_DEFINED_MASK"}, 8900 {"bits": [23, 23], "name": "IA_BUSY_USER_DEFINED_MASK"}, 8901 {"bits": [24, 24], "name": "GDS_BUSY_USER_DEFINED_MASK"}, 8902 {"bits": [25, 25], "name": "BCI_BUSY_USER_DEFINED_MASK"}, 8903 {"bits": [26, 26], "name": "RLC_BUSY_USER_DEFINED_MASK"}, 8904 {"bits": [27, 27], "name": "TC_BUSY_USER_DEFINED_MASK"}, 8905 {"bits": [28, 28], "name": "WD_BUSY_USER_DEFINED_MASK"} 8906 ] 8907 }, 8908 "GRBM_PWR_CNTL": { 8909 "fields": [ 8910 {"bits": [0, 3], "name": "REQ_TYPE"}, 8911 {"bits": [4, 7], "name": "RSP_TYPE"} 8912 ] 8913 }, 8914 "GRBM_READ_ERROR": { 8915 "fields": [ 8916 {"bits": [2, 17], "name": "READ_ADDRESS"}, 8917 {"bits": [20, 21], "name": "READ_PIPEID"}, 8918 {"bits": [22, 23], "name": "READ_MEID"}, 8919 {"bits": [31, 31], "name": "READ_ERROR"} 8920 ] 8921 }, 8922 "GRBM_SE0_PERFCOUNTER_SELECT": { 8923 "fields": [ 8924 {"bits": [0, 5], "name": "PERF_SEL"}, 8925 {"bits": [10, 10], "name": "DB_CLEAN_USER_DEFINED_MASK"}, 8926 {"bits": [11, 11], "name": "CB_CLEAN_USER_DEFINED_MASK"}, 8927 {"bits": [12, 12], "name": "TA_BUSY_USER_DEFINED_MASK"}, 8928 {"bits": [13, 13], "name": "SX_BUSY_USER_DEFINED_MASK"}, 8929 {"bits": [15, 15], "name": "SPI_BUSY_USER_DEFINED_MASK"}, 8930 {"bits": [16, 16], "name": "SC_BUSY_USER_DEFINED_MASK"}, 8931 {"bits": [17, 17], "name": "DB_BUSY_USER_DEFINED_MASK"}, 8932 {"bits": [18, 18], "name": "CB_BUSY_USER_DEFINED_MASK"}, 8933 {"bits": [19, 19], "name": "VGT_BUSY_USER_DEFINED_MASK"}, 8934 {"bits": [20, 20], "name": "PA_BUSY_USER_DEFINED_MASK"}, 8935 {"bits": [21, 21], "name": "BCI_BUSY_USER_DEFINED_MASK"} 8936 ] 8937 }, 8938 "GRBM_SKEW_CNTL": { 8939 "fields": [ 8940 {"bits": [0, 5], "name": "SKEW_TOP_THRESHOLD"}, 8941 {"bits": [6, 11], "name": "SKEW_COUNT"} 8942 ] 8943 }, 8944 "GRBM_SOFT_RESET": { 8945 "fields": [ 8946 {"bits": [0, 0], "name": "SOFT_RESET_CP"}, 8947 {"bits": [2, 2], "name": "SOFT_RESET_RLC"}, 8948 {"bits": [16, 16], "name": "SOFT_RESET_GFX"}, 8949 {"bits": [17, 17], "name": "SOFT_RESET_CPF"}, 8950 {"bits": [18, 18], "name": "SOFT_RESET_CPC"}, 8951 {"bits": [19, 19], "name": "SOFT_RESET_CPG"} 8952 ] 8953 }, 8954 "GRBM_STATUS": { 8955 "fields": [ 8956 {"bits": [0, 3], "name": "ME0PIPE0_CMDFIFO_AVAIL"}, 8957 {"bits": [5, 5], "name": "SRBM_RQ_PENDING"}, 8958 {"bits": [7, 7], "name": "ME0PIPE0_CF_RQ_PENDING"}, 8959 {"bits": [8, 8], "name": "ME0PIPE0_PF_RQ_PENDING"}, 8960 {"bits": [9, 9], "name": "GDS_DMA_RQ_PENDING"}, 8961 {"bits": [12, 12], "name": "DB_CLEAN"}, 8962 {"bits": [13, 13], "name": "CB_CLEAN"}, 8963 {"bits": [14, 14], "name": "TA_BUSY"}, 8964 {"bits": [15, 15], "name": "GDS_BUSY"}, 8965 {"bits": [16, 16], "name": "WD_BUSY_NO_DMA"}, 8966 {"bits": [17, 17], "name": "VGT_BUSY"}, 8967 {"bits": [18, 18], "name": "IA_BUSY_NO_DMA"}, 8968 {"bits": [19, 19], "name": "IA_BUSY"}, 8969 {"bits": [20, 20], "name": "SX_BUSY"}, 8970 {"bits": [21, 21], "name": "WD_BUSY"}, 8971 {"bits": [22, 22], "name": "SPI_BUSY"}, 8972 {"bits": [23, 23], "name": "BCI_BUSY"}, 8973 {"bits": [24, 24], "name": "SC_BUSY"}, 8974 {"bits": [25, 25], "name": "PA_BUSY"}, 8975 {"bits": [26, 26], "name": "DB_BUSY"}, 8976 {"bits": [28, 28], "name": "CP_COHERENCY_BUSY"}, 8977 {"bits": [29, 29], "name": "CP_BUSY"}, 8978 {"bits": [30, 30], "name": "CB_BUSY"}, 8979 {"bits": [31, 31], "name": "GUI_ACTIVE"} 8980 ] 8981 }, 8982 "GRBM_STATUS2": { 8983 "fields": [ 8984 {"bits": [0, 3], "name": "ME0PIPE1_CMDFIFO_AVAIL"}, 8985 {"bits": [0, 0], "name": "RLC_RQ_PENDING"}, 8986 {"bits": [4, 4], "name": "ME0PIPE1_CF_RQ_PENDING"}, 8987 {"bits": [5, 5], "name": "ME0PIPE1_PF_RQ_PENDING"}, 8988 {"bits": [6, 6], "name": "ME1PIPE0_RQ_PENDING"}, 8989 {"bits": [7, 7], "name": "ME1PIPE1_RQ_PENDING"}, 8990 {"bits": [8, 8], "name": "ME1PIPE2_RQ_PENDING"}, 8991 {"bits": [8, 8], "name": "RLC_BUSY"}, 8992 {"bits": [9, 9], "name": "ME1PIPE3_RQ_PENDING"}, 8993 {"bits": [9, 9], "name": "TC_BUSY"}, 8994 {"bits": [10, 10], "name": "ME2PIPE0_RQ_PENDING"}, 8995 {"bits": [11, 11], "name": "ME2PIPE1_RQ_PENDING"}, 8996 {"bits": [12, 12], "name": "ME2PIPE2_RQ_PENDING"}, 8997 {"bits": [13, 13], "name": "ME2PIPE3_RQ_PENDING"}, 8998 {"bits": [28, 28], "name": "CPF_BUSY"}, 8999 {"bits": [29, 29], "name": "CPC_BUSY"}, 9000 {"bits": [30, 30], "name": "CPG_BUSY"} 9001 ] 9002 }, 9003 "GRBM_STATUS_SE0": { 9004 "fields": [ 9005 {"bits": [1, 1], "name": "DB_CLEAN"}, 9006 {"bits": [2, 2], "name": "CB_CLEAN"}, 9007 {"bits": [22, 22], "name": "BCI_BUSY"}, 9008 {"bits": [23, 23], "name": "VGT_BUSY"}, 9009 {"bits": [24, 24], "name": "PA_BUSY"}, 9010 {"bits": [25, 25], "name": "TA_BUSY"}, 9011 {"bits": [26, 26], "name": "SX_BUSY"}, 9012 {"bits": [27, 27], "name": "SPI_BUSY"}, 9013 {"bits": [29, 29], "name": "SC_BUSY"}, 9014 {"bits": [30, 30], "name": "DB_BUSY"}, 9015 {"bits": [31, 31], "name": "CB_BUSY"} 9016 ] 9017 }, 9018 "GRBM_WAIT_IDLE_CLOCKS": { 9019 "fields": [ 9020 {"bits": [0, 7], "name": "WAIT_IDLE_CLOCKS"} 9021 ] 9022 }, 9023 "IA_CNTL_STATUS": { 9024 "fields": [ 9025 {"bits": [0, 0], "name": "IA_BUSY"}, 9026 {"bits": [1, 1], "name": "IA_DMA_BUSY"}, 9027 {"bits": [2, 2], "name": "IA_DMA_REQ_BUSY"}, 9028 {"bits": [3, 3], "name": "IA_GRP_BUSY"}, 9029 {"bits": [4, 4], "name": "IA_ADC_BUSY"} 9030 ] 9031 }, 9032 "IA_DEBUG_CNTL": { 9033 "fields": [ 9034 {"bits": [0, 5], "name": "IA_DEBUG_INDX"}, 9035 {"bits": [6, 6], "name": "IA_DEBUG_SEL_BUS_B"} 9036 ] 9037 }, 9038 "IA_MULTI_VGT_PARAM": { 9039 "fields": [ 9040 {"bits": [0, 15], "name": "PRIMGROUP_SIZE"}, 9041 {"bits": [16, 16], "name": "PARTIAL_VS_WAVE_ON"}, 9042 {"bits": [17, 17], "name": "SWITCH_ON_EOP"}, 9043 {"bits": [18, 18], "name": "PARTIAL_ES_WAVE_ON"}, 9044 {"bits": [19, 19], "name": "SWITCH_ON_EOI"}, 9045 {"bits": [20, 20], "name": "WD_SWITCH_ON_EOP"} 9046 ] 9047 }, 9048 "IA_PERFCOUNTER0_SELECT": { 9049 "fields": [ 9050 {"bits": [0, 7], "name": "PERF_SEL"}, 9051 {"bits": [10, 19], "name": "PERF_SEL1"}, 9052 {"bits": [20, 23], "name": "CNTR_MODE"}, 9053 {"bits": [24, 27], "name": "PERF_MODE1"}, 9054 {"bits": [28, 31], "name": "PERF_MODE"} 9055 ] 9056 }, 9057 "IA_PERFCOUNTER1_SELECT": { 9058 "fields": [ 9059 {"bits": [0, 7], "name": "PERF_SEL"}, 9060 {"bits": [28, 31], "name": "PERF_MODE"} 9061 ] 9062 }, 9063 "IA_VMID_OVERRIDE": { 9064 "fields": [ 9065 {"bits": [0, 0], "name": "ENABLE"}, 9066 {"bits": [1, 4], "name": "VMID"} 9067 ] 9068 }, 9069 "PA_CL_CLIP_CNTL": { 9070 "fields": [ 9071 {"bits": [0, 0], "name": "UCP_ENA_0"}, 9072 {"bits": [1, 1], "name": "UCP_ENA_1"}, 9073 {"bits": [2, 2], "name": "UCP_ENA_2"}, 9074 {"bits": [3, 3], "name": "UCP_ENA_3"}, 9075 {"bits": [4, 4], "name": "UCP_ENA_4"}, 9076 {"bits": [5, 5], "name": "UCP_ENA_5"}, 9077 {"bits": [13, 13], "name": "PS_UCP_Y_SCALE_NEG"}, 9078 {"bits": [14, 15], "name": "PS_UCP_MODE"}, 9079 {"bits": [16, 16], "name": "CLIP_DISABLE"}, 9080 {"bits": [17, 17], "name": "UCP_CULL_ONLY_ENA"}, 9081 {"bits": [18, 18], "name": "BOUNDARY_EDGE_FLAG_ENA"}, 9082 {"bits": [19, 19], "name": "DX_CLIP_SPACE_DEF"}, 9083 {"bits": [20, 20], "name": "DIS_CLIP_ERR_DETECT"}, 9084 {"bits": [21, 21], "name": "VTX_KILL_OR"}, 9085 {"bits": [22, 22], "name": "DX_RASTERIZATION_KILL"}, 9086 {"bits": [24, 24], "name": "DX_LINEAR_ATTR_CLIP_ENA"}, 9087 {"bits": [25, 25], "name": "VTE_VPORT_PROVOKE_DISABLE"}, 9088 {"bits": [26, 26], "name": "ZCLIP_NEAR_DISABLE"}, 9089 {"bits": [27, 27], "name": "ZCLIP_FAR_DISABLE"} 9090 ] 9091 }, 9092 "PA_CL_CNTL_STATUS": { 9093 "fields": [ 9094 {"bits": [31, 31], "name": "CL_BUSY"} 9095 ] 9096 }, 9097 "PA_CL_ENHANCE": { 9098 "fields": [ 9099 {"bits": [0, 0], "name": "CLIP_VTX_REORDER_ENA"}, 9100 {"bits": [1, 2], "name": "NUM_CLIP_SEQ"}, 9101 {"bits": [3, 3], "name": "CLIPPED_PRIM_SEQ_STALL"}, 9102 {"bits": [4, 4], "name": "VE_NAN_PROC_DISABLE"}, 9103 {"bits": [5, 5], "name": "XTRA_DEBUG_REG_SEL"}, 9104 {"bits": [28, 28], "name": "ECO_SPARE3"}, 9105 {"bits": [29, 29], "name": "ECO_SPARE2"}, 9106 {"bits": [30, 30], "name": "ECO_SPARE1"}, 9107 {"bits": [31, 31], "name": "ECO_SPARE0"} 9108 ] 9109 }, 9110 "PA_CL_NANINF_CNTL": { 9111 "fields": [ 9112 {"bits": [0, 0], "name": "VTE_XY_INF_DISCARD"}, 9113 {"bits": [1, 1], "name": "VTE_Z_INF_DISCARD"}, 9114 {"bits": [2, 2], "name": "VTE_W_INF_DISCARD"}, 9115 {"bits": [3, 3], "name": "VTE_0XNANINF_IS_0"}, 9116 {"bits": [4, 4], "name": "VTE_XY_NAN_RETAIN"}, 9117 {"bits": [5, 5], "name": "VTE_Z_NAN_RETAIN"}, 9118 {"bits": [6, 6], "name": "VTE_W_NAN_RETAIN"}, 9119 {"bits": [7, 7], "name": "VTE_W_RECIP_NAN_IS_0"}, 9120 {"bits": [8, 8], "name": "VS_XY_NAN_TO_INF"}, 9121 {"bits": [9, 9], "name": "VS_XY_INF_RETAIN"}, 9122 {"bits": [10, 10], "name": "VS_Z_NAN_TO_INF"}, 9123 {"bits": [11, 11], "name": "VS_Z_INF_RETAIN"}, 9124 {"bits": [12, 12], "name": "VS_W_NAN_TO_INF"}, 9125 {"bits": [13, 13], "name": "VS_W_INF_RETAIN"}, 9126 {"bits": [14, 14], "name": "VS_CLIP_DIST_INF_DISCARD"}, 9127 {"bits": [20, 20], "name": "VTE_NO_OUTPUT_NEG_0"} 9128 ] 9129 }, 9130 "PA_CL_VS_OUT_CNTL": { 9131 "fields": [ 9132 {"bits": [0, 0], "name": "CLIP_DIST_ENA_0"}, 9133 {"bits": [1, 1], "name": "CLIP_DIST_ENA_1"}, 9134 {"bits": [2, 2], "name": "CLIP_DIST_ENA_2"}, 9135 {"bits": [3, 3], "name": "CLIP_DIST_ENA_3"}, 9136 {"bits": [4, 4], "name": "CLIP_DIST_ENA_4"}, 9137 {"bits": [5, 5], "name": "CLIP_DIST_ENA_5"}, 9138 {"bits": [6, 6], "name": "CLIP_DIST_ENA_6"}, 9139 {"bits": [7, 7], "name": "CLIP_DIST_ENA_7"}, 9140 {"bits": [8, 8], "name": "CULL_DIST_ENA_0"}, 9141 {"bits": [9, 9], "name": "CULL_DIST_ENA_1"}, 9142 {"bits": [10, 10], "name": "CULL_DIST_ENA_2"}, 9143 {"bits": [11, 11], "name": "CULL_DIST_ENA_3"}, 9144 {"bits": [12, 12], "name": "CULL_DIST_ENA_4"}, 9145 {"bits": [13, 13], "name": "CULL_DIST_ENA_5"}, 9146 {"bits": [14, 14], "name": "CULL_DIST_ENA_6"}, 9147 {"bits": [15, 15], "name": "CULL_DIST_ENA_7"}, 9148 {"bits": [16, 16], "name": "USE_VTX_POINT_SIZE"}, 9149 {"bits": [17, 17], "name": "USE_VTX_EDGE_FLAG"}, 9150 {"bits": [18, 18], "name": "USE_VTX_RENDER_TARGET_INDX"}, 9151 {"bits": [19, 19], "name": "USE_VTX_VIEWPORT_INDX"}, 9152 {"bits": [20, 20], "name": "USE_VTX_KILL_FLAG"}, 9153 {"bits": [21, 21], "name": "VS_OUT_MISC_VEC_ENA"}, 9154 {"bits": [22, 22], "name": "VS_OUT_CCDIST0_VEC_ENA"}, 9155 {"bits": [23, 23], "name": "VS_OUT_CCDIST1_VEC_ENA"}, 9156 {"bits": [24, 24], "name": "VS_OUT_MISC_SIDE_BUS_ENA"}, 9157 {"bits": [25, 25], "name": "USE_VTX_GS_CUT_FLAG"} 9158 ] 9159 }, 9160 "PA_CL_VTE_CNTL": { 9161 "fields": [ 9162 {"bits": [0, 0], "name": "VPORT_X_SCALE_ENA"}, 9163 {"bits": [1, 1], "name": "VPORT_X_OFFSET_ENA"}, 9164 {"bits": [2, 2], "name": "VPORT_Y_SCALE_ENA"}, 9165 {"bits": [3, 3], "name": "VPORT_Y_OFFSET_ENA"}, 9166 {"bits": [4, 4], "name": "VPORT_Z_SCALE_ENA"}, 9167 {"bits": [5, 5], "name": "VPORT_Z_OFFSET_ENA"}, 9168 {"bits": [8, 8], "name": "VTX_XY_FMT"}, 9169 {"bits": [9, 9], "name": "VTX_Z_FMT"}, 9170 {"bits": [10, 10], "name": "VTX_W0_FMT"}, 9171 {"bits": [11, 11], "name": "PERFCOUNTER_REF"} 9172 ] 9173 }, 9174 "PA_SC_AA_CONFIG": { 9175 "fields": [ 9176 {"bits": [0, 2], "name": "MSAA_NUM_SAMPLES"}, 9177 {"bits": [4, 4], "name": "AA_MASK_CENTROID_DTMN"}, 9178 {"bits": [13, 16], "name": "MAX_SAMPLE_DIST"}, 9179 {"bits": [20, 22], "name": "MSAA_EXPOSED_SAMPLES"}, 9180 {"bits": [24, 25], "name": "DETAIL_TO_EXPOSED_MODE"} 9181 ] 9182 }, 9183 "PA_SC_AA_MASK_X0Y0_X1Y0": { 9184 "fields": [ 9185 {"bits": [0, 15], "name": "AA_MASK_X0Y0"}, 9186 {"bits": [16, 31], "name": "AA_MASK_X1Y0"} 9187 ] 9188 }, 9189 "PA_SC_AA_MASK_X0Y1_X1Y1": { 9190 "fields": [ 9191 {"bits": [0, 15], "name": "AA_MASK_X0Y1"}, 9192 {"bits": [16, 31], "name": "AA_MASK_X1Y1"} 9193 ] 9194 }, 9195 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0": { 9196 "fields": [ 9197 {"bits": [0, 3], "name": "S0_X"}, 9198 {"bits": [4, 7], "name": "S0_Y"}, 9199 {"bits": [8, 11], "name": "S1_X"}, 9200 {"bits": [12, 15], "name": "S1_Y"}, 9201 {"bits": [16, 19], "name": "S2_X"}, 9202 {"bits": [20, 23], "name": "S2_Y"}, 9203 {"bits": [24, 27], "name": "S3_X"}, 9204 {"bits": [28, 31], "name": "S3_Y"} 9205 ] 9206 }, 9207 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1": { 9208 "fields": [ 9209 {"bits": [0, 3], "name": "S4_X"}, 9210 {"bits": [4, 7], "name": "S4_Y"}, 9211 {"bits": [8, 11], "name": "S5_X"}, 9212 {"bits": [12, 15], "name": "S5_Y"}, 9213 {"bits": [16, 19], "name": "S6_X"}, 9214 {"bits": [20, 23], "name": "S6_Y"}, 9215 {"bits": [24, 27], "name": "S7_X"}, 9216 {"bits": [28, 31], "name": "S7_Y"} 9217 ] 9218 }, 9219 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2": { 9220 "fields": [ 9221 {"bits": [0, 3], "name": "S8_X"}, 9222 {"bits": [4, 7], "name": "S8_Y"}, 9223 {"bits": [8, 11], "name": "S9_X"}, 9224 {"bits": [12, 15], "name": "S9_Y"}, 9225 {"bits": [16, 19], "name": "S10_X"}, 9226 {"bits": [20, 23], "name": "S10_Y"}, 9227 {"bits": [24, 27], "name": "S11_X"}, 9228 {"bits": [28, 31], "name": "S11_Y"} 9229 ] 9230 }, 9231 "PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3": { 9232 "fields": [ 9233 {"bits": [0, 3], "name": "S12_X"}, 9234 {"bits": [4, 7], "name": "S12_Y"}, 9235 {"bits": [8, 11], "name": "S13_X"}, 9236 {"bits": [12, 15], "name": "S13_Y"}, 9237 {"bits": [16, 19], "name": "S14_X"}, 9238 {"bits": [20, 23], "name": "S14_Y"}, 9239 {"bits": [24, 27], "name": "S15_X"}, 9240 {"bits": [28, 31], "name": "S15_Y"} 9241 ] 9242 }, 9243 "PA_SC_CENTROID_PRIORITY_0": { 9244 "fields": [ 9245 {"bits": [0, 3], "name": "DISTANCE_0"}, 9246 {"bits": [4, 7], "name": "DISTANCE_1"}, 9247 {"bits": [8, 11], "name": "DISTANCE_2"}, 9248 {"bits": [12, 15], "name": "DISTANCE_3"}, 9249 {"bits": [16, 19], "name": "DISTANCE_4"}, 9250 {"bits": [20, 23], "name": "DISTANCE_5"}, 9251 {"bits": [24, 27], "name": "DISTANCE_6"}, 9252 {"bits": [28, 31], "name": "DISTANCE_7"} 9253 ] 9254 }, 9255 "PA_SC_CENTROID_PRIORITY_1": { 9256 "fields": [ 9257 {"bits": [0, 3], "name": "DISTANCE_8"}, 9258 {"bits": [4, 7], "name": "DISTANCE_9"}, 9259 {"bits": [8, 11], "name": "DISTANCE_10"}, 9260 {"bits": [12, 15], "name": "DISTANCE_11"}, 9261 {"bits": [16, 19], "name": "DISTANCE_12"}, 9262 {"bits": [20, 23], "name": "DISTANCE_13"}, 9263 {"bits": [24, 27], "name": "DISTANCE_14"}, 9264 {"bits": [28, 31], "name": "DISTANCE_15"} 9265 ] 9266 }, 9267 "PA_SC_CLIPRECT_0_BR": { 9268 "fields": [ 9269 {"bits": [0, 14], "name": "BR_X"}, 9270 {"bits": [16, 30], "name": "BR_Y"} 9271 ] 9272 }, 9273 "PA_SC_CLIPRECT_0_TL": { 9274 "fields": [ 9275 {"bits": [0, 14], "name": "TL_X"}, 9276 {"bits": [16, 30], "name": "TL_Y"} 9277 ] 9278 }, 9279 "PA_SC_CLIPRECT_RULE": { 9280 "fields": [ 9281 {"bits": [0, 15], "enum_ref": "CLIP_RULE", "name": "CLIP_RULE"} 9282 ] 9283 }, 9284 "PA_SC_DEBUG_CNTL": { 9285 "fields": [ 9286 {"bits": [0, 5], "name": "SC_DEBUG_INDX"} 9287 ] 9288 }, 9289 "PA_SC_EDGERULE": { 9290 "fields": [ 9291 {"bits": [0, 3], "name": "ER_TRI"}, 9292 {"bits": [4, 7], "name": "ER_POINT"}, 9293 {"bits": [8, 11], "name": "ER_RECT"}, 9294 {"bits": [12, 17], "name": "ER_LINE_LR"}, 9295 {"bits": [18, 23], "name": "ER_LINE_RL"}, 9296 {"bits": [24, 27], "name": "ER_LINE_TB"}, 9297 {"bits": [28, 31], "name": "ER_LINE_BT"} 9298 ] 9299 }, 9300 "PA_SC_ENHANCE": { 9301 "fields": [ 9302 {"bits": [0, 0], "name": "ENABLE_PA_SC_OUT_OF_ORDER"}, 9303 {"bits": [1, 1], "name": "DISABLE_SC_DB_TILE_FIX"}, 9304 {"bits": [2, 2], "name": "DISABLE_AA_MASK_FULL_FIX"}, 9305 {"bits": [3, 3], "name": "ENABLE_1XMSAA_SAMPLE_LOCATIONS"}, 9306 {"bits": [4, 4], "name": "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID"}, 9307 {"bits": [5, 5], "name": "DISABLE_SCISSOR_FIX"}, 9308 {"bits": [6, 7], "name": "DISABLE_PW_BUBBLE_COLLAPSE"}, 9309 {"bits": [8, 8], "name": "SEND_UNLIT_STILES_TO_PACKER"}, 9310 {"bits": [9, 9], "name": "DISABLE_DUALGRAD_PERF_OPTIMIZATION"}, 9311 {"bits": [10, 10], "name": "DISABLE_SC_PROCESS_RESET_PRIM"}, 9312 {"bits": [11, 11], "name": "DISABLE_SC_PROCESS_RESET_SUPERTILE"}, 9313 {"bits": [12, 12], "name": "DISABLE_SC_PROCESS_RESET_TILE"}, 9314 {"bits": [13, 13], "name": "DISABLE_PA_SC_GUIDANCE"}, 9315 {"bits": [14, 14], "name": "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS"}, 9316 {"bits": [15, 15], "name": "ENABLE_MULTICYCLE_BUBBLE_FREEZE"}, 9317 {"bits": [16, 16], "name": "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE"}, 9318 {"bits": [17, 17], "name": "ENABLE_OUT_OF_ORDER_POLY_MODE"}, 9319 {"bits": [18, 18], "name": "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST"}, 9320 {"bits": [19, 19], "name": "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING"}, 9321 {"bits": [20, 20], "name": "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY"}, 9322 {"bits": [21, 21], "name": "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING"}, 9323 {"bits": [22, 22], "name": "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING"}, 9324 {"bits": [23, 23], "name": "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS"}, 9325 {"bits": [24, 24], "name": "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID"}, 9326 {"bits": [30, 30], "name": "ECO_SPARE1"}, 9327 {"bits": [31, 31], "name": "ECO_SPARE0"} 9328 ] 9329 }, 9330 "PA_SC_FIFO_DEPTH_CNTL": { 9331 "fields": [ 9332 {"bits": [0, 7], "name": "DEPTH"} 9333 ] 9334 }, 9335 "PA_SC_FIFO_SIZE": { 9336 "fields": [ 9337 {"bits": [0, 5], "name": "SC_FRONTEND_PRIM_FIFO_SIZE"}, 9338 {"bits": [6, 14], "name": "SC_BACKEND_PRIM_FIFO_SIZE"}, 9339 {"bits": [15, 20], "name": "SC_HIZ_TILE_FIFO_SIZE"}, 9340 {"bits": [23, 31], "name": "SC_EARLYZ_TILE_FIFO_SIZE"} 9341 ] 9342 }, 9343 "PA_SC_FORCE_EOV_MAX_CNTS": { 9344 "fields": [ 9345 {"bits": [0, 15], "name": "FORCE_EOV_MAX_CLK_CNT"}, 9346 {"bits": [16, 31], "name": "FORCE_EOV_MAX_REZ_CNT"} 9347 ] 9348 }, 9349 "PA_SC_GENERIC_SCISSOR_TL": { 9350 "fields": [ 9351 {"bits": [0, 14], "name": "TL_X"}, 9352 {"bits": [16, 30], "name": "TL_Y"}, 9353 {"bits": [31, 31], "name": "WINDOW_OFFSET_DISABLE"} 9354 ] 9355 }, 9356 "PA_SC_IF_FIFO_SIZE": { 9357 "fields": [ 9358 {"bits": [0, 5], "name": "SC_DB_TILE_IF_FIFO_SIZE"}, 9359 {"bits": [6, 11], "name": "SC_DB_QUAD_IF_FIFO_SIZE"}, 9360 {"bits": [12, 17], "name": "SC_SPI_IF_FIFO_SIZE"}, 9361 {"bits": [18, 23], "name": "SC_BCI_IF_FIFO_SIZE"} 9362 ] 9363 }, 9364 "PA_SC_LINE_CNTL": { 9365 "fields": [ 9366 {"bits": [9, 9], "name": "EXPAND_LINE_WIDTH"}, 9367 {"bits": [10, 10], "name": "LAST_PIXEL"}, 9368 {"bits": [11, 11], "name": "PERPENDICULAR_ENDCAP_ENA"}, 9369 {"bits": [12, 12], "name": "DX10_DIAMOND_TEST_ENA"} 9370 ] 9371 }, 9372 "PA_SC_LINE_STIPPLE": { 9373 "fields": [ 9374 {"bits": [0, 15], "name": "LINE_PATTERN"}, 9375 {"bits": [16, 23], "name": "REPEAT_COUNT"}, 9376 {"bits": [28, 28], "name": "PATTERN_BIT_ORDER"}, 9377 {"bits": [29, 30], "name": "AUTO_RESET_CNTL"} 9378 ] 9379 }, 9380 "PA_SC_LINE_STIPPLE_STATE": { 9381 "fields": [ 9382 {"bits": [0, 3], "name": "CURRENT_PTR"}, 9383 {"bits": [8, 15], "name": "CURRENT_COUNT"} 9384 ] 9385 }, 9386 "PA_SC_MODE_CNTL_0": { 9387 "fields": [ 9388 {"bits": [0, 0], "name": "MSAA_ENABLE"}, 9389 {"bits": [1, 1], "name": "VPORT_SCISSOR_ENABLE"}, 9390 {"bits": [2, 2], "name": "LINE_STIPPLE_ENABLE"}, 9391 {"bits": [3, 3], "name": "SEND_UNLIT_STILES_TO_PKR"} 9392 ] 9393 }, 9394 "PA_SC_MODE_CNTL_1": { 9395 "fields": [ 9396 {"bits": [0, 0], "name": "WALK_SIZE"}, 9397 {"bits": [1, 1], "name": "WALK_ALIGNMENT"}, 9398 {"bits": [2, 2], "name": "WALK_ALIGN8_PRIM_FITS_ST"}, 9399 {"bits": [3, 3], "name": "WALK_FENCE_ENABLE"}, 9400 {"bits": [4, 6], "name": "WALK_FENCE_SIZE"}, 9401 {"bits": [7, 7], "name": "SUPERTILE_WALK_ORDER_ENABLE"}, 9402 {"bits": [8, 8], "name": "TILE_WALK_ORDER_ENABLE"}, 9403 {"bits": [9, 9], "name": "TILE_COVER_DISABLE"}, 9404 {"bits": [10, 10], "name": "TILE_COVER_NO_SCISSOR"}, 9405 {"bits": [11, 11], "name": "ZMM_LINE_EXTENT"}, 9406 {"bits": [12, 12], "name": "ZMM_LINE_OFFSET"}, 9407 {"bits": [13, 13], "name": "ZMM_RECT_EXTENT"}, 9408 {"bits": [14, 14], "name": "KILL_PIX_POST_HI_Z"}, 9409 {"bits": [15, 15], "name": "KILL_PIX_POST_DETAIL_MASK"}, 9410 {"bits": [16, 16], "name": "PS_ITER_SAMPLE"}, 9411 {"bits": [17, 17], "name": "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE"}, 9412 {"bits": [18, 18], "name": "MULTI_GPU_SUPERTILE_ENABLE"}, 9413 {"bits": [19, 19], "name": "GPU_ID_OVERRIDE_ENABLE"}, 9414 {"bits": [20, 23], "name": "GPU_ID_OVERRIDE"}, 9415 {"bits": [24, 24], "name": "MULTI_GPU_PRIM_DISCARD_ENABLE"}, 9416 {"bits": [25, 25], "name": "FORCE_EOV_CNTDWN_ENABLE"}, 9417 {"bits": [26, 26], "name": "FORCE_EOV_REZ_ENABLE"}, 9418 {"bits": [27, 27], "name": "OUT_OF_ORDER_PRIMITIVE_ENABLE"}, 9419 {"bits": [28, 30], "name": "OUT_OF_ORDER_WATER_MARK"} 9420 ] 9421 }, 9422 "PA_SC_PERFCOUNTER0_SELECT": { 9423 "fields": [ 9424 {"bits": [0, 8], "name": "PERF_SEL"}, 9425 {"bits": [10, 19], "name": "PERF_SEL1"}, 9426 {"bits": [20, 23], "name": "CNTR_MODE"} 9427 ] 9428 }, 9429 "PA_SC_PERFCOUNTER1_SELECT": { 9430 "fields": [ 9431 {"bits": [0, 8], "name": "PERF_SEL"} 9432 ] 9433 }, 9434 "PA_SC_RASTER_CONFIG": { 9435 "fields": [ 9436 {"bits": [0, 1], "enum_ref": "RbMap", "name": "RB_MAP_PKR0"}, 9437 {"bits": [2, 3], "enum_ref": "RbMap", "name": "RB_MAP_PKR1"}, 9438 {"bits": [4, 5], "enum_ref": "RbXsel2", "name": "RB_XSEL2"}, 9439 {"bits": [6, 6], "enum_ref": "RbXsel", "name": "RB_XSEL"}, 9440 {"bits": [7, 7], "enum_ref": "RbYsel", "name": "RB_YSEL"}, 9441 {"bits": [8, 9], "enum_ref": "PkrMap", "name": "PKR_MAP"}, 9442 {"bits": [10, 11], "enum_ref": "PkrXsel", "name": "PKR_XSEL"}, 9443 {"bits": [12, 13], "enum_ref": "PkrYsel", "name": "PKR_YSEL"}, 9444 {"bits": [14, 15], "enum_ref": "PkrXsel2", "name": "PKR_XSEL2"}, 9445 {"bits": [16, 17], "enum_ref": "ScMap", "name": "SC_MAP"}, 9446 {"bits": [18, 19], "enum_ref": "ScXsel", "name": "SC_XSEL"}, 9447 {"bits": [20, 21], "enum_ref": "ScYsel", "name": "SC_YSEL"}, 9448 {"bits": [24, 25], "enum_ref": "SeMap", "name": "SE_MAP"}, 9449 {"bits": [26, 27], "enum_ref": "SeXsel", "name": "SE_XSEL"}, 9450 {"bits": [28, 29], "enum_ref": "SeYsel", "name": "SE_YSEL"} 9451 ] 9452 }, 9453 "PA_SC_SCREEN_SCISSOR_BR": { 9454 "fields": [ 9455 {"bits": [0, 15], "name": "BR_X"}, 9456 {"bits": [16, 31], "name": "BR_Y"} 9457 ] 9458 }, 9459 "PA_SC_SCREEN_SCISSOR_TL": { 9460 "fields": [ 9461 {"bits": [0, 15], "name": "TL_X"}, 9462 {"bits": [16, 31], "name": "TL_Y"} 9463 ] 9464 }, 9465 "PA_SC_WINDOW_OFFSET": { 9466 "fields": [ 9467 {"bits": [0, 15], "name": "WINDOW_X_OFFSET"}, 9468 {"bits": [16, 31], "name": "WINDOW_Y_OFFSET"} 9469 ] 9470 }, 9471 "PA_SU_CNTL_STATUS": { 9472 "fields": [ 9473 {"bits": [31, 31], "name": "SU_BUSY"} 9474 ] 9475 }, 9476 "PA_SU_DEBUG_CNTL": { 9477 "fields": [ 9478 {"bits": [0, 4], "name": "SU_DEBUG_INDX"} 9479 ] 9480 }, 9481 "PA_SU_HARDWARE_SCREEN_OFFSET": { 9482 "fields": [ 9483 {"bits": [0, 8], "name": "HW_SCREEN_OFFSET_X"}, 9484 {"bits": [16, 24], "name": "HW_SCREEN_OFFSET_Y"} 9485 ] 9486 }, 9487 "PA_SU_LINE_CNTL": { 9488 "fields": [ 9489 {"bits": [0, 15], "name": "WIDTH"} 9490 ] 9491 }, 9492 "PA_SU_LINE_STIPPLE_CNTL": { 9493 "fields": [ 9494 {"bits": [0, 1], "name": "LINE_STIPPLE_RESET"}, 9495 {"bits": [2, 2], "name": "EXPAND_FULL_LENGTH"}, 9496 {"bits": [3, 3], "name": "FRACTIONAL_ACCUM"}, 9497 {"bits": [4, 4], "name": "DIAMOND_ADJUST"} 9498 ] 9499 }, 9500 "PA_SU_LINE_STIPPLE_VALUE": { 9501 "fields": [ 9502 {"bits": [0, 23], "name": "LINE_STIPPLE_VALUE"} 9503 ] 9504 }, 9505 "PA_SU_PERFCOUNTER0_HI": { 9506 "fields": [ 9507 {"bits": [0, 15], "name": "PERFCOUNTER_HI"} 9508 ] 9509 }, 9510 "PA_SU_PERFCOUNTER0_SELECT": { 9511 "fields": [ 9512 {"bits": [0, 7], "name": "PERF_SEL"}, 9513 {"bits": [10, 19], "name": "PERF_SEL1"}, 9514 {"bits": [20, 23], "name": "CNTR_MODE"} 9515 ] 9516 }, 9517 "PA_SU_PERFCOUNTER2_SELECT": { 9518 "fields": [ 9519 {"bits": [0, 7], "name": "PERF_SEL"}, 9520 {"bits": [20, 23], "name": "CNTR_MODE"} 9521 ] 9522 }, 9523 "PA_SU_POINT_MINMAX": { 9524 "fields": [ 9525 {"bits": [0, 15], "name": "MIN_SIZE"}, 9526 {"bits": [16, 31], "name": "MAX_SIZE"} 9527 ] 9528 }, 9529 "PA_SU_POINT_SIZE": { 9530 "fields": [ 9531 {"bits": [0, 15], "name": "HEIGHT"}, 9532 {"bits": [16, 31], "name": "WIDTH"} 9533 ] 9534 }, 9535 "PA_SU_POLY_OFFSET_DB_FMT_CNTL": { 9536 "fields": [ 9537 {"bits": [0, 7], "name": "POLY_OFFSET_NEG_NUM_DB_BITS"}, 9538 {"bits": [8, 8], "name": "POLY_OFFSET_DB_IS_FLOAT_FMT"} 9539 ] 9540 }, 9541 "PA_SU_PRIM_FILTER_CNTL": { 9542 "fields": [ 9543 {"bits": [0, 0], "name": "TRIANGLE_FILTER_DISABLE"}, 9544 {"bits": [1, 1], "name": "LINE_FILTER_DISABLE"}, 9545 {"bits": [2, 2], "name": "POINT_FILTER_DISABLE"}, 9546 {"bits": [3, 3], "name": "RECTANGLE_FILTER_DISABLE"}, 9547 {"bits": [4, 4], "name": "TRIANGLE_EXPAND_ENA"}, 9548 {"bits": [5, 5], "name": "LINE_EXPAND_ENA"}, 9549 {"bits": [6, 6], "name": "POINT_EXPAND_ENA"}, 9550 {"bits": [7, 7], "name": "RECTANGLE_EXPAND_ENA"}, 9551 {"bits": [8, 15], "name": "PRIM_EXPAND_CONSTANT"}, 9552 {"bits": [30, 30], "name": "XMAX_RIGHT_EXCLUSION"}, 9553 {"bits": [31, 31], "name": "YMAX_BOTTOM_EXCLUSION"} 9554 ] 9555 }, 9556 "PA_SU_SC_MODE_CNTL": { 9557 "fields": [ 9558 {"bits": [0, 0], "name": "CULL_FRONT"}, 9559 {"bits": [1, 1], "name": "CULL_BACK"}, 9560 {"bits": [2, 2], "name": "FACE"}, 9561 {"bits": [3, 4], "enum_ref": "PA_SU_SC_MODE_CNTL__POLY_MODE", "name": "POLY_MODE"}, 9562 {"bits": [5, 7], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_FRONT_PTYPE"}, 9563 {"bits": [8, 10], "enum_ref": "PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE", "name": "POLYMODE_BACK_PTYPE"}, 9564 {"bits": [11, 11], "name": "POLY_OFFSET_FRONT_ENABLE"}, 9565 {"bits": [12, 12], "name": "POLY_OFFSET_BACK_ENABLE"}, 9566 {"bits": [13, 13], "name": "POLY_OFFSET_PARA_ENABLE"}, 9567 {"bits": [16, 16], "name": "VTX_WINDOW_OFFSET_ENABLE"}, 9568 {"bits": [19, 19], "name": "PROVOKING_VTX_LAST"}, 9569 {"bits": [20, 20], "name": "PERSP_CORR_DIS"}, 9570 {"bits": [21, 21], "name": "MULTI_PRIM_IB_ENA"} 9571 ] 9572 }, 9573 "PA_SU_VTX_CNTL": { 9574 "fields": [ 9575 {"bits": [0, 0], "name": "PIX_CENTER"}, 9576 {"bits": [1, 2], "enum_ref": "PA_SU_VTX_CNTL__ROUND_MODE", "name": "ROUND_MODE"}, 9577 {"bits": [3, 5], "enum_ref": "QUANT_MODE", "name": "QUANT_MODE"} 9578 ] 9579 }, 9580 "SCRATCH_UMSK": { 9581 "fields": [ 9582 {"bits": [0, 7], "name": "OBSOLETE_UMSK"}, 9583 {"bits": [16, 17], "name": "OBSOLETE_SWAP"} 9584 ] 9585 }, 9586 "SPI_BARYC_CNTL": { 9587 "fields": [ 9588 {"bits": [0, 0], "name": "PERSP_CENTER_CNTL"}, 9589 {"bits": [4, 4], "name": "PERSP_CENTROID_CNTL"}, 9590 {"bits": [8, 8], "name": "LINEAR_CENTER_CNTL"}, 9591 {"bits": [12, 12], "name": "LINEAR_CENTROID_CNTL"}, 9592 {"bits": [16, 17], "name": "POS_FLOAT_LOCATION"}, 9593 {"bits": [20, 20], "name": "POS_FLOAT_ULC"}, 9594 {"bits": [24, 24], "name": "FRONT_FACE_ALL_BITS"} 9595 ] 9596 }, 9597 "SPI_CONFIG_CNTL": { 9598 "fields": [ 9599 {"bits": [0, 20], "name": "GPR_WRITE_PRIORITY"}, 9600 {"bits": [21, 23], "name": "EXP_PRIORITY_ORDER"}, 9601 {"bits": [24, 24], "name": "ENABLE_SQG_TOP_EVENTS"}, 9602 {"bits": [25, 25], "name": "ENABLE_SQG_BOP_EVENTS"}, 9603 {"bits": [26, 26], "name": "RSRC_MGMT_RESET"}, 9604 {"bits": [27, 27], "name": "TTRACE_STALL_ALL"} 9605 ] 9606 }, 9607 "SPI_INTERP_CONTROL_0": { 9608 "fields": [ 9609 {"bits": [0, 0], "name": "FLAT_SHADE_ENA"}, 9610 {"bits": [1, 1], "name": "PNT_SPRITE_ENA"}, 9611 {"bits": [2, 4], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_X"}, 9612 {"bits": [5, 7], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Y"}, 9613 {"bits": [8, 10], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_Z"}, 9614 {"bits": [11, 13], "enum_ref": "SPI_PNT_SPRITE_OVERRIDE", "name": "PNT_SPRITE_OVRD_W"}, 9615 {"bits": [14, 14], "name": "PNT_SPRITE_TOP_1"} 9616 ] 9617 }, 9618 "SPI_PS_INPUT_ADDR": { 9619 "fields": [ 9620 {"bits": [0, 0], "name": "PERSP_SAMPLE_ENA"}, 9621 {"bits": [1, 1], "name": "PERSP_CENTER_ENA"}, 9622 {"bits": [2, 2], "name": "PERSP_CENTROID_ENA"}, 9623 {"bits": [3, 3], "name": "PERSP_PULL_MODEL_ENA"}, 9624 {"bits": [4, 4], "name": "LINEAR_SAMPLE_ENA"}, 9625 {"bits": [5, 5], "name": "LINEAR_CENTER_ENA"}, 9626 {"bits": [6, 6], "name": "LINEAR_CENTROID_ENA"}, 9627 {"bits": [7, 7], "name": "LINE_STIPPLE_TEX_ENA"}, 9628 {"bits": [8, 8], "name": "POS_X_FLOAT_ENA"}, 9629 {"bits": [9, 9], "name": "POS_Y_FLOAT_ENA"}, 9630 {"bits": [10, 10], "name": "POS_Z_FLOAT_ENA"}, 9631 {"bits": [11, 11], "name": "POS_W_FLOAT_ENA"}, 9632 {"bits": [12, 12], "name": "FRONT_FACE_ENA"}, 9633 {"bits": [13, 13], "name": "ANCILLARY_ENA"}, 9634 {"bits": [14, 14], "name": "SAMPLE_COVERAGE_ENA"}, 9635 {"bits": [15, 15], "name": "POS_FIXED_PT_ENA"} 9636 ] 9637 }, 9638 "SPI_PS_INPUT_CNTL_0": { 9639 "fields": [ 9640 {"bits": [0, 5], "name": "OFFSET"}, 9641 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 9642 {"bits": [10, 10], "name": "FLAT_SHADE"}, 9643 {"bits": [13, 16], "name": "CYL_WRAP"}, 9644 {"bits": [17, 17], "name": "PT_SPRITE_TEX"}, 9645 {"bits": [18, 18], "name": "DUP"} 9646 ] 9647 }, 9648 "SPI_PS_INPUT_CNTL_20": { 9649 "fields": [ 9650 {"bits": [0, 5], "name": "OFFSET"}, 9651 {"bits": [8, 9], "name": "DEFAULT_VAL"}, 9652 {"bits": [10, 10], "name": "FLAT_SHADE"}, 9653 {"bits": [18, 18], "name": "DUP"} 9654 ] 9655 }, 9656 "SPI_PS_IN_CONTROL": { 9657 "fields": [ 9658 {"bits": [0, 5], "name": "NUM_INTERP"}, 9659 {"bits": [6, 6], "name": "PARAM_GEN"}, 9660 {"bits": [14, 14], "name": "BC_OPTIMIZE_DISABLE"} 9661 ] 9662 }, 9663 "SPI_SHADER_COL_FORMAT": { 9664 "fields": [ 9665 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL0_EXPORT_FORMAT"}, 9666 {"bits": [4, 7], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL1_EXPORT_FORMAT"}, 9667 {"bits": [8, 11], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL2_EXPORT_FORMAT"}, 9668 {"bits": [12, 15], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL3_EXPORT_FORMAT"}, 9669 {"bits": [16, 19], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL4_EXPORT_FORMAT"}, 9670 {"bits": [20, 23], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL5_EXPORT_FORMAT"}, 9671 {"bits": [24, 27], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL6_EXPORT_FORMAT"}, 9672 {"bits": [28, 31], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "COL7_EXPORT_FORMAT"} 9673 ] 9674 }, 9675 "SPI_SHADER_PGM_HI_ES": { 9676 "fields": [ 9677 {"bits": [0, 7], "name": "MEM_BASE"} 9678 ] 9679 }, 9680 "SPI_SHADER_PGM_RSRC1_ES": { 9681 "fields": [ 9682 {"bits": [0, 5], "name": "VGPRS"}, 9683 {"bits": [6, 9], "name": "SGPRS"}, 9684 {"bits": [10, 11], "name": "PRIORITY"}, 9685 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9686 {"bits": [20, 20], "name": "PRIV"}, 9687 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9688 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9689 {"bits": [23, 23], "name": "IEEE_MODE"}, 9690 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 9691 {"bits": [26, 26], "name": "CU_GROUP_ENABLE"}, 9692 {"bits": [27, 29], "name": "CACHE_CTL"}, 9693 {"bits": [30, 30], "name": "CDBG_USER"} 9694 ] 9695 }, 9696 "SPI_SHADER_PGM_RSRC1_GS": { 9697 "fields": [ 9698 {"bits": [0, 5], "name": "VGPRS"}, 9699 {"bits": [6, 9], "name": "SGPRS"}, 9700 {"bits": [10, 11], "name": "PRIORITY"}, 9701 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9702 {"bits": [20, 20], "name": "PRIV"}, 9703 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9704 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9705 {"bits": [23, 23], "name": "IEEE_MODE"}, 9706 {"bits": [24, 24], "name": "CU_GROUP_ENABLE"}, 9707 {"bits": [25, 27], "name": "CACHE_CTL"}, 9708 {"bits": [28, 28], "name": "CDBG_USER"} 9709 ] 9710 }, 9711 "SPI_SHADER_PGM_RSRC1_HS": { 9712 "fields": [ 9713 {"bits": [0, 5], "name": "VGPRS"}, 9714 {"bits": [6, 9], "name": "SGPRS"}, 9715 {"bits": [10, 11], "name": "PRIORITY"}, 9716 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9717 {"bits": [20, 20], "name": "PRIV"}, 9718 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9719 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9720 {"bits": [23, 23], "name": "IEEE_MODE"}, 9721 {"bits": [24, 26], "name": "CACHE_CTL"}, 9722 {"bits": [27, 27], "name": "CDBG_USER"} 9723 ] 9724 }, 9725 "SPI_SHADER_PGM_RSRC1_LS": { 9726 "fields": [ 9727 {"bits": [0, 5], "name": "VGPRS"}, 9728 {"bits": [6, 9], "name": "SGPRS"}, 9729 {"bits": [10, 11], "name": "PRIORITY"}, 9730 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9731 {"bits": [20, 20], "name": "PRIV"}, 9732 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9733 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9734 {"bits": [23, 23], "name": "IEEE_MODE"}, 9735 {"bits": [24, 25], "name": "VGPR_COMP_CNT"}, 9736 {"bits": [26, 28], "name": "CACHE_CTL"}, 9737 {"bits": [29, 29], "name": "CDBG_USER"} 9738 ] 9739 }, 9740 "SPI_SHADER_PGM_RSRC1_PS": { 9741 "fields": [ 9742 {"bits": [0, 5], "name": "VGPRS"}, 9743 {"bits": [6, 9], "name": "SGPRS"}, 9744 {"bits": [10, 11], "name": "PRIORITY"}, 9745 {"bits": [12, 19], "enum_ref": "FLOAT_MODE", "name": "FLOAT_MODE"}, 9746 {"bits": [20, 20], "name": "PRIV"}, 9747 {"bits": [21, 21], "name": "DX10_CLAMP"}, 9748 {"bits": [22, 22], "name": "DEBUG_MODE"}, 9749 {"bits": [23, 23], "name": "IEEE_MODE"}, 9750 {"bits": [24, 24], "name": "CU_GROUP_DISABLE"}, 9751 {"bits": [25, 27], "name": "CACHE_CTL"}, 9752 {"bits": [28, 28], "name": "CDBG_USER"} 9753 ] 9754 }, 9755 "SPI_SHADER_PGM_RSRC2_ES": { 9756 "fields": [ 9757 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9758 {"bits": [1, 5], "name": "USER_SGPR"}, 9759 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9760 {"bits": [7, 7], "name": "OC_LDS_EN"}, 9761 {"bits": [8, 14], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 9762 {"bits": [20, 28], "name": "LDS_SIZE"} 9763 ] 9764 }, 9765 "SPI_SHADER_PGM_RSRC2_GS": { 9766 "fields": [ 9767 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9768 {"bits": [1, 5], "name": "USER_SGPR"}, 9769 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9770 {"bits": [7, 13], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9771 ] 9772 }, 9773 "SPI_SHADER_PGM_RSRC2_HS": { 9774 "fields": [ 9775 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9776 {"bits": [1, 5], "name": "USER_SGPR"}, 9777 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9778 {"bits": [7, 7], "name": "OC_LDS_EN"}, 9779 {"bits": [8, 8], "name": "TG_SIZE_EN"}, 9780 {"bits": [9, 15], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9781 ] 9782 }, 9783 "SPI_SHADER_PGM_RSRC2_LS": { 9784 "fields": [ 9785 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9786 {"bits": [1, 5], "name": "USER_SGPR"}, 9787 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9788 {"bits": [7, 15], "name": "LDS_SIZE"}, 9789 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9790 ] 9791 }, 9792 "SPI_SHADER_PGM_RSRC2_PS": { 9793 "fields": [ 9794 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9795 {"bits": [1, 5], "name": "USER_SGPR"}, 9796 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9797 {"bits": [7, 7], "name": "WAVE_CNT_EN"}, 9798 {"bits": [8, 15], "name": "EXTRA_LDS_SIZE"}, 9799 {"bits": [16, 22], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9800 ] 9801 }, 9802 "SPI_SHADER_PGM_RSRC2_VS": { 9803 "fields": [ 9804 {"bits": [0, 0], "name": "SCRATCH_EN"}, 9805 {"bits": [1, 5], "name": "USER_SGPR"}, 9806 {"bits": [6, 6], "name": "TRAP_PRESENT"}, 9807 {"bits": [7, 7], "name": "OC_LDS_EN"}, 9808 {"bits": [8, 8], "name": "SO_BASE0_EN"}, 9809 {"bits": [9, 9], "name": "SO_BASE1_EN"}, 9810 {"bits": [10, 10], "name": "SO_BASE2_EN"}, 9811 {"bits": [11, 11], "name": "SO_BASE3_EN"}, 9812 {"bits": [12, 12], "name": "SO_EN"}, 9813 {"bits": [13, 19], "enum_ref": "EXCP_EN", "name": "EXCP_EN"} 9814 ] 9815 }, 9816 "SPI_SHADER_POS_FORMAT": { 9817 "fields": [ 9818 {"bits": [0, 3], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS0_EXPORT_FORMAT"}, 9819 {"bits": [4, 7], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS1_EXPORT_FORMAT"}, 9820 {"bits": [8, 11], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS2_EXPORT_FORMAT"}, 9821 {"bits": [12, 15], "enum_ref": "SPI_SHADER_FORMAT", "name": "POS3_EXPORT_FORMAT"} 9822 ] 9823 }, 9824 "SPI_SHADER_Z_FORMAT": { 9825 "fields": [ 9826 {"bits": [0, 3], "enum_ref": "SPI_SHADER_EX_FORMAT", "name": "Z_EXPORT_FORMAT"} 9827 ] 9828 }, 9829 "SPI_VS_OUT_CONFIG": { 9830 "fields": [ 9831 {"bits": [1, 5], "name": "VS_EXPORT_COUNT"}, 9832 {"bits": [6, 6], "name": "VS_HALF_PACK"} 9833 ] 9834 }, 9835 "SQC_CACHES": { 9836 "fields": [ 9837 {"bits": [0, 0], "name": "INST_INVALIDATE"}, 9838 {"bits": [1, 1], "name": "DATA_INVALIDATE"}, 9839 {"bits": [2, 2], "name": "INVALIDATE_VOLATILE"} 9840 ] 9841 }, 9842 "SQC_CONFIG": { 9843 "fields": [ 9844 {"bits": [0, 1], "name": "INST_CACHE_SIZE"}, 9845 {"bits": [2, 3], "name": "DATA_CACHE_SIZE"}, 9846 {"bits": [4, 5], "name": "MISS_FIFO_DEPTH"}, 9847 {"bits": [6, 6], "name": "HIT_FIFO_DEPTH"}, 9848 {"bits": [7, 7], "name": "FORCE_ALWAYS_MISS"}, 9849 {"bits": [8, 8], "name": "FORCE_IN_ORDER"}, 9850 {"bits": [9, 9], "name": "IDENTITY_HASH_BANK"}, 9851 {"bits": [10, 10], "name": "IDENTITY_HASH_SET"}, 9852 {"bits": [11, 11], "name": "PER_VMID_INV_DISABLE"} 9853 ] 9854 }, 9855 "SQC_SECDED_CNT": { 9856 "fields": [ 9857 {"bits": [0, 7], "name": "INST_SEC"}, 9858 {"bits": [8, 15], "name": "INST_DED"}, 9859 {"bits": [16, 23], "name": "DATA_SEC"}, 9860 {"bits": [24, 31], "name": "DATA_DED"} 9861 ] 9862 }, 9863 "SQ_ALU_CLK_CTRL": { 9864 "fields": [ 9865 {"bits": [0, 15], "name": "FORCE_CU_ON_SH0"}, 9866 {"bits": [16, 31], "name": "FORCE_CU_ON_SH1"} 9867 ] 9868 }, 9869 "SQ_BUF_RSRC_WORD1": { 9870 "fields": [ 9871 {"bits": [0, 15], "name": "BASE_ADDRESS_HI"}, 9872 {"bits": [16, 29], "name": "STRIDE"}, 9873 {"bits": [30, 30], "name": "CACHE_SWIZZLE"}, 9874 {"bits": [31, 31], "name": "SWIZZLE_ENABLE"} 9875 ] 9876 }, 9877 "SQ_BUF_RSRC_WORD3": { 9878 "fields": [ 9879 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 9880 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 9881 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 9882 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 9883 {"bits": [12, 14], "enum_ref": "BUF_NUM_FORMAT", "name": "NUM_FORMAT"}, 9884 {"bits": [15, 18], "enum_ref": "BUF_DATA_FORMAT", "name": "DATA_FORMAT"}, 9885 {"bits": [19, 20], "name": "ELEMENT_SIZE"}, 9886 {"bits": [21, 22], "name": "INDEX_STRIDE"}, 9887 {"bits": [23, 23], "name": "ADD_TID_ENABLE"}, 9888 {"bits": [24, 24], "name": "ATC"}, 9889 {"bits": [25, 25], "name": "HASH_ENABLE"}, 9890 {"bits": [26, 26], "name": "HEAP"}, 9891 {"bits": [27, 29], "name": "MTYPE"}, 9892 {"bits": [30, 31], "enum_ref": "SQ_RSRC_BUF_TYPE", "name": "TYPE"} 9893 ] 9894 }, 9895 "SQ_CONFIG": { 9896 "fields": [ 9897 {"bits": [0, 7], "name": "UNUSED"}, 9898 {"bits": [8, 8], "name": "DEBUG_EN"}, 9899 {"bits": [9, 9], "name": "DISABLE_SCA_BYPASS"}, 9900 {"bits": [10, 10], "name": "DISABLE_IB_DEP_CHECK"}, 9901 {"bits": [11, 11], "name": "ENABLE_SOFT_CLAUSE"}, 9902 {"bits": [12, 12], "name": "EARLY_TA_DONE_DISABLE"}, 9903 {"bits": [13, 13], "name": "DUA_FLAT_LOCK_ENABLE"}, 9904 {"bits": [14, 14], "name": "DUA_LDS_BYPASS_DISABLE"}, 9905 {"bits": [15, 15], "name": "DUA_FLAT_LDS_PINGPONG_DISABLE"} 9906 ] 9907 }, 9908 "SQ_DEBUG_STS_GLOBAL": { 9909 "fields": [ 9910 {"bits": [0, 0], "name": "BUSY"}, 9911 {"bits": [1, 1], "name": "INTERRUPT_MSG_BUSY"}, 9912 {"bits": [4, 15], "name": "WAVE_LEVEL_SH0"}, 9913 {"bits": [16, 27], "name": "WAVE_LEVEL_SH1"} 9914 ] 9915 }, 9916 "SQ_DED_CNT": { 9917 "fields": [ 9918 {"bits": [0, 5], "name": "LDS_DED"}, 9919 {"bits": [8, 12], "name": "SGPR_DED"}, 9920 {"bits": [16, 24], "name": "VGPR_DED"} 9921 ] 9922 }, 9923 "SQ_DED_INFO": { 9924 "fields": [ 9925 {"bits": [0, 3], "name": "WAVE_ID"}, 9926 {"bits": [4, 5], "name": "SIMD_ID"}, 9927 {"bits": [6, 8], "name": "SOURCE"}, 9928 {"bits": [9, 12], "name": "VM_ID"} 9929 ] 9930 }, 9931 "SQ_FIFO_SIZES": { 9932 "fields": [ 9933 {"bits": [0, 3], "name": "INTERRUPT_FIFO_SIZE"}, 9934 {"bits": [8, 11], "name": "TTRACE_FIFO_SIZE"}, 9935 {"bits": [16, 17], "name": "EXPORT_BUF_SIZE"}, 9936 {"bits": [18, 19], "name": "VMEM_DATA_FIFO_SIZE"} 9937 ] 9938 }, 9939 "SQ_IMG_RSRC_WORD1": { 9940 "fields": [ 9941 {"bits": [0, 7], "name": "BASE_ADDRESS_HI"}, 9942 {"bits": [8, 19], "name": "MIN_LOD"}, 9943 {"bits": [20, 25], "enum_ref": "IMG_DATA_FORMAT", "name": "DATA_FORMAT"}, 9944 {"bits": [26, 29], "enum_ref": "IMG_NUM_FORMAT", "name": "NUM_FORMAT"}, 9945 {"bits": [30, 31], "name": "MTYPE"} 9946 ] 9947 }, 9948 "SQ_IMG_RSRC_WORD2": { 9949 "fields": [ 9950 {"bits": [0, 13], "name": "WIDTH"}, 9951 {"bits": [14, 27], "name": "HEIGHT"}, 9952 {"bits": [28, 30], "name": "PERF_MOD"}, 9953 {"bits": [31, 31], "name": "INTERLACED"} 9954 ] 9955 }, 9956 "SQ_IMG_RSRC_WORD3": { 9957 "fields": [ 9958 {"bits": [0, 2], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_X"}, 9959 {"bits": [3, 5], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Y"}, 9960 {"bits": [6, 8], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_Z"}, 9961 {"bits": [9, 11], "enum_ref": "SQ_SEL_XYZW01", "name": "DST_SEL_W"}, 9962 {"bits": [12, 15], "name": "BASE_LEVEL"}, 9963 {"bits": [16, 19], "name": "LAST_LEVEL"}, 9964 {"bits": [20, 24], "name": "TILING_INDEX"}, 9965 {"bits": [25, 25], "name": "POW2_PAD"}, 9966 {"bits": [26, 26], "name": "MTYPE"}, 9967 {"bits": [27, 27], "name": "ATC"}, 9968 {"bits": [28, 31], "enum_ref": "SQ_RSRC_IMG_TYPE", "name": "TYPE"} 9969 ] 9970 }, 9971 "SQ_IMG_RSRC_WORD4": { 9972 "fields": [ 9973 {"bits": [0, 12], "name": "DEPTH"}, 9974 {"bits": [13, 26], "name": "PITCH"} 9975 ] 9976 }, 9977 "SQ_IMG_RSRC_WORD5": { 9978 "fields": [ 9979 {"bits": [0, 12], "name": "BASE_ARRAY"}, 9980 {"bits": [13, 25], "name": "LAST_ARRAY"} 9981 ] 9982 }, 9983 "SQ_IMG_RSRC_WORD6": { 9984 "fields": [ 9985 {"bits": [0, 11], "name": "MIN_LOD_WARN"}, 9986 {"bits": [12, 19], "name": "COUNTER_BANK_ID"}, 9987 {"bits": [20, 20], "name": "LOD_HDW_CNT_EN"}, 9988 {"bits": [21, 31], "name": "UNUNSED"} 9989 ] 9990 }, 9991 "SQ_IMG_SAMP_WORD0": { 9992 "fields": [ 9993 {"bits": [0, 2], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_X"}, 9994 {"bits": [3, 5], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Y"}, 9995 {"bits": [6, 8], "enum_ref": "SQ_TEX_CLAMP", "name": "CLAMP_Z"}, 9996 {"bits": [9, 11], "name": "MAX_ANISO_RATIO"}, 9997 {"bits": [12, 14], "enum_ref": "SQ_TEX_DEPTH_COMPARE", "name": "DEPTH_COMPARE_FUNC"}, 9998 {"bits": [15, 15], "name": "FORCE_UNNORMALIZED"}, 9999 {"bits": [16, 18], "name": "ANISO_THRESHOLD"}, 10000 {"bits": [19, 19], "name": "MC_COORD_TRUNC"}, 10001 {"bits": [20, 20], "name": "FORCE_DEGAMMA"}, 10002 {"bits": [21, 26], "name": "ANISO_BIAS"}, 10003 {"bits": [27, 27], "name": "TRUNC_COORD"}, 10004 {"bits": [28, 28], "name": "DISABLE_CUBE_WRAP"}, 10005 {"bits": [29, 30], "enum_ref": "SQ_IMG_FILTER_TYPE", "name": "FILTER_MODE"} 10006 ] 10007 }, 10008 "SQ_IMG_SAMP_WORD1": { 10009 "fields": [ 10010 {"bits": [0, 11], "name": "MIN_LOD"}, 10011 {"bits": [12, 23], "name": "MAX_LOD"}, 10012 {"bits": [24, 27], "name": "PERF_MIP"}, 10013 {"bits": [28, 31], "name": "PERF_Z"} 10014 ] 10015 }, 10016 "SQ_IMG_SAMP_WORD2": { 10017 "fields": [ 10018 {"bits": [0, 13], "name": "LOD_BIAS"}, 10019 {"bits": [14, 19], "name": "LOD_BIAS_SEC"}, 10020 {"bits": [20, 21], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MAG_FILTER"}, 10021 {"bits": [22, 23], "enum_ref": "SQ_TEX_XY_FILTER", "name": "XY_MIN_FILTER"}, 10022 {"bits": [24, 25], "enum_ref": "SQ_TEX_Z_FILTER", "name": "Z_FILTER"}, 10023 {"bits": [26, 27], "enum_ref": "SQ_TEX_MIP_FILTER", "name": "MIP_FILTER"}, 10024 {"bits": [28, 28], "name": "MIP_POINT_PRECLAMP"}, 10025 {"bits": [29, 29], "name": "DISABLE_LSB_CEIL"}, 10026 {"bits": [30, 30], "name": "FILTER_PREC_FIX"} 10027 ] 10028 }, 10029 "SQ_IMG_SAMP_WORD3": { 10030 "fields": [ 10031 {"bits": [0, 11], "name": "BORDER_COLOR_PTR"}, 10032 {"bits": [29, 29], "name": "UPGRADED_DEPTH"}, 10033 {"bits": [30, 31], "enum_ref": "SQ_TEX_BORDER_COLOR", "name": "BORDER_COLOR_TYPE"} 10034 ] 10035 }, 10036 "SQ_IND_INDEX": { 10037 "fields": [ 10038 {"bits": [0, 3], "name": "WAVE_ID"}, 10039 {"bits": [4, 5], "name": "SIMD_ID"}, 10040 {"bits": [6, 11], "name": "THREAD_ID"}, 10041 {"bits": [12, 12], "name": "AUTO_INCR"}, 10042 {"bits": [13, 13], "name": "FORCE_READ"}, 10043 {"bits": [14, 14], "name": "READ_TIMEOUT"}, 10044 {"bits": [15, 15], "name": "UNINDEXED"}, 10045 {"bits": [16, 31], "name": "INDEX"} 10046 ] 10047 }, 10048 "SQ_INTERRUPT_WORD_AUTO": { 10049 "fields": [ 10050 {"bits": [0, 0], "name": "THREAD_TRACE"}, 10051 {"bits": [1, 1], "name": "WLT"}, 10052 {"bits": [2, 2], "name": "THREAD_TRACE_BUF_FULL"}, 10053 {"bits": [3, 3], "name": "REG_TIMESTAMP"}, 10054 {"bits": [4, 4], "name": "CMD_TIMESTAMP"}, 10055 {"bits": [5, 5], "name": "HOST_CMD_OVERFLOW"}, 10056 {"bits": [6, 6], "name": "HOST_REG_OVERFLOW"}, 10057 {"bits": [7, 7], "name": "IMMED_OVERFLOW"}, 10058 {"bits": [25, 25], "name": "SE_ID"}, 10059 {"bits": [26, 27], "name": "ENCODING"} 10060 ] 10061 }, 10062 "SQ_LB_CTR_CTRL": { 10063 "fields": [ 10064 {"bits": [0, 0], "name": "START"}, 10065 {"bits": [1, 1], "name": "LOAD"}, 10066 {"bits": [2, 2], "name": "CLEAR"} 10067 ] 10068 }, 10069 "SQ_PERFCOUNTER0_SELECT": { 10070 "fields": [ 10071 {"bits": [0, 8], "name": "PERF_SEL"}, 10072 {"bits": [12, 15], "name": "SQC_BANK_MASK"}, 10073 {"bits": [16, 19], "name": "SQC_CLIENT_MASK"}, 10074 {"bits": [20, 23], "name": "SPM_MODE"}, 10075 {"bits": [24, 27], "name": "SIMD_MASK"}, 10076 {"bits": [28, 31], "name": "PERF_MODE"} 10077 ] 10078 }, 10079 "SQ_PERFCOUNTER_CTRL": { 10080 "fields": [ 10081 {"bits": [0, 0], "name": "PS_EN"}, 10082 {"bits": [1, 1], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 10083 {"bits": [2, 2], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 10084 {"bits": [3, 3], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 10085 {"bits": [4, 4], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 10086 {"bits": [5, 5], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 10087 {"bits": [6, 6], "name": "CS_EN"}, 10088 {"bits": [8, 12], "name": "CNTR_RATE"}, 10089 {"bits": [13, 13], "name": "DISABLE_FLUSH"} 10090 ] 10091 }, 10092 "SQ_POWER_THROTTLE": { 10093 "fields": [ 10094 {"bits": [0, 13], "name": "MIN_POWER"}, 10095 {"bits": [16, 29], "name": "MAX_POWER"}, 10096 {"bits": [30, 31], "name": "PHASE_OFFSET"} 10097 ] 10098 }, 10099 "SQ_POWER_THROTTLE2": { 10100 "fields": [ 10101 {"bits": [0, 13], "name": "MAX_POWER_DELTA"}, 10102 {"bits": [16, 25], "name": "SHORT_TERM_INTERVAL_SIZE"}, 10103 {"bits": [27, 30], "name": "LONG_TERM_INTERVAL_RATIO"}, 10104 {"bits": [31, 31], "name": "USE_REF_CLOCK"} 10105 ] 10106 }, 10107 "SQ_RANDOM_WAVE_PRI": { 10108 "fields": [ 10109 {"bits": [0, 6], "name": "RET"}, 10110 {"bits": [7, 9], "name": "RUI"}, 10111 {"bits": [10, 20], "name": "RNG"} 10112 ] 10113 }, 10114 "SQ_REG_CREDITS": { 10115 "fields": [ 10116 {"bits": [0, 5], "name": "SRBM_CREDITS"}, 10117 {"bits": [8, 11], "name": "CMD_CREDITS"}, 10118 {"bits": [28, 28], "name": "REG_BUSY"}, 10119 {"bits": [29, 29], "name": "SRBM_OVERFLOW"}, 10120 {"bits": [30, 30], "name": "IMMED_OVERFLOW"}, 10121 {"bits": [31, 31], "name": "CMD_OVERFLOW"} 10122 ] 10123 }, 10124 "SQ_SEC_CNT": { 10125 "fields": [ 10126 {"bits": [0, 5], "name": "LDS_SEC"}, 10127 {"bits": [8, 12], "name": "SGPR_SEC"}, 10128 {"bits": [16, 24], "name": "VGPR_SEC"} 10129 ] 10130 }, 10131 "SQ_THREAD_TRACE_CTRL": { 10132 "fields": [ 10133 {"bits": [31, 31], "name": "RESET_BUFFER"} 10134 ] 10135 }, 10136 "SQ_THREAD_TRACE_HIWATER": { 10137 "fields": [ 10138 {"bits": [0, 2], "name": "HIWATER"} 10139 ] 10140 }, 10141 "SQ_THREAD_TRACE_MASK": { 10142 "fields": [ 10143 {"bits": [0, 4], "name": "CU_SEL"}, 10144 {"bits": [5, 5], "name": "SH_SEL"}, 10145 {"bits": [7, 7], "name": "REG_STALL_EN"}, 10146 {"bits": [12, 13], "name": "VM_ID_MASK"}, 10147 {"bits": [14, 14], "name": "SPI_STALL_EN"}, 10148 {"bits": [15, 15], "name": "SQ_STALL_EN"}, 10149 {"bits": [16, 31], "name": "RANDOM_SEED"}, 10150 {"bits": [16, 31], "name": "RANDOM_SEED"} 10151 ] 10152 }, 10153 "SQ_THREAD_TRACE_MODE": { 10154 "fields": [ 10155 {"bits": [0, 2], "name": "MASK_PS"}, 10156 {"bits": [3, 5], "name": "MASK_VS"}, 10157 {"bits": [6, 8], "name": "MASK_GS"}, 10158 {"bits": [9, 11], "name": "MASK_ES"}, 10159 {"bits": [12, 14], "name": "MASK_HS"}, 10160 {"bits": [15, 17], "name": "MASK_LS"}, 10161 {"bits": [18, 20], "name": "MASK_CS"}, 10162 {"bits": [21, 22], "name": "MODE"}, 10163 {"bits": [23, 24], "name": "CAPTURE_MODE"}, 10164 {"bits": [25, 25], "name": "AUTOFLUSH_EN"}, 10165 {"bits": [26, 26], "name": "PRIV"}, 10166 {"bits": [27, 28], "name": "ISSUE_MASK"}, 10167 {"bits": [29, 29], "name": "TEST_MODE"}, 10168 {"bits": [30, 30], "name": "INTERRUPT_EN"}, 10169 {"bits": [31, 31], "name": "WRAP"} 10170 ] 10171 }, 10172 "SQ_THREAD_TRACE_PERF_MASK": { 10173 "fields": [ 10174 {"bits": [0, 15], "name": "SH0_MASK"}, 10175 {"bits": [16, 31], "name": "SH1_MASK"} 10176 ] 10177 }, 10178 "SQ_THREAD_TRACE_SIZE": { 10179 "fields": [ 10180 {"bits": [0, 21], "name": "SIZE"} 10181 ] 10182 }, 10183 "SQ_THREAD_TRACE_STATUS": { 10184 "fields": [ 10185 {"bits": [0, 2], "name": "FINISH_PENDING"}, 10186 {"bits": [16, 18], "name": "FINISH_DONE"}, 10187 {"bits": [29, 29], "name": "NEW_BUF"}, 10188 {"bits": [30, 30], "name": "BUSY"}, 10189 {"bits": [31, 31], "name": "FULL"} 10190 ] 10191 }, 10192 "SQ_THREAD_TRACE_TOKEN_MASK": { 10193 "fields": [ 10194 {"bits": [0, 15], "name": "TOKEN_MASK"}, 10195 {"bits": [16, 23], "name": "REG_MASK"}, 10196 {"bits": [24, 24], "name": "REG_DROP_ON_STALL"} 10197 ] 10198 }, 10199 "SQ_THREAD_TRACE_WPTR": { 10200 "fields": [ 10201 {"bits": [0, 29], "name": "WPTR"}, 10202 {"bits": [30, 31], "name": "READ_OFFSET"} 10203 ] 10204 }, 10205 "SQ_WAVE_GPR_ALLOC": { 10206 "fields": [ 10207 {"bits": [0, 5], "name": "VGPR_BASE"}, 10208 {"bits": [8, 13], "name": "VGPR_SIZE"}, 10209 {"bits": [16, 21], "name": "SGPR_BASE"}, 10210 {"bits": [24, 27], "name": "SGPR_SIZE"} 10211 ] 10212 }, 10213 "SQ_WAVE_HW_ID": { 10214 "fields": [ 10215 {"bits": [0, 3], "name": "WAVE_ID"}, 10216 {"bits": [4, 5], "name": "SIMD_ID"}, 10217 {"bits": [6, 7], "name": "PIPE_ID"}, 10218 {"bits": [8, 11], "name": "CU_ID"}, 10219 {"bits": [12, 12], "name": "SH_ID"}, 10220 {"bits": [13, 13], "name": "SE_ID"}, 10221 {"bits": [16, 19], "name": "TG_ID"}, 10222 {"bits": [20, 23], "name": "VM_ID"}, 10223 {"bits": [24, 26], "name": "QUEUE_ID"}, 10224 {"bits": [27, 29], "name": "STATE_ID"}, 10225 {"bits": [30, 31], "name": "ME_ID"} 10226 ] 10227 }, 10228 "SQ_WAVE_IB_DBG0": { 10229 "fields": [ 10230 {"bits": [0, 2], "name": "IBUF_ST"}, 10231 {"bits": [3, 3], "name": "PC_INVALID"}, 10232 {"bits": [4, 4], "name": "NEED_NEXT_DW"}, 10233 {"bits": [5, 7], "name": "NO_PREFETCH_CNT"}, 10234 {"bits": [8, 9], "name": "IBUF_RPTR"}, 10235 {"bits": [10, 11], "name": "IBUF_WPTR"}, 10236 {"bits": [16, 18], "name": "INST_STR_ST"}, 10237 {"bits": [19, 21], "name": "MISC_CNT"}, 10238 {"bits": [22, 23], "name": "ECC_ST"}, 10239 {"bits": [24, 24], "name": "IS_HYB"}, 10240 {"bits": [25, 26], "name": "HYB_CNT"}, 10241 {"bits": [27, 27], "name": "KILL"}, 10242 {"bits": [28, 28], "name": "NEED_KILL_IFETCH"} 10243 ] 10244 }, 10245 "SQ_WAVE_IB_STS": { 10246 "fields": [ 10247 {"bits": [0, 3], "name": "VM_CNT"}, 10248 {"bits": [4, 6], "name": "EXP_CNT"}, 10249 {"bits": [8, 12], "name": "LGKM_CNT"}, 10250 {"bits": [13, 15], "name": "VALU_CNT"} 10251 ] 10252 }, 10253 "SQ_WAVE_LDS_ALLOC": { 10254 "fields": [ 10255 {"bits": [0, 7], "name": "LDS_BASE"}, 10256 {"bits": [12, 20], "name": "LDS_SIZE"} 10257 ] 10258 }, 10259 "SQ_WAVE_MODE": { 10260 "fields": [ 10261 {"bits": [0, 3], "name": "FP_ROUND"}, 10262 {"bits": [4, 7], "name": "FP_DENORM"}, 10263 {"bits": [8, 8], "name": "DX10_CLAMP"}, 10264 {"bits": [9, 9], "name": "IEEE"}, 10265 {"bits": [10, 10], "name": "LOD_CLAMPED"}, 10266 {"bits": [11, 11], "name": "DEBUG_EN"}, 10267 {"bits": [12, 18], "enum_ref": "EXCP_EN", "name": "EXCP_EN"}, 10268 {"bits": [28, 28], "name": "VSKIP"}, 10269 {"bits": [29, 31], "name": "CSP"} 10270 ] 10271 }, 10272 "SQ_WAVE_PC_HI": { 10273 "fields": [ 10274 {"bits": [0, 7], "name": "PC_HI"} 10275 ] 10276 }, 10277 "SQ_WAVE_STATUS": { 10278 "fields": [ 10279 {"bits": [0, 0], "name": "SCC"}, 10280 {"bits": [1, 2], "name": "SPI_PRIO"}, 10281 {"bits": [3, 4], "name": "WAVE_PRIO"}, 10282 {"bits": [5, 5], "name": "PRIV"}, 10283 {"bits": [6, 6], "name": "TRAP_EN"}, 10284 {"bits": [7, 7], "name": "TTRACE_EN"}, 10285 {"bits": [8, 8], "name": "EXPORT_RDY"}, 10286 {"bits": [9, 9], "name": "EXECZ"}, 10287 {"bits": [10, 10], "name": "VCCZ"}, 10288 {"bits": [11, 11], "name": "IN_TG"}, 10289 {"bits": [12, 12], "name": "IN_BARRIER"}, 10290 {"bits": [13, 13], "name": "HALT"}, 10291 {"bits": [14, 14], "name": "TRAP"}, 10292 {"bits": [15, 15], "name": "TTRACE_CU_EN"}, 10293 {"bits": [16, 16], "name": "VALID"}, 10294 {"bits": [17, 17], "name": "ECC_ERR"}, 10295 {"bits": [18, 18], "name": "SKIP_EXPORT"}, 10296 {"bits": [19, 19], "name": "PERF_EN"}, 10297 {"bits": [20, 20], "name": "COND_DBG_USER"}, 10298 {"bits": [21, 21], "name": "COND_DBG_SYS"}, 10299 {"bits": [22, 22], "name": "DATA_ATC"}, 10300 {"bits": [23, 23], "name": "INST_ATC"}, 10301 {"bits": [24, 26], "name": "DISPATCH_CACHE_CTRL"}, 10302 {"bits": [27, 27], "name": "MUST_EXPORT"} 10303 ] 10304 }, 10305 "SQ_WAVE_TBA_HI": { 10306 "fields": [ 10307 {"bits": [0, 7], "name": "ADDR_HI"} 10308 ] 10309 }, 10310 "SQ_WAVE_TRAPSTS": { 10311 "fields": [ 10312 {"bits": [0, 6], "enum_ref": "EXCP_EN", "name": "EXCP"}, 10313 {"bits": [16, 21], "name": "EXCP_CYCLE"}, 10314 {"bits": [29, 31], "name": "DP_RATE"} 10315 ] 10316 }, 10317 "VGT_CACHE_INVALIDATION": { 10318 "fields": [ 10319 {"bits": [0, 1], "name": "CACHE_INVALIDATION"}, 10320 {"bits": [5, 5], "name": "VS_NO_EXTRA_BUFFER"}, 10321 {"bits": [6, 7], "name": "AUTO_INVLD_EN"}, 10322 {"bits": [9, 9], "name": "USE_GS_DONE"}, 10323 {"bits": [11, 11], "name": "DIS_RANGE_FULL_INVLD"}, 10324 {"bits": [12, 12], "name": "GS_LATE_ALLOC_EN"}, 10325 {"bits": [13, 13], "name": "STREAMOUT_FULL_FLUSH"}, 10326 {"bits": [16, 20], "name": "ES_LIMIT"} 10327 ] 10328 }, 10329 "VGT_CNTL_STATUS": { 10330 "fields": [ 10331 {"bits": [0, 0], "name": "VGT_BUSY"}, 10332 {"bits": [1, 1], "name": "VGT_OUT_INDX_BUSY"}, 10333 {"bits": [2, 2], "name": "VGT_OUT_BUSY"}, 10334 {"bits": [3, 3], "name": "VGT_PT_BUSY"}, 10335 {"bits": [4, 4], "name": "VGT_TE_BUSY"}, 10336 {"bits": [5, 5], "name": "VGT_VR_BUSY"}, 10337 {"bits": [6, 6], "name": "VGT_PI_BUSY"}, 10338 {"bits": [7, 7], "name": "VGT_GS_BUSY"}, 10339 {"bits": [8, 8], "name": "VGT_HS_BUSY"}, 10340 {"bits": [9, 9], "name": "VGT_TE11_BUSY"} 10341 ] 10342 }, 10343 "VGT_DEBUG_CNTL": { 10344 "fields": [ 10345 {"bits": [0, 5], "name": "VGT_DEBUG_INDX"}, 10346 {"bits": [6, 6], "name": "VGT_DEBUG_SEL_BUS_B"} 10347 ] 10348 }, 10349 "VGT_DMA_BASE_HI": { 10350 "fields": [ 10351 {"bits": [0, 7], "name": "BASE_ADDR"} 10352 ] 10353 }, 10354 "VGT_DMA_DATA_FIFO_DEPTH": { 10355 "fields": [ 10356 {"bits": [0, 8], "name": "DMA_DATA_FIFO_DEPTH"} 10357 ] 10358 }, 10359 "VGT_DMA_INDEX_TYPE": { 10360 "fields": [ 10361 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"}, 10362 {"bits": [2, 3], "enum_ref": "VGT_DMA_SWAP_MODE", "name": "SWAP_MODE"}, 10363 {"bits": [4, 5], "enum_ref": "VGT_DMA_BUF_TYPE", "name": "BUF_TYPE"}, 10364 {"bits": [6, 7], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"}, 10365 {"bits": [8, 8], "name": "ATC"}, 10366 {"bits": [9, 9], "name": "NOT_EOP"}, 10367 {"bits": [10, 10], "name": "REQ_PATH"} 10368 ] 10369 }, 10370 "VGT_DMA_REQ_FIFO_DEPTH": { 10371 "fields": [ 10372 {"bits": [0, 5], "name": "DMA_REQ_FIFO_DEPTH"} 10373 ] 10374 }, 10375 "VGT_DRAW_INITIATOR": { 10376 "fields": [ 10377 {"bits": [0, 1], "enum_ref": "VGT_DI_SOURCE_SELECT", "name": "SOURCE_SELECT"}, 10378 {"bits": [2, 3], "enum_ref": "VGT_DI_MAJOR_MODE_SELECT", "name": "MAJOR_MODE"}, 10379 {"bits": [4, 4], "name": "SPRITE_EN_R6XX"}, 10380 {"bits": [5, 5], "name": "NOT_EOP"}, 10381 {"bits": [6, 6], "name": "USE_OPAQUE"} 10382 ] 10383 }, 10384 "VGT_DRAW_INIT_FIFO_DEPTH": { 10385 "fields": [ 10386 {"bits": [0, 5], "name": "DRAW_INIT_FIFO_DEPTH"} 10387 ] 10388 }, 10389 "VGT_ESGS_RING_ITEMSIZE": { 10390 "fields": [ 10391 {"bits": [0, 14], "name": "ITEMSIZE"} 10392 ] 10393 }, 10394 "VGT_ES_PER_GS": { 10395 "fields": [ 10396 {"bits": [0, 10], "name": "ES_PER_GS"} 10397 ] 10398 }, 10399 "VGT_EVENT_ADDRESS_REG": { 10400 "fields": [ 10401 {"bits": [0, 27], "name": "ADDRESS_LOW"} 10402 ] 10403 }, 10404 "VGT_EVENT_INITIATOR": { 10405 "fields": [ 10406 {"bits": [0, 5], "enum_ref": "VGT_EVENT_TYPE", "name": "EVENT_TYPE"}, 10407 {"bits": [18, 26], "name": "ADDRESS_HI"}, 10408 {"bits": [27, 27], "name": "EXTENDED_EVENT"} 10409 ] 10410 }, 10411 "VGT_FIFO_DEPTHS": { 10412 "fields": [ 10413 {"bits": [0, 6], "name": "VS_DEALLOC_TBL_DEPTH"}, 10414 {"bits": [7, 7], "name": "RESERVED_0"}, 10415 {"bits": [8, 21], "name": "CLIPP_FIFO_DEPTH"}, 10416 {"bits": [22, 31], "name": "RESERVED_1"} 10417 ] 10418 }, 10419 "VGT_GROUP_DECR": { 10420 "fields": [ 10421 {"bits": [0, 3], "name": "DECR"} 10422 ] 10423 }, 10424 "VGT_GROUP_FIRST_DECR": { 10425 "fields": [ 10426 {"bits": [0, 3], "name": "FIRST_DECR"} 10427 ] 10428 }, 10429 "VGT_GROUP_PRIM_TYPE": { 10430 "fields": [ 10431 {"bits": [0, 4], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"}, 10432 {"bits": [14, 14], "name": "RETAIN_ORDER"}, 10433 {"bits": [15, 15], "name": "RETAIN_QUADS"}, 10434 {"bits": [16, 18], "name": "PRIM_ORDER"} 10435 ] 10436 }, 10437 "VGT_GROUP_VECT_0_CNTL": { 10438 "fields": [ 10439 {"bits": [0, 0], "name": "COMP_X_EN"}, 10440 {"bits": [1, 1], "name": "COMP_Y_EN"}, 10441 {"bits": [2, 2], "name": "COMP_Z_EN"}, 10442 {"bits": [3, 3], "name": "COMP_W_EN"}, 10443 {"bits": [8, 15], "name": "STRIDE"}, 10444 {"bits": [16, 23], "name": "SHIFT"} 10445 ] 10446 }, 10447 "VGT_GROUP_VECT_0_FMT_CNTL": { 10448 "fields": [ 10449 {"bits": [0, 3], "name": "X_CONV"}, 10450 {"bits": [4, 7], "name": "X_OFFSET"}, 10451 {"bits": [8, 11], "name": "Y_CONV"}, 10452 {"bits": [12, 15], "name": "Y_OFFSET"}, 10453 {"bits": [16, 19], "name": "Z_CONV"}, 10454 {"bits": [20, 23], "name": "Z_OFFSET"}, 10455 {"bits": [24, 27], "name": "W_CONV"}, 10456 {"bits": [28, 31], "name": "W_OFFSET"} 10457 ] 10458 }, 10459 "VGT_GSVS_RING_OFFSET_1": { 10460 "fields": [ 10461 {"bits": [0, 14], "name": "OFFSET"} 10462 ] 10463 }, 10464 "VGT_GS_INSTANCE_CNT": { 10465 "fields": [ 10466 {"bits": [0, 0], "name": "ENABLE"}, 10467 {"bits": [2, 8], "name": "CNT"} 10468 ] 10469 }, 10470 "VGT_GS_MAX_VERT_OUT": { 10471 "fields": [ 10472 {"bits": [0, 10], "name": "MAX_VERT_OUT"} 10473 ] 10474 }, 10475 "VGT_GS_MODE": { 10476 "fields": [ 10477 {"bits": [0, 2], "enum_ref": "VGT_GS_MODE_TYPE", "name": "MODE"}, 10478 {"bits": [3, 3], "name": "RESERVED_0"}, 10479 {"bits": [4, 5], "enum_ref": "VGT_GS_CUT_MODE", "name": "CUT_MODE"}, 10480 {"bits": [6, 10], "name": "RESERVED_1"}, 10481 {"bits": [11, 11], "name": "GS_C_PACK_EN"}, 10482 {"bits": [12, 12], "name": "RESERVED_2"}, 10483 {"bits": [13, 13], "name": "ES_PASSTHRU"}, 10484 {"bits": [14, 14], "name": "COMPUTE_MODE"}, 10485 {"bits": [15, 15], "name": "FAST_COMPUTE_MODE"}, 10486 {"bits": [16, 16], "name": "ELEMENT_INFO_EN"}, 10487 {"bits": [17, 17], "name": "PARTIAL_THD_AT_EOI"}, 10488 {"bits": [18, 18], "name": "SUPPRESS_CUTS"}, 10489 {"bits": [19, 19], "name": "ES_WRITE_OPTIMIZE"}, 10490 {"bits": [20, 20], "name": "GS_WRITE_OPTIMIZE"}, 10491 {"bits": [21, 22], "name": "ONCHIP"} 10492 ] 10493 }, 10494 "VGT_GS_OUT_PRIM_TYPE": { 10495 "fields": [ 10496 {"bits": [0, 5], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE"}, 10497 {"bits": [8, 13], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_1"}, 10498 {"bits": [16, 21], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_2"}, 10499 {"bits": [22, 27], "enum_ref": "VGT_GS_OUTPRIM_TYPE", "name": "OUTPRIM_TYPE_3"}, 10500 {"bits": [31, 31], "name": "UNIQUE_TYPE_PER_STREAM"} 10501 ] 10502 }, 10503 "VGT_GS_PER_ES": { 10504 "fields": [ 10505 {"bits": [0, 10], "name": "GS_PER_ES"} 10506 ] 10507 }, 10508 "VGT_GS_PER_VS": { 10509 "fields": [ 10510 {"bits": [0, 3], "name": "GS_PER_VS"} 10511 ] 10512 }, 10513 "VGT_GS_VERTEX_REUSE": { 10514 "fields": [ 10515 {"bits": [0, 4], "name": "VERT_REUSE"} 10516 ] 10517 }, 10518 "VGT_HOS_CNTL": { 10519 "fields": [ 10520 {"bits": [0, 1], "name": "TESS_MODE"} 10521 ] 10522 }, 10523 "VGT_HOS_REUSE_DEPTH": { 10524 "fields": [ 10525 {"bits": [0, 7], "name": "REUSE_DEPTH"} 10526 ] 10527 }, 10528 "VGT_HS_OFFCHIP_PARAM": { 10529 "fields": [ 10530 {"bits": [0, 6], "name": "OFFCHIP_BUFFERING"}, 10531 {"bits": [9, 10], "enum_ref": "VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY", "name": "OFFCHIP_GRANULARITY"} 10532 ] 10533 }, 10534 "VGT_INDEX_TYPE": { 10535 "fields": [ 10536 {"bits": [0, 1], "enum_ref": "VGT_INDEX_TYPE_MODE", "name": "INDEX_TYPE"} 10537 ] 10538 }, 10539 "VGT_LAST_COPY_STATE": { 10540 "fields": [ 10541 {"bits": [0, 2], "name": "SRC_STATE_ID"}, 10542 {"bits": [16, 18], "name": "DST_STATE_ID"} 10543 ] 10544 }, 10545 "VGT_LS_HS_CONFIG": { 10546 "fields": [ 10547 {"bits": [0, 7], "name": "NUM_PATCHES"}, 10548 {"bits": [8, 13], "name": "HS_NUM_INPUT_CP"}, 10549 {"bits": [14, 19], "name": "HS_NUM_OUTPUT_CP"} 10550 ] 10551 }, 10552 "VGT_MC_LAT_CNTL": { 10553 "fields": [ 10554 {"bits": [0, 1], "name": "MC_TIME_STAMP_RES"} 10555 ] 10556 }, 10557 "VGT_MULTI_PRIM_IB_RESET_EN": { 10558 "fields": [ 10559 {"bits": [0, 0], "name": "RESET_EN"} 10560 ] 10561 }, 10562 "VGT_OUTPUT_PATH_CNTL": { 10563 "fields": [ 10564 {"bits": [0, 2], "name": "PATH_SELECT"} 10565 ] 10566 }, 10567 "VGT_OUT_DEALLOC_CNTL": { 10568 "fields": [ 10569 {"bits": [0, 6], "name": "DEALLOC_DIST"} 10570 ] 10571 }, 10572 "VGT_PERFCOUNTER_SEID_MASK": { 10573 "fields": [ 10574 {"bits": [0, 7], "name": "PERF_SEID_IGNORE_MASK"} 10575 ] 10576 }, 10577 "VGT_PRIMITIVEID_EN": { 10578 "fields": [ 10579 {"bits": [0, 0], "name": "PRIMITIVEID_EN"}, 10580 {"bits": [1, 1], "name": "DISABLE_RESET_ON_EOI"} 10581 ] 10582 }, 10583 "VGT_PRIMITIVE_TYPE": { 10584 "fields": [ 10585 {"bits": [0, 5], "enum_ref": "VGT_DI_PRIM_TYPE", "name": "PRIM_TYPE"} 10586 ] 10587 }, 10588 "VGT_REUSE_OFF": { 10589 "fields": [ 10590 {"bits": [0, 0], "name": "REUSE_OFF"} 10591 ] 10592 }, 10593 "VGT_SHADER_STAGES_EN": { 10594 "fields": [ 10595 {"bits": [0, 1], "enum_ref": "VGT_STAGES_LS_EN", "name": "LS_EN"}, 10596 {"bits": [2, 2], "enum_ref": "VGT_STAGES_HS_EN", "name": "HS_EN"}, 10597 {"bits": [3, 4], "enum_ref": "VGT_STAGES_ES_EN", "name": "ES_EN"}, 10598 {"bits": [5, 5], "enum_ref": "VGT_STAGES_GS_EN", "name": "GS_EN"}, 10599 {"bits": [6, 7], "enum_ref": "VGT_STAGES_VS_EN", "name": "VS_EN"}, 10600 {"bits": [8, 8], "name": "DYNAMIC_HS"} 10601 ] 10602 }, 10603 "VGT_STRMOUT_BUFFER_CONFIG": { 10604 "fields": [ 10605 {"bits": [0, 3], "name": "STREAM_0_BUFFER_EN"}, 10606 {"bits": [4, 7], "name": "STREAM_1_BUFFER_EN"}, 10607 {"bits": [8, 11], "name": "STREAM_2_BUFFER_EN"}, 10608 {"bits": [12, 15], "name": "STREAM_3_BUFFER_EN"} 10609 ] 10610 }, 10611 "VGT_STRMOUT_CONFIG": { 10612 "fields": [ 10613 {"bits": [0, 0], "name": "STREAMOUT_0_EN"}, 10614 {"bits": [1, 1], "name": "STREAMOUT_1_EN"}, 10615 {"bits": [2, 2], "name": "STREAMOUT_2_EN"}, 10616 {"bits": [3, 3], "name": "STREAMOUT_3_EN"}, 10617 {"bits": [4, 6], "name": "RAST_STREAM"}, 10618 {"bits": [8, 11], "name": "RAST_STREAM_MASK"}, 10619 {"bits": [31, 31], "name": "USE_RAST_STREAM_MASK"} 10620 ] 10621 }, 10622 "VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE": { 10623 "fields": [ 10624 {"bits": [0, 8], "name": "VERTEX_STRIDE"} 10625 ] 10626 }, 10627 "VGT_STRMOUT_VTX_STRIDE_0": { 10628 "fields": [ 10629 {"bits": [0, 9], "name": "STRIDE"} 10630 ] 10631 }, 10632 "VGT_SYS_CONFIG": { 10633 "fields": [ 10634 {"bits": [0, 0], "name": "DUAL_CORE_EN"}, 10635 {"bits": [1, 6], "name": "MAX_LS_HS_THDGRP"}, 10636 {"bits": [7, 7], "name": "ADC_EVENT_FILTER_DISABLE"} 10637 ] 10638 }, 10639 "VGT_TF_PARAM": { 10640 "fields": [ 10641 {"bits": [0, 1], "enum_ref": "VGT_TESS_TYPE", "name": "TYPE"}, 10642 {"bits": [2, 4], "enum_ref": "VGT_TESS_PARTITION", "name": "PARTITIONING"}, 10643 {"bits": [5, 7], "enum_ref": "VGT_TESS_TOPOLOGY", "name": "TOPOLOGY"}, 10644 {"bits": [8, 8], "name": "RESERVED_REDUC_AXIS"}, 10645 {"bits": [9, 9], "name": "DEPRECATED"}, 10646 {"bits": [10, 13], "name": "NUM_DS_WAVES_PER_SIMD"}, 10647 {"bits": [14, 14], "name": "DISABLE_DONUTS"}, 10648 {"bits": [15, 16], "enum_ref": "VGT_RDREQ_POLICY", "name": "RDREQ_POLICY"} 10649 ] 10650 }, 10651 "VGT_TF_RING_SIZE": { 10652 "fields": [ 10653 {"bits": [0, 15], "name": "SIZE"} 10654 ] 10655 }, 10656 "VGT_VERTEX_REUSE_BLOCK_CNTL": { 10657 "fields": [ 10658 {"bits": [0, 7], "name": "VTX_REUSE_DEPTH"} 10659 ] 10660 }, 10661 "VGT_VTX_CNT_EN": { 10662 "fields": [ 10663 {"bits": [0, 0], "name": "VTX_CNT_EN"} 10664 ] 10665 }, 10666 "VGT_VTX_VECT_EJECT_REG": { 10667 "fields": [ 10668 {"bits": [0, 9], "name": "PRIM_COUNT"} 10669 ] 10670 } 10671 } 10672} 10673