1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd"> 5<import file="freedreno_copyright.xml"/> 6 7<!-- These registers are used on the DSI hosts v2 to control PHY --> 8 9<domain name="DSI_PHY_8610" width="32"> 10 <reg32 offset="0x00200" name="PHY_PLL_CTRL_0"> 11 <bitfield name="ENABLE" pos="0" type="boolean"/> 12 </reg32> 13 <reg32 offset="0x00204" name="PHY_PLL_CTRL_1"/> 14 <reg32 offset="0x00208" name="PHY_PLL_CTRL_2"/> 15 <reg32 offset="0x0020c" name="PHY_PLL_CTRL_3"/> 16 <reg32 offset="0x00210" name="PHY_PLL_CTRL_4"/> 17 <reg32 offset="0x00214" name="PHY_PLL_CTRL_5"/> 18 <reg32 offset="0x00218" name="PHY_PLL_CTRL_6"/> 19 <reg32 offset="0x0021c" name="PHY_PLL_CTRL_7"/> 20 <reg32 offset="0x00220" name="PHY_PLL_CTRL_8"/> 21 <reg32 offset="0x00224" name="PHY_PLL_CTRL_9"/> 22 <reg32 offset="0x00228" name="PHY_PLL_CTRL_10"/> 23 <reg32 offset="0x0022c" name="PHY_PLL_CTRL_11"/> 24 <reg32 offset="0x00230" name="PHY_PLL_CTRL_12"/> 25 <reg32 offset="0x00234" name="PHY_PLL_CTRL_13"/> 26 <reg32 offset="0x00238" name="PHY_PLL_CTRL_14"/> 27 <reg32 offset="0x0023c" name="PHY_PLL_CTRL_15"/> 28 <reg32 offset="0x00240" name="PHY_PLL_CTRL_16"/> 29 <reg32 offset="0x00244" name="PHY_PLL_CTRL_17"/> 30 <reg32 offset="0x00248" name="PHY_PLL_CTRL_18"/> 31 <reg32 offset="0x0024c" name="PHY_PLL_CTRL_19"/> 32 <reg32 offset="0x00250" name="PHY_PLL_CTRL_20"/> 33 34 <reg32 offset="0x00280" name="PHY_PLL_STATUS"> 35 <bitfield name="PLL_BUSY" pos="0" type="boolean"/> 36 </reg32> 37</domain> 38 39<domain name="DSI_PHY_8x60" width="32"> 40 <reg32 offset="0x00258" name="PHY_TPA_CTRL_1"/> 41 <reg32 offset="0x0025c" name="PHY_TPA_CTRL_2"/> 42 <reg32 offset="0x00260" name="PHY_TIMING_CTRL_0"/> 43 <reg32 offset="0x00264" name="PHY_TIMING_CTRL_1"/> 44 <reg32 offset="0x00268" name="PHY_TIMING_CTRL_2"/> 45 <reg32 offset="0x0026c" name="PHY_TIMING_CTRL_3"/> 46 <reg32 offset="0x00270" name="PHY_TIMING_CTRL_4"/> 47 <reg32 offset="0x00274" name="PHY_TIMING_CTRL_5"/> 48 <reg32 offset="0x00278" name="PHY_TIMING_CTRL_6"/> 49 <reg32 offset="0x0027c" name="PHY_TIMING_CTRL_7"/> 50 <reg32 offset="0x00280" name="PHY_TIMING_CTRL_8"/> 51 <reg32 offset="0x00284" name="PHY_TIMING_CTRL_9"/> 52 <reg32 offset="0x00288" name="PHY_TIMING_CTRL_10"/> 53 <reg32 offset="0x0028c" name="PHY_TIMING_CTRL_11"/> 54 <reg32 offset="0x00290" name="PHY_CTRL_0"/> 55 <reg32 offset="0x00294" name="PHY_CTRL_1"/> 56 <reg32 offset="0x00298" name="PHY_CTRL_2"/> 57 <reg32 offset="0x0029c" name="PHY_CTRL_3"/> 58 <reg32 offset="0x002a0" name="PHY_STRENGTH_0"/> 59 <reg32 offset="0x002a4" name="PHY_STRENGTH_1"/> 60 <reg32 offset="0x002a8" name="PHY_STRENGTH_2"/> 61 <reg32 offset="0x002ac" name="PHY_STRENGTH_3"/> 62 <reg32 offset="0x002cc" name="PHY_REGULATOR_CTRL_0"/> 63 <reg32 offset="0x002d0" name="PHY_REGULATOR_CTRL_1"/> 64 <reg32 offset="0x002d4" name="PHY_REGULATOR_CTRL_2"/> 65 <reg32 offset="0x002d8" name="PHY_REGULATOR_CTRL_3"/> 66 <reg32 offset="0x002dc" name="PHY_REGULATOR_CTRL_4"/> 67 68 <reg32 offset="0x000f0" name="PHY_CAL_HW_TRIGGER"/> 69 <reg32 offset="0x000f4" name="PHY_CAL_CTRL"/> 70 <reg32 offset="0x000fc" name="PHY_CAL_STATUS"> 71 <bitfield name="CAL_BUSY" pos="28" type="boolean"/> 72 </reg32> 73</domain> 74 75</database> 76