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1 /*
2  * Copyright 2021 Alyssa Rosenzweig
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #
24 #include <stdint.h>
25 #include "agx_state.h"
26 #include "magic.h"
27 
28 /* The structures managed in this file appear to be software defined (either in
29  * the macOS kernel driver or in the AGX firmware) */
30 
31 /* Odd pattern */
32 static uint64_t
demo_unk6(struct agx_pool * pool)33 demo_unk6(struct agx_pool *pool)
34 {
35    struct agx_ptr ptr = agx_pool_alloc_aligned(pool, 0x4000 * sizeof(uint64_t), 64);
36    uint64_t *buf = ptr.cpu;
37    memset(buf, 0, sizeof(*buf));
38 
39    for (unsigned i = 1; i < 0x3ff; ++i)
40       buf[i] = (i + 1);
41 
42    return ptr.gpu;
43 }
44 
45 static uint64_t
demo_zero(struct agx_pool * pool,unsigned count)46 demo_zero(struct agx_pool *pool, unsigned count)
47 {
48    struct agx_ptr ptr = agx_pool_alloc_aligned(pool, count, 64);
49    memset(ptr.cpu, 0, count);
50    return ptr.gpu;
51 }
52 
53 unsigned
demo_cmdbuf(uint64_t * buf,size_t size,struct agx_pool * pool,uint64_t encoder_ptr,uint64_t encoder_id,uint64_t scissor_ptr,unsigned width,unsigned height,uint32_t pipeline_null,uint32_t pipeline_clear,uint32_t pipeline_store,uint64_t rt0,bool clear_pipeline_textures)54 demo_cmdbuf(uint64_t *buf, size_t size,
55             struct agx_pool *pool,
56             uint64_t encoder_ptr,
57             uint64_t encoder_id,
58             uint64_t scissor_ptr,
59             unsigned width, unsigned height,
60             uint32_t pipeline_null,
61             uint32_t pipeline_clear,
62             uint32_t pipeline_store,
63             uint64_t rt0,
64             bool clear_pipeline_textures)
65 {
66    uint32_t *map = (uint32_t *) buf;
67    memset(map, 0, 474 * 4);
68 
69    map[54] = 0x6b0003;
70    map[55] = 0x3a0012;
71    map[56] = 1;
72 
73    map[106] = 1;
74    map[108] = 0x1c;
75    map[112] = 0xffffffff;
76    map[113] = 0xffffffff;
77    map[114] = 0xffffffff;
78 
79    uint64_t unk_buffer = demo_zero(pool, 0x1000);
80    uint64_t unk_buffer_2 = demo_zero(pool, 0x8000);
81 
82    // This is a pipeline bind
83    map[156] = 0xffff8002 | (clear_pipeline_textures ? 0x210 : 0);
84    map[158] = pipeline_clear | 0x4;
85    map[163] = 0x12;
86    map[164] = pipeline_store | 0x4;
87    map[166] = scissor_ptr & 0xFFFFFFFF;
88    map[167] = scissor_ptr >> 32;
89    map[168] = unk_buffer & 0xFFFFFFFF;
90    map[169] = unk_buffer >> 32;
91 
92    map[220] = 4;
93    map[222] = 0xc000;
94    map[224] = width;
95    map[225] = height;
96    map[226] = unk_buffer_2 & 0xFFFFFFFF;
97    map[227] = unk_buffer_2 >> 32;
98 
99    float depth_clear = 1.0;
100    uint8_t stencil_clear = 0;
101 
102    map[278] = fui(depth_clear);
103    map[279] = (0x3 << 8) | stencil_clear;
104    map[282] = 0x1000000;
105    map[284] = 0xffffffff;
106    map[285] = 0xffffffff;
107    map[286] = 0xffffffff;
108 
109    map[298] = 0xffff8212;
110    map[300] = pipeline_null | 0x4;
111    map[305] = 0x12;
112    map[306] = pipeline_store | 0x4;
113    map[352] = 1;
114    map[360] = 0x1c;
115    map[362] = encoder_id;
116    map[365] = 0xffffffff;
117    map[366] = 1;
118 
119    uint64_t unk6 = demo_unk6(pool);
120    map[370] = unk6 & 0xFFFFFFFF;
121    map[371] = unk6 >> 32;
122 
123    map[374] = width;
124    map[375] = height;
125    map[376] = 1;
126    map[377] = 8;
127    map[378] = 8;
128 
129    map[393] = 8;
130    map[394] = 32;
131    map[395] = 32;
132    map[396] = 1;
133 
134    unsigned offset_unk = (458 * 4);
135    unsigned offset_attachments = (470 * 4);
136    unsigned nr_attachments = 1;
137 
138    map[473] = nr_attachments;
139 
140    /* A single attachment follows, depth/stencil have their own attachments */
141    agx_pack((map + (offset_attachments / 4) + 4), IOGPU_ATTACHMENT, cfg) {
142       cfg.address = rt0;
143       cfg.type = AGX_IOGPU_ATTACHMENT_TYPE_COLOUR;
144       cfg.unk_1 = 0x80000000;
145       cfg.unk_2 = 0x5;
146       cfg.bytes_per_pixel = 4;
147       cfg.percent = 100;
148    }
149 
150    unsigned total_size = offset_attachments + (AGX_IOGPU_ATTACHMENT_LENGTH * nr_attachments) + 16;
151 
152    agx_pack(map, IOGPU_HEADER, cfg) {
153       cfg.total_size = total_size;
154       cfg.attachment_offset_1 = offset_attachments;
155       cfg.attachment_offset_2 = offset_attachments;
156       cfg.attachment_length = nr_attachments * AGX_IOGPU_ATTACHMENT_LENGTH;
157       cfg.unknown_offset = offset_unk;
158       cfg.encoder = encoder_ptr;
159    }
160 
161    return total_size;
162 }
163 
164 static struct agx_map_header
demo_map_header(uint64_t cmdbuf_id,uint64_t encoder_id,unsigned cmdbuf_size,unsigned count)165 demo_map_header(uint64_t cmdbuf_id, uint64_t encoder_id, unsigned cmdbuf_size, unsigned count)
166 {
167    return (struct agx_map_header) {
168       .cmdbuf_id = cmdbuf_id,
169       .unk2 = 0x1,
170       .unk3 = 0x528, // 1320
171       .encoder_id = encoder_id,
172       .unk6 = 0x0,
173       .cmdbuf_size = cmdbuf_size,
174 
175       /* +1 for the sentinel ending */
176       .nr_entries = count + 1,
177       .nr_handles = count + 1,
178       .indices = {0x0b},
179    };
180 }
181 
182 void
demo_mem_map(void * map,size_t size,unsigned * handles,unsigned count,uint64_t cmdbuf_id,uint64_t encoder_id,unsigned cmdbuf_size)183 demo_mem_map(void *map, size_t size, unsigned *handles, unsigned count,
184              uint64_t cmdbuf_id, uint64_t encoder_id, unsigned cmdbuf_size)
185 {
186    struct agx_map_header *header = map;
187    struct agx_map_entry *entries = (struct agx_map_entry *) (((uint8_t *) map) + 0x40);
188    struct agx_map_entry *end = (struct agx_map_entry *) (((uint8_t *) map) + size);
189 
190    /* Header precedes the entry */
191    *header = demo_map_header(cmdbuf_id, encoder_id, cmdbuf_size, count);
192 
193    /* Add an entry for each BO mapped */
194    for (unsigned i = 0; i < count; ++i) {
195 	   assert((entries + i) < end);
196       entries[i] = (struct agx_map_entry) {
197          .unkAAA = 0x20,
198          .unkBBB = 0x1,
199          .unka = 0x1ffff,
200          .indices = {handles[i]}
201       };
202    }
203 
204    /* Final entry is a sentinel */
205    assert((entries + count) < end);
206    entries[count] = (struct agx_map_entry) {
207       .unkAAA = 0x40,
208       .unkBBB = 0x1,
209       .unka = 0x1ffff,
210    };
211 }
212