1#include "arm_arch.h" 2 3.text 4#if defined(__thumb2__) && !defined(__APPLE__) 5.syntax unified 6.thumb 7#else 8.code 32 9#undef __thumb2__ 10#endif 11 12.align 5 13.globl OPENSSL_atomic_add 14.type OPENSSL_atomic_add,%function 15OPENSSL_atomic_add: 16#if __ARM_ARCH__>=6 17.Ladd: ldrex r2,[r0] 18 add r3,r2,r1 19 strex r2,r3,[r0] 20 cmp r2,#0 21 bne .Ladd 22 mov r0,r3 23 bx lr 24#else 25 stmdb sp!,{r4,r5,r6,lr} 26 ldr r2,.Lspinlock 27 adr r3,.Lspinlock 28 mov r4,r0 29 mov r5,r1 30 add r6,r3,r2 @ &spinlock 31 b .+8 32.Lspin: bl sched_yield 33 mov r0,#-1 34 swp r0,r0,[r6] 35 cmp r0,#0 36 bne .Lspin 37 38 ldr r2,[r4] 39 add r2,r2,r5 40 str r2,[r4] 41 str r0,[r6] @ release spinlock 42 ldmia sp!,{r4,r5,r6,lr} 43 tst lr,#1 44 moveq pc,lr 45.word 0xe12fff1e @ bx lr 46#endif 47.size OPENSSL_atomic_add,.-OPENSSL_atomic_add 48 49.globl OPENSSL_cleanse 50.type OPENSSL_cleanse,%function 51OPENSSL_cleanse: 52 eor ip,ip,ip 53 cmp r1,#7 54#ifdef __thumb2__ 55 itt hs 56#endif 57 subhs r1,r1,#4 58 bhs .Lot 59 cmp r1,#0 60 beq .Lcleanse_done 61.Little: 62 strb ip,[r0],#1 63 subs r1,r1,#1 64 bhi .Little 65 b .Lcleanse_done 66 67.Lot: tst r0,#3 68 beq .Laligned 69 strb ip,[r0],#1 70 sub r1,r1,#1 71 b .Lot 72.Laligned: 73 str ip,[r0],#4 74 subs r1,r1,#4 75 bhs .Laligned 76 adds r1,r1,#4 77 bne .Little 78.Lcleanse_done: 79#if __ARM_ARCH__>=5 80 bx lr 81#else 82 tst lr,#1 83 moveq pc,lr 84.word 0xe12fff1e @ bx lr 85#endif 86.size OPENSSL_cleanse,.-OPENSSL_cleanse 87 88.globl CRYPTO_memcmp 89.type CRYPTO_memcmp,%function 90.align 4 91CRYPTO_memcmp: 92 eor ip,ip,ip 93 cmp r2,#0 94 beq .Lno_data 95 stmdb sp!,{r4,r5} 96 97.Loop_cmp: 98 ldrb r4,[r0],#1 99 ldrb r5,[r1],#1 100 eor r4,r4,r5 101 orr ip,ip,r4 102 subs r2,r2,#1 103 bne .Loop_cmp 104 105 ldmia sp!,{r4,r5} 106.Lno_data: 107 rsb r0,ip,#0 108 mov r0,r0,lsr#31 109#if __ARM_ARCH__>=5 110 bx lr 111#else 112 tst lr,#1 113 moveq pc,lr 114.word 0xe12fff1e @ bx lr 115#endif 116.size CRYPTO_memcmp,.-CRYPTO_memcmp 117 118#if __ARM_MAX_ARCH__>=7 119.arch armv7-a 120.fpu neon 121 122.align 5 123.globl _armv7_neon_probe 124.type _armv7_neon_probe,%function 125_armv7_neon_probe: 126 vorr q0,q0,q0 127 bx lr 128.size _armv7_neon_probe,.-_armv7_neon_probe 129 130.globl _armv7_tick 131.type _armv7_tick,%function 132_armv7_tick: 133#ifdef __APPLE__ 134 mrrc p15,0,r0,r1,c14 @ CNTPCT 135#else 136 mrrc p15,1,r0,r1,c14 @ CNTVCT 137#endif 138 bx lr 139.size _armv7_tick,.-_armv7_tick 140 141.globl _armv8_aes_probe 142.type _armv8_aes_probe,%function 143_armv8_aes_probe: 144#if defined(__thumb2__) && !defined(__APPLE__) 145.byte 0xb0,0xff,0x00,0x03 @ aese.8 q0,q0 146#else 147.byte 0x00,0x03,0xb0,0xf3 @ aese.8 q0,q0 148#endif 149 bx lr 150.size _armv8_aes_probe,.-_armv8_aes_probe 151 152.globl _armv8_sha1_probe 153.type _armv8_sha1_probe,%function 154_armv8_sha1_probe: 155#if defined(__thumb2__) && !defined(__APPLE__) 156.byte 0x00,0xef,0x40,0x0c @ sha1c.32 q0,q0,q0 157#else 158.byte 0x40,0x0c,0x00,0xf2 @ sha1c.32 q0,q0,q0 159#endif 160 bx lr 161.size _armv8_sha1_probe,.-_armv8_sha1_probe 162 163.globl _armv8_sha256_probe 164.type _armv8_sha256_probe,%function 165_armv8_sha256_probe: 166#if defined(__thumb2__) && !defined(__APPLE__) 167.byte 0x00,0xff,0x40,0x0c @ sha256h.32 q0,q0,q0 168#else 169.byte 0x40,0x0c,0x00,0xf3 @ sha256h.32 q0,q0,q0 170#endif 171 bx lr 172.size _armv8_sha256_probe,.-_armv8_sha256_probe 173.globl _armv8_pmull_probe 174.type _armv8_pmull_probe,%function 175_armv8_pmull_probe: 176#if defined(__thumb2__) && !defined(__APPLE__) 177.byte 0xa0,0xef,0x00,0x0e @ vmull.p64 q0,d0,d0 178#else 179.byte 0x00,0x0e,0xa0,0xf2 @ vmull.p64 q0,d0,d0 180#endif 181 bx lr 182.size _armv8_pmull_probe,.-_armv8_pmull_probe 183#endif 184 185.globl OPENSSL_wipe_cpu 186.type OPENSSL_wipe_cpu,%function 187OPENSSL_wipe_cpu: 188#if __ARM_MAX_ARCH__>=7 189 ldr r0,.LOPENSSL_armcap 190 adr r1,.LOPENSSL_armcap 191 ldr r0,[r1,r0] 192#ifdef __APPLE__ 193 ldr r0,[r0] 194#endif 195#endif 196 eor r2,r2,r2 197 eor r3,r3,r3 198 eor ip,ip,ip 199#if __ARM_MAX_ARCH__>=7 200 tst r0,#1 201 beq .Lwipe_done 202 veor q0, q0, q0 203 veor q1, q1, q1 204 veor q2, q2, q2 205 veor q3, q3, q3 206 veor q8, q8, q8 207 veor q9, q9, q9 208 veor q10, q10, q10 209 veor q11, q11, q11 210 veor q12, q12, q12 211 veor q13, q13, q13 212 veor q14, q14, q14 213 veor q15, q15, q15 214.Lwipe_done: 215#endif 216 mov r0,sp 217#if __ARM_ARCH__>=5 218 bx lr 219#else 220 tst lr,#1 221 moveq pc,lr 222.word 0xe12fff1e @ bx lr 223#endif 224.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu 225 226.globl OPENSSL_instrument_bus 227.type OPENSSL_instrument_bus,%function 228OPENSSL_instrument_bus: 229 eor r0,r0,r0 230#if __ARM_ARCH__>=5 231 bx lr 232#else 233 tst lr,#1 234 moveq pc,lr 235.word 0xe12fff1e @ bx lr 236#endif 237.size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus 238 239.globl OPENSSL_instrument_bus2 240.type OPENSSL_instrument_bus2,%function 241OPENSSL_instrument_bus2: 242 eor r0,r0,r0 243#if __ARM_ARCH__>=5 244 bx lr 245#else 246 tst lr,#1 247 moveq pc,lr 248.word 0xe12fff1e @ bx lr 249#endif 250.size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2 251 252.align 5 253#if __ARM_MAX_ARCH__>=7 254.LOPENSSL_armcap: 255.word OPENSSL_armcap_P-. 256#endif 257#if __ARM_ARCH__>=6 258.align 5 259#else 260.Lspinlock: 261.word atomic_add_spinlock-.Lspinlock 262.align 5 263 264.data 265.align 2 266atomic_add_spinlock: 267.word 0 268#endif 269 270.comm OPENSSL_armcap_P,4,4 271.hidden OPENSSL_armcap_P 272