Lines Matching refs:pmwrite
100 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32) in pmwrite() function
126 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
127 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
128 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
129 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
132 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_enable()
133 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_enable()
134 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_enable()
135 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_enable()
137 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff); in pm3393_interrupt_enable()
138 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
139 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
140 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
141 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
142 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff); in pm3393_interrupt_enable()
143 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff); in pm3393_interrupt_enable()
144 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff); in pm3393_interrupt_enable()
145 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff); in pm3393_interrupt_enable()
150 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, in pm3393_interrupt_enable()
165 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
166 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
167 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
168 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
169 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_disable()
170 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_disable()
171 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0); in pm3393_interrupt_disable()
172 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0); in pm3393_interrupt_disable()
173 pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0); in pm3393_interrupt_disable()
174 pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
175 pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
176 pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
177 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
178 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0); in pm3393_interrupt_disable()
179 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0); in pm3393_interrupt_disable()
180 pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0); in pm3393_interrupt_disable()
181 pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0); in pm3393_interrupt_disable()
184 pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0); in pm3393_interrupt_disable()
264 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, in pm3393_enable()
274 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val); in pm3393_enable()
284 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_enable_port()
303 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL); in pm3393_disable()
305 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL); in pm3393_disable()
337 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu); in pm3393_set_mtu()
338 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu); in pm3393_set_mtu()
357 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, in pm3393_set_rx_mode()
366 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff); in pm3393_set_rx_mode()
367 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff); in pm3393_set_rx_mode()
368 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff); in pm3393_set_rx_mode()
369 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff); in pm3393_set_rx_mode()
382 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]); in pm3393_set_rx_mode()
383 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]); in pm3393_set_rx_mode()
384 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]); in pm3393_set_rx_mode()
385 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]); in pm3393_set_rx_mode()
389 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode); in pm3393_set_rx_mode()
449 pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL, in pm3393_update_statistics()
533 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo); in pm3393_macaddress_set()
534 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid); in pm3393_macaddress_set()
535 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi); in pm3393_macaddress_set()
538 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo); in pm3393_macaddress_set()
539 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid); in pm3393_macaddress_set()
540 pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi); in pm3393_macaddress_set()
548 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); in pm3393_macaddress_set()
550 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo); in pm3393_macaddress_set()
551 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid); in pm3393_macaddress_set()
552 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi); in pm3393_macaddress_set()
555 pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val); in pm3393_macaddress_set()