| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/cs1000lite_regs/ |
| D | cs1000Lite_rtc_core.h | 58 #define CS1000LITE_RTC_CORE_RTC_RG_XTAL32K_COMP_IBIT(n) (((n)&7)<<2) argument
59 #define CS1000LITE_RTC_CORE_RTC_RG_XTAL32K_IBIT(n) (((n)&7)<<5) argument
60 #define CS1000LITE_RTC_CORE_RTC_RG_XTAL32K_AMP_BIT(n) (((n)&7)<<8) argument
61 #define CS1000LITE_RTC_CORE_RTC_RG_XTAL32K_CLK_EN(n) (((n)&7)<<11) argument
62 #define CS1000LITE_RTC_CORE_RTC_RG_POR_CLK32K_FBIT(n) (((n)&7)<<14) argument
63 #define CS1000LITE_RTC_CORE_RTC_RG_XTAL_CAP_STEP(n) (((n)&0x3F)<<17) argument
64 #define CS1000LITE_RTC_CORE_RTC_RG_LPO512K_TEMP_COEF_BIT(n) (((n)&7)<<23) argument
71 #define CS1000LITE_RTC_CORE_RTC_RG_MDLL128K_DIV_BIT(n) (((n)&7)<<1) argument
72 #define CS1000LITE_RTC_CORE_RTC_RG_MDLL128K_FREQ_C_BIT(n) (((n)&15)<<4) argument
73 #define CS1000LITE_RTC_CORE_RTC_RG_MDLL128K_FREQ_F_BIT(n) (((n)&0x3F)<<8) argument
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| D | cs1000Lite_analog_reg.h | 83 #define CS1000LITE_ANALOG_REG_CFG_USB_CTRL(n) (((n)&0x7FFFFFFF)<<0) argument
89 #define CS1000LITE_ANALOG_REG_CFG_USBPLL_SDM_CLK_SEL(n) (((n)&3)<<2) argument
90 #define CS1000LITE_ANALOG_REG_CFG_USBPLL_SDM_RESETN_DELAY(n) (((n)&0xFF)<<4) argument
91 #define CS1000LITE_ANALOG_REG_CFG_USBPLL_SDM_INTDEC_SEL(n) (((n)&7)<<20) argument
102 #define CS1000LITE_ANALOG_REG_CFG_USBPLL_SDM_FREQ(n) (((n)&0xFFFFFFF)<<0) argument
107 #define CS1000LITE_ANALOG_REG_CFG_USBPLL_SDM_AMP_CT(n) (((n)&7)<<1) argument
108 #define CS1000LITE_ANALOG_REG_CFG_USBPLL_SDM_CYC_CT(n) (((n)&3)<<4) argument
121 #define CS1000LITE_ANALOG_REG_CFG_ANA_USB_HS_CLK_SEL(n) (((n)&3)<<10) argument
122 #define CS1000LITE_ANALOG_REG_CFG_ANA_USB_ISET_SEQ(n) (((n)&7)<<12) argument
124 #define CS1000LITE_ANALOG_REG_CFG_ANA_USB_ISET_OTG(n) (((n)&7)<<16) argument
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| D | cs1000Lite_sys_ctrl.h | 70 #define CS1000LITE_SYS_CTRL_CHIP_ID(n) (((n)&0xFFFF)<<0) argument
71 #define CS1000LITE_SYS_CTRL_METAL_ID(n) (((n)&0xFF)<<16) argument
72 #define CS1000LITE_SYS_CTRL_BOND_ID(n) (((n)&0xFF)<<24) argument
86 #define CS1000LITE_SYS_CTRL_CFG_HCLK_MODE(n) (((n)&0xFFFFFFFF)<<0) argument
89 #define CS1000LITE_SYS_CTRL_CFG_OTHERS_CLK_MODE(n) (((n)&0xFFFF)<<0) argument
92 #define CS1000LITE_SYS_CTRL_CFG_HCLK_DIV_DENOM(n) (((n)&0xFF)<<0) argument
96 #define CS1000LITE_SYS_CTRL_CFG_CLK_MSADC_DIV_DENOM(n) (((n)&0xFF)<<0) argument
100 #define CS1000LITE_SYS_CTRL_CFG_MEM_SRAM(n) (((n)&0xFFFF)<<0) argument
103 #define CS1000LITE_SYS_CTRL_CFG_USB_CTRL(n) (((n)&0x7FFFFFFF)<<0) argument
107 #define CS1000LITE_SYS_CTRL_CFG_DET_SDIO_TRIG_CMD_ARGUMENT(n) (((n)&0xFFFFFFFF)<<0) argument
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| D | cs1000Lite_iomux.h | 37 #define CS1000LITE_IOMUX_PAD_GPIO_DRV_STRENGTH(n) (((n)&3)<<18) argument
42 #define CS1000LITE_IOMUX_PAD_GPIO_ANA(n) (((n)&15)<<4) argument
43 #define CS1000LITE_IOMUX_PAD_GPIO_SEL(n) (((n)&15)<<0) argument
51 #define CS1000LITE_IOMUX_PAD_GPIO_0_DRV_STRENGTH(n) (((n)&3)<<18) argument
56 #define CS1000LITE_IOMUX_PAD_GPIO_0_ANA(n) (((n)&15)<<4) argument
57 #define CS1000LITE_IOMUX_PAD_GPIO_0_SEL(n) (((n)&15)<<0) argument
74 #define CS1000LITE_IOMUX_PAD_GPIO_1_DRV_STRENGTH(n) (((n)&3)<<18) argument
79 #define CS1000LITE_IOMUX_PAD_GPIO_1_ANA(n) (((n)&15)<<4) argument
80 #define CS1000LITE_IOMUX_PAD_GPIO_1_SEL(n) (((n)&15)<<0) argument
97 #define CS1000LITE_IOMUX_PAD_GPIO_2_DRV_STRENGTH(n) (((n)&3)<<18) argument
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| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/cs1000aud_regs/ |
| D | cs1000Aud_rtc_core.h | 65 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_LP_BIT(n) (((n)&31)<<0) argument
66 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_NOR_DELTA(n) (((n)&0x3F)<<5) argument
67 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_NOR_BIT(n) (((n)&31)<<11) argument
68 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_STEP(n) (((n)&0x3F)<<16) argument
69 #define CS1000AUD_RTC_CORE_RTC_RG_LPO256K_TEMP_COEF_BIT(n) (((n)&15)<<22) argument
73 #define CS1000AUD_RTC_CORE_RTC_RG_POR_CLK32K_FBIT(n) (((n)&7)<<29) argument
76 #define CS1000AUD_RTC_CORE_RTC_RG_BG_TRIM(n) (((n)&7)<<0) argument
81 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_LP_DELTA(n) (((n)&0x3F)<<7) argument
82 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_RF_ON_DELTA(n) (((n)&0x3F)<<13) argument
83 #define CS1000AUD_RTC_CORE_RTC_RG_XTAL_CAP_RF_ON_BIT(n) (((n)&31)<<19) argument
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| D | cs1000Aud_analog_reg.h | 75 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_CHOP_EN(n) (((n)&3)<<1) argument
77 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_CDC_MODE(n) (((n)&3)<<4) argument
80 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_REFV1_BIT(n) (((n)&3)<<8) argument
81 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_PU_BIT(n) (((n)&3)<<10) argument
82 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_REFV_BIT(n) (((n)&7)<<12) argument
83 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_REFC_BIT(n) (((n)&7)<<16) argument
84 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_IBIT(n) (((n)&7)<<20) argument
85 #define CS1000AUD_ANALOG_REG_CFG_ANA_TOUCH_IOS_BIT(n) (((n)&7)<<24) argument
88 #define CS1000AUD_ANALOG_REG_CFG_ANA_DCDC_RF_VBIT_OFFSET(n) (((n)&15)<<0) argument
89 #define CS1000AUD_ANALOG_REG_CFG_ANA_DCDC_RF_FBIT(n) (((n)&3)<<4) argument
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| D | cs1000Aud_sys_ctrl.h | 55 #define CS1000AUD_SYS_CTRL_CHIP_ID(n) (((n)&0xFFFF)<<0) argument
56 #define CS1000AUD_SYS_CTRL_METAL_ID(n) (((n)&0xFF)<<16) argument
57 #define CS1000AUD_SYS_CTRL_BOND_ID(n) (((n)&15)<<24) argument
58 #define CS1000AUD_SYS_CTRL_REV_ID(n) (((n)&15)<<28) argument
68 #define CS1000AUD_SYS_CTRL_CFG_PCLK_MODE(n) (((n)&0xFFFFFFFF)<<0) argument
71 #define CS1000AUD_SYS_CTRL_CFG_OTHERS_CLK_MODE(n) (((n)&0xFFFF)<<0) argument
74 #define CS1000AUD_SYS_CTRL_CFG_PCLK_DIV_DENOM(n) (((n)&0xFF)<<0) argument
78 #define CS1000AUD_SYS_CTRL_CFG_CLK_MSADC_DIV_DENOM(n) (((n)&0xFF)<<0) argument
82 #define CS1000AUD_SYS_CTRL_CFG_CLK_TOUCH_DIV_MODE(n) (((n)&3)<<0) argument
85 #define CS1000AUD_SYS_CTRL_CFG_DCDC_REF_CLK_DIV_DENOM(n) (((n)&0xFF)<<0) argument
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| D | cs1000Aud_iomux.h | 37 #define CS1000AUD_IOMUX_PAD_GPIO_DRV_STRENGTH(n) (((n)&3)<<18) argument
42 #define CS1000AUD_IOMUX_PAD_GPIO_ANA(n) (((n)&15)<<4) argument
43 #define CS1000AUD_IOMUX_PAD_GPIO_SEL(n) (((n)&15)<<0) argument
51 #define CS1000AUD_IOMUX_PAD_GPIO_0_DRV_STRENGTH(n) (((n)&3)<<18) argument
56 #define CS1000AUD_IOMUX_PAD_GPIO_0_ANA(n) (((n)&15)<<4) argument
57 #define CS1000AUD_IOMUX_PAD_GPIO_0_SEL(n) (((n)&15)<<0) argument
69 #define CS1000AUD_IOMUX_PAD_GPIO_1_DRV_STRENGTH(n) (((n)&3)<<18) argument
74 #define CS1000AUD_IOMUX_PAD_GPIO_1_ANA(n) (((n)&15)<<4) argument
75 #define CS1000AUD_IOMUX_PAD_GPIO_1_SEL(n) (((n)&15)<<0) argument
87 #define CS1000AUD_IOMUX_PAD_GPIO_2_DRV_STRENGTH(n) (((n)&3)<<18) argument
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/best2003/ |
| D | reg_wfcmu_best2003.h | 32 #define WLAN_CMU_MANUAL_HCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
37 #define WLAN_CMU_MANUAL_HCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
42 #define WLAN_CMU_MANUAL_PCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
47 #define WLAN_CMU_MANUAL_PCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
52 #define WLAN_CMU_MANUAL_OCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
57 #define WLAN_CMU_MANUAL_OCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
62 #define WLAN_CMU_MANUAL_MCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
67 #define WLAN_CMU_MANUAL_MCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
72 #define WLAN_CMU_MANUAL_YCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
77 #define WLAN_CMU_MANUAL_YCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
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| D | reg_psc_best2003.h | 111 #define PSC_AON_MCU_RESERVED(n) (((n) & 0x7F) << 1) argument
114 #define PSC_AON_MCU_MAIN_STATE(n) (((n) & 0x3) << 8) argument
117 #define PSC_AON_MCU_POWERDN_STATE(n) (((n) & 0x7) << 10) argument
120 #define PSC_AON_MCU_POWERUP_STATE(n) (((n) & 0x7) << 13) argument
125 #define PSC_AON_MCU_POWERDN_TIMER1(n) (((n) & 0x3F) << 0) argument
128 #define PSC_AON_MCU_POWERDN_TIMER2(n) (((n) & 0x3F) << 6) argument
131 #define PSC_AON_MCU_POWERDN_TIMER3(n) (((n) & 0x3F) << 12) argument
134 #define PSC_AON_MCU_POWERDN_TIMER4(n) (((n) & 0x3F) << 18) argument
137 #define PSC_AON_MCU_POWERDN_TIMER5(n) (((n) & 0xFF) << 24) argument
142 #define PSC_AON_MCU_POWERUP_TIMER1(n) (((n) & 0x3F) << 0) argument
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| D | reg_iomux_best2003.h | 62 #define IOMUX_32_H00001300(n) (((n) & 0xFFFFFFFF) << 0) argument
67 #define IOMUX_GPIO_P00_SEL(n) (((n) & 0xF) << 0) argument
70 #define IOMUX_GPIO_P01_SEL(n) (((n) & 0xF) << 4) argument
73 #define IOMUX_GPIO_P02_SEL(n) (((n) & 0xF) << 8) argument
76 #define IOMUX_GPIO_P03_SEL(n) (((n) & 0xF) << 12) argument
79 #define IOMUX_GPIO_P04_SEL(n) (((n) & 0xF) << 16) argument
82 #define IOMUX_GPIO_P05_SEL(n) (((n) & 0xF) << 20) argument
85 #define IOMUX_GPIO_P06_SEL(n) (((n) & 0xF) << 24) argument
88 #define IOMUX_GPIO_P07_SEL(n) (((n) & 0xF) << 28) argument
93 #define IOMUX_GPIO_P10_SEL(n) (((n) & 0xF) << 0) argument
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| D | reg_cmu_best2003.h | 130 #define CMU_MANUAL_HCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
135 #define CMU_MANUAL_HCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
140 #define CMU_MANUAL_PCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
145 #define CMU_MANUAL_PCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
150 #define CMU_MANUAL_OCLK_ENABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
155 #define CMU_MANUAL_OCLK_DISABLE(n) (((n) & 0xFFFFFFFF) << 0) argument
160 #define CMU_MODE_HCLK(n) (((n) & 0xFFFFFFFF) << 0) argument
165 #define CMU_MODE_PCLK(n) (((n) & 0xFFFFFFFF) << 0) argument
170 #define CMU_MODE_OCLK(n) (((n) & 0xFFFFFFFF) << 0) argument
175 #define CMU_HRESETN_PULSE(n) (((n) & 0xFFFFFFFF) << 0) argument
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| /device/board/isoftstone/zhiyuan/kernel/hdf/driver/audio/dai/include/ |
| D | t507_dai_ahub_impl_linux.h | 31 #define SUNXI_AHUB_APBIF_TX_CTL(n) (0x10 + ((n) * 0x30)) argument
32 #define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n) (0x14 + ((n) * 0x30)) argument
33 #define SUNXI_AHUB_APBIF_TX_IRQ_STA(n) (0x18 + ((n) * 0x30)) argument
35 #define SUNXI_AHUB_APBIF_TXFIFO_CTL(n) (0x20 + ((n) * 0x30)) argument
36 #define SUNXI_AHUB_APBIF_TXFIFO_STA(n) (0x24 + ((n) * 0x30)) argument
38 #define SUNXI_AHUB_APBIF_TXFIFO(n) (0x30 + ((n) * 0x30)) argument
39 #define SUNXI_AHUB_APBIF_TXFIFO_CNT(n) (0x34 + ((n) * 0x30)) argument
41 #define SUNXI_AHUB_APBIF_RX_CTL(n) (0x100 + ((n) * 0x30)) argument
42 #define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n) (0x104 + ((n) * 0x30)) argument
43 #define SUNXI_AHUB_APBIF_RX_IRQ_STA(n) (0x108 + ((n) * 0x30)) argument
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/ |
| D | reg_lcdc.h | 139 #define LCD_CFG_TVD_SA_Y0(n) (((n) & 0xFFFFFFFF) << 0) argument
144 #define LCD_CFG_TVD_SA_U0(n) (((n) & 0xFFFFFFFF) << 0) argument
149 #define LCD_CFG_TVD_SA_V0(n) (((n) & 0xFFFFFFFF) << 0) argument
154 #define LCD_CFG_TVD_SA_C0(n) (((n) & 0xFFFFFFFF) << 0) argument
159 #define LCD_CFG_TVD_SA_Y1(n) (((n) & 0xFFFFFFFF) << 0) argument
164 #define LCD_CFG_TVD_SA_U1(n) (((n) & 0xFFFFFFFF) << 0) argument
169 #define LCD_CFG_TVD_SA_V1(n) (((n) & 0xFFFFFFFF) << 0) argument
174 #define LCD_CFG_TVD_SA_C1(n) (((n) & 0xFFFFFFFF) << 0) argument
179 #define LCD_CFG_TVD_PITCH_Y(n) (((n) & 0xFFFF) << 0) argument
182 #define LCD_CFG_TVD_PITCH_C(n) (((n) & 0xFFFF) << 16) argument
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| D | reg_psram_mc_v2.h | 110 #define PSRAM_ULP_MC_CHIP_CA_PATTERN(n) (((n) & 0x7) << 3) argument
117 #define PSRAM_ULP_MC_DTR_MODE(n) (((n) & 0x7) << 10) argument
125 #define PSRAM_ULP_MC_MGR_CMD(n) (((n) & 0xFF) << 0) argument
130 #define PSRAM_ULP_MC_MGR_ADDR(n) (((n) & 0xFFFFFFFF) << 0) argument
135 #define PSRAM_ULP_MC_MGR_LEN(n) (((n) & 0xFF) << 0) argument
141 #define PSRAM_ULP_MC_MGR_WSTRB(n) (((n) & 0xFF) << 0) argument
146 #define PSRAM_ULP_MC_MGR_TX_FIFO(n) (((n) & 0xFFFFFFFF) << 0) argument
151 #define PSRAM_ULP_MC_MGR_RX_FIFO(n) (((n) & 0xFFFFFFFF) << 0) argument
168 #define PSRAM_ULP_MC_RES_7_4_REG24(n) (((n) & 0xF) << 4) argument
171 #define PSRAM_ULP_MC_PD_MR(n) (((n) & 0xFF) << 8) argument
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| D | reg_dsi.h | 50 #define DSI_R_LANE_NUM(n) (((n) & 0x3) << 0) argument
54 #define DSI_R_LPCD_DLY(n) (((n) & 0x3) << 3) argument
64 #define DSI_R_T_BTA(n) (((n) & 0xF) << 12) argument
67 #define DSI_R_T_LPX(n) (((n) & 0xF) << 16) argument
70 #define DSI_R_CLK_T_LPX(n) (((n) & 0xF) << 20) argument
73 #define DSI_R_CLK_PRE(n) (((n) & 0x3) << 24) argument
76 #define DSI_R_CLK_POST(n) (((n) & 0x3F) << 26) argument
81 #define DSI_R_HS_EXIT_TIME(n) (((n) & 0x3F) << 0) argument
84 #define DSI_R_HS_PRPR_TIME(n) (((n) & 0xF) << 6) argument
87 #define DSI_R_HS_ZERO_TIME(n) (((n) & 0x3F) << 10) argument
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| D | hal_location.h | 40 #define BOOT_TEXT_SRAM_DEF(n) HAL_SEC_DEF(.boot_text_sram, n) argument
42 #define BOOT_TEXT_FLASH_DEF(n) HAL_SEC_DEF(.boot_text_flash, n) argument
44 #define BOOT_RODATA_SRAM_DEF(n) HAL_SEC_DEF(.boot_rodata_sram, n) argument
46 #define BOOT_RODATA_FLASH_DEF(n) HAL_SEC_DEF(.boot_rodata_flash, n) argument
48 #define BOOT_DATA_DEF(n) HAL_SEC_DEF(.boot_data, n) argument
51 #define BOOT_BSS_DEF(n) HAL_SEC_DEF(.bss.boot_bss, n) argument
58 #define SRAM_TEXT_DEF(n) HAL_SEC_DEF(.sram_text, n) argument
60 #define SRAM_DATA_DEF(n) HAL_SEC_DEF(.sram_data, n) argument
62 #define SRAM_STACK_DEF(n) ALIGNED(8) HAL_SEC_LOC(.sram_data, n) argument
65 #define SRAM_BSS_DEF(n) HAL_SEC_DEF(.bss.sram_bss, n) argument
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| D | reg_pwm.h | 47 #define PWM_PHASE01_0(n) (((n) & 0xFFFF) << 0) argument
50 #define PWM_PHASE01_1(n) (((n) & 0xFFFF) << 16) argument
54 #define PWM_PHASE23_2(n) (((n) & 0xFFFF) << 0) argument
57 #define PWM_PHASE23_3(n) (((n) & 0xFFFF) << 16) argument
61 #define PWM_LOAD01_0(n) (((n) & 0xFFFF) << 0) argument
64 #define PWM_LOAD01_1(n) (((n) & 0xFFFF) << 16) argument
68 #define PWM_LOAD23_2(n) (((n) & 0xFFFF) << 0) argument
71 #define PWM_LOAD23_3(n) (((n) & 0xFFFF) << 16) argument
75 #define PWM_TOGGLE01_0(n) (((n) & 0xFFFF) << 0) argument
78 #define PWM_TOGGLE01_1(n) (((n) & 0xFFFF) << 16) argument
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| D | reg_psram_phy_v2.h | 50 #define PSRAM_ULP_PHY_MEMORY_WIDTH(n) (((n) & 0x3) << 2) argument
53 #define PSRAM_ULP_PHY_FRE_RATIO(n) (((n) & 0x3) << 4) argument
58 #define PSRAM_ULP_PHY_CTRL_DELAY(n) (((n) & 0x3) << 0) argument
66 #define PSRAM_ULP_PHY_SQPI_SAMPLE_SEL(n) (((n) & 0xF) << 7) argument
77 #define PSRAM_ULP_PHY_T_WPST(n) (((n) & 0x7) << 0) argument
82 #define PSRAM_ULP_PHY_RESERVED(n) (((n) & 0x3F) << 0) argument
100 #define PSRAM_ULP_PHY_PHY_FSM_STATE(n) (((n) & 0xF) << 1) argument
104 #define PSRAM_ULP_PHY_SQPI_PHY_FSM_STATE(n) (((n) & 0xF) << 6) argument
111 #define PSRAM_ULP_PHY_REG_LDO_IEN1(n) (((n) & 0xF) << 2) argument
114 #define PSRAM_ULP_PHY_REG_LDO_IEN2(n) (((n) & 0xF) << 6) argument
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| /device/soc/winnermicro/wm800/board/include/driver/ |
| D | wm_adc.h | 39 #define ADC_RESULT_VAL(n) ((n)&ADC_RESULT_MASK) argument
43 #define CONFIG_ADC_CHL_SEL(n) ((n)<<8) argument
46 #define CONFIG_PD_ADC_VAL(n) ((n)<<2) /* 1:pd adc, 0: normal work */ argument
49 #define CONFIG_RSTN_ADC_VAL(n) ((n)<<1) /* 1:normal work, 0:adc reset */ argument
52 #define CONFIG_EN_LDO_ADC_VAL(n) ((n)<<0) /* 1:ldo work, 0: ldo shutdown */ argument
56 #define CLK_CHOP_SEL_PGA_VAL(n) ((n)<<4) argument
59 #define GAIN_CTRL_PGA_VAL(n) ((n)<<7) argument
62 #define PGA_BYPASS_VAL(n) ((n)<<3) /* 1:bypass pga, 0:use pga */ argument
67 #define PGA_CHOP_ENP_VAL(n) ((n)<<1) /* 1: enable chop, 0: disable chop */ argument
70 #define PGA_EN_VAL(n) ((n)<<0) /* 1: enable pga, 0: disable pga */ argument
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| /device/board/unionman/unionpi_tiger/kernel/drivers/media/drivers/stream_input/parser/demux/sw_demux/dvbcsa2/ |
| D | dvbcsa_bs_uint64.h | 34 #define BS_VAL(n) ((dvbcsa_bs_word_t)(n)) argument
37 #define BS_VAL64(n) BS_VAL(0x##n##UL) argument
39 #define BS_VAL64(n) BS_VAL(0x##n##ULL) argument
42 #define BS_VAL32(n) BS_VAL64(n##n) argument
43 #define BS_VAL16(n) BS_VAL32(n##n) argument
44 #define BS_VAL8(n) BS_VAL16(n##n) argument
51 #define BS_SHL(a, n) ((a) << (n)) argument
52 #define BS_SHR(a, n) ((a) >> (n)) argument
53 #define BS_SHL8(a, n) ((a) << (8 * (n))) argument
54 #define BS_SHR8(a, n) ((a) >> (8 * (n))) argument
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| D | dvbcsa_bs_mmx.h | 36 #define BS_VAL(n) ((dvbcsa_bs_word_t)(n)) argument
37 #define BS_VAL64(n) BS_VAL(0x##n##ULL) argument
38 #define BS_VAL32(n) BS_VAL64(n##n) argument
39 #define BS_VAL16(n) BS_VAL32(n##n) argument
40 #define BS_VAL8(n) BS_VAL16(n##n) argument
47 #define BS_SHL(a, n) _m_psllqi((a), n) argument
48 #define BS_SHR(a, n) _m_psrlqi((a), n) argument
49 #define BS_SHL8(a, n) BS_SHL(a, 8 * (n)) argument
50 #define BS_SHR8(a, n) BS_SHR(a, 8 * (n)) argument
51 #define BS_EXTRACT8(a, n) _mm_cvtsi64_si32(_m_psrlqi((a), 8 * (n))) argument
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| D | dvbcsa_bs_sse.h | 37 #define BS_VAL(n, m) _mm_set_epi64x(n, m) argument
38 #define BS_VAL64(n) BS_VAL(0x##n##ULL, 0x##n##ULL) argument
39 #define BS_VAL32(n) BS_VAL64(n##n) argument
40 #define BS_VAL16(n) BS_VAL32(n##n) argument
41 #define BS_VAL8(n) BS_VAL16(n##n) argument
48 #define BS_SHL(a, n) _mm_slli_epi64(a, n) argument
49 #define BS_SHR(a, n) _mm_srli_epi64(a, n) argument
50 #define BS_SHL8(a, n) _mm_slli_si128(a, n) argument
51 #define BS_SHR8(a, n) _mm_srli_si128(a, n) argument
53 #define BS_EXTRACT8(a, n) ((uint8_t*)&(a))[n] argument
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| D | dvbcsa_bs_neon.h | 34 #define BS_VAL(n, m) vreinterpretq_u32_u64(vcombine_u64(vcreate_u64(m), vcreate_u64(n))) argument
35 #define BS_VAL64(n) vreinterpretq_u32_u64(vdupq_n_u64(0x##n##ULL)) argument
36 #define BS_VAL32(n) vdupq_n_u32(0x##n##UL) argument
37 #define BS_VAL16(n) BS_VAL32(n##n) argument
38 #define BS_VAL8(n) BS_VAL16(n##n) argument
45 #define BS_SHL(a, n) vreinterpretq_u32_u64(vshlq_n_u64 (vreinterpretq_u64_u32(a), n)) argument
46 #define BS_SHR(a, n) vreinterpretq_u32_u64(vshrq_n_u64 (vreinterpretq_u64_u32(a), n)) argument
47 #define BS_SHL8(a, n) (n == 1 ? vreinterpretq_u32_u8(vrev16q_u8(vreinterpretq_u8_u32(a))) : ( \ argument
50 #define BS_SHR8(a, n) BS_SHL8(a, n) argument
52 #define BS_EXTRACT8(a, n) ((uint8_t*)&(a))[n] argument
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| /device/soc/esp/esp32/components/xtensa/ |
| D | stdatomic.c | 40 #define ATOMIC_EXCHANGE(n, type) type __atomic_exchange_ ## n (type* mem, type val, int memorder) \ argument
49 #define CMP_EXCHANGE(n, type) bool __atomic_compare_exchange_ ## n (type* mem, type* expect, type d… argument
63 #define FETCH_ADD(n, type) type __atomic_fetch_add_ ## n (type* ptr, type value, int memorder) \ argument
72 #define FETCH_SUB(n, type) type __atomic_fetch_sub_ ## n (type* ptr, type value, int memorder) \ argument
81 #define FETCH_AND(n, type) type __atomic_fetch_and_ ## n (type* ptr, type value, int memorder) \ argument
90 #define FETCH_OR(n, type) type __atomic_fetch_or_ ## n (type* ptr, type value, int memorder) \ argument
99 #define FETCH_XOR(n, type) type __atomic_fetch_xor_ ## n (type* ptr, type value, int memorder) \ argument
108 #define SYNC_FETCH_OP(op, n, type) type __sync_fetch_and_ ## op ##_ ## n (type* ptr, type value, ..… argument
113 #define SYNC_BOOL_CMP_EXCHANGE(n, type) bool __sync_bool_compare_and_swap_ ## n (type *ptr, type … argument
125 #define SYNC_VAL_CMP_EXCHANGE(n, type) type __sync_val_compare_and_swap_ ## n (type *ptr, type ol… argument
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