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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx-pinctrl.txt7 different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
[all …]
Datmel,at91-pinctrl.txt7 different PAD settings (like pull up, keeper, etc) the controller controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
[all …]
Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic pin multiplexing node schema
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
[all …]
Dfsl,imx7d-pinctrl.txt3 iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar
4 as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low
5 power state retention capabilities on gpios that are part of iomuxc-lpsr
6 (GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for
7 mux and pad control settings, it shares the input select register from main
8 iomuxc controller for daisy chain settings, the fsl,input-sel property extends
9 fsl,imx-pinctrl driver to support iomuxc-lpsr controller.
11 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
12 compatible = "fsl,imx7d-iomuxc-lpsr";
14 fsl,input-sel = <&iomuxc>;
[all …]
Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
[all …]
Dfsl,imx7ulp-pinctrl.txt8 supports generic pin config.
10 Please refer to fsl,imx-pinctrl.txt in this directory for common binding
14 - compatible: "fsl,imx7ulp-iomuxc1".
15 - fsl,pins: Each entry consists of 5 integers which represents the mux
16 and config setting for one pin. The first 4 integers
19 imx7ulp-pinfunc.h in the device tree source folder.
21 pull-up on this pin.
24 CONFIG settings.
39 #include "imx7ulp-pinfunc.h"
41 /* Pin Controller Node */
[all …]
Dcirrus,madera.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
30 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
33 pinctrl-0:
38 pinctrl-names:
43 pin-settings:
45 One subnode is required to contain the default settings. It
47 each group or pin configuration you want to apply as a default.
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/mvebu/
Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
31 * @pid: first pin id handled by this control
38 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
40 * between two or more different settings, e.g. assign mpp pin 13 to
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
[all …]
Dpinctrl-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
24 #include "pinctrl-mvebu.h"
40 struct mvebu_mpp_ctrl_setting *settings; member
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
88 pid < pctl->groups[n].pins[0] + in mvebu_pinctrl_find_group_by_pid()
[all …]
/kernel/linux/linux-5.10/Documentation/arm/pxa/
Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
14 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
18 detection of each pin. Below is a diagram of internal connections between
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
13 #include <linux/radix-tree.h>
20 * struct pinctrl_dev - pin control class device
21 * @node: node to include this pin controller in the global pin controller list
22 * @desc: the pin controller descriptor supplied when initializing this pin
24 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
26 * @pin_group_tree: optionally each pin group can be stored in this radix tree
[all …]
Dpinctrl-single.c2 * Generic device tree based pinctrl driver for one register per pin
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
87 * @conf: array of pin configurations
88 * @nconfs: number of pin configurations available
[all …]
Dpinconf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin config portions of the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
27 const struct pinconf_ops *ops = pctldev->desc->confops; in pinconf_check_ops()
30 if (!ops->pin_config_set && !ops->pin_config_group_set) { in pinconf_check_ops()
31 dev_err(pctldev->dev, in pinconf_check_ops()
33 return -EINVAL; in pinconf_check_ops()
40 if (!map->data.configs.group_or_pin) { in pinconf_validate_map()
41 pr_err("failed to register map %s (%d): no group/pin given\n", in pinconf_validate_map()
[all …]
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
31 #include <asm-generic/gpio.h>
51 /* Global list of pin control devices (struct pinctrl_dev) */
54 /* List of pin controller handles (struct pinctrl) */
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
[all …]
/kernel/linux/linux-5.10/include/linux/ssb/
Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
210 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
214 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dgpio-cfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * S3C Platform - GPIO pin configuration
12 * pin configuration done such as setting a pin to input or output or
13 * changing the pull-{up,down} configurations.
27 /* forward declaration if gpio-core.h hasn't been included */
41 * per-bank configuration information that other systems such as the
64 /* Defines for generic pin configurations */
73 * s3c_gpio_cfgpin() - Change the GPIO function of a pin.
74 * @pin pin The pin number to configure.
75 * @to to The configuration for the pin's function.
[all …]
Dpm-s3c24xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2004-2006 Simtec Electronics
6 // S3C24XX Power Manager (Suspend-To-RAM) support
8 // See Documentation/arm/samsung-s3c24xx/suspend.rst for more information
10 // Parts based on arch/arm/mach-pxa/pm.c
24 #include "regs-clock.h"
25 #include "regs-gpio.h"
26 #include "regs-irq.h"
27 #include "gpio-samsung.h"
31 #include "gpio-cfg.h"
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tilcdc/
Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
Dsmu9_driver_if.h46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47 #define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48 #define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53 #define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
65 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
141 /* External Component Communication Settings */
[all …]
/kernel/linux/linux-5.10/Documentation/driver-api/
Dpinctl.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Top-level interface
20 Definition of PIN CONTROLLER:
22 - A pin controller is a piece of hardware, usually a set of registers, that
26 Definition of PIN:
[all …]
/kernel/linux/linux-5.10/drivers/hwmon/
Dabituguru3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2008 Hans de Goede <hdegoede@redhat.com>
11 * only reading the sensors and their settings is supported.
25 #include <linux/hwmon-sysfs.h>
55 * cpu-speed independent, since the ISA-bus and not the CPU should be the
96 (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
104 /* Two i/o-ports are used by uGuru */
111 * of the DATA register (0-255) on failure.
113 #define ABIT_UGURU3_SUCCESS -1
135 /* + 1 -> end of sensors indicated by a sensor with name == NULL */
[all …]
/kernel/linux/linux-5.10/arch/arm/plat-pxa/
Dmfp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/plat-pxa/mfp.c
5 * Multi-Function Pin Support
9 * 2007-08-21: eric miao <eric.miao@marvell.com>
42 * Table that determines the low power modes outputs, with actual settings
43 * used in parentheses for don't-care values. Except for the float output,
45 * non-LPM pulled output, the same configuration could probably be used.
66 * The pullup and pulldown state of the MFP pin at run mode is by default
85 * (most likely a read-modify-write operation) is atomic, and that
93 unsigned long config; /* -1 for not configured */
[all …]
/kernel/linux/linux-5.10/drivers/media/rc/
Dnuvoton-cir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
18 #define NVT_DRIVER_NAME "nuvoton-cir"
71 /* hardware I/O settings */
91 /* CIR settings */
117 /* CIR IRCON settings */
134 /* CIR IRSTS settings */
144 /* CIR IREN settings */
154 /* CIR FIFOCON settings */
177 /* CIR IRFIFOSTS settings */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/input/touchscreen/
Dsis_i2c.txt4 - compatible: must be "sis,9200-ts"
5 - reg: i2c slave address
6 - interrupts: touch controller interrupt (see interrupt
10 - pinctrl-names: should be "default" (see pinctrl binding [1]).
11 - pinctrl-0: a phandle pointing to the pin settings for the
13 - attn-gpios: the gpio pin used as attention line
14 - reset-gpios: the gpio pin used to reset the controller
15 - wakeup-source: touchscreen can be used as a wakeup source
17 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
18 [1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Duda1334.txt3 This device uses simple GPIO pins for controlling codec settings.
7 - compatible : "nxp,uda1334"
8 - nxp,mute-gpios: a GPIO spec for the MUTE pin.
9 - nxp,deemph-gpios: a GPIO spec for the De-emphasis pin
13 uda1334: audio-codec {
15 nxp,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
16 nxp,deemph-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;

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