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Searched refs:HiethWritelBits (Results 1 – 6 of 6) sorted by relevance

/device/soc/hisilicon/common/platform/hieth-sf/adapter/
Dhieth_mac.c52 HiethWritelBits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_ALL); in HiethPortReset()
54 HiethWritelBits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_ALL); in HiethPortReset()
56 HiethWritelBits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_ALL); in HiethPortReset()
58 HiethWritelBits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_ALL); in HiethPortReset()
61 HiethWritelBits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); in HiethPortReset()
63 HiethWritelBits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); in HiethPortReset()
65 HiethWritelBits(ld, 1, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); in HiethPortReset()
67 HiethWritelBits(ld, 0, GLB_SOFT_RESET, BITS_ETH_SOFT_RESET_DOWN); in HiethPortReset()
86 HiethWritelBits(ld, 0, GLB_RW_IRQ_ENA, UD_BIT_NAME(BITS_IRQS_ENA)); in HiethPortInit()
91 HiethWritelBits(ld, 1, UD_REG_NAME(GLB_TSO_DBG_EN), BITS_TSO_DBG_EN); in HiethPortInit()
[all …]
/device/soc/hisilicon/common/platform/hieth-sf/src/
Deth_mac.c29 HiethWritelBits(ld, mode, UD_REG_NAME(MAC_PORTSET), BITS_MACSTAT); in SetLinkStat()
38 HiethWritelBits(ld, mode, UD_REG_NAME(MAC_PORTSEL), BITS_NEGMODE); in SetNegMode()
63 HiethWritelBits(ld, cnt, UD_REG_NAME(MAC_TX_IPGCTRL), BITS_PRE_CNT_LIMIT); in HiethSetMacLeadcodeCntLimit()
80 HiethWritelBits(ld, nbits, UD_REG_NAME(MAC_TX_IPGCTRL), BITS_IPG); in HiethSetMacTransIntervalBits()
96 HiethWritelBits(ld, para, UD_REG_NAME(MAC_TX_IPGCTRL), BITS_FC_INTER); in HiethSetMacFcInterval()
126 HiethWritelBits(ld, mode, UD_REG_NAME(MAC_PORTSEL), BITS_MII_MODE); in HiethSetMiiMode()
133 HiethWritelBits(ld, cnt, UD_REG_NAME(MAC_SET), BITS_LEN_MAX); in HiethSetRcvLenMax()
Dctrl.c105 HiethWritelBits(ld, drop, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_IPHDR_DROP); in HiethEnableRxcsumDrop()
106 HiethWritelBits(ld, false, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_PAYLOAD_DROP); in HiethEnableRxcsumDrop()
107 HiethWritelBits(ld, drop, UD_REG_NAME(GLB_RX_COE_CTRL), BITS_COE_IPV6_UDP_ZERO_DROP); in HiethEnableRxcsumDrop()
178 HiethWritelBits(ld, 1, GLB_DN_HOSTMAC_ENA, BITS_DN_HOST_ENA); in HiethHwSetMacAddress()
267 HiethWritelBits(ld, mode, GLB_ENDIAN_MOD, BITS_ENDIAN); in HiethSetEndianMode()
278 HiethWritelBits(ld, ld->depth.hwXmitq, UD_REG_NAME(GLB_QLEN_SET), BITS_TXQ_DEP); in HiethSetHwqDepth()
279 …HiethWritelBits(ld, HIETH_MAX_QUEUE_DEPTH - ld->depth.hwXmitq, UD_REG_NAME(GLB_QLEN_SET), BITS_RXQ… in HiethSetHwqDepth()
Dinterface.c273 HiethWritelBits(ld, 0, GLB_RW_IRQ_ENA, BITS_IRQS_ENA_ALLPORT); in HiethDeliver()
323 HiethWritelBits(ld, 1, GLB_RW_IRQ_ENA, BITS_IRQS_ENA_ALLPORT); in HiethDeliver()
557 HiethWritelBits(ld, 1, GLB_RW_IRQ_ENA, UD_BIT_NAME(BITS_IRQS_ENA)); in RegisterHiethData()
558 HiethWritelBits(ld, 1, GLB_RW_IRQ_ENA, BITS_IRQS_ENA_ALLPORT); in RegisterHiethData()
/device/soc/hisilicon/common/platform/hieth-sf/include/internal/
Dhieth_pri.h130 #define HiethWritelBits(ld, v, ofs, bits_desc) \ macro
Dctrl.h285 HiethWritelBits(ld, (len), UD_REG_NAME(GLB_EQFRM_LEN), BITS_TXINQ_LEN); \