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Searched refs:SOC_CPU_CORES_NUM (Results 1 – 15 of 15) sorted by relevance

/device/soc/esp/esp32/components/hal/esp32/include/hal/
Dsoc_ll.h27 …const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
28 …const int rtc_cntl_c1_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_S, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
29 …const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
30 …const int rtc_cntl_c0_s[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_S, RTC_CNTL_SW_STALL_APP… in soc_ll_stall_core()
40 …const int rtc_cntl_c1_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C1_M, RTC_CNTL_SW_STALL_APP… in soc_ll_unstall_core()
41 …const int rtc_cntl_c0_m[SOC_CPU_CORES_NUM] = {RTC_CNTL_SW_STALL_PROCPU_C0_M, RTC_CNTL_SW_STALL_APP… in soc_ll_unstall_core()
/device/soc/esp/esp32/components/esp_system/
Dstartup.c80 #if !(SOC_CPU_CORES_NUM > 1) && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
107 static volatile bool s_system_inited[SOC_CPU_CORES_NUM] = { false };
109 const sys_startup_fn_t g_startup_fn[SOC_CPU_CORES_NUM] = { [0] = start_cpu0,
110 #if SOC_CPU_CORES_NUM > 1
111 [1 ... SOC_CPU_CORES_NUM - 1] = start_cpu_other_cores
360 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in do_secondary_init()
415 #if SOC_CPU_CORES_NUM > 1 && !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE in start_cpu0_default()
Dintr_alloc.c104 static uint32_t non_iram_int_mask[SOC_CPU_CORES_NUM];
107 static uint32_t non_iram_int_disabled[SOC_CPU_CORES_NUM];
108 static bool non_iram_int_disabled_flag[SOC_CPU_CORES_NUM];
197 if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG; in esp_intr_mark_shared()
215 if (cpu>=SOC_CPU_CORES_NUM) return ESP_ERR_INVALID_ARG; in esp_intr_reserve()
/device/soc/esp/esp32/components/esp_system/port/
Dcpu_start.c125 static volatile bool s_cpu_up[SOC_CPU_CORES_NUM] = { false };
126 static volatile bool s_cpu_inited[SOC_CPU_CORES_NUM] = { false };
228 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in start_other_core()
254 RESET_REASON rst_reas[SOC_CPU_CORES_NUM]; in call_start_cpu0()
372 #if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors in call_start_cpu0()
526 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) { in call_start_cpu0()
Dpanic_handler.c59 void *g_exc_frames[SOC_CPU_CORES_NUM] = {NULL};
101 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
/device/soc/esp/esp32/components/hal/include/hal/
Dsoc_hal.h30 #if SOC_CPU_CORES_NUM > 1
33 … for (uint32_t i = 0, cur = cpu_hal_get_core_id(); i < SOC_CPU_CORES_NUM; i++) { \
Dinterrupt_controller_types.h39 int_desc_flag_t cpuflags[SOC_CPU_CORES_NUM];
/device/soc/esp/esp32/components/esp_hw_support/
Dcpu_util.c33 #if SOC_CPU_CORES_NUM > 1 in esp_cpu_stall()
40 #if SOC_CPU_CORES_NUM > 1 in esp_cpu_unstall()
/device/soc/esp/esp32/components/hal/
Dsoc_hal.c26 #if SOC_CPU_CORES_NUM > 1
/device/soc/esp/esp32/components/soc/include/soc/
Ddedic_gpio_periph.h33 } cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix
/device/soc/esp/esp32/components/esp_system/include/esp_private/
Dstartup_internal.h36 extern sys_startup_fn_t const g_startup_fn[SOC_CPU_CORES_NUM];
Dpanic_internal.h31 extern void *g_exc_frames[SOC_CPU_CORES_NUM];
/device/soc/esp/esp32/components/newlib/
Dabort.c29 _Static_assert(SOC_CPU_CORES_NUM < 10, "abort() assumes number of cores is 1 to 9"); in abort()
/device/soc/esp/esp32/components/soc/esp32/include/soc/
Dsoc_caps.h73 #define SOC_CPU_CORES_NUM 2 macro
/device/soc/esp/esp32/components/driver/
Ddedic_gpio.c55 static dedic_gpio_platform_t *s_platform[SOC_CPU_CORES_NUM];
57 static _lock_t s_platform_mutexlock[SOC_CPU_CORES_NUM];