1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <stdlib.h>
15
16 #include "esp_spi_flash.h"
17
18 #include "esp_private/system_internal.h"
19
20 #include "soc/soc_memory_layout.h"
21 #include "soc/cpu.h"
22 #include "soc/soc_caps.h"
23 #include "soc/rtc.h"
24
25 #include "hal/soc_hal.h"
26 #include "hal/cpu_hal.h"
27
28 #include "sdkconfig.h"
29 #include "esp_rom_sys.h"
30
31 #if CONFIG_IDF_TARGET_ESP32
32 #include "esp32/dport_access.h"
33 #include "esp32/cache_err_int.h"
34 #elif CONFIG_IDF_TARGET_ESP32S2
35 #include "esp32s2/memprot.h"
36 #include "esp32s2/cache_err_int.h"
37 #elif CONFIG_IDF_TARGET_ESP32S3
38 #include "esp32s3/memprot.h"
39 #include "esp32s3/cache_err_int.h"
40 #elif CONFIG_IDF_TARGET_ESP32C3
41 #include "esp32c3/memprot.h"
42 #include "esp32c3/cache_err_int.h"
43 #endif
44
45 #include "esp_private/panic_internal.h"
46 #include "esp_private/panic_reason.h"
47
48 #include "hal/wdt_types.h"
49 #include "hal/wdt_hal.h"
50
51 extern int _invalid_pc_placeholder;
52
53 extern void esp_panic_handler_reconfigure_wdts(void);
54
55 extern void esp_panic_handler(panic_info_t *);
56
57 static wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
58
59 void *g_exc_frames[SOC_CPU_CORES_NUM] = {NULL};
60
61 /*
62 Panic handlers; these get called when an unhandled exception occurs or the assembly-level
63 task switching / interrupt code runs into an unrecoverable error. The default task stack
64 overflow handler and abort handler are also in here.
65 */
66
67 /*
68 Note: The linker script will put everything in this file in IRAM/DRAM, so it also works with flash cache disabled.
69 */
print_state_for_core(const void * f,int core)70 static void print_state_for_core(const void *f, int core)
71 {
72 /* On Xtensa (with Window ABI), register dump is not required for backtracing.
73 * Don't print it on abort to reduce clutter.
74 * On other architectures, register values need to be known for backtracing.
75 */
76 #if defined(__XTENSA__) && defined(XCHAL_HAVE_WINDOWED)
77 if (!g_panic_abort) {
78 #else
79 if (true) {
80 #endif
81 panic_print_registers(f, core);
82 panic_print_str("\r\n");
83 }
84 panic_print_backtrace(f, core);
85 }
86
87 static void print_state(const void *f)
88 {
89 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
90 int err_core = f == g_exc_frames[0] ? 0 : 1;
91 #else
92 int err_core = 0;
93 #endif
94
95 print_state_for_core(f, err_core);
96
97 panic_print_str("\r\n");
98
99 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
100 // If there are other frame info, print them as well
101 for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
102 // `f` is the frame for the offending core, see note above.
103 if (err_core != i && g_exc_frames[i] != NULL) {
104 print_state_for_core(g_exc_frames[i], i);
105 panic_print_str("\r\n");
106 }
107 }
108 #endif
109 }
110
111 static void frame_to_panic_info(void *frame, panic_info_t *info, bool pseudo_excause)
112 {
113 info->core = cpu_hal_get_core_id();
114 info->exception = PANIC_EXCEPTION_FAULT;
115 info->details = NULL;
116 info->reason = "Unknown";
117 info->pseudo_excause = pseudo_excause;
118
119 if (pseudo_excause) {
120 panic_soc_fill_info(frame, info);
121 } else {
122 panic_arch_fill_info(frame, info);
123 }
124
125 info->state = print_state;
126 info->frame = frame;
127 }
128
129 static void panic_handler(void *frame, bool pseudo_excause)
130 {
131 panic_info_t info = { 0 };
132
133 /*
134 * Setup environment and perform necessary architecture/chip specific
135 * steps here prior to the system panic handler.
136 * */
137 int core_id = cpu_hal_get_core_id();
138
139 // If multiple cores arrive at panic handler, save frames for all of them
140 g_exc_frames[core_id] = frame;
141
142 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
143 // These are cases where both CPUs both go into panic handler. The following code ensures
144 // only one core proceeds to the system panic handler.
145 if (pseudo_excause) {
146 #define BUSY_WAIT_IF_TRUE(b) { if (b) while(1); }
147 // For WDT expiry, pause the non-offending core - offending core handles panic
148 BUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0 && core_id == 1);
149 BUSY_WAIT_IF_TRUE(panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1 && core_id == 0);
150
151 // For cache error, pause the non-offending core - offending core handles panic
152 if (panic_get_cause(frame) == PANIC_RSN_CACHEERR && core_id != esp_cache_err_get_cpuid()) {
153 // Only print the backtrace for the offending core in case of the cache error
154 g_exc_frames[core_id] = NULL;
155 while (1) {
156 ;
157 }
158 }
159 }
160
161 // Need to reconfigure WDTs before we stall any other CPU
162 esp_panic_handler_reconfigure_wdts();
163
164 esp_rom_delay_us(1);
165 SOC_HAL_STALL_OTHER_CORES();
166 #endif
167
168 #if CONFIG_IDF_TARGET_ESP32
169 esp_dport_access_int_abort();
170 #endif
171
172 #if !CONFIG_ESP_PANIC_HANDLER_IRAM
173 // Re-enable CPU cache for current CPU if it was disabled
174 if (!spi_flash_cache_enabled()) {
175 spi_flash_enable_cache(core_id);
176 panic_print_str("Re-enable cpu cache.\r\n");
177 }
178 #endif
179
180 if (esp_cpu_in_ocd_debug_mode()) {
181 #if __XTENSA__
182 if (!(esp_ptr_executable(cpu_ll_pc_to_ptr(panic_get_address(frame))) && (panic_get_address(frame) & 0xC0000000U))) {
183 /* Xtensa ABI sets the 2 MSBs of the PC according to the windowed call size
184 * Incase the PC is invalid, GDB will fail to translate addresses to function names
185 * Hence replacing the PC to a placeholder address in case of invalid PC
186 */
187 panic_set_address(frame, (uint32_t)&_invalid_pc_placeholder);
188 }
189 #endif
190 if (panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU0
191 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
192 || panic_get_cause(frame) == PANIC_RSN_INTWDT_CPU1
193 #endif
194 ) {
195 wdt_hal_write_protect_disable(&wdt0_context);
196 wdt_hal_handle_intr(&wdt0_context);
197 wdt_hal_write_protect_enable(&wdt0_context);
198 }
199 }
200
201 // Convert architecture exception frame into abstracted panic info
202 frame_to_panic_info(frame, &info, pseudo_excause);
203
204 // Call the system panic handler
205 esp_panic_handler(&info);
206 }
207
208 void panicHandler(void *frame)
209 {
210 // This panic handler gets called for when the double exception vector,
211 // kernel exception vector gets used; as well as handling interrupt-based
212 // faults cache error, wdt expiry. EXCAUSE register gets written with
213 // one of PANIC_RSN_* values.
214 panic_handler(frame, true);
215 }
216
217 void xt_unhandled_exception(void *frame)
218 {
219 panic_handler(frame, false);
220 }
221
222 void __attribute__((noreturn)) panic_restart(void)
223 {
224 bool digital_reset_needed = false;
225 #ifdef CONFIG_IDF_TARGET_ESP32
226 // On the ESP32, cache error status can only be cleared by system reset
227 if (esp_cache_err_get_cpuid() != -1) {
228 digital_reset_needed = true;
229 }
230 #endif
231 #if CONFIG_ESP_SYSTEM_CONFIG_MEMPROT_FEATURE
232 if (esp_memprot_is_intr_ena_any() || esp_memprot_is_locked_any()) {
233 digital_reset_needed = true;
234 }
235 #endif
236 if (digital_reset_needed) {
237 esp_restart_noos_dig();
238 }
239 esp_restart_noos();
240 }
241