| /device/soc/asrmicro/asr582x/liteos_m/sdk/drivers/driver/inc/ |
| D | duet.h | 81 __I uint32_t rsv0 : 1;
83 __I uint32_t rsv1 : 14;
89 __I uint32_t REG_0C;
90 __I uint32_t REG_10;
105 __I uint32_t REG_28;
109 __I uint32_t REG_38;
110 __I uint32_t REG_3C;
169 __I uint32_t rsv7 : 4;
187 __I uint32_t REG_AC;
243 __I uint32_t STAT;
[all …]
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/ |
| D | reg_uart.h | 24 __I uint32_t UARTRSR; // 0x004
28 __I uint32_t UARTFR; // 0x018
37 __I uint32_t UARTRIS; // 0x03C
38 __I uint32_t UARTMIS; // 0x040
45 __I uint32_t UARTPID0; // 0xFE0
46 __I uint32_t UARTPID1; // 0xFE4
47 __I uint32_t UARTPID2; // 0xFE8
48 __I uint32_t UARTPID3; // 0xFEC
49 __I uint32_t UARTPCID0; // 0xFF0
50 __I uint32_t UARTPCID1; // 0xFF4
[all …]
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| D | reg_dma.h | 51 __I uint32_t INTSTAT; // 0x000 DMA Interrupt Status Register
52 …__I uint32_t INTTCSTAT; // 0x004 DMA Interrupt Terminal Count Request Status Regis…
54 __I uint32_t INTERRSTAT; // 0x00C DMA Interrupt Error Status Register
56 … __I uint32_t RAWINTTCSTAT; // 0x014 DMA Raw Interrupt Terminal Count Status Register
57 __I uint32_t RAWINTERRSTAT; // 0x018 DMA Raw Error Interrupt Status Register
58 __I uint32_t ENBLDCHNS; // 0x01C DMA Enabled Channel Register
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| D | reg_timer.h | 26 __I uint32_t Value; /* Offset: 0x004 (R/ ) Timer X Counter Current Value */
29 __I uint32_t RIS; /* Offset: 0x010 (R/ ) Timer X Raw Interrupt Status */
30 __I uint32_t MIS; /* Offset: 0x014 (R/ ) Timer X Masked Interrupt Status */
36 __I uint32_t ElapsedVal;
|
| D | reg_gpio_v1.h | 35 __I uint32_t GPIO_INTSTATUS; // 0x40
36 __I uint32_t GPIO_RAW_INTSTATUS; // 0x44
39 __I uint32_t GPIO_EXT_PORT[HAL_GPIO_PORT_NUM]; // 0x50
40 __I uint32_t GPIO_EXT_PORT_reserved[3];
|
| D | reg_ir.h | 21 __I uint32_t RX_DATA; //0x00
33 __I uint32_t INT_STATUS; //0x30
34 __I uint32_t TXRX_STATUS; //0x34
35 __I uint32_t FIFO_STATUS; //0x38
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| D | reg_spi.h | 25 __I uint32_t SSPSR; //0x0000000C
28 __I uint32_t SSPRIS; //0x00000018
29 __I uint32_t SSPMIS; //0x0000001C
|
| D | plat_types.h | 91 #ifndef __I
93 #define __I volatile /*!< Defines 'read only' permissions */ macro
95 #define __I volatile const /*!< Defines 'read only' permissions */ macro
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| D | reg_pwm.h | 23 __I uint32_t ID; // 0x000
|
| /device/soc/rockchip/rk2206/hardware/lib/CMSIS/Device/RK2206/Include/ |
| D | rk2206.h | 30 __I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */
39 __I uint32_t CCVR; /* Address Offset: 0x0008 */
41 __I uint32_t STAT; /* Address Offset: 0x0010 */
42 __I uint32_t EOI; /* Address Offset: 0x0014 */
54 __I uint32_t FCNT; /* Address Offset: 0x0020 */
59 __I uint32_t RXDATA[8]; /* Address Offset: 0x0200 */
60 __I uint32_t ST; /* Address Offset: 0x0220 */
66 __I uint32_t RBR; /* Address Offset: 0x0000 */
75 __I uint32_t IIR; /* Address Offset: 0x0008 */
80 __I uint32_t LSR; /* Address Offset: 0x0014 */
[all …]
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| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/dma/ |
| D | reg_dma.h | 26 __I uint32_t RESERVED0[6]; /* 0x000 (R) : Reserved */
27 __I uint32_t RSR; /* 0x018 (R) : Req St Reg */
28 __I uint32_t RESERVED1[1017]; /* 0x01C (R) : Reserved */
48 __I uint32_t RESERVED3[800]; /* 0x380 (R) : Reserved */
51 __I uint32_t RESERVED4[40]; /* 0x060 (R) : Reserved */
54 __I uint32_t RDMR; /* 0x100 (R) : Rd Mon Reg */
55 __I uint32_t WRMR; /* 0x104 (R) : Wr Mon Reg */
58 __I uint32_t RESERVED5[36]; /* 0x170 (R) : Reserved */
85 __I uint32_t RESERVED0[3]; /* 0x090 (R) : */
87 __I uint32_t RESERVED1[6]; /* 0x0A0 (R) : */
|
| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/gpio/ |
| D | reg_gpio.h | 31 __I uint32_t RESERVED0; /* 0x01C (R) : Reserved */
32 __I uint32_t ISR; /* 0x020 (R) : Int Stat Reg */
|
| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/cs1000lite_regs/ |
| D | cs1000Lite_gpio.h | 33 __I uint32_t RESERVED0; /* 0x01C (R) : Reserved */
34 __I uint32_t ISR; /* 0x020 (R) : Int Stat Reg */
|
| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/cs1000aud_regs/ |
| D | cs1000Aud_gpio.h | 33 __I uint32_t RESERVED0; /* 0x01C (R) : Reserved */
34 __I uint32_t ISR; /* 0x020 (R) : Int Stat Reg */
|
| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/arch/riscv/include/ |
| D | mcu_ip.h | 35 #define __I volatile const /* 'read only' permissions */ macro
56 __I unsigned int SYSTEMVER; /* 0x00 SYSTEM ID and Revision Register */
|
| /device/soc/winnermicro/wm800/board/include/driver/ |
| D | wm_i2c.h | 43 __I uint32_t TXR;
44 __I uint32_t CR;
|
| D | wm_i2s.h | 34 __I uint32_t INT_STATUS;
36 __I uint32_t RX;
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| /device/soc/chipsea/cst85/liteos_m/sdk/bsp/driver/ticker/ |
| D | reg_timer.h | 32 __I uint32_t IS; /* 0x01C: Interrupt Status */
40 __I uint32_t IS; /* 0x00C: Interrupt Status */
|
| /device/soc/hpmicro/sdk/hpm_sdk/drivers/inc/ |
| D | hpm_common.h | 29 #ifndef __I
30 #define __I __R macro
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/cmsis/inc/ |
| D | core_cm0.h | 160 #define __I volatile /*!< Defines 'read only' permissions */ macro
162 #define __I volatile const /*!< Defines 'read only' permissions */
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| D | core_cm1.h | 160 #define __I volatile /*!< Defines 'read only' permissions */ macro
162 #define __I volatile const /*!< Defines 'read only' permissions */
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| D | core_sc000.h | 170 #define __I volatile /*!< Defines 'read only' permissions */ macro
172 #define __I volatile const /*!< Defines 'read only' permissions */
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| D | core_cm0plus.h | 170 #define __I volatile /*!< Defines 'read only' permissions */ macro
172 #define __I volatile const /*!< Defines 'read only' permissions */
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| /device/soc/bestechnic/bes2600/liteos_m/sdk/bsp/platform/hal/best2003/ |
| D | reg_aoncmu_best2003.h | 21 __I uint32_t CHIP_ID; // 0x00
31 __I uint32_t MEMSC_STATUS; // 0x34
|
| /device/soc/winnermicro/wm800/board/include/ |
| D | wm_regs.h | 76 #define __I volatile /*!< Defines 'read only' permissions */ macro
78 #define __I volatile const /*!< Defines 'read only' permissions */ macro
|