1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef _REG_TIMER_H_ 16 #define _REG_TIMER_H_ 17 18 #include "chip.h" 19 20 /** 21 * Timer registers 22 */ 23 typedef struct { 24 struct { 25 __IO uint32_t CTL; /* 0x000: Control */ 26 __IO uint32_t TC; /* 0x004: Timer Counter */ 27 __IO uint32_t PR; /* 0x008: Prescale */ 28 __IO uint32_t PC; /* 0x00C: Prescale Counter */ 29 __IO uint32_t MR; /* 0x010: Match Register */ 30 __IO uint32_t TD; /* 0x014: Tick Divider */ 31 __IO uint32_t IC; /* 0x018: Interrupt Control */ 32 __I uint32_t IS; /* 0x01C: Interrupt Status */ 33 } TMR[3]; 34 } CS_TIM_TypeDef; 35 36 typedef struct { 37 __IO uint32_t CTL; /* 0x000: Control */ 38 __IO uint32_t TD; /* 0x004: Tick Divider */ 39 __IO uint32_t IC; /* 0x008: Interrupt Control */ 40 __I uint32_t IS; /* 0x00C: Interrupt Status */ 41 __IO uint32_t TCL; /* 0x010: Timer Counter low-32bit */ 42 __IO uint32_t TCH; /* 0x014: Timer Counter high-16bit */ 43 uint32_t RESERVED0[2U]; 44 struct { 45 __IO uint32_t L; /* 0x020: Match Register low-32bit */ 46 __IO uint32_t H; /* 0x024: Match Register high-16bit */ 47 } MR[4]; 48 } CS_AONTIM_TypeDef; 49 50 /** 51 * Timer Peripherals 52 */ 53 static CS_TIM_TypeDef * const CS_TIM0 = ((CS_TIM_TypeDef *)CS_TIM0_BASE); 54 static CS_TIM_TypeDef * const CS_TIM1 = ((CS_TIM_TypeDef *)CS_TIM1_BASE); 55 static CS_AONTIM_TypeDef * const CS_TIM2 = ((CS_AONTIM_TypeDef *)CS_TIM2_BASE); 56 57 #endif /* _REG_TIMER_H_ */ 58