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/device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/
Drtmx_eink.c111 unsigned int base;
114 base = sel ? (de_base + RTMX1_BASE) : (de_base + RTMX0_BASE);
226 de_writel(base + 0x00000, 0x00000000);
227 de_writel(base + 0x01000, 0x00000100);
228 de_writel(base + 0x01004, 0x00000000);
229 de_writel(base + 0x01008, ((outh - 1) << 16) | (outw - 1));
230 de_writel(base + 0x0100c, 0x00000000);
231 de_writel(base + 0x01010, 0x00000000);
232 de_writel(base + 0x01014, 0x00000000);
233 de_writel(base + 0x01018, 0x00000000);
[all …]
/device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/v4l2_dev/inc/isp/
Dacamera_isp1_config.h57 static __inline void acamera_isp_top_active_width_write(uintptr_t base, uint16_t data) { in acamera_isp_top_active_width_write() argument
58 uint32_t curr = system_sw_read_32(base + 0x18e88L); in acamera_isp_top_active_width_write()
59 system_sw_write_32(base + 0x18e88L, (((uint32_t) (data & 0xffff)) << 0) | (curr & 0xffff0000)); in acamera_isp_top_active_width_write()
61 static __inline uint16_t acamera_isp_top_active_width_read(uintptr_t base) { in acamera_isp_top_active_width_read() argument
62 return (uint16_t)((system_sw_read_32(base + 0x18e88L) & 0xffff) >> 0); in acamera_isp_top_active_width_read()
78 static __inline void acamera_isp_top_active_height_write(uintptr_t base, uint16_t data) { in acamera_isp_top_active_height_write() argument
79 uint32_t curr = system_sw_read_32(base + 0x18e88L); in acamera_isp_top_active_height_write()
80 system_sw_write_32(base + 0x18e88L, (((uint32_t) (data & 0xffff)) << 16) | (curr & 0xffff)); in acamera_isp_top_active_height_write()
82 static __inline uint16_t acamera_isp_top_active_height_read(uintptr_t base) { in acamera_isp_top_active_height_read() argument
83 return (uint16_t)((system_sw_read_32(base + 0x18e88L) & 0xffff0000) >> 16); in acamera_isp_top_active_height_read()
[all …]
Dacamera_fpga_config.h57 static __inline void acamera_fpga_fpga_gdc_axi_write_waddr_39_32_write(uintptr_t base, uint8_t data… in acamera_fpga_fpga_gdc_axi_write_waddr_39_32_write() argument
61 static __inline uint8_t acamera_fpga_fpga_gdc_axi_write_waddr_39_32_read(uintptr_t base) { in acamera_fpga_fpga_gdc_axi_write_waddr_39_32_read() argument
78 static __inline void acamera_fpga_fpga_gdc_axi_read_raddr_39_32_write(uintptr_t base, uint8_t data)… in acamera_fpga_fpga_gdc_axi_read_raddr_39_32_write() argument
82 static __inline uint8_t acamera_fpga_fpga_gdc_axi_read_raddr_39_32_read(uintptr_t base) { in acamera_fpga_fpga_gdc_axi_read_raddr_39_32_read() argument
99 static __inline void acamera_fpga_fpga_frame_reader_raddr_39_32_write(uintptr_t base, uint8_t data)… in acamera_fpga_fpga_frame_reader_raddr_39_32_write() argument
103 static __inline uint8_t acamera_fpga_fpga_frame_reader_raddr_39_32_read(uintptr_t base) { in acamera_fpga_fpga_frame_reader_raddr_39_32_read() argument
116 static __inline void acamera_fpga_fpga_dma_wdr_frame_buffer1_highaddr_write(uintptr_t base, uint8_t… in acamera_fpga_fpga_dma_wdr_frame_buffer1_highaddr_write() argument
120 static __inline uint8_t acamera_fpga_fpga_dma_wdr_frame_buffer1_highaddr_read(uintptr_t base) { in acamera_fpga_fpga_dma_wdr_frame_buffer1_highaddr_read() argument
133 static __inline void acamera_fpga_fpga_dma_writer1_highaddr_write(uintptr_t base, uint8_t data) { in acamera_fpga_fpga_dma_writer1_highaddr_write() argument
137 static __inline uint8_t acamera_fpga_fpga_dma_writer1_highaddr_read(uintptr_t base) { in acamera_fpga_fpga_dma_writer1_highaddr_read() argument
[all …]
Dacamera_isp_config.h52 static __inline uint32_t acamera_isp_id_api_read(uintptr_t base) { in acamera_isp_id_api_read() argument
65 static __inline uint32_t acamera_isp_id_product_read(uintptr_t base) { in acamera_isp_id_product_read() argument
78 static __inline uint32_t acamera_isp_id_version_read(uintptr_t base) { in acamera_isp_id_version_read() argument
91 static __inline uint32_t acamera_isp_id_revision_read(uintptr_t base) { in acamera_isp_id_revision_read() argument
133 static __inline void acamera_isp_isp_global_global_fsm_reset_write(uintptr_t base, uint8_t data) { in acamera_isp_isp_global_global_fsm_reset_write() argument
137 static __inline uint8_t acamera_isp_isp_global_global_fsm_reset_read(uintptr_t base) { in acamera_isp_isp_global_global_fsm_reset_read() argument
154 static __inline void acamera_isp_isp_global_scaler_fsm_reset_write(uintptr_t base, uint8_t data) { in acamera_isp_isp_global_scaler_fsm_reset_write() argument
158 static __inline uint8_t acamera_isp_isp_global_scaler_fsm_reset_read(uintptr_t base) { in acamera_isp_isp_global_scaler_fsm_reset_read() argument
192 static __inline void acamera_isp_isp_global_dma_global_config_write(uintptr_t base, uint32_t data) { in acamera_isp_isp_global_dma_global_config_write() argument
196 static __inline uint32_t acamera_isp_isp_global_dma_global_config_read(uintptr_t base) { in acamera_isp_isp_global_dma_global_config_read() argument
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/drivers/inc/
Dhpm_can_drv.h273 static inline void can_reset(CAN_Type *base, bool enable) in can_reset() argument
276 base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RESET_MASK; in can_reset()
278 base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_RESET_MASK; in can_reset()
292 static inline void can_set_node_mode(CAN_Type *base, can_node_mode_t mode) in can_set_node_mode() argument
294 …uint32_t cfg_stat = base->CMD_STA_CMD_CTRL & ~(CAN_CMD_STA_CMD_CTRL_LBME_MASK | CAN_CMD_STA_CMD_CT… in can_set_node_mode()
304 base->CMD_STA_CMD_CTRL = cfg_stat; in can_set_node_mode()
314 static inline void can_enable_listen_only_mode(CAN_Type *base, bool enable) in can_enable_listen_only_mode() argument
317 base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_LOM_MASK; in can_enable_listen_only_mode()
319 base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_LOM_MASK; in can_enable_listen_only_mode()
330 static inline void can_enter_standby_mode(CAN_Type *base, bool enable) in can_enter_standby_mode() argument
[all …]
Dhpm_sdxc_drv.h485 static inline uint32_t sdxc_get_interrupt_status(SDXC_Type *base) in sdxc_get_interrupt_status() argument
487 return base->INT_STAT; in sdxc_get_interrupt_status()
496 static inline bool sdxc_is_card_inserted(SDXC_Type *base) in sdxc_is_card_inserted() argument
498 return IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CARD_INSERTED_MASK); in sdxc_is_card_inserted()
506 static inline void sdxc_clear_interrupt_status(SDXC_Type *base, uint32_t status_mask) in sdxc_clear_interrupt_status() argument
508 base->INT_STAT = status_mask; in sdxc_clear_interrupt_status()
517 static inline void sdxc_enable_interrupt_status(SDXC_Type *base, uint32_t mask, bool enable) in sdxc_enable_interrupt_status() argument
520 base->INT_STAT_EN |= mask; in sdxc_enable_interrupt_status()
522 base->INT_STAT_EN &= ~mask; in sdxc_enable_interrupt_status()
532 static inline void sdxc_enable_interrupt_signal(SDXC_Type *base, uint32_t mask, bool enable) in sdxc_enable_interrupt_signal() argument
[all …]
Dhpm_wdg_drv.h98 static inline void wdg_write_enable(WDG_Type *base) in wdg_write_enable() argument
100 base->WREN = WDG_WRITE_ENABLE_MAGIC_NUM; in wdg_write_enable()
108 static inline void wdg_enable(WDG_Type *base) in wdg_enable() argument
110 wdg_write_enable(base); in wdg_enable()
111 base->CTRL |= WDG_CTRL_EN_MASK; in wdg_enable()
119 static inline void wdg_disable(WDG_Type *base) in wdg_disable() argument
121 wdg_write_enable(base); in wdg_disable()
122 base->CTRL &= ~WDG_CTRL_EN_MASK; in wdg_disable()
130 static inline void wdg_reset_enable(WDG_Type *base) in wdg_reset_enable() argument
132 wdg_write_enable(base); in wdg_reset_enable()
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/drivers/src/
Dhpm_sdxc_drv.c30 static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags,
33 static uint32_t sdxc_read_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words);
35 static hpm_stat_t sdxc_read_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data);
37 static uint32_t sdxc_write_data_port(SDXC_Type *base, sdxc_data_t *data, uint32_t transferred_words…
39 static hpm_stat_t sdxc_write_by_data_port_blocking(SDXC_Type *base, sdxc_data_t *data);
41 static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data, bool enable_dma);
43 static hpm_stat_t sdxc_tuning_error_recovery(SDXC_Type *base);
45 static bool sdxc_is_bus_idle(SDXC_Type *base);
47 static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, uint32_t xfer_flags, in sdxc_set_transfer_config() argument
50 …uint32_t flags = base->CMD_XFER & ~(SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_E… in sdxc_set_transfer_config()
[all …]
Dhpm_sdp_drv.c60 static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx);
62 static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg,…
64 static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg,…
66 static hpm_stat_t sdp_hash_finalize(SDP_Type *base, sdp_hash_ctx_t *hash_ctx);
68 static inline void sdp_clear_error_status(SDP_Type *base) in sdp_clear_error_status() argument
70 base->STA = 0xFFFFFFFFUL; in sdp_clear_error_status()
77 static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, sdp_aes_ctx_t *aes_ctx,
100 hpm_stat_t sdp_wait_done(SDP_Type *base) in sdp_wait_done() argument
105 sdp_sta = base->STA; in sdp_wait_done()
126 hpm_stat_t sdp_init(SDP_Type *base) in sdp_init() argument
[all …]
Dhpm_can_drv.c132 static void can_fill_tx_buffer(CAN_Type *base, const can_transmit_buf_t *message);
243 hpm_stat_t can_set_bit_timing(CAN_Type *base, can_bit_timing_option_t option, in can_set_bit_timing() argument
250 if (base == NULL) { in can_set_bit_timing()
259 …base->S_PRESC = CAN_S_PRESC_S_PRESC_SET(timing_param.prescaler - 1U) | CAN_S_PRESC_S_SEG_1_SET(tim… in can_set_bit_timing()
262 …base->F_PRESC = CAN_F_PRESC_F_PRESC_SET(timing_param.prescaler - 1U) | CAN_F_PRESC_F_SEG_1_SET(tim… in can_set_bit_timing()
274 hpm_stat_t can_set_filter(CAN_Type *base, const can_filter_config_t *config) in can_set_filter() argument
279 if ((base == NULL) || (config == NULL)) { in can_set_filter()
288 base->ACFCTRL = CAN_ACFCTRL_ACFADR_SET(config->index); in can_set_filter()
289 base->ACF = CAN_ACF_CODE_MASK_SET(config->code); in can_set_filter()
302 base->ACFCTRL = CAN_ACFCTRL_SELMASK_MASK | CAN_ACFCTRL_ACFADR_SET(config->index); in can_set_filter()
[all …]
/device/qemu/riscv32_virt/liteos_m/board/driver/
Dvirtmmio.c26 return GET_UINT32(dev->base + VIRTMMIO_REG_STATUS); in VirtioGetStatus()
31 FENCE_WRITE_UINT32(VirtioGetStatus(dev) | val, dev->base + VIRTMMIO_REG_STATUS); in VirtioAddStatus()
36 FENCE_WRITE_UINT32(VIRTIO_STATUS_RESET, dev->base + VIRTMMIO_REG_STATUS); in VirtioResetStatus()
41 VADDR_T base; in VirtmmioDiscover() local
44 base = IO_DEVICE_ADDR(VIRTMMIO_BASE_ADDR) + VIRTMMIO_BASE_SIZE * (NUM_VIRTIO_TRANSPORTS - 1); in VirtmmioDiscover()
46 if ((GET_UINT32(base + VIRTMMIO_REG_MAGICVALUE) == VIRTMMIO_MAGIC) && in VirtmmioDiscover()
47 (GET_UINT32(base + VIRTMMIO_REG_VERSION) == VIRTMMIO_VERSION) && in VirtmmioDiscover()
48 (GET_UINT32(base + VIRTMMIO_REG_DEVICEID) == devId)) { in VirtmmioDiscover()
49 dev->base = base; in VirtmmioDiscover()
54 base -= VIRTMMIO_BASE_SIZE; in VirtmmioDiscover()
[all …]
/device/qemu/drivers/virtio/
Dvirtmmio.c21 return GET_UINT32(dev->base + VIRTMMIO_REG_STATUS); in VirtioGetStatus()
26 WRITE_UINT32(VirtioGetStatus(dev) | val, dev->base + VIRTMMIO_REG_STATUS); in VirtioAddStatus()
31 WRITE_UINT32(VIRTIO_STATUS_RESET, dev->base + VIRTMMIO_REG_STATUS); in VirtioResetStatus()
36 VADDR_T base; in VirtmmioDiscover() local
39 base = IO_DEVICE_ADDR(VIRTMMIO_BASE_ADDR) + VIRTMMIO_BASE_SIZE * (NUM_VIRTIO_TRANSPORTS - 1); in VirtmmioDiscover()
41 if ((GET_UINT32(base + VIRTMMIO_REG_MAGICVALUE) == VIRTMMIO_MAGIC) && in VirtmmioDiscover()
42 (GET_UINT32(base + VIRTMMIO_REG_VERSION) == VIRTMMIO_VERSION) && in VirtmmioDiscover()
43 (GET_UINT32(base + VIRTMMIO_REG_DEVICEID) == devId)) { in VirtmmioDiscover()
44 dev->base = base; in VirtmmioDiscover()
49 base -= VIRTMMIO_BASE_SIZE; in VirtmmioDiscover()
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6360/
Dhpm_sdxc_soc_drv.h19 static inline void sdxc_enable_tm_clock(SDXC_Type *base) in sdxc_enable_tm_clock() argument
21 base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; in sdxc_enable_tm_clock()
24 static inline void sdxc_enable_freq_selection(SDXC_Type *base) in sdxc_enable_freq_selection() argument
26 base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; in sdxc_enable_freq_selection()
29 static inline void sdxc_disable_freq_selection(SDXC_Type *base) in sdxc_disable_freq_selection() argument
31 base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; in sdxc_disable_freq_selection()
34 static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) in sdxc_set_clock_divider() argument
36 …base->MISC_CTRL0 = (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_S… in sdxc_set_clock_divider()
39 static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) in sdxc_get_clock_divider() argument
41 return SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0); in sdxc_get_clock_divider()
[all …]
Dhpm_romapi.h116 hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config);
118 hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg);
120 … hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel);
122 …hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint…
124 hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer);
126 void (*software_reset)(XPI_Type *base);
128 bool (*is_idle)(XPI_Type *base);
130 void (*update_dllcr)(XPI_Type *base,
137 …(*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *o…
147 …hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_o…
[all …]
Dhpm_plic_drv.h54 ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) in __plic_set_feature() argument
56 *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; in __plic_set_feature()
67 ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, in __plic_set_threshold() argument
71 volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + in __plic_set_threshold()
85 ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, in __plic_set_irq_priority() argument
89 volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + in __plic_set_irq_priority()
101 ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) in __plic_set_irq_pending() argument
103 volatile uint32_t *current_ptr = (volatile uint32_t *)(base + in __plic_set_irq_pending()
116 ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, in __plic_enable_irq() argument
120 volatile uint32_t *current_ptr = (volatile uint32_t *)(base + in __plic_enable_irq()
[all …]
/device/soc/goodix/gr551x/sdk_liteos/platform/system/
Dsystem.c65 const char *_parse_integer_fixup_radix(const char *str, unsigned int *base) in _parse_integer_fixup_radix() argument
69 if (*base == BASE_0) { in _parse_integer_fixup_radix()
72 *base = BASE_16; in _parse_integer_fixup_radix()
74 *base = BASE_8; in _parse_integer_fixup_radix()
77 *base = BASE_10; in _parse_integer_fixup_radix()
80 if (*base == BASE_16 && s[INDEX_0] == '0' && tolower_re(s[INDEX_1]) == 'x') { in _parse_integer_fixup_radix()
86 unsigned int _parse_integer(const char *str, unsigned int base, unsigned long long *p) in _parse_integer() argument
106 if (val >= base) { in _parse_integer()
114 if (res > div_u64(ULLONG_MAX - val, base)) { in _parse_integer()
118 res = res * base + val; in _parse_integer()
[all …]
/device/soc/rockchip/rk2206/sdk_liteos/platform/system/
Dsystem.c68 const char *_parse_integer_fixup_radix(const char *str, unsigned int *base) in _parse_integer_fixup_radix() argument
72 if (*base == BASE_0) { in _parse_integer_fixup_radix()
75 *base = BASE_16; in _parse_integer_fixup_radix()
77 *base = BASE_8; in _parse_integer_fixup_radix()
80 *base = BASE_10; in _parse_integer_fixup_radix()
83 if (*base == BASE_16 && s[INDEX_0] == '0' && tolower_re(s[INDEX_1]) == 'x') { in _parse_integer_fixup_radix()
89 unsigned int _parse_integer(const char *str, unsigned int base, unsigned long long *p) in _parse_integer() argument
109 if (val >= base) { in _parse_integer()
117 if (res > div_u64(ULLONG_MAX - val, base)) { in _parse_integer()
121 res = res * base + val; in _parse_integer()
[all …]
/device/soc/st/common/platform/uart/
Dstm32mp1_uart_hw.c64 static inline uint32_t RegRead(void volatile *base, uint32_t reg) in RegRead() argument
66 return OSAL_READL((uintptr_t)base + reg); in RegRead()
69 static inline void RegWrite(void volatile *base, uint32_t reg, uint32_t val) in RegWrite() argument
71 OSAL_WRITEL(val, (uintptr_t)base + reg); in RegWrite()
78 dprintf("USART_CR1 : %#x.\r\n", RegRead(uart->base, USART_CR1)); in Mp1xxUartDump()
79 dprintf("USART_CR2 : %#x.\r\n", RegRead(uart->base, USART_CR2)); in Mp1xxUartDump()
80 dprintf("USART_CR3 : %#x.\r\n", RegRead(uart->base, USART_CR3)); in Mp1xxUartDump()
81 dprintf("USART_BRR : %#x.\r\n", RegRead(uart->base, USART_BRR)); in Mp1xxUartDump()
82 dprintf("USART_GTPR : %#x.\r\n", RegRead(uart->base, USART_GTPR)); in Mp1xxUartDump()
83 dprintf("USART_RTOR : %#x.\r\n", RegRead(uart->base, USART_RTOR)); in Mp1xxUartDump()
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/middleware/hpm_sdmmc/lib/
Dhpm_sdmmc_host.c36 …host->host_param.host_clk_freq = host->host_param.clock_init_func(host->host_param.base, SDMMC_CLO… in sdmmchost_init()
37 host->host_param.io_init_func(host->host_param.base); in sdmmchost_init()
42 sdxc_init(host->host_param.base, &sdxc_config); in sdmmchost_init()
44 sdxc_wait_card_active(host->host_param.base); in sdmmchost_init()
61 sdxc_enable_inverse_clock(host->host_param.base, false); in sdmmchost_switch_to_1v8()
62 sdxc_enable_sd_clock(host->host_param.base, false); in sdmmchost_switch_to_1v8()
68 data3_0_level = sdxc_get_data3_0_level(host->host_param.base); in sdmmchost_switch_to_1v8()
76 board_sd_switch_pins_to_1v8(host->host_param.base); in sdmmchost_switch_to_1v8()
82 sdxc_enable_inverse_clock(host->host_param.base, true); in sdmmchost_switch_to_1v8()
83 sdxc_enable_sd_clock(host->host_param.base, true); in sdmmchost_switch_to_1v8()
[all …]
/device/soc/rockchip/common/sdk_linux/drivers/nvmem/
Drockchip-efuse.c98 void __iomem *base; member
105 static void rk1808_efuse_timing_init(void __iomem *base) in rk1808_efuse_timing_init() argument
108 writel(readl(base + RK1808_MOD) & (~RK1808_USER_MODE), base + RK1808_MOD); in rk1808_efuse_timing_init()
111 writel((T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P); in rk1808_efuse_timing_init()
112 writel((T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P); in rk1808_efuse_timing_init()
113 writel((T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P); in rk1808_efuse_timing_init()
114 writel((T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P); in rk1808_efuse_timing_init()
115 writel((T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P); in rk1808_efuse_timing_init()
116 writel((T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R); in rk1808_efuse_timing_init()
117 writel((T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R); in rk1808_efuse_timing_init()
[all …]
/device/soc/hpmicro/sdk/hpm_sdk/soc/HPM6750/
Dhpm_romapi.h116 hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config);
118 hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg);
120 … hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel);
122 …hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint…
124 hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer);
126 void (*software_reset)(XPI_Type *base);
128 bool (*is_idle)(XPI_Type *base);
130 …void (*update_dllcr)(XPI_Type *base, uint32_t serial_root_clk_freq, uint32_t data_valid_time, xpi_…
133 …hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, …
143 …hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_o…
[all …]
Dhpm_plic_drv.h54 ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) in __plic_set_feature() argument
56 *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; in __plic_set_feature()
67 ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, in __plic_set_threshold() argument
71 volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + in __plic_set_threshold()
85 ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, in __plic_set_irq_priority() argument
89 volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + in __plic_set_irq_priority()
101 ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) in __plic_set_irq_pending() argument
103 volatile uint32_t *current_ptr = (volatile uint32_t *)(base + in __plic_set_irq_pending()
116 ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, in __plic_enable_irq() argument
120 volatile uint32_t *current_ptr = (volatile uint32_t *)(base + in __plic_enable_irq()
[all …]
/device/soc/rockchip/common/vendor/drivers/rockchip/
Drockchip-cpuinfo.c131 void __iomem *base; in rk3288_init() local
135 base = ioremap(RK3288_HDMI_PHYS, SZ_4K); in rk3288_init()
136 if (base) { in rk3288_init()
138 if (readl_relaxed(base + 0x4) == 0x1A) { in rk3288_init()
141 iounmap(base); in rk3288_init()
147 void __iomem *base; in rk3126_init() local
153 base = ioremap(RK312X_GRF_PHYS, SZ_4K); in rk3126_init()
154 if (base) { in rk3126_init()
155 if (readl_relaxed(base + RK312X_GRF_CHIP_TAG) == 0x3136) { in rk3126_init()
156 if (readl_relaxed(base + RK312X_GRF_SOC_CON1) & 0x1) { in rk3126_init()
[all …]
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
Drockchip-cpuinfo.c123 void __iomem *base; in rk3288_init() local
127 base = ioremap(RK3288_HDMI_PHYS, SZ_4K); in rk3288_init()
128 if (base) { in rk3288_init()
130 if (readl_relaxed(base + 4) == 0x1A) in rk3288_init()
132 iounmap(base); in rk3288_init()
138 void __iomem *base; in rk3126_init() local
144 base = ioremap(RK312X_GRF_PHYS, SZ_4K); in rk3126_init()
145 if (base) { in rk3126_init()
146 if (readl_relaxed(base + RK312X_GRF_CHIP_TAG) == 0x3136) { in rk3126_init()
147 if (readl_relaxed(base + RK312X_GRF_SOC_CON1) & 0x1) in rk3126_init()
[all …]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/linux/
Dmali_osk_mali.c77 .base = MALI_OFFSET_GP,
82 .base = MALI_OFFSET_GP_MMU,
87 .base = MALI_OFFSET_PP0,
92 .base = MALI_OFFSET_PP0_MMU,
97 .base = MALI_OFFSET_PP1,
102 .base = MALI_OFFSET_PP1_MMU,
108 .base = MALI_OFFSET_PP2,
113 .base = MALI_OFFSET_PP2_MMU,
118 .base = MALI_OFFSET_PP3,
123 .base = MALI_OFFSET_PP3_MMU,
[all …]

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