| /device/board/isoftstone/yangfan/common/seetafaceengine/opencv2/3rdparty/carotene/src/ |
| D | gaussian_blur.cpp | 233 u16* lane = internal::alignPtr(&_buf[cn << 1], 32); in gaussianBlur5x5() local
238 lane[-cn+k] = borderValue; in gaussianBlur5x5()
239 lane[-cn-cn+k] = borderValue; in gaussianBlur5x5()
240 lane[colsn+k] = borderValue; in gaussianBlur5x5()
241 lane[colsn+cn+k] = borderValue; in gaussianBlur5x5()
279 vst1q_u16(lane + x, v); in gaussianBlur5x5()
282 lane[x] = ln0[x] + ln4[x] + u16(4) * (ln1[x] + ln3[x]) + u16(6) * ln2[x]; in gaussianBlur5x5()
288 lane[-cn+k] = lane[idx_l1 + k]; in gaussianBlur5x5()
289 lane[-cn-cn+k] = lane[idx_l2 + k]; in gaussianBlur5x5()
291 lane[colsn+k] = lane[idx_r1 + k]; in gaussianBlur5x5()
[all …]
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| /device/board/isoftstone/yangfan/kernel/src/driv/phy/ |
| D | phy-rockchip-naneng-edp.c | 35 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, \ argument
36 4 * (lane))
38 #define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, \ argument
39 4 * (lane))
42 #define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, \ argument
43 2 * (lane))
92 u8 lane; in rockchip_edp_phy_set_voltages() local
95 for (lane = 0; lane < dp->lanes; lane++) { in rockchip_edp_phy_set_voltages()
96 val = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltages()
97 writel(EDP_PHY_TX_AMP(lane, val), in rockchip_edp_phy_set_voltages()
[all …]
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| D | phy-rockchip-usbdp.c | 1351 u32 voltage, u32 pre, u32 lane) in rk3588_dp_phy_set_voltage() argument
1353 u32 offset = 0x800 * lane; in rk3588_dp_phy_set_voltage()
1372 u32 i, lane; in rk3588_dp_phy_set_voltages() local
1375 lane = udphy->dp_lane_sel[i]; in rk3588_dp_phy_set_voltages()
1379 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), in rk3588_dp_phy_set_voltages()
1382 udphy->lane_mux_sel[lane])); in rk3588_dp_phy_set_voltages()
1386 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), in rk3588_dp_phy_set_voltages()
1393 dp->pre[i], lane); in rk3588_dp_phy_set_voltages()
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| D | phy-rockchip-naneng-edp.c | 35 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, \ argument
36 4 * (lane))
38 #define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, \ argument
39 4 * (lane))
42 #define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, \ argument
43 2 * (lane))
92 u8 lane; in rockchip_edp_phy_set_voltages() local
95 for (lane = 0; lane < dp->lanes; lane++) { in rockchip_edp_phy_set_voltages()
96 val = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltages()
97 writel(EDP_PHY_TX_AMP(lane, val), in rockchip_edp_phy_set_voltages()
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| D | phy-rockchip-samsung-hdptx.c | 322 #define LANE_REG(lane, offset) (0x400 * (lane) + (offset)) argument
489 u8 lane) in rockchip_hdptx_phy_set_voltage() argument
493 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), in rockchip_hdptx_phy_set_voltage()
499 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
500 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), in rockchip_hdptx_phy_set_voltage()
503 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30), in rockchip_hdptx_phy_set_voltage()
506 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), in rockchip_hdptx_phy_set_voltage()
511 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; in rockchip_hdptx_phy_set_voltage()
512 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), in rockchip_hdptx_phy_set_voltage()
515 regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34), in rockchip_hdptx_phy_set_voltage()
[all …]
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| D | phy-rockchip-usbdp.c | 1351 u32 voltage, u32 pre, u32 lane) in rk3588_dp_phy_set_voltage() argument
1353 u32 offset = 0x800 * lane; in rk3588_dp_phy_set_voltage()
1372 u32 i, lane; in rk3588_dp_phy_set_voltages() local
1375 lane = udphy->dp_lane_sel[i]; in rk3588_dp_phy_set_voltages()
1379 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), in rk3588_dp_phy_set_voltages()
1382 udphy->lane_mux_sel[lane])); in rk3588_dp_phy_set_voltages()
1386 regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), in rk3588_dp_phy_set_voltages()
1393 dp->pre[i], lane); in rk3588_dp_phy_set_voltages()
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| /device/soc/rockchip/common/vendor/drivers/phy/ |
| D | phy-rockchip-naneng-edp.c | 34 #define EDP_PHY_TX_EMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 1, 4 * (lane)) argument
36 #define EDP_PHY_TX_AMP(lane, x) HIWORD_UPDATE(x, 4 * ((lane) + 1) - 2, 4 * (lane)) argument
39 #define EDP_PHY_TX_AMP_SCALE(lane, x) HIWORD_UPDATE(x, 2 * ((lane) + 1) - 1, 2 * (lane)) argument
87 u8 lane; in rockchip_edp_phy_set_voltages() local
90 for (lane = 0; lane < dp->lanes; lane++) { in rockchip_edp_phy_set_voltages()
91 val = vp[dp->voltage[lane]][dp->pre[lane]].amp; in rockchip_edp_phy_set_voltages()
92 writel(EDP_PHY_TX_AMP(lane, val), edpphy->regs + EDP_PHY_GRF_CON4); in rockchip_edp_phy_set_voltages()
94 val = vp[dp->voltage[lane]][dp->pre[lane]].amp_scale; in rockchip_edp_phy_set_voltages()
95 writel(EDP_PHY_TX_AMP_SCALE(lane, val), edpphy->regs + EDP_PHY_GRF_CON5); in rockchip_edp_phy_set_voltages()
97 val = vp[dp->voltage[lane]][dp->pre[lane]].emp; in rockchip_edp_phy_set_voltages()
[all …]
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| D | phy-rockchip-usbdp.c | 1293 static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u32 voltage, u32 pre, u32 lane) in rk3588_dp_phy_set_voltage() argument
1295 u32 offset = 0x800 * lane; in rk3588_dp_phy_set_voltage()
1313 u32 i, lane; in rk3588_dp_phy_set_voltages() local
1316 lane = udphy->dp_lane_sel[i]; in rk3588_dp_phy_set_voltages()
1320 … regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), LN_ANA_TX_SER_TXCLK_INV, in rk3588_dp_phy_set_voltages()
1321 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, udphy->lane_mux_sel[lane])); in rk3588_dp_phy_set_voltages()
1325 … regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), LN_ANA_TX_SER_TXCLK_INV, in rk3588_dp_phy_set_voltages()
1330 rk3588_dp_phy_set_voltage(udphy, dp->voltage[i], dp->pre[i], lane); in rk3588_dp_phy_set_voltages()
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 319 int lane, lane_count, retval; in analogix_dp_link_start() local
326 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_link_start()
327 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
358 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_link_start()
359 … dp->link_train.training_lane[lane] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0; in analogix_dp_link_start()
372 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_link_start()
373 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; in analogix_dp_link_start()
384 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) in analogix_dp_get_lane_status() argument
386 int shift = (lane & 1) * 0x4; in analogix_dp_get_lane_status()
387 u8 link_value = link_status[lane >> 1]; in analogix_dp_get_lane_status()
[all …]
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| D | analogix_dp_reg.c | 650 u8 lane; in analogix_dp_set_lane_link_training() local
653 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
654 …gix_dp_write(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane, dp->link_train.training_lane[lane]); in analogix_dp_set_lane_link_training()
660 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
661 u8 training_lane = dp->link_train.training_lane[lane]; in analogix_dp_set_lane_link_training()
666 phy_cfg.dp.voltage[lane] = vs; in analogix_dp_set_lane_link_training()
667 phy_cfg.dp.pre[lane] = pe; in analogix_dp_set_lane_link_training()
683 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) in analogix_dp_get_lane_link_training() argument
685 return analogix_dp_read(dp, ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); in analogix_dp_get_lane_link_training()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/vin-mipi/combo_rx/ |
| D | combo_rx_reg.c | 445 int lane; in cmb_rx_lvds_sync_code() local
447 for (lane = 0; lane < 12; lane++) { in cmb_rx_lvds_sync_code()
448 vin_reg_writel(cmb_rx_base_addr[sel] + CMB_LVDS_LANE0_SOF_SET0_REG_OFF + 0x20 * lane, in cmb_rx_lvds_sync_code()
449 lvds_sync_code->lane_sof[lane].low_bit); in cmb_rx_lvds_sync_code()
450 vin_reg_writel(cmb_rx_base_addr[sel] + CMB_LVDS_LANE0_SOF_SET1_REG_OFF + 0x20 * lane, in cmb_rx_lvds_sync_code()
451 lvds_sync_code->lane_sof[lane].high_bit); in cmb_rx_lvds_sync_code()
452 vin_reg_writel(cmb_rx_base_addr[sel] + CMB_LVDS_LANE0_SOL_SET0_REG_OFF + 0x20 * lane, in cmb_rx_lvds_sync_code()
453 lvds_sync_code->lane_sol[lane].low_bit); in cmb_rx_lvds_sync_code()
454 vin_reg_writel(cmb_rx_base_addr[sel] + CMB_LVDS_LANE0_SOL_SET1_REG_OFF + 0x20 * lane, in cmb_rx_lvds_sync_code()
455 lvds_sync_code->lane_sol[lane].high_bit); in cmb_rx_lvds_sync_code()
[all …]
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| /device/soc/bestechnic/bes2600/liteos_m/components/drivers/display/hal/ |
| D | lcd_abs_if.c | 118 if (info->mipi.lane == 0) { in CalcDataRate()
119 info->mipi.lane = 1; // default 1 lane in CalcDataRate()
121 if ((bitClk % info->mipi.lane) == 0) { in CalcDataRate()
122 return bitClk / info->mipi.lane; in CalcDataRate()
124 return bitClk / info->mipi.lane + 1; in CalcDataRate()
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| /device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/ |
| D | phy-rockchip-typec.c | 716 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_tx_usb3_cfg_lane() argument
718 writel(0x7799, tcphy->base + TX_PSC_A0(lane)); in tcphy_tx_usb3_cfg_lane()
719 writel(0x7798, tcphy->base + TX_PSC_A1(lane)); in tcphy_tx_usb3_cfg_lane()
720 writel(0x5098, tcphy->base + TX_PSC_A2(lane)); in tcphy_tx_usb3_cfg_lane()
721 writel(0x5098, tcphy->base + TX_PSC_A3(lane)); in tcphy_tx_usb3_cfg_lane()
722 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); in tcphy_tx_usb3_cfg_lane()
723 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); in tcphy_tx_usb3_cfg_lane()
726 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) in tcphy_rx_usb3_cfg_lane() argument
728 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); in tcphy_rx_usb3_cfg_lane()
729 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); in tcphy_rx_usb3_cfg_lane()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v3x/ |
| D | de_dsi_28.c | 790 __u32 mode, lane, format, dclk; in dsi_dphy_cfg() local
798 lane = panel->lcd_dsi_lane; in dsi_dphy_cfg()
825 dclk * dsi_bits_per_pixel[format] / lane); in dsi_dphy_cfg()
826 dsi_dphy_cfg_pll(sel, dsi_bits_per_pixel[format] * 2, lane * 2); in dsi_dphy_cfg()
844 dsi_dev[sel]->dsi_ctl1.bits.phy_lane_num = lane - 1; in dsi_dphy_cfg()
876 __u32 mode, lane, format, dclk; in dsi_basic_cfg() local
884 lane = panel->lcd_dsi_lane; in dsi_basic_cfg()
891 ((dclk * dsi_bits_per_pixel[format] + 4 * lane * 10) / in dsi_basic_cfg()
892 (8 * lane * 10)) & in dsi_basic_cfg()
896 ((dclk * dsi_bits_per_pixel[format] + 4 * lane * 10) / in dsi_basic_cfg()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/ |
| D | de_dsi_28.c | 788 __u32 mode, lane, format, dclk; in dsi_dphy_cfg() local
796 lane = panel->lcd_dsi_lane; in dsi_dphy_cfg()
823 dclk * dsi_bits_per_pixel[format] / lane); in dsi_dphy_cfg()
824 dsi_dphy_cfg_pll(sel, dsi_bits_per_pixel[format] * 2, lane * 2); in dsi_dphy_cfg()
842 dsi_dev[sel]->dsi_ctl1.bits.phy_lane_num = lane - 1; in dsi_dphy_cfg()
875 __u32 mode, lane, format, dclk; in dsi_basic_cfg() local
883 lane = panel->lcd_dsi_lane; in dsi_basic_cfg()
890 ((dclk * dsi_bits_per_pixel[format] + 4 * lane * 10) / in dsi_basic_cfg()
891 (8 * lane * 10)) & in dsi_basic_cfg()
895 ((dclk * dsi_bits_per_pixel[format] + 4 * lane * 10) / in dsi_basic_cfg()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v33x/tcon/ |
| D | de_dsi_28.c | 790 __u32 mode, lane, format, dclk; in dsi_dphy_cfg() local
798 lane = panel->lcd_dsi_lane; in dsi_dphy_cfg()
825 dclk * dsi_bits_per_pixel[format] / lane); in dsi_dphy_cfg()
826 dsi_dphy_cfg_pll(sel, dsi_bits_per_pixel[format] * 2, lane * 2); in dsi_dphy_cfg()
844 dsi_dev[sel]->dsi_ctl1.bits.phy_lane_num = lane - 1; in dsi_dphy_cfg()
876 __u32 mode, lane, format, dclk; in dsi_basic_cfg() local
884 lane = panel->lcd_dsi_lane; in dsi_basic_cfg()
891 ((dclk * dsi_bits_per_pixel[format] + 4 * lane * 10) / in dsi_basic_cfg()
892 (8 * lane * 10)) & in dsi_basic_cfg()
896 ((dclk * dsi_bits_per_pixel[format] + 4 * lane * 10) / in dsi_basic_cfg()
[all …]
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/vin/vin-mipi/dphy/ |
| D | dphy_reg.h | 63 extern unsigned char dphy_get_hs_data(unsigned int sel, enum dphy_lane lane);
65 enum dphy_lane lane);
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| /device/board/isoftstone/yangfan/kernel/src/driv/gpu/rockchip/ |
| D | cdn-dp-link-training.c | 150 int lane; in cdn_dp_link_max_vswing_reached() local
152 for (lane = 0; lane < dp->link.num_lanes; lane++) in cdn_dp_link_max_vswing_reached()
153 if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdn_dp_link_max_vswing_reached()
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| /device/board/hihope/rk3568/ |
| D | README_zh.md | 102 | 摄像头接口 | MIPI-CSI2, 1x4-lane/2x2-lane@2.5Gbps/lane …
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| /device/soc/bestechnic/bes2600/liteos_m/components/drivers/display/hal/panel/ |
| D | ili9488.c | 148 cfg.lane = panelInfo->mipi.lane; in PanelInit()
219 hal_dsi_init(WIDTH, priv.panelInfo.mipi.lane); in PanelCheckStatus()
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| D | rm69330.c | 100 cfg.lane = panelInfo->mipi.lane; in PanelInit()
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| D | a064.c | 204 cfg.lane = panelInfo->mipi.lane; in PanelInit()
275 hal_dsi_init(WIDTH, priv.panelInfo.mipi.lane); in PanelCheckStatus()
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| /device/board/unionman/unionpi_tiger/kernel/drivers/panel/ |
| D | Kconfig | 21 system interfaces, with 2 lane.
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| /device/soc/hisilicon/common/platform/mipi_csi/ |
| D | mipi_rx_hi2121.c | 1658 short GetSensorLaneIndex(short lane, const short laneId[LVDS_LANE_NUM]) in GetSensorLaneIndex() argument
1663 if (laneId[i] == lane) { in GetSensorLaneIndex()
1681 short lane; in MipiRxDrvSetLvdsPhySyncCode() local
1690 lane = 0 + 4 * phyId; /* 4 -- 1 phy have 4 lane */ in MipiRxDrvSetLvdsPhySyncCode()
1691 sensorLaneIdx = GetSensorLaneIndex(lane, laneId); in MipiRxDrvSetLvdsPhySyncCode()
1697 lane = 1 + 4 * phyId; /* 4 -- 1 phy have 4 lane */ in MipiRxDrvSetLvdsPhySyncCode()
1698 sensorLaneIdx = GetSensorLaneIndex(lane, laneId); in MipiRxDrvSetLvdsPhySyncCode()
1704 lane = 2 + 4 * phyId; /* 4 -- 1 phy have 4 lane, 2 -- laneId 2 */ in MipiRxDrvSetLvdsPhySyncCode()
1705 sensorLaneIdx = GetSensorLaneIndex(lane, laneId); in MipiRxDrvSetLvdsPhySyncCode()
1711 lane = 3 + 4 * phyId; /* 4 -- 1 phy have 4 lane, 3 -- laneId 3 */ in MipiRxDrvSetLvdsPhySyncCode()
[all …]
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| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/hi3516cv500/mipi_rx/ |
| D | mipi_rx_hal.c | 1663 short get_sensor_lane_index(short lane, const short lane_id[LVDS_LANE_NUM]) in get_sensor_lane_index() argument
1668 if (lane_id[i] == lane) { in get_sensor_lane_index()
1688 short lane; in mipi_rx_drv_set_lvds_phy_sync_code() local
1697 lane = 0 + 4 * phy_id; /* 4 -- 1 phy have 4 lane */ in mipi_rx_drv_set_lvds_phy_sync_code()
1698 sensor_lane_idx = get_sensor_lane_index(lane, lane_id); in mipi_rx_drv_set_lvds_phy_sync_code()
1704 lane = 1 + 4 * phy_id; /* 4 -- 1 phy have 4 lane */ in mipi_rx_drv_set_lvds_phy_sync_code()
1705 sensor_lane_idx = get_sensor_lane_index(lane, lane_id); in mipi_rx_drv_set_lvds_phy_sync_code()
1711 lane = 2 + 4 * phy_id; /* 4 -- 1 phy have 4 lane, 2 -- lane_id 2 */ in mipi_rx_drv_set_lvds_phy_sync_code()
1712 sensor_lane_idx = get_sensor_lane_index(lane, lane_id); in mipi_rx_drv_set_lvds_phy_sync_code()
1718 lane = 3 + 4 * phy_id; /* 4 -- 1 phy have 4 lane, 3 -- lane_id 3 */ in mipi_rx_drv_set_lvds_phy_sync_code()
[all …]
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