| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/clk/ |
| D | ccu_phase.c | 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_set_phase() local
110 spin_lock_irqsave(phase->common.lock, flags); in ccu_phase_set_phase()
111 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_set_phase()
112 reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift); in ccu_phase_set_phase()
113 writel(reg | (delay << phase->shift), in ccu_phase_set_phase()
114 phase->common.base + phase->common.reg); in ccu_phase_set_phase()
[all …]
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| /device/soc/esp/esp32/components/hal/esp32/include/hal/ |
| D | dac_ll.h | 151 static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cw_phase_t phase) in dac_ll_cw_set_phase() argument
154 SENS.sar_dac_ctrl2.dac_inv1 = phase; in dac_ll_cw_set_phase()
156 SENS.sar_dac_ctrl2.dac_inv2 = phase; in dac_ll_cw_set_phase()
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| /device/soc/rockchip/common/sdk_linux/drivers/mmc/host/ |
| D | dw_mmc-rockchip.c | 115 int phase; in dw_mci_rk3288_set_ios() local
123 phase = RK_NINTY_DEGREE_PHASE; in dw_mci_rk3288_set_ios()
133 phase = RK_ONE_HUNDRED_EIGHTY_DEGREE_PHASE; in dw_mci_rk3288_set_ios()
146 phase = RK_ONE_HUNDRED_EIGHTY_DEGREE_PHASE; in dw_mci_rk3288_set_ios()
150 clk_set_phase(priv->drv_clk, phase); in dw_mci_rk3288_set_ios()
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| /device/soc/hpmicro/sdk/hpm_sdk/middleware/hpm_mcl/src/ |
| D | hpm_bldc_block_func.c | 124 uint8_t bldc_block_step_get(bldc_hall_phase_t phase, uint8_t hall_u, uint8_t hall_v, uint8_t hall_w) in bldc_block_step_get() argument
132 if (phase == bldc_hall_phase_120) { in bldc_block_step_get()
134 } else if (phase == bldc_hall_phase_60) { in bldc_block_step_get()
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| /device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/drv/ |
| D | ddr_training_impl.c | 2530 if (wdqs_new->phase[i] == wdqs_old->phase[i] in ddr_wl_wdq_adjust()
2602 if (wdqs_new->phase[i] == wdqs_old->phase[i] in ddr_wl_bdl_sync()
2608 wdqs_new->phase[i], wdqs_new->bdl[i], in ddr_wl_bdl_sync()
2609 wdqs_old->phase[i], wdqs_old->bdl[i]); in ddr_wl_bdl_sync()
2617 + (wdqs_new->phase[i] - wdqs_old->phase[i]); in ddr_wl_bdl_sync()
2691 type, j, wdqs->phase[j], wdqs->bdl[j], wl_result); in ddr_wl_process()
2694 ddr_phase_inc(&wdqs->phase[j]); in ddr_wl_process()
2698 ddr_write((wdqs->phase[j] << PHY_WDQS_PHASE_BIT) in ddr_wl_process()
2745 wdqs_old.phase[i] = (tmp >> PHY_WDQS_PHASE_BIT) in ddr_write_leveling()
2749 wdqs_new.phase[i] = wdqs_old.phase[i]; in ddr_write_leveling()
[all …]
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| /device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/drv/ |
| D | ddr_training_impl.c | 2528 if (wdqs_new->phase[i] == wdqs_old->phase[i] in ddr_wl_wdq_adjust()
2600 if (wdqs_new->phase[i] == wdqs_old->phase[i] in ddr_wl_bdl_sync()
2606 wdqs_new->phase[i], wdqs_new->bdl[i], in ddr_wl_bdl_sync()
2607 wdqs_old->phase[i], wdqs_old->bdl[i]); in ddr_wl_bdl_sync()
2615 + (wdqs_new->phase[i] - wdqs_old->phase[i]); in ddr_wl_bdl_sync()
2689 type, j, wdqs->phase[j], wdqs->bdl[j], wl_result); in ddr_wl_process()
2692 ddr_phase_inc(&wdqs->phase[j]); in ddr_wl_process()
2696 ddr_write((wdqs->phase[j] << PHY_WDQS_PHASE_BIT) in ddr_wl_process()
2743 wdqs_old.phase[i] = (tmp >> PHY_WDQS_PHASE_BIT) in ddr_write_leveling()
2747 wdqs_new.phase[i] = wdqs_old.phase[i]; in ddr_write_leveling()
[all …]
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| D | ddr_training_impl.h | 236 unsigned int phase[DDR_PHY_BYTE_MAX]; member
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| /device/soc/esp/esp32/components/esp_netif/lwip/ |
| D | esp_netif_lwip_ppp.c | 185 static void on_ppp_notify_phase(ppp_pcb *pcb, u8_t phase, void *ctx) in on_ppp_notify_phase() argument
187 switch (phase) { in on_ppp_notify_phase()
213 ESP_LOGW(TAG, "Phase Unknown: %d", phase); in on_ppp_notify_phase()
220 …esp_err_t err = esp_event_post(NETIF_PPP_STATUS, NETIF_PP_PHASE_OFFSET + phase, &netif, sizeof(net… in on_ppp_notify_phase()
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| /device/soc/hpmicro/sdk/hpm_sdk/drivers/inc/ |
| D | hpm_romapi_xpi_def.h | 205 #define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | … argument
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| /device/soc/hisilicon/common/platform/mmc/sdhci/ |
| D | sdhci.c | 668 static void SdhciSetDrvPhase(uint32_t id, uint32_t phase) in SdhciSetDrvPhase() argument
679 value |= (phase << SDHCI_DRV_CLK_PHASE_SHFT); in SdhciSetDrvPhase()
692 static void SdhciSetSampPhase(struct SdhciHost *host, uint32_t phase) in SdhciSetSampPhase() argument
698 val |= phase; in SdhciSetSampPhase()
840 uint32_t drvPhase, phase; in SdhciSetPhase() local
852 phase = host->tuningPhase; in SdhciSetPhase()
855 phase = host->tuningPhase; in SdhciSetPhase()
858 phase = SDHCI_SAMPLE_PHASE; in SdhciSetPhase()
861 phase = SDHCI_SAMPLE_PHASE; in SdhciSetPhase()
864 phase = 0; in SdhciSetPhase()
[all …]
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| D | sdhci.h | 152 #define SDHCI_SAMPLB_SEL(phase) ((phase) << 0) argument
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| /device/board/hisilicon/hispark_aries/liteos_a/board/include/hisoc/ |
| D | mmc.h | 85 #define SDIO_SAMPLB_SEL(phase) ((phase) << 0) argument
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| /device/board/isoftstone/zhiyuan/bootloader/configs/default/linux-5.10/ |
| D | rp-lcd-rgb-7-1024-600.dtsi | 156 ;lcd_io_phase: 0:noraml; 1:intert phase(0~3bit: vsync phase; 4~7bit:hsync phase;
157 ; 8~11bit:dclk phase; 12~15bit:de phase)
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| /device/soc/esp/esp32/components/hal/ |
| D | dac_hal.c | 21 dac_ll_cw_set_phase(cw->en_ch, cw->phase); in dac_hal_cw_generator_config()
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| /device/soc/hpmicro/sdk/hpm_sdk/middleware/hpm_mcl/inc/ |
| D | hpm_bldc_block_func.h | 15 uint8_t bldc_block_step_get(bldc_hall_phase_t phase, uint8_t hall_u, uint8_t hall_v, uint8_t hall_w…
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| /device/soc/esp/esp32/components/hal/include/hal/ |
| D | dac_types.h | 58 dac_cw_phase_t phase; /*!< Set the phase of the cosine wave generator output. */ member
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/include/driver/hal/ |
| D | hal_spi_types.h | 108 spi_phase_t phase; /**< SPI clock phase */ member
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| /device/soc/hisilicon/common/platform/mmc/himci_v200/ |
| D | himci.c | 982 uint32_t phase; in HimciCfgPhase() local
987 phase = DRV_PHASE_135 | SMP_PHASE_0; in HimciCfgPhase()
989 phase = DRV_PHASE_180 | SMP_PHASE_45; in HimciCfgPhase()
991 phase = DRV_PHASE_180 | SMP_PHASE_0; in HimciCfgPhase()
995 phase = DRV_PHASE_135 | SMP_PHASE_0; in HimciCfgPhase()
997 phase = DRV_PHASE_90 | SMP_PHASE_0; in HimciCfgPhase()
999 phase = DRV_PHASE_180 | SMP_PHASE_45; in HimciCfgPhase()
1001 phase = DRV_PHASE_135 | SMP_PHASE_45; in HimciCfgPhase()
1003 phase = DRV_PHASE_180 | SMP_PHASE_0; in HimciCfgPhase()
1009 value |= phase; in HimciCfgPhase()
[all …]
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| /device/board/unionman/unionpi_tiger/kernel/drivers/isp/drivers/v4l2_dev/src/platform/ |
| D | system_am_sc.c | 198 u16 phase; member
303 vphase->phase = in f2v_get_vertical_phase()
313 vphase->phase = (offset_out - offset_in) >> 2; in f2v_get_vertical_phase()
448 top_vphase = vphase.phase; in isp_sc_setting()
458 top_vphase = vphase.phase; in isp_sc_setting()
465 bot_vphase = vphase.phase; in isp_sc_setting()
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| /device/board/openvalley/niobeu4/liteos_m/arch/ |
| D | los_arch_interrupt.h | 226 UINT16 phase; member
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/soc/common/hal/ |
| D | spi_hal.c | 92 spi_ll_set_cpha(hal->hw, config->phase); in spi_hal_configure()
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| /device/soc/winnermicro/wm800/board/src/bt/blehost/nimble/host/mesh/src/ |
| D | cfg_srv.c | 2560 u16_t idx, u8_t phase, u8_t status) in send_krp_status() argument
2566 net_buf_simple_add_u8(msg, phase); in send_krp_status()
2599 u8_t phase; in krp_set() local
2602 phase = net_buf_simple_pull_u8(buf); in krp_set()
2608 BT_DBG("idx 0x%04x transition 0x%02x", idx, phase); in krp_set()
2615 BT_DBG("%u -> %u", sub->kr_phase, phase); in krp_set()
2616 if (phase < BT_MESH_KR_PHASE_2 || phase > BT_MESH_KR_PHASE_3 || in krp_set()
2618 phase == BT_MESH_KR_PHASE_2)) { in krp_set()
2619 BT_WARN("Prohibited transition %u -> %u", sub->kr_phase, phase); in krp_set()
2623 phase == BT_MESH_KR_PHASE_2) { in krp_set()
[all …]
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/driver/flash/ |
| D | flash_bypass.c | 49 config.phase = 1; in flash_bypass_init()
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| /device/board/unionman/unionpi_tiger/kernel/drivers/media/drivers/include/linux/amlogic/media/video_sink/ |
| D | vpp.h | 75 u8 phase; member
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| /device/board/unionman/unionpi_tiger/kernel/drivers/media/drivers/include/linux/amlogic/media/frame_provider/tvin/ |
| D | tvin.h | 403 unsigned short phase; /* phase is 0~31, it is absolute value */ member
|