| /device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/csf/ |
| D | mali_gpu_csf_registers.h | 242 #define CS_REQ_STATE_GET(reg_val) (((reg_val)&CS_REQ_STATE_MASK) >> CS_REQ_STATE_SHIFT) argument
243 #define CS_REQ_STATE_SET(reg_val, value) … argument
244 (((reg_val) & ~CS_REQ_STATE_MASK) | (((value) << CS_REQ_STATE_SHIFT) & CS_REQ_STATE_MASK))
251 #define CS_REQ_EXTRACT_EVENT_GET(reg_val) (((reg_val)&CS_REQ_EXTRACT_EVENT_MASK) >> CS_REQ_EXTRACT_… argument
252 #define CS_REQ_EXTRACT_EVENT_SET(reg_val, value) … argument
253 …(((reg_val) & ~CS_REQ_EXTRACT_EVENT_MASK) | (((value) << CS_REQ_EXTRACT_EVENT_SHIFT) & CS_REQ_EXTR…
260 #define CS_REQ_ERROR_MODE_GET(reg_val) (((reg_val)&CS_REQ_ERROR_MODE_MASK) >> CS_REQ_ERROR_MODE_SHI… argument
261 #define CS_REQ_ERROR_MODE_SET(reg_val, value) … argument
262 …(((reg_val) & ~CS_REQ_ERROR_MODE_MASK) | (((value) << CS_REQ_ERROR_MODE_SHIFT) & CS_REQ_ERROR_MODE…
266 #define CS_REQ_IDLE_SYNC_WAIT_GET(reg_val) (((reg_val)&CS_REQ_IDLE_SYNC_WAIT_MASK) >> CS_REQ_IDLE_S… argument
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/csf/ |
| D | mali_gpu_csf_registers.h | 255 #define GLB_VERSION_PATCH_GET(reg_val) (((reg_val)&GLB_VERSION_PATCH_MASK) >> GLB_VERSION_PATCH_SHI… argument
256 #define GLB_VERSION_PATCH_SET(reg_val, value) \ argument
257 …(((reg_val) & ~GLB_VERSION_PATCH_MASK) | (((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH…
260 #define GLB_VERSION_MINOR_GET(reg_val) (((reg_val)&GLB_VERSION_MINOR_MASK) >> GLB_VERSION_MINOR_SHI… argument
261 #define GLB_VERSION_MINOR_SET(reg_val, value) \ argument
262 …(((reg_val) & ~GLB_VERSION_MINOR_MASK) | (((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR…
265 #define GLB_VERSION_MAJOR_GET(reg_val) (((reg_val)&GLB_VERSION_MAJOR_MASK) >> GLB_VERSION_MAJOR_SHI… argument
266 #define GLB_VERSION_MAJOR_SET(reg_val, value) \ argument
267 …(((reg_val) & ~GLB_VERSION_MAJOR_MASK) | (((value) << GLB_VERSION_MAJOR_SHIFT) & GLB_VERSION_MAJOR…
272 #define CS_REQ_STATE_GET(reg_val) (((reg_val)&CS_REQ_STATE_MASK) >> CS_REQ_STATE_SHIFT) argument
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| /device/soc/winnermicro/wm800/board/platform/drivers/spi/ |
| D | wm_spi_hal.h | 41 u32 reg_val; in spi_set_mode() local
43 reg_val = tls_reg_read32(HR_SPI_SPICFG_REG); in spi_set_mode()
47 reg_val &= ~(0x03U); in spi_set_mode()
48 reg_val |= (SPI_SET_CPOL(0) | SPI_SET_CPHA(0)); in spi_set_mode()
52 reg_val &= ~(0x03U); in spi_set_mode()
53 reg_val |= (SPI_SET_CPOL(0) | SPI_SET_CPHA(1)); in spi_set_mode()
57 reg_val &= ~(0x03U); in spi_set_mode()
58 reg_val |= (SPI_SET_CPOL(1) | SPI_SET_CPHA(0)); in spi_set_mode()
62 reg_val &= ~(0x03U); in spi_set_mode()
63 reg_val |= (SPI_SET_CPOL(1) | SPI_SET_CPHA(1)); in spi_set_mode()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/usb/sunxi_usb/usbc/ |
| D | usbc.c | 32 __u8 reg_val = 0; in USBC_GetVbusStatus() local
37 reg_val = USBC_Readb(USBC_REG_DEVCTL(usbc_otg->base_addr)); in USBC_GetVbusStatus()
38 reg_val = reg_val >> USBC_BP_DEVCTL_VBUS; in USBC_GetVbusStatus()
39 switch (reg_val & 0x03) { in USBC_GetVbusStatus()
545 __u32 reg_val = 0; in USBC_SelectBus() local
550 reg_val = USBC_Readb(USBC_REG_VEND0(usbc_otg->base_addr)); in USBC_SelectBus()
553 reg_val |= ((ep_index - 0x01) << 1) in USBC_SelectBus()
555 reg_val |= 0x1<<USBC_BP_VEND0_BUS_SEL; /* io_dma */ in USBC_SelectBus()
557 reg_val |= ((ep_index << 1) - 0x01) in USBC_SelectBus()
559 reg_val |= 0x1<<USBC_BP_VEND0_BUS_SEL; in USBC_SelectBus()
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| D | usbc_phy.c | 57 __u32 reg_val = 0; in USBC_PHY_GetCommonConfig() local
59 return reg_val; in USBC_PHY_GetCommonConfig()
169 __u32 reg_val = 0; in UsbPhyCtl() local
171 reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL); in UsbPhyCtl()
172 reg_val |= (0x01 << USBC_PHY_CTL_VBUSVLDEXT); in UsbPhyCtl()
173 USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL)); in UsbPhyCtl()
178 __u32 reg_val = 0; in USBC_PHY_Set_Ctl() local
180 reg_val = USBC_Readl(regs + USBPHYC_REG_o_PHYCTL); in USBC_PHY_Set_Ctl()
181 reg_val |= (0x01 << mask); in USBC_PHY_Set_Ctl()
182 USBC_Writel(reg_val, (regs + USBPHYC_REG_o_PHYCTL)); in USBC_PHY_Set_Ctl()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/g2d/g2d_legacy/ |
| D | g2d_bsp_sun8iw11.c | 602 __u32 reg_val = 0; in mixer_get_irq() local
604 reg_val = read_wvalue(G2D_STATUS_REG); in mixer_get_irq()
606 return reg_val; in mixer_get_irq()
611 __u32 reg_val = 0; in mixer_get_irq0() local
613 reg_val = read_wvalue(G2D_CMDQ_STS_REG); in mixer_get_irq0()
615 return reg_val; in mixer_get_irq0()
662 __u32 reg_val = 0; in mixer_fillrectangle() local
674 reg_val |= (para->alpha << 24) | 0x4; in mixer_fillrectangle()
676 reg_val |= (para->alpha << 24) | 0x8; in mixer_fillrectangle()
677 reg_val |= 0x1; in mixer_fillrectangle()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_sun8iw8/ |
| D | de_clock.c | 28 u32 reg_val; in de_clk_set_div() local
32 reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
33 reg_val = in de_clk_set_div()
35 de_clk_tbl[i].mod_div_width, reg_val, in de_clk_set_div()
37 writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
51 u32 reg_val; in __de_clk_enable() local
61 reg_val = in __de_clk_enable()
64 reg_val = in __de_clk_enable()
67 reg_val, 1); in __de_clk_enable()
68 writel(reg_val, in __de_clk_enable()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/ |
| D | de_clock.c | 26 u32 reg_val; in de_clk_set_div() local
30 reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
31 reg_val = SET_BITS(de_clk_tbl[i].mod_div_shift, de_clk_tbl[i].mod_div_width, reg_val, (div - 1)); in de_clk_set_div()
32 writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
46 u32 reg_val; in __de_clk_enable() local
55 reg_val = readl(de_clk_tbl[i].ahb_reset_adr + de_base); in __de_clk_enable()
56 reg_val = SET_BITS(de_clk_tbl[i].ahb_reset_shift, 1, reg_val, 1); in __de_clk_enable()
57 writel(reg_val, de_clk_tbl[i].ahb_reset_adr + de_base); in __de_clk_enable()
62 reg_val = readl(de_clk_tbl[i].ahb_gate_adr + de_base); in __de_clk_enable()
63 reg_val = SET_BITS(de_clk_tbl[i].ahb_gate_shift, 1, reg_val, 1); in __de_clk_enable()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v33x/de330/ |
| D | de_top.c | 107 u32 reg_val = en & 0x1; in __de_mbus_clk_enable() local
109 writel(reg_val, de_base + DE_MBUS_CLOCK_ADDR); in __de_mbus_clk_enable()
115 u32 reg_val; in __de_clk_enable() local
119 reg_val = readl(reg_base); in __de_clk_enable()
120 reg_val = SET_BITS(para->ahb_reset_shift, para->ahb_reset_width, in __de_clk_enable()
121 reg_val, val); in __de_clk_enable()
122 writel(reg_val, reg_base); in __de_clk_enable()
126 reg_val = readl(reg_base); in __de_clk_enable()
127 reg_val = SET_BITS(para->mod_en_shift, para->mod_en_width, in __de_clk_enable()
128 reg_val, val); in __de_clk_enable()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v3x/ |
| D | de_clock.c | 70 u32 reg_val; in de_clk_set_div() local
75 reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
76 reg_val = in de_clk_set_div()
78 de_clk_tbl[i].mod_div_width, reg_val, in de_clk_set_div()
80 writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
94 u32 reg_val; in __de_clk_enable() local
103 reg_val = readl(de_clk_tbl[i].ahb_reset_adr in __de_clk_enable()
105 reg_val = in __de_clk_enable()
107 reg_val, 1); in __de_clk_enable()
108 writel(reg_val, in __de_clk_enable()
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| /device/soc/rockchip/rk3588/kernel/include/uapi/gpu/arm/bifrost/gpu/ |
| D | mali_kbase_gpu_regmap.h | 284 #define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \ argument
285 (((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
290 #define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \ argument
291 (((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
300 #define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \ argument
301 (((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT)
306 #define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \ argument
307 (((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \
353 #define AS_LOCKADDR_LOCKADDR_SIZE_GET(reg_val) \ argument
354 (((reg_val)&AS_LOCKADDR_LOCKADDR_SIZE_MASK) >> \
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/video/sunxi/disp2/disp/de/lowlevel_v2x/ |
| D | de_clock.c | 87 u32 reg_val; in de_clk_set_div() local
93 reg_val = readl(de_clk_tbl[i].mod_div_adr + de1_base); in de_clk_set_div()
94 reg_val = in de_clk_set_div()
96 de_clk_tbl[i].mod_div_width, reg_val, in de_clk_set_div()
98 writel(reg_val, de_clk_tbl[i].mod_div_adr + de1_base); in de_clk_set_div()
106 reg_val = readl(de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
107 reg_val = in de_clk_set_div()
109 de_clk_tbl[i].mod_div_width, reg_val, in de_clk_set_div()
111 writel(reg_val, de_clk_tbl[i].mod_div_adr + de_base); in de_clk_set_div()
125 u32 reg_val; in __de_clk_enable() local
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| D | de_eink.c | 108 unsigned reg_val = 0; in eink_irq_query() local
110 reg_val = EINK_RUINT32(ee_base + EE_IRQ); in eink_irq_query()
111 dec_irq = reg_val&0x1; in eink_irq_query()
112 idx_irq = reg_val&0x2; in eink_irq_query()
115 EINK_WUINT32(reg_val&0x1d, ee_base + EE_IRQ); in eink_irq_query()
119 EINK_WUINT32(reg_val&0x1e, ee_base + EE_IRQ); in eink_irq_query()
128 unsigned reg_val = 0; in eink_irq_query_index() local
130 reg_val = EINK_RUINT32(ee_base + EE_IRQ); in eink_irq_query_index()
131 idx_irq = reg_val&0x2; in eink_irq_query_index()
134 EINK_WUINT32(reg_val&0x1e, ee_base + EE_IRQ); in eink_irq_query_index()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/gpadc/ |
| D | sunxi_gpadc.c | 95 u32 reg_val = 0, ldoa; in sunxi_gpadc_check_vin() local
97 reg_val = readl(vaddr); in sunxi_gpadc_check_vin()
99 if (reg_val > 0) { in sunxi_gpadc_check_vin()
100 if ((reg_val & 0x80) == 0x80) in sunxi_gpadc_check_vin()
101 ldoa = (reg_val & 0x7f) + 1800; in sunxi_gpadc_check_vin()
103 ldoa = (reg_val & 0x7f) + 1700; in sunxi_gpadc_check_vin()
127 u32 div, reg_val; in sunxi_gpadc_sample_rate_set() local
132 reg_val = readl(reg_base + GP_SR_REG); in sunxi_gpadc_sample_rate_set()
133 reg_val &= ~GP_SR_CON; in sunxi_gpadc_sample_rate_set()
134 reg_val |= (div << 16); in sunxi_gpadc_sample_rate_set()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/usb/sunxi_usb/misc/ |
| D | sunxi_usb_debug.c | 172 __u32 reg_val = 0; in clear_usb_reg() local
176 reg_val = USBC_Readl(USBC_REG_EX_USB_GCS(usb_base)); in clear_usb_reg()
177 reg_val = 0x20; in clear_usb_reg()
178 USBC_Writel(reg_val, USBC_REG_EX_USB_GCS(usb_base)); in clear_usb_reg()
181 reg_val = USBC_Readl(USBC_REG_EX_USB_EPINTF(usb_base)); in clear_usb_reg()
182 reg_val = 0x44; in clear_usb_reg()
183 USBC_Writel(reg_val, USBC_REG_EX_USB_EPINTF(usb_base)); in clear_usb_reg()
186 reg_val = USBC_Readl(USBC_REG_EX_USB_EPINTE(usb_base)); in clear_usb_reg()
187 reg_val = 0x48; in clear_usb_reg()
188 USBC_Writel(reg_val, USBC_REG_EX_USB_EPINTE(usb_base)); in clear_usb_reg()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/io/ |
| D | hi_flashboot_io.c | 40 hi_u32 reg_val = 0; in hi_io_get_func() local
42 hi_reg_read(reg_addr, reg_val); in hi_io_get_func()
43 *val = (hi_u8)reg_val; in hi_io_get_func()
52 hi_u32 reg_val = 0; in hi_io_get_pull() local
53 …hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shi… in hi_io_get_pull()
54 *val = (hi_io_pull) ((reg_val >> IO_DRV_PULL_START_BIT) & IO_DRV_PULL_MASK); in hi_io_get_pull()
64 hi_u32 reg_val = 0; in hi_io_set_driver_strength() local
70 …hi_reg_read((HI_IOCFG_REG_BASE + IO_CTRL_REG_BASE_ADDR + ((hi_u32)id << 2)), reg_val); /* lift shi… in hi_io_set_driver_strength()
71 reg_val &= ~(IO_DRV_STRENGTH_MASK << IO_DRV_STRENGTH_START_BIT); in hi_io_set_driver_strength()
72 reg_val |= ((hi_u32) val & IO_DRV_STRENGTH_MASK) << IO_DRV_STRENGTH_START_BIT; in hi_io_set_driver_strength()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/spi/ |
| D | spi.c | 29 hi_u16 reg_val = 0; in spi_check_rx_fifo_empty() local
30 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_rx_fifo_empty()
31 if (reg_val & MASK_SPI_SR_RNE) { in spi_check_rx_fifo_empty()
39 hi_u16 reg_val = 0; in spi_check_busy() local
40 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_busy()
41 if (reg_val & MASK_SPI_SR_BSY) { in spi_check_busy()
49 hi_u16 reg_val = 0; in spi_check_write_timeout() local
52 hi_reg_read16(reg_base + REG_SPI_SR, reg_val); in spi_check_write_timeout()
53 if ((reg_val & MASK_SPI_SR_TFE) && (!(reg_val & MASK_SPI_SR_BSY))) { in spi_check_write_timeout()
68 hi_u16 reg_val = 0; in spi_check_tnf_timeout() local
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/i2c/ |
| D | i2c-sunxi.c | 439 u32 reg_val = readl(base_addr + I2C_CNTR); in sunxi_i2c_engine_clear_irq() local
442 reg_val |= INT_FLAG; in sunxi_i2c_engine_clear_irq()
443 reg_val &= ~(M_STA | M_STP); in sunxi_i2c_engine_clear_irq()
445 writel(reg_val, base_addr + I2C_CNTR); in sunxi_i2c_engine_clear_irq()
459 unsigned int reg_val; in sunxi_i2c_engine_put_byte() local
461 reg_val = *buffer & I2C_DATA_MASK; in sunxi_i2c_engine_put_byte()
462 writel(reg_val, i2c->base_addr + I2C_DATA); in sunxi_i2c_engine_put_byte()
464 dev_dbg(i2c->dev, "engine-mode: data 0x%x xfered\n", reg_val); in sunxi_i2c_engine_put_byte()
469 unsigned int reg_val = readl(base_addr + I2C_CNTR); in sunxi_i2c_engine_enable_irq() local
476 reg_val |= INT_EN; in sunxi_i2c_engine_enable_irq()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/emac/ |
| D | sun4i-emac.c | 264 unsigned int reg_val; in emac_update_speed() local
267 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
268 reg_val &= ~(0x1 << 8); in emac_update_speed()
270 reg_val |= 1 << 8; in emac_update_speed()
271 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
277 unsigned int reg_val; in emac_update_duplex() local
280 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
281 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
283 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
284 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/boot/flashboot/drivers/gpio/ |
| D | hi_flashboot_gpio.c | 38 hi_u16 reg_val = 0; in hi_gpio_get_dir() local
40 hi_reg_read16((HI_GPIO_REG_BASE + GPIO_SWPORT_DDR), reg_val); in hi_gpio_get_dir()
41 hi_io_dir_get(reg_val, (hi_u16) id, dir); in hi_gpio_get_dir()
52 hi_u16 reg_val = 0; in hi_gpio_get_output_val() local
54 hi_reg_read16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_get_output_val()
55 hi_io_val_get(reg_val, (hi_u16) id, val); in hi_gpio_get_output_val()
66 hi_u16 reg_val = 0; in hi_gpio_set_output_val() local
68 hi_reg_read16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_set_output_val()
69 hi_io_val_set(val, (hi_u16) id, reg_val); in hi_gpio_set_output_val()
70 hi_reg_write16((HI_GPIO_REG_BASE + GPIO_SWPORT_DR), reg_val); in hi_gpio_set_output_val()
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| /device/board/isoftstone/zhiyuan/kernel/driver/drivers/spi/ |
| D | spi-sunxi.c | 209 u32 reg_val = readl(base_addr + SPI_DBI_INT_REG); in dbi_disable_irq() local
212 reg_val &= ~bitmap; in dbi_disable_irq()
213 writel(reg_val, base_addr + SPI_DBI_INT_REG); in dbi_disable_irq()
218 u32 reg_val = readl(base_addr + SPI_DBI_INT_REG); in dbi_enable_irq() local
222 reg_val |= bitmap; in dbi_enable_irq()
223 writel(reg_val, base_addr + SPI_DBI_INT_REG); in dbi_enable_irq()
295 u32 reg_val = 0; in spi_config_dbi() local
302 reg_val |= DBI_CR_READ; in spi_config_dbi()
307 reg_val &= ~DBI_CR_READ; in spi_config_dbi()
311 reg_val |= DBI_CR_LSB_FIRST; in spi_config_dbi()
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/platform/vexpress/ |
| D | mali_kbase_cpu_vexpress.c | 83 u32 reg_val = 0; in kbase_get_vexpress_cpu_clock_speed() local
115 reg_val = readl(syscfg_reg + SYS_CFGCTRL_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
118 if (reg_val & SYS_CFGCTRL_START_BIT_VALUE) { in kbase_get_vexpress_cpu_clock_speed()
138 reg_val = readl(syscfg_reg + SYS_CFGSTAT_OFFSET); in kbase_get_vexpress_cpu_clock_speed()
140 if (reg_val & SYS_CFG_ERROR_BIT_VALUE) { in kbase_get_vexpress_cpu_clock_speed()
148 reg_val = readl(scc_reg); in kbase_get_vexpress_cpu_clock_speed()
157 if (IS_SINGLE_BIT_SET(reg_val, 0)) { in kbase_get_vexpress_cpu_clock_speed()
160 pa_divide = ((reg_val & (FEED_REG_BIT_MASK << in kbase_get_vexpress_cpu_clock_speed()
164 pb_divide = ((reg_val & (FEED_REG_BIT_MASK << in kbase_get_vexpress_cpu_clock_speed()
168 } else if (IS_SINGLE_BIT_SET(reg_val, 1)) { in kbase_get_vexpress_cpu_clock_speed()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/pwm/ |
| D | hi_pwm.c | 36 hi_u16 reg_val; in hi_pwm_init() local
43 hi_reg_read16(CLDO_CTL_CLKEN1_REG, reg_val); in hi_pwm_init()
47 reg_val |= 1 << CLKEN1_PWM0; in hi_pwm_init()
51 reg_val |= 1 << CLKEN1_PWM1; in hi_pwm_init()
55 reg_val |= 1 << CLKEN1_PWM2; in hi_pwm_init()
59 reg_val |= 1 << CLKEN1_PWM3; in hi_pwm_init()
63 reg_val |= 1 << CLKEN1_PWM4; in hi_pwm_init()
67 reg_val |= 1 << CLKEN1_PWM5; in hi_pwm_init()
73 reg_val |= (1 << CLKEN1_PWM_BUS) | (1 << CLKEN1_PWM); in hi_pwm_init()
74 hi_reg_write16(CLDO_CTL_CLKEN1_REG, reg_val); /* enable pwmx clk bus */ in hi_pwm_init()
[all …]
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| /device/soc/beken/bk7235/liteos_m/bk_sdk_armino/middleware/driver/sys_ctrl/ |
| D | sys_ctrl.c | 254 UINT32 reg_val; in clock_dco_cali() local
259 reg_val = sys_drv_analog_get(ANALOG_REG1); in clock_dco_cali()
260 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI)); in clock_dco_cali()
261 reg_val |= ((0x127 & DCO_CNTI_MASK) << DCO_CNTI_POSI); in clock_dco_cali()
262 reg_val |= DIV_BYPASS_BIT; in clock_dco_cali()
263 sys_drv_analog_set(ANALOG_REG1, reg_val); in clock_dco_cali()
268 reg_val = sys_drv_analog_get(ANALOG_REG1); in clock_dco_cali()
269 reg_val &= ~((DCO_CNTI_MASK << DCO_CNTI_POSI) | (DCO_DIV_MASK << DCO_DIV_POSI)); in clock_dco_cali()
270 reg_val |= ((0xDD & DCO_CNTI_MASK) << DCO_CNTI_POSI); in clock_dco_cali()
272 reg_val |= DIV_BYPASS_BIT; in clock_dco_cali()
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| /device/soc/hisilicon/hi3861v100/sdk_liteos/platform/drivers/i2c/ |
| D | i2c.c | 87 hi_u32 reg_val = 0; in i2c_wait() local
90 hi_reg_read32((i2c_base(id) + I2C_SR), reg_val); in i2c_wait()
91 while ((!(reg_val & I2C_INT_DONE)) && (time_out < g_i2c_ctrl[id].timeout_us)) { in i2c_wait()
94 hi_reg_read32((i2c_base(id) + I2C_SR), reg_val); in i2c_wait()
103 if (I2C_ACK_INTR & reg_val) { in i2c_wait()
107 hi_reg_read32((i2c_base(id) + I2C_ICR), reg_val); in i2c_wait()
108 hi_reg_write32((i2c_base(id) + I2C_ICR), (reg_val | I2C_CLEAR_OVER)); in i2c_wait()
115 hi_u32 reg_val = 0; in i2c_cfg_clk() local
119 hi_reg_read32((i2c_base(id) + I2C_CTRL), reg_val); in i2c_cfg_clk()
122 hi_reg_write32((i2c_base(id) + I2C_CTRL), (reg_val & (~I2C_UNMASK_ALL))); in i2c_cfg_clk()
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