1 /*
2 * Copyright (c) 2022 Winner Microelectronics Co., Ltd. All rights reserved.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 /*****************************************************************************
17 *
18 * File Name : wm_spi_hal.h
19 *
20 * Description: host spi Driver Module
21 *
22 * Copyright (c) 2014 Winner Microelectronics Co., Ltd.
23 * All rights reserved.
24 *
25 * Author : dave
26 *
27 * Date : 2014-6-6
28 *****************************************************************************/
29 #ifndef __WM_SPI_HAL_H__
30 #define __WM_SPI_HAL_H__
31
32 #include "wm_regs.h"
33 #include "list.h"
34 #include "wm_hostspi.h"
35 #include "wm_cpu.h"
36
37 static __inline void spi_set_mode(u8 mode);
38
spi_set_mode(u8 mode)39 static __inline void spi_set_mode(u8 mode)
40 {
41 u32 reg_val;
42
43 reg_val = tls_reg_read32(HR_SPI_SPICFG_REG);
44
45 switch (mode) {
46 case TLS_SPI_MODE_0:
47 reg_val &= ~(0x03U);
48 reg_val |= (SPI_SET_CPOL(0) | SPI_SET_CPHA(0));
49 break;
50
51 case TLS_SPI_MODE_1:
52 reg_val &= ~(0x03U);
53 reg_val |= (SPI_SET_CPOL(0) | SPI_SET_CPHA(1));
54 break;
55
56 case TLS_SPI_MODE_2:
57 reg_val &= ~(0x03U);
58 reg_val |= (SPI_SET_CPOL(1) | SPI_SET_CPHA(0));
59 break;
60
61 case TLS_SPI_MODE_3:
62 reg_val &= ~(0x03U);
63 reg_val |= (SPI_SET_CPOL(1) | SPI_SET_CPHA(1));
64 break;
65
66 default:
67 break;
68 }
69
70 tls_reg_write32(HR_SPI_SPICFG_REG, reg_val);
71 }
72
spi_set_endian(u8 endian)73 static __inline void spi_set_endian(u8 endian)
74 {
75 u32 reg_val;
76
77 reg_val = tls_reg_read32(HR_SPI_SPICFG_REG);
78
79 if (endian == 0) {
80 reg_val &= ~(0x01U << 3);
81 reg_val |= SPI_LITTLE_ENDIAN;
82 } else if (endian == 1) {
83 reg_val &= ~(0x01U << 3);
84 reg_val |= SPI_BIG_ENDIAN;
85 }
86
87 tls_reg_write32(HR_SPI_SPICFG_REG, reg_val);
88 }
89
spi_set_chipselect_mode(u8 cs_active)90 static __inline void spi_set_chipselect_mode(u8 cs_active)
91 {
92 u32 reg_val;
93
94 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
95
96 if (cs_active == 0) {
97 reg_val &= ~(0x01U << 2);
98 reg_val |= SPI_CS_LOW;
99 } else if (cs_active == 1) {
100 reg_val &= ~(0x01U << 2);
101 reg_val |= SPI_CS_HIGH;
102 }
103
104 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
105 }
106
spi_clear_fifo(void)107 static __inline void spi_clear_fifo(void)
108 {
109 u32 reg_val;
110
111 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
112
113 reg_val |= SPI_CLEAR_FIFOS;
114
115 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
116 }
117
spi_set_rx_channel(u8 on_off)118 static __inline void spi_set_rx_channel(u8 on_off)
119 {
120 u32 reg_val;
121
122 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
123
124 if (on_off == 0) {
125 reg_val &= ~(0x01U << 20);
126 reg_val |= SPI_RX_CHANNEL_OFF;
127 } else if (on_off == 1) {
128 reg_val &= ~(0x01U << 20);
129 reg_val |= SPI_RX_CHANNEL_ON;
130 }
131
132 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
133 }
134
spi_set_tx_channel(u8 on_off)135 static __inline void spi_set_tx_channel(u8 on_off)
136 {
137 u32 reg_val;
138
139 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
140
141 if (on_off == 0) {
142 reg_val &= ~(0x01U << 19);
143 reg_val |= SPI_TX_CHANNEL_OFF;
144 } else if (on_off == 1) {
145 reg_val &= ~(0x01U << 19);
146 reg_val |= SPI_TX_CHANNEL_ON;
147 }
148
149 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
150 }
151
spi_set_sclk_length(u16 sclk_num,u8 invalid_rx_sclk_num)152 static __inline void spi_set_sclk_length(u16 sclk_num, u8 invalid_rx_sclk_num)
153 {
154 u32 reg_val;
155
156 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
157
158 reg_val &= ~((0xffU << 23) | (0xffff << 3));
159 reg_val |= SPI_VALID_CLKS_NUM(sclk_num) | SPI_RX_INVALID_BITS(invalid_rx_sclk_num);
160
161 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
162 }
163
spi_force_cs_out(u8 enable)164 static __inline void spi_force_cs_out(u8 enable)
165 {
166 u32 reg_val;
167
168 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
169
170 if (enable) {
171 reg_val |= SPI_FORCE_SPI_CS_OUT;
172 } else {
173 reg_val &= ~SPI_FORCE_SPI_CS_OUT;
174 }
175
176 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
177 }
178
spi_sclk_start(void)179 static __inline void spi_sclk_start(void)
180 {
181 u32 reg_val;
182
183 reg_val = tls_reg_read32(HR_SPI_CHCFG_REG);
184
185 reg_val |= SPI_START;
186
187 tls_reg_write32(HR_SPI_CHCFG_REG, reg_val);
188 }
189
spi_set_sclk(u32 fclk)190 static __inline void spi_set_sclk(u32 fclk)
191 {
192 u32 reg_val;
193 tls_sys_clk sysclk;
194
195 tls_sys_clk_get(&sysclk);
196
197 reg_val = tls_reg_read32(HR_SPI_CLKCFG_REG);
198
199 reg_val &= ~(0xffffU);
200 reg_val |= sysclk.apbclk*UNIT_MHZ/(fclk*2) - 1;
201
202 tls_reg_write32(HR_SPI_CLKCFG_REG, reg_val);
203 }
204
spi_set_tx_trigger_level(u8 level)205 static __inline void spi_set_tx_trigger_level(u8 level)
206 {
207 u32 reg_val;
208
209 reg_val = tls_reg_read32(HR_SPI_MODECFG_REG);
210
211 reg_val &= ~(0x07U << 2);
212 reg_val |= SPI_TX_TRIGGER_LEVEL(level);
213
214 tls_reg_write32(HR_SPI_MODECFG_REG, reg_val);
215 }
216
spi_set_rx_trigger_level(u8 level)217 static __inline void spi_set_rx_trigger_level(u8 level)
218 {
219 u32 reg_val;
220
221 reg_val = tls_reg_read32(HR_SPI_MODECFG_REG);
222
223 reg_val &= ~(0x07U << 6);
224 reg_val |= SPI_RX_TRIGGER_LEVEL(level);
225
226 tls_reg_write32(HR_SPI_MODECFG_REG, reg_val);
227 }
spi_get_busy_status(void)228 static __inline uint8_t spi_get_busy_status(void)
229 {
230 u32 reg_val;
231
232 reg_val = tls_reg_read32(HR_SPI_STATUS_REG);
233
234 return SPI_IS_BUSY(reg_val);
235 }
236
spi_set_timeout(u32 timeout,u8 enable)237 static __inline void spi_set_timeout(u32 timeout, u8 enable)
238 {
239 u32 reg_val;
240
241 reg_val = SPI_TIME_OUT(timeout);
242 reg_val |= enable ? SPI_TIMER_EN : 0;
243
244 tls_reg_write32(HR_SPI_TIMEOUT_REG, reg_val);
245 }
246
spi_get_status(u8 * busy,u8 * rx_fifo_level,u8 * tx_fifo_level)247 static __inline void spi_get_status(u8 *busy, u8 *rx_fifo_level, u8 *tx_fifo_level)
248 {
249 u32 reg_val;
250
251 reg_val = tls_reg_read32(HR_SPI_STATUS_REG);
252
253 if (busy) {*busy = SPI_IS_BUSY(reg_val);}
254 if (rx_fifo_level) {*rx_fifo_level = SPI_GET_RX_FIFO_CNT(reg_val);}
255 if (tx_fifo_level) {*tx_fifo_level = 32 - SPI_GET_TX_FIFO_CNT(reg_val);}
256 }
257
spi_int_mask(void)258 static __inline u32 spi_int_mask(void)
259 {
260 u32 reg_val;
261
262 reg_val = tls_reg_read32(HR_SPI_INT_MASK_REG);
263
264 return reg_val & SPI_INT_MASK_ALL;
265 }
266
spi_mask_int(u32 mask)267 static __inline void spi_mask_int(u32 mask)
268 {
269 u32 reg_val;
270
271 reg_val = tls_reg_read32(HR_SPI_INT_MASK_REG);
272
273 reg_val |= mask & SPI_INT_MASK_ALL;
274
275 tls_reg_write32(HR_SPI_INT_MASK_REG, reg_val);
276 }
277
spi_unmask_int(u32 mask)278 static __inline void spi_unmask_int(u32 mask)
279 {
280 u32 reg_val;
281
282 reg_val = tls_reg_read32(HR_SPI_INT_MASK_REG);
283
284 reg_val &= ~(mask & SPI_INT_MASK_ALL);
285
286 tls_reg_write32(HR_SPI_INT_MASK_REG, reg_val);
287 }
288
spi_get_int_status(void)289 static __inline u32 spi_get_int_status(void)
290 {
291 u32 reg_val;
292
293 reg_val = tls_reg_read32(HR_SPI_INT_STATUS_REG);
294
295 return reg_val;
296 }
297
spi_clear_int_status(u32 int_srcs)298 static __inline void spi_clear_int_status(u32 int_srcs)
299 {
300 u32 reg_val;
301
302 reg_val = tls_reg_read32(HR_SPI_INT_STATUS_REG);
303
304 reg_val &= ~(int_srcs & SPI_INT_CLEAR_ALL);
305 reg_val |= int_srcs & SPI_INT_CLEAR_ALL;
306
307 tls_reg_write32(HR_SPI_INT_STATUS_REG, reg_val);
308 }
309
spi_data_put(u32 data)310 static __inline void spi_data_put(u32 data)
311 {
312 tls_reg_write32(HR_SPI_TXDATA_REG, data);
313 }
314
spi_data_get(void)315 static __inline u32 spi_data_get(void)
316 {
317 return tls_reg_read32(HR_SPI_RXDATA_REG);
318 }
319
320 #endif /* __WM_SPI_HAL_H__ */