| /kernel/linux/linux-5.10/drivers/spi/ |
| D | spi-qup.c | 156 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
172 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
174 return controller->n_words * controller->w_size; in spi_qup_len()
177 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
184 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
190 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
202 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
[all …]
|
| D | spi-pxa2xx-dma.c | 23 struct spi_message *msg = drv_data->controller->cur_msg; in pxa2xx_spi_dma_transfer_complete()
59 spi_finalize_current_transfer(drv_data->controller); in pxa2xx_spi_dma_transfer_complete()
74 spi_get_ctldata(drv_data->controller->cur_msg->spi); in pxa2xx_spi_dma_prepare_one()
102 chan = drv_data->controller->dma_tx; in pxa2xx_spi_dma_prepare_one()
109 chan = drv_data->controller->dma_rx; in pxa2xx_spi_dma_prepare_one()
130 dmaengine_terminate_async(drv_data->controller->dma_rx); in pxa2xx_spi_dma_transfer()
131 dmaengine_terminate_async(drv_data->controller->dma_tx); in pxa2xx_spi_dma_transfer()
171 dmaengine_terminate_async(drv_data->controller->dma_tx); in pxa2xx_spi_dma_prepare()
178 dma_async_issue_pending(drv_data->controller->dma_rx); in pxa2xx_spi_dma_start()
179 dma_async_issue_pending(drv_data->controller->dma_tx); in pxa2xx_spi_dma_start()
[all …]
|
| D | spi-fsl-lpspi.c | 174 static bool fsl_lpspi_can_dma(struct spi_controller *controller, in fsl_lpspi_can_dma() argument
180 if (!controller->dma_rx) in fsl_lpspi_can_dma()
197 static int lpspi_prepare_xfer_hardware(struct spi_controller *controller) in lpspi_prepare_xfer_hardware() argument
200 spi_controller_get_devdata(controller); in lpspi_prepare_xfer_hardware()
212 static int lpspi_unprepare_xfer_hardware(struct spi_controller *controller) in lpspi_unprepare_xfer_hardware() argument
215 spi_controller_get_devdata(controller); in lpspi_unprepare_xfer_hardware()
331 static int fsl_lpspi_dma_configure(struct spi_controller *controller) in fsl_lpspi_dma_configure() argument
337 spi_controller_get_devdata(controller); in fsl_lpspi_dma_configure()
357 ret = dmaengine_slave_config(controller->dma_tx, &tx); in fsl_lpspi_dma_configure()
368 ret = dmaengine_slave_config(controller->dma_rx, &rx); in fsl_lpspi_dma_configure()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
15 "fsl,b4420-l2-cache-controller"
16 "fsl,b4860-l2-cache-controller"
17 "fsl,bsc9131-l2-cache-controller"
18 "fsl,bsc9132-l2-cache-controller"
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/musb/ |
| D | musb_cppi41.c | 37 struct dma_controller controller; member
61 if (!is_host_active(cppi41_channel->controller->controller.musb)) in save_rx_toggle()
187 struct cppi41_dma_controller *controller; in cppi41_recheck_tx_req() local
193 controller = container_of(timer, struct cppi41_dma_controller, in cppi41_recheck_tx_req()
195 musb = controller->controller.musb; in cppi41_recheck_tx_req()
198 list_for_each_entry_safe(cppi41_channel, n, &controller->early_tx_list, in cppi41_recheck_tx_req()
210 if (!list_empty(&controller->early_tx_list) && in cppi41_recheck_tx_req()
211 !hrtimer_is_queued(&controller->early_tx)) { in cppi41_recheck_tx_req()
213 hrtimer_forward_now(&controller->early_tx, 20 * NSEC_PER_USEC); in cppi41_recheck_tx_req()
226 struct cppi41_dma_controller *controller; in cppi41_dma_callback() local
[all …]
|
| D | musbhsdma.c | 55 struct musb_dma_controller *controller; member
65 struct dma_controller controller; member
76 static void dma_controller_stop(struct musb_dma_controller *controller) in dma_controller_stop() argument
78 struct musb *musb = controller->private_data; in dma_controller_stop()
82 if (controller->used_channels != 0) { in dma_controller_stop()
83 dev_err(musb->controller, in dma_controller_stop()
87 if (controller->used_channels & (1 << bit)) { in dma_controller_stop()
88 channel = &controller->channel[bit].channel; in dma_controller_stop()
91 if (!controller->used_channels) in dma_controller_stop()
101 struct musb_dma_controller *controller = container_of(c, in dma_channel_allocate() local
[all …]
|
| D | ux500_dma.c | 32 struct ux500_dma_controller *controller; member
43 struct dma_controller controller; member
59 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", in ux500_dma_callback()
82 struct musb *musb = ux500_channel->controller->private_data; in ux500_configure_channel()
84 ux500_channel->controller->phy_base); in ux500_configure_channel()
86 dev_dbg(musb->controller, in ux500_configure_channel()
131 struct ux500_dma_controller *controller = container_of(c, in ux500_dma_channel_allocate() local
132 struct ux500_dma_controller, controller); in ux500_dma_channel_allocate()
134 struct musb *musb = controller->private_data; in ux500_dma_channel_allocate()
147 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : in ux500_dma_channel_allocate()
[all …]
|
| D | cppi_dma.c | 119 c->controller = cppi; in cppi_pool_init()
138 struct cppi *cppi = c->controller; in cppi_pool_free()
143 c->controller = NULL; in cppi_pool_free()
155 static void cppi_controller_start(struct cppi *controller) in cppi_controller_start() argument
161 for (i = 0; i < ARRAY_SIZE(controller->tx); i++) { in cppi_controller_start()
162 controller->tx[i].transmit = true; in cppi_controller_start()
163 controller->tx[i].index = i; in cppi_controller_start()
165 for (i = 0; i < ARRAY_SIZE(controller->rx); i++) { in cppi_controller_start()
166 controller->rx[i].transmit = false; in cppi_controller_start()
167 controller->rx[i].index = i; in cppi_controller_start()
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-zevio.c | 77 struct zevio_gpio *controller = gpiochip_get_data(chip); in zevio_gpio_get() local
80 spin_lock(&controller->lock); in zevio_gpio_get()
81 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION); in zevio_gpio_get()
83 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT); in zevio_gpio_get()
85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_get()
86 spin_unlock(&controller->lock); in zevio_gpio_get()
93 struct zevio_gpio *controller = gpiochip_get_data(chip); in zevio_gpio_set() local
96 spin_lock(&controller->lock); in zevio_gpio_set()
97 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT); in zevio_gpio_set()
103 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val); in zevio_gpio_set()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | exynos5410-pinctrl.dtsi | 13 gpio-controller;
16 interrupt-controller;
21 gpio-controller;
24 interrupt-controller;
29 gpio-controller;
32 interrupt-controller;
37 gpio-controller;
40 interrupt-controller;
45 gpio-controller;
48 interrupt-controller;
[all …]
|
| D | exynos5260-pinctrl.dtsi | 16 gpio-controller;
19 interrupt-controller;
24 gpio-controller;
27 interrupt-controller;
32 gpio-controller;
35 interrupt-controller;
40 gpio-controller;
43 interrupt-controller;
48 gpio-controller;
51 interrupt-controller;
[all …]
|
| D | exynos5420-pinctrl.dtsi | 16 gpio-controller;
19 interrupt-controller;
24 gpio-controller;
27 interrupt-controller;
35 gpio-controller;
38 interrupt-controller;
46 gpio-controller;
49 interrupt-controller;
54 gpio-controller;
57 interrupt-controller;
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/hotplug/ |
| D | pciehp.h | 85 struct controller { struct
157 void pciehp_request(struct controller *ctrl, int action);
158 void pciehp_handle_button_press(struct controller *ctrl);
159 void pciehp_handle_disable_request(struct controller *ctrl);
160 void pciehp_handle_presence_or_link_change(struct controller *ctrl, u32 events);
161 int pciehp_configure_device(struct controller *ctrl);
162 void pciehp_unconfigure_device(struct controller *ctrl, bool presence);
164 struct controller *pcie_init(struct pcie_device *dev);
165 int pcie_init_notification(struct controller *ctrl);
166 void pcie_shutdown_notification(struct controller *ctrl);
[all …]
|
| /kernel/linux/linux-5.10/drivers/mtd/spi-nor/controllers/ |
| D | aspeed-smc.c | 94 struct aspeed_smc_controller *controller; member
197 #define SEGMENT_ADDR_REG(controller, cs) \ argument
198 ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4)
258 return BIT(chip->controller->info->we0 + chip->cs); in aspeed_smc_chip_write_bit()
263 struct aspeed_smc_controller *controller = chip->controller; in aspeed_smc_chip_check_config() local
266 reg = readl(controller->regs + CONFIG_REG); in aspeed_smc_chip_check_config()
271 dev_dbg(controller->dev, "config write is not set ! @%p: 0x%08x\n", in aspeed_smc_chip_check_config()
272 controller->regs + CONFIG_REG, reg); in aspeed_smc_chip_check_config()
274 writel(reg, controller->regs + CONFIG_REG); in aspeed_smc_chip_check_config()
312 mutex_lock(&chip->controller->mutex); in aspeed_smc_prep()
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/ |
| D | exynos7-pinctrl.dtsi | 16 gpio-controller;
19 interrupt-controller;
33 gpio-controller;
36 interrupt-controller;
50 gpio-controller;
53 interrupt-controller;
58 gpio-controller;
61 interrupt-controller;
68 gpio-controller;
71 interrupt-controller;
[all …]
|
| D | exynos5433-pinctrl.dtsi | 24 gpio-controller;
27 interrupt-controller;
41 gpio-controller;
44 interrupt-controller;
58 gpio-controller;
61 interrupt-controller;
66 gpio-controller;
69 interrupt-controller;
74 gpio-controller;
77 interrupt-controller;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos5433-clock.txt | 3 The Exynos5433 clock controller generates and supplies clock to various
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
24 - "samsung,exynos5433-cmu-disp" - clock controller compatible for CMU_DISP
26 - "samsung,exynos5433-cmu-aud" - clock controller compatible for CMU_AUD
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
53 the root complex and MSI controller do not pass sideband data with MSI
54 writes, this property may be used to describe the MSI controller(s)
66 msi: msi-controller@a {
68 compatible = "vendor,some-controller";
69 msi-controller;
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | Kconfig | 23 bool "TI DRA7xx PCIe controller Host Mode"
31 Enables support for the PCIe controller in the DRA7xx SoC to work in
32 host mode. There are two instances of PCIe controller in DRA7xx.
33 This controller can work either as EP or RC. In order to enable
39 bool "TI DRA7xx PCIe controller Endpoint Mode"
46 Enables support for the PCIe controller in the DRA7xx SoC to work in
47 endpoint mode. There are two instances of PCIe controller in DRA7xx.
48 This controller can work either as EP or RC. In order to enable
62 Enables support for the PCIe controller in the Designware IP to
63 work in host mode. There are two instances of PCIe controller in
[all …]
|
| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | mucmc52.dts | 13 &gpt0 { gpio-controller; };
14 &gpt1 { gpio-controller; };
15 &gpt2 { gpio-controller; };
16 &gpt3 { gpio-controller; };
160 simple100: gpio-controller-100@3,600100 {
163 gpio-controller;
166 simple104: gpio-controller-104@3,600104 {
169 gpio-controller;
172 simple200: gpio-controller-200@3,600200 {
175 gpio-controller;
[all …]
|
| /kernel/linux/linux-5.10/drivers/char/agp/ |
| D | frontend.c | 293 struct agp_controller *controller; in agp_find_controller_by_pid() local
295 controller = agp_fe.controllers; in agp_find_controller_by_pid()
297 while (controller != NULL) { in agp_find_controller_by_pid()
298 if (controller->pid == id) in agp_find_controller_by_pid()
299 return controller; in agp_find_controller_by_pid()
300 controller = controller->next; in agp_find_controller_by_pid()
308 struct agp_controller *controller; in agp_create_controller() local
310 controller = kzalloc(sizeof(struct agp_controller), GFP_KERNEL); in agp_create_controller()
311 if (controller == NULL) in agp_create_controller()
314 controller->pid = id; in agp_create_controller()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mux/ |
| D | mux-controller.txt | 1 Common multiplexer controller bindings
4 A multiplexer (or mux) controller will have one, or several, consumer devices
5 that uses the mux controller. Thus, a mux controller can possibly control
7 multiplexer needed by each consumer, but a single mux controller can of course
10 A mux controller provides a number of states to its consumers, and the state
18 Mux controller consumers should specify a list of mux controllers that they
23 mux-ctrl-phandle : phandle to mux controller node
25 given mux controller (controller specific)
27 Mux controller properties should be named "mux-controls". The exact meaning of
28 each mux controller property must be documented in the device tree binding for
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
6 Layerscape PCIe MSI controller block such as:
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
14 - interrupts: an interrupt to the parent interrupt controller.
16 This interrupt controller hardware is a second level interrupt controller that
17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 controller will be used.
21 MSI controller node
25 msi1: msi-controller@1571000 {
[all …]
|
| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
6 controller in some SoCs, e.g. Hisilicon SD5203.
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
27 /* dw_apb_ictl is used as secondary interrupt controller */
28 aic: interrupt-controller@3000 {
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | samsung-pinctrl.txt | 1 Samsung GPIO and Pin Mux/Config controller
4 controller. It controls the input/output settings on the available pads/pins
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
|