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Searched refs:FMA (Results 1 – 25 of 93) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFMA.td1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===//
9 // This file describes FMA (Fused Multiply-Add) instructions.
17 // For all FMA opcodes declared in fma3p_rm_* and fma3s_rm_* multiclasses
23 // FMA*213*:
27 // FMA*132*:
31 // FMA*231*:
168 // All source register operands of FMA opcodes defined in fma3s_rm multiclass
170 // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form
171 // would require an opcode change to FMA*231:
172 // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2;
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DX86IntrinsicsInfo.h935 X86_INTRINSIC_DATA(avx512_vfmadd_f32, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
936 X86_INTRINSIC_DATA(avx512_vfmadd_f64, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
937 X86_INTRINSIC_DATA(avx512_vfmadd_pd_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
938 X86_INTRINSIC_DATA(avx512_vfmadd_ps_512, INTR_TYPE_3OP, ISD::FMA, X86ISD::FMADD_RND),
/third_party/mesa3d/src/panfrost/bifrost/valhall/test/
Dnegative-cases.txt21 FMA.f32 r0, u0, u1, 0x0
22 FMA.f32 r0, u0, 0x40490FDB, 0x0
23 FMA.f32 r0, 0x3F317218, 0x40490FDB, 0x0
Dassembler-cases.txt55 00 dd c0 08 14 c2 b2 00 FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
56 41 88 c0 00 04 c1 b2 00 FMA.f32 r1, ^r1, u8, 0x0.neg
57 40 88 c0 00 04 c0 b2 10 FMA.f32.wait1 r0, ^r0, u8, 0x0.neg
202 49 3e c0 22 04 c9 b3 30 FMA.v2f16.wait12 r9, ^r9, r62.h00, 0x0.neg
208 48 7e c0 22 04 ff b3 00 FMA.v2f16 r63, ^r8, ^r62.h00, 0x0.neg
/third_party/flutter/skia/src/core/
DSkCpu.h23 FMA = 1 << 8, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
DSkCpu.cpp64 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; } in read_cpu_features()
/third_party/skia/src/core/
DSkCpu.h23 FMA = 1 << 8, enumerator
28 HSW = AVX2 | BMI1 | BMI2 | F16C | FMA,
DSkCpu.cpp54 if (abcd[2] & (1<<12)) { features |= SkCpu:: FMA; } in read_cpu_features()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUFeatures.td16 "FMA",
18 "Enable single precision FMA (not as fast as mul+add, but fused)"
DAMDGPUSubtarget.h320 bool FMA; variable
550 return FMA; in hasFMA()
1224 bool FMA; variable
1309 bool hasFMA() const { return FMA; } in hasFMA()
DSIISelLowering.cpp521 setOperationAction(ISD::FMA, MVT::f16, Legal); in SITargetLowering()
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal); in SITargetLowering()
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom); in SITargetLowering()
726 setTargetDAGCombine(ISD::FMA); in SITargetLowering()
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) && in isFPExtFoldable()
4087 case ISD::FMA: in LowerOperation()
7627 case ISD::FMA: in getFPTernOp()
7760 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, in LowerFDIV32()
7763 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, in LowerFDIV32()
7769 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, in LowerFDIV32()
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/third_party/openh264/codec/common/x86/
Dcpuid.asm190 ; refer to detection of FMA addressed in INTEL AVX manual document
192 cmp ecx, 018001000H ; check OSXSAVE, AVX, FMA feature flags
194 ; processor supports AVX,FMA instructions and XGETBV is enabled by OS
/third_party/ffmpeg/libavcodec/x86/
Dsynth_filter.asm64 %else ; non-FMA
93 %else ; non-FMA
Djpeg2000dsp.asm89 %else ; non FMA
/third_party/mesa3d/src/panfrost/bifrost/test/
Dtest-scheduler-predicates.cpp57 TEST_F(SchedulerPredicates, FMA) in TEST_F() argument
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DConstrainedOps.def63 FUNCTION(fma, 3, 1, experimental_constrained_fma, FMA)
/third_party/mesa3d/src/panfrost/bifrost/
DNotes.txt41 // These instructions in the FMA slot, together with LSHIFT_ADD_HIGH32.i32
51 // FMA to ADD instead of being passed explicitly. Hence, these two must be
/third_party/mesa3d/docs/relnotes/
D20.1.8.rst89 - Revert "ac: generate FMA for inexact instructions for radeonsi"
D18.2.5.rst114 - glsl_to_tgsi: don't create 64-bit integer MAD/FMA
D17.0.3.rst104 - nvc0/ir: treat FMA like MAD for operand propagation
D20.1.0.rst373 - pan/bi: Move notes on FMA opcodes from disassembler
378 - pan/bi: Identify extended FMA opcodes
522 - pan/bi: Implement FMA/MOV without modifiers
564 - pan/bi: Finish FMA structures
567 - pan/bi: Pack outmod and roundmode with FMA
568 - pan/bi: Expand out FMA conversion opcodes
570 - pan/bi: Handle standard FMA conversions
578 - pan/bi: Handle abs packing for fp16/FMA add/min
600 - pan/bit: Add preliminary FMA/ADD/MOV implementations
607 - pan/bit: Add FMA tests
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h356 FMA, enumerator
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/IR/
DAutoUpgrade.cpp3141 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); in UpgradeIntrinsicCall() local
3142 Rep = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3144 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3147 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3201 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), in UpgradeIntrinsicCall() local
3204 Rep = Builder.CreateCall(FMA, { A, B, C }); in UpgradeIntrinsicCall()
3220 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
3222 Value *Odd = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3224 Value *Even = Builder.CreateCall(FMA, Ops); in UpgradeIntrinsicCall()
3267 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, in UpgradeIntrinsicCall() local
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DInterleavedLoadCombinePass.cpp1184 auto FMA = MSSA.getMemoryAccess(First); in combine() local
1187 if (!MSSA.dominates(MADef, FMA)) in combine()
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_info_opcodes.h20 OPCODE(1, 3, COMP, FMA)

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