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Searched refs:read_registers (Results 1 – 9 of 9) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_gpu_load.c86 sscreen->ws->read_registers(sscreen->ws, GRBM_STATUS, 1, &value); in si_update_mmio_counters()
106 sscreen->ws->read_registers(sscreen->ws, SRBM_STATUS2, 1, &value); in si_update_mmio_counters()
114 sscreen->ws->read_registers(sscreen->ws, CP_STAT, 1, &value); in si_update_mmio_counters()
Dsi_debug.c299 if (ws->read_registers(ws, offset, 1, &value)) in si_dump_mmapped_reg()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_gpu_load.c89 rscreen->ws->read_registers(rscreen->ws, GRBM_STATUS, 1, &value); in r600_update_mmio_counters()
/third_party/mesa3d/src/amd/vulkan/
Dradv_radeon_winsys.h227 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers, member
Dradv_debug.c116 if (ws->read_registers(ws, offset, 1, &value)) in radv_dump_mmapped_reg()
/third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_winsys.c286 ws->base.read_registers = radv_amdgpu_winsys_read_registers; in radv_amdgpu_winsys_create()
/third_party/mesa3d/src/gallium/include/winsys/
Dradeon_winsys.h701 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers, member
/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_winsys.c532 ws->base.read_registers = amdgpu_read_registers; in amdgpu_winsys_create()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c860 ws->base.read_registers = radeon_read_registers; in radeon_drm_winsys_create()