1 /* 2 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #ifndef __RK817_CODEC_H__ 16 #define __RK817_CODEC_H__ 17 18 /* codec register */ 19 #define RK817_CODEC_BASE 0x0000 20 21 #define RK817_CODEC_DTOP_VUCTL (RK817_CODEC_BASE + 0x12) 22 #define RK817_CODEC_DTOP_VUCTIME (RK817_CODEC_BASE + 0x13) 23 #define RK817_CODEC_DTOP_LPT_SRST (RK817_CODEC_BASE + 0x14) 24 #define RK817_CODEC_DTOP_DIGEN_CLKE (RK817_CODEC_BASE + 0x15) 25 #define RK817_CODEC_AREF_RTCFG0 (RK817_CODEC_BASE + 0x16) 26 #define RK817_CODEC_AREF_RTCFG1 (RK817_CODEC_BASE + 0x17) 27 #define RK817_CODEC_AADC_CFG0 (RK817_CODEC_BASE + 0x18) 28 #define RK817_CODEC_AADC_CFG1 (RK817_CODEC_BASE + 0x19) 29 #define RK817_CODEC_DADC_VOLL (RK817_CODEC_BASE + 0x1a) 30 #define RK817_CODEC_DADC_VOLR (RK817_CODEC_BASE + 0x1b) 31 #define RK817_CODEC_DADC_SR_ACL0 (RK817_CODEC_BASE + 0x1e) 32 #define RK817_CODEC_DADC_ALC1 (RK817_CODEC_BASE + 0x1f) 33 #define RK817_CODEC_DADC_ALC2 (RK817_CODEC_BASE + 0x20) 34 #define RK817_CODEC_DADC_NG (RK817_CODEC_BASE + 0x21) 35 #define RK817_CODEC_DADC_HPF (RK817_CODEC_BASE + 0x22) 36 #define RK817_CODEC_DADC_RVOLL (RK817_CODEC_BASE + 0x23) 37 #define RK817_CODEC_DADC_RVOLR (RK817_CODEC_BASE + 0x24) 38 #define RK817_CODEC_AMIC_CFG0 (RK817_CODEC_BASE + 0x27) 39 #define RK817_CODEC_AMIC_CFG1 (RK817_CODEC_BASE + 0x28) 40 #define RK817_CODEC_DMIC_PGA_GAIN (RK817_CODEC_BASE + 0x29) 41 #define RK817_CODEC_DMIC_LMT1 (RK817_CODEC_BASE + 0x2a) 42 #define RK817_CODEC_DMIC_LMT2 (RK817_CODEC_BASE + 0x2b) 43 #define RK817_CODEC_DMIC_NG1 (RK817_CODEC_BASE + 0x2c) 44 #define RK817_CODEC_DMIC_NG2 (RK817_CODEC_BASE + 0x2d) 45 #define RK817_CODEC_ADAC_CFG0 (RK817_CODEC_BASE + 0x2e) 46 #define RK817_CODEC_ADAC_CFG1 (RK817_CODEC_BASE + 0x2f) 47 #define RK817_CODEC_DDAC_POPD_DACST (RK817_CODEC_BASE + 0x30) 48 #define RK817_CODEC_DDAC_VOLL (RK817_CODEC_BASE + 0x31) 49 #define RK817_CODEC_DDAC_VOLR (RK817_CODEC_BASE + 0x32) 50 #define RK817_CODEC_DDAC_SR_LMT0 (RK817_CODEC_BASE + 0x35) 51 #define RK817_CODEC_DDAC_LMT1 (RK817_CODEC_BASE + 0x36) 52 #define RK817_CODEC_DDAC_LMT2 (RK817_CODEC_BASE + 0x37) 53 #define RK817_CODEC_DDAC_MUTE_MIXCTL (RK817_CODEC_BASE + 0x38) 54 #define RK817_CODEC_DDAC_RVOLL (RK817_CODEC_BASE + 0x39) 55 #define RK817_CODEC_DDAC_RVOLR (RK817_CODEC_BASE + 0x3a) 56 #define RK817_CODEC_AHP_ANTI0 (RK817_CODEC_BASE + 0x3b) 57 #define RK817_CODEC_AHP_ANTI1 (RK817_CODEC_BASE + 0x3c) 58 #define RK817_CODEC_AHP_CFG0 (RK817_CODEC_BASE + 0x3d) 59 #define RK817_CODEC_AHP_CFG1 (RK817_CODEC_BASE + 0x3e) 60 #define RK817_CODEC_AHP_CP (RK817_CODEC_BASE + 0x3f) 61 #define RK817_CODEC_ACLASSD_CFG1 (RK817_CODEC_BASE + 0x40) 62 #define RK817_CODEC_ACLASSD_CFG2 (RK817_CODEC_BASE + 0x41) 63 #define RK817_CODEC_APLL_CFG0 (RK817_CODEC_BASE + 0x42) 64 #define RK817_CODEC_APLL_CFG1 (RK817_CODEC_BASE + 0x43) 65 #define RK817_CODEC_APLL_CFG2 (RK817_CODEC_BASE + 0x44) 66 #define RK817_CODEC_APLL_CFG3 (RK817_CODEC_BASE + 0x45) 67 #define RK817_CODEC_APLL_CFG4 (RK817_CODEC_BASE + 0x46) 68 #define RK817_CODEC_APLL_CFG5 (RK817_CODEC_BASE + 0x47) 69 #define RK817_CODEC_DI2S_CKM (RK817_CODEC_BASE + 0x48) 70 #define RK817_CODEC_DI2S_RSD (RK817_CODEC_BASE + 0x49) 71 #define RK817_CODEC_DI2S_RXCR1 (RK817_CODEC_BASE + 0x4a) 72 #define RK817_CODEC_DI2S_RXCR2 (RK817_CODEC_BASE + 0x4b) 73 #define RK817_CODEC_DI2S_RXCMD_TSD (RK817_CODEC_BASE + 0x4c) 74 #define RK817_CODEC_DI2S_TXCR1 (RK817_CODEC_BASE + 0x4d) 75 #define RK817_CODEC_DI2S_TXCR2 (RK817_CODEC_BASE + 0x4e) 76 #define RK817_CODEC_DI2S_TXCR3_TXCMD (RK817_CODEC_BASE + 0x4f) 77 78 /* RK817_CODEC_DTOP_DIGEN_CLKE */ 79 #define ADC_DIG_CLK_MASK (0xf << 4) 80 #define ADC_DIG_CLK_SFT 4 81 #define ADC_DIG_CLK_DIS (0x0 << 4) 82 #define ADC_DIG_CLK_EN (0xf << 4) 83 84 #define DAC_DIG_CLK_MASK (0xf << 0) 85 #define DAC_DIG_CLK_SFT 0 86 #define DAC_DIG_CLK_DIS (0x0 << 0) 87 #define DAC_DIG_CLK_EN (0xf << 0) 88 89 /* RK817_CODEC_APLL_CFG5 */ 90 #define PLL_PW_DOWN (0x01 << 0) 91 #define PLL_PW_UP (0x00 << 0) 92 93 /* RK817_CODEC_DI2S_CKM */ 94 #define PDM_EN_MASK (0x1 << 3) 95 #define PDM_EN_SFT 3 96 #define PDM_EN_DISABLE (0x0 << 3) 97 #define PDM_EN_ENABLE (0x1 << 3) 98 99 #define SCK_EN_ENABLE (0x1 << 2) 100 #define SCK_EN_DISABLE (0x0 << 2) 101 102 #define RK817_I2S_MODE_MASK (0x1 << 0) 103 #define RK817_I2S_MODE_SFT 0 104 #define RK817_I2S_MODE_MST (0x1 << 0) 105 #define RK817_I2S_MODE_SLV (0x0 << 0) 106 107 /* RK817_CODEC_DDAC_SR_LMT0 */ 108 #define DACSRT_MASK (0x7 << 0) 109 110 /* RK817_CODEC_DDAC_MUTE_MIXCTL */ 111 #define DACMT_ENABLE (0x1 << 0) 112 #define DACMT_DISABLE (0x0 << 0) 113 114 /* RK817_CODEC_DI2S_RXCR2 */ 115 #define VDW_RX_24BITS (0x17) 116 #define VDW_RX_16BITS (0x0f) 117 /* RK817_CODEC_DI2S_TXCR2 */ 118 #define VDW_TX_24BITS (0x17) 119 #define VDW_TX_16BITS (0x0f) 120 121 /* RK817_CODEC_AHP_CFG1 */ 122 #define HP_ANTIPOP_ENABLE (0x1 << 4) 123 #define HP_ANTIPOP_DISABLE (0x0 << 4) 124 125 /* RK817_CODEC_ADAC_CFG1 */ 126 #define PWD_DACBIAS_MASK (0x1 << 3) 127 #define PWD_DACBIAS_SFT 3 128 #define PWD_DACBIAS_DOWN (0x1 << 3) 129 #define PWD_DACBIAS_ON (0x0 << 3) 130 131 #define PWD_DACD_MASK (0x1 << 2) 132 #define PWD_DACD_SFT 2 133 #define PWD_DACD_DOWN (0x1 << 2) 134 #define PWD_DACD_ON (0x0 << 2) 135 136 #define PWD_DACL_MASK (0x1 << 1) 137 #define PWD_DACL_SFT 1 138 #define PWD_DACL_DOWN (0x1 << 1) 139 #define PWD_DACL_ON (0x0 << 1) 140 141 #define PWD_DACR_MASK (0x1 << 0) 142 #define PWD_DACR_SFT 0 143 #define PWD_DACR_DOWN (0x1 << 0) 144 #define PWD_DACR_ON (0x0 << 0) 145 146 /* RK817_CODEC_AADC_CFG0 */ 147 #define ADC_L_PWD_MASK (0x1 << 7) 148 #define ADC_L_PWD_SFT 7 149 #define ADC_L_PWD_DIS (0x0 << 7) 150 #define ADC_L_PWD_EN (0x1 << 7) 151 152 #define ADC_R_PWD_MASK (0x1 << 6) 153 #define ADC_R_PWD_SFT 6 154 #define ADC_R_PWD_DIS (0x0 << 6) 155 #define ADC_R_PWD_EN (0x1 << 6) 156 157 /* RK817_CODEC_AMIC_CFG0 */ 158 #define MIC_DIFF_MASK (0x1 << 7) 159 #define MIC_DIFF_SFT 7 160 #define MIC_DIFF_DIS (0x0 << 7) 161 #define MIC_DIFF_EN (0x1 << 7) 162 163 #define PWD_PGA_L_MASK (0x1 << 5) 164 #define PWD_PGA_L_SFT 5 165 #define PWD_PGA_L_DIS (0x0 << 5) 166 #define PWD_PGA_L_EN (0x1 << 5) 167 168 #define PWD_PGA_R_MASK (0x1 << 4) 169 #define PWD_PGA_R_SFT 4 170 #define PWD_PGA_R_DIS (0x0 << 4) 171 #define PWD_PGA_R_EN (0x1 << 4) 172 173 enum { 174 RK817_HIFI, 175 RK817_VOICE, 176 }; 177 178 enum { 179 RK817_MONO = 1, 180 RK817_STEREO, 181 }; 182 183 enum { 184 OFF, 185 RCV, 186 SPK_PATH, 187 HP_PATH, 188 HP_NO_MIC, 189 BT, 190 SPK_HP, 191 RING_SPK, 192 RING_HP, 193 RING_HP_NO_MIC, 194 RING_SPK_HP, 195 }; 196 197 enum { 198 MIC_OFF, 199 MAIN_MIC, 200 HANDS_FREE_MIC, 201 BT_SCO_MIC, 202 }; 203 204 struct rk817_reg_val_typ { 205 unsigned int reg; 206 unsigned int value; 207 }; 208 209 struct rk817_init_bit_typ { 210 unsigned int reg; 211 unsigned int power_bit; 212 unsigned int init_bit; 213 }; 214 struct platform_device *GetCodecPlatformDevice(void); 215 struct regmap_config getCodecRegmap(void); 216 #endif /* __RK817_CODEC_H__ */ 217