1 /* 2 * Copyright (C) 2022 HiHope Open Source Organization . 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef RK3568_DAI_LINUX_H 10 #define RK3568_DAI_LINUX_H 11 12 #include <linux/dmaengine.h> 13 14 #ifdef __cplusplus 15 #if __cplusplus 16 extern "C" { 17 #endif 18 #endif /* __cplusplus */ 19 20 /* I2S REGS */ 21 #define I2S_TXCR (0x0000) 22 #define I2S_RXCR (0x0004) 23 #define I2S_CKR (0x0008) 24 #define I2S_TXFIFOLR (0x000c) 25 #define I2S_DMACR (0x0010) 26 #define I2S_INTCR (0x0014) 27 #define I2S_INTSR (0x0018) 28 #define I2S_XFER (0x001c) 29 #define I2S_CLR (0x0020) 30 #define I2S_TXDR (0x0024) 31 #define I2S_RXDR (0x0028) 32 #define I2S_RXFIFOLR (0x002c) 33 #define I2S_TDM_TXCR (0x0030) 34 #define I2S_TDM_RXCR (0x0034) 35 #define I2S_CLKDIV (0x0038) 36 37 38 /* 39 * TXCR 40 * transmit operation control register 41 */ 42 #define I2S_TXCR_PATH_SHIFT(x) (23 + (x) * 2) 43 #define I2S_TXCR_PATH_MASK(x) (0x3 << I2S_TXCR_PATH_SHIFT(x)) 44 #define I2S_TXCR_PATH(x, v) ((v) << I2S_TXCR_PATH_SHIFT(x)) 45 #define I2S_TXCR_RCNT_SHIFT 17 46 #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) 47 #define I2S_TXCR_CSR_SHIFT 15 48 #define I2S_TXCR_CSR(x) ((x) << I2S_TXCR_CSR_SHIFT) 49 #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) 50 #define I2S_TXCR_HWT BIT(14) 51 #define I2S_TXCR_SJM_SHIFT 12 52 #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) 53 #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) 54 #define I2S_TXCR_FBM_SHIFT 11 55 #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) 56 #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) 57 #define I2S_TXCR_IBM_SHIFT 9 58 #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) 59 #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) 60 #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) 61 #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) 62 #define I2S_TXCR_PBM_SHIFT 7 63 #define I2S_TXCR_PBM_MODE(x) ((x) << I2S_TXCR_PBM_SHIFT) 64 #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) 65 #define I2S_TXCR_TFS_SHIFT 5 66 #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) 67 #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) 68 #define I2S_TXCR_TFS_TDM_PCM (2 << I2S_TXCR_TFS_SHIFT) 69 #define I2S_TXCR_TFS_TDM_I2S (3 << I2S_TXCR_TFS_SHIFT) 70 #define I2S_TXCR_TFS_MASK (3 << I2S_TXCR_TFS_SHIFT) 71 #define I2S_TXCR_VDW_SHIFT 0 72 #define I2S_TXCR_VDW(x) (((x) - 1) << I2S_TXCR_VDW_SHIFT) 73 #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) 74 75 76 #define I2S_RXCR_PATH_SHIFT(x) (17 + (x) * 2) 77 #define I2S_RXCR_PATH_MASK(x) (0x3 << I2S_RXCR_PATH_SHIFT(x)) 78 #define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x)) 79 #define I2S_RXCR_CSR_SHIFT 15 80 #define I2S_RXCR_CSR(x) ((x) << I2S_RXCR_CSR_SHIFT) 81 #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) 82 #define I2S_RXCR_HWT BIT(14) 83 #define I2S_RXCR_SJM_SHIFT 12 84 #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) 85 #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) 86 #define I2S_RXCR_FBM_SHIFT 11 87 #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) 88 #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) 89 #define I2S_RXCR_IBM_SHIFT 9 90 #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) 91 #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) 92 #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) 93 #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) 94 #define I2S_RXCR_PBM_SHIFT 7 95 #define I2S_RXCR_PBM_MODE(x) ((x) << I2S_RXCR_PBM_SHIFT) 96 #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) 97 #define I2S_RXCR_TFS_SHIFT 5 98 #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) 99 #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) 100 #define I2S_RXCR_TFS_TDM_PCM (2 << I2S_RXCR_TFS_SHIFT) 101 #define I2S_RXCR_TFS_TDM_I2S (3 << I2S_RXCR_TFS_SHIFT) 102 #define I2S_RXCR_TFS_MASK (3 << I2S_RXCR_TFS_SHIFT) 103 #define I2S_RXCR_VDW_SHIFT 0 104 #define I2S_RXCR_VDW(x) (((x) - 1) << I2S_RXCR_VDW_SHIFT) 105 #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) 106 107 #define I2S_CSR_SHIFT 15 108 #define I2S_CHN_2 (0 << I2S_CSR_SHIFT) 109 #define I2S_CHN_4 (1 << I2S_CSR_SHIFT) 110 #define I2S_CHN_6 (2 << I2S_CSR_SHIFT) 111 #define I2S_CHN_8 (3 << I2S_CSR_SHIFT) 112 113 #define I2S_CLKDIV_TXM_SHIFT 0 114 #define I2S_CLKDIV_TXM(x) (((x) - 1) << I2S_CLKDIV_TXM_SHIFT) 115 #define I2S_CLKDIV_TXM_MASK (0xff << I2S_CLKDIV_TXM_SHIFT) 116 #define I2S_CLKDIV_RXM_SHIFT 8 117 #define I2S_CLKDIV_RXM(x) (((x) - 1) << I2S_CLKDIV_RXM_SHIFT) 118 #define I2S_CLKDIV_RXM_MASK (0xff << I2S_CLKDIV_RXM_SHIFT) 119 120 121 /* 122 * CKR 123 * clock generation register 124 */ 125 #define I2S_CKR_TRCM_SHIFT 28 126 #define I2S_CKR_TRCM(x) ((x) << I2S_CKR_TRCM_SHIFT) 127 #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) 128 #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT) 129 #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT) 130 #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) 131 #define I2S_CKR_MSS_SHIFT 27 132 #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) 133 #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) 134 #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) 135 #define I2S_CKR_CKP_SHIFT 26 136 #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT) 137 #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT) 138 #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT) 139 #define I2S_CKR_RLP_SHIFT 25 140 #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) 141 #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT) 142 #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT) 143 #define I2S_CKR_TLP_SHIFT 24 144 #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) 145 #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT) 146 #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT) 147 #define I2S_CKR_MDIV_SHIFT 16 148 #define I2S_CKR_MDIV(x) (((x) - 1) << I2S_CKR_MDIV_SHIFT) 149 #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) 150 #define I2S_CKR_RSD_SHIFT 8 151 #define I2S_CKR_RSD(x) (((x) - 1) << I2S_CKR_RSD_SHIFT) 152 #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) 153 #define I2S_CKR_TSD_SHIFT 0 154 #define I2S_CKR_TSD(x) (((x) - 1) << I2S_CKR_TSD_SHIFT) 155 #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) 156 157 158 #define I2S_DMACR_RDE_SHIFT 24 159 #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) 160 #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) 161 #define I2S_DMACR_RDL_SHIFT 16 162 #define I2S_DMACR_RDL(x) (((x) - 1) << I2S_DMACR_RDL_SHIFT) 163 #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) 164 #define I2S_DMACR_TDE_SHIFT 8 165 #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) 166 #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) 167 #define I2S_DMACR_TDL_SHIFT 0 168 #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) 169 #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) 170 171 /* 172 * XFER 173 * Transfer start register 174 */ 175 #define I2S_XFER_RXS_SHIFT 1 176 #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) 177 #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) 178 #define I2S_XFER_TXS_SHIFT 0 179 #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) 180 #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) 181 182 /* 183 * CLR 184 * clear SCLK domain logic register 185 */ 186 #define I2S_CLR_RXC BIT(1) 187 #define I2S_CLR_TXC BIT(0) 188 #define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) 189 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_TX HIWORD_UPDATE(1, 5, 5) 190 #define RK3568_I2S1_MCLK_OUT_SRC_FROM_RX HIWORD_UPDATE(0, 5, 5) 191 192 #define RK3568_I2S1_CLK_TXONLY \ 193 RK3568_I2S1_MCLK_OUT_SRC_FROM_TX 194 195 #define RK3568_I2S1_CLK_RXONLY \ 196 RK3568_I2S1_MCLK_OUT_SRC_FROM_RX 197 198 #define CH_GRP_MAX 4 199 struct rk3568_snd_dmaengine_dai_dma_data { 200 dma_addr_t addr; 201 enum dma_slave_buswidth addr_width; 202 u32 maxburst; 203 unsigned int slave_id; 204 void *filter_data; 205 const char *chan_name; 206 unsigned int fifo_size; 207 unsigned int flags; 208 }; 209 struct rk3568_i2s_tdm_dev { 210 struct device *dev; 211 struct clk *hclk; 212 struct clk *mclk_tx; 213 struct clk *mclk_rx; 214 /* The mclk_tx_src is parent of mclk_tx */ 215 struct clk *mclk_tx_src; 216 /* The mclk_rx_src is parent of mclk_rx */ 217 struct clk *mclk_rx_src; 218 /* 219 * The mclk_root0 and mclk_root1 are root parent and supplies for 220 * the different FS. 221 * 222 * e.g: 223 * mclk_root0 is VPLL0, used for FS=48000Hz 224 * mclk_root0 is VPLL1, used for FS=44100Hz 225 */ 226 struct clk *mclk_root0; 227 struct clk *mclk_root1; 228 struct regmap *regmap; 229 struct regmap *grf; 230 struct rk3568_snd_dmaengine_dai_dma_data capture_dma_data; 231 struct rk3568_snd_dmaengine_dai_dma_data playback_dma_data; 232 struct reset_control *tx_reset; 233 struct reset_control *rx_reset; 234 const struct rk_i2s_soc_data *soc_data; 235 #ifdef HAVE_SYNC_RESET 236 void __iomem *cru_base; 237 int tx_reset_id; 238 int rx_reset_id; 239 #endif 240 bool is_master_mode; 241 bool io_multiplex; 242 bool mclk_calibrate; 243 bool tdm_mode; 244 bool tdm_fsync_half_frame; 245 unsigned int mclk_rx_freq; 246 unsigned int mclk_tx_freq; 247 unsigned int mclk_root0_freq; 248 unsigned int mclk_root1_freq; 249 unsigned int mclk_root0_initial_freq; 250 unsigned int mclk_root1_initial_freq; 251 unsigned int bclk_fs; 252 unsigned int clk_trcm; 253 unsigned int i2s_sdis[CH_GRP_MAX]; 254 unsigned int i2s_sdos[CH_GRP_MAX]; 255 int clk_ppm; 256 atomic_t refcount; 257 spinlock_t lock; /* xfer lock */ 258 bool txStart; 259 bool rxStart; 260 }; 261 262 263 #ifdef __cplusplus 264 #if __cplusplus 265 } 266 #endif 267 #endif /* __cplusplus */ 268 269 #endif 270 271