1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * dw-hdmi-qp-i2s-audio.c
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 * Author: Sugar Zhang <sugar.zhang@rock-chips.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/module.h>
11
12 #include <drm/bridge/dw_hdmi.h>
13 #include <drm/drm_crtc.h>
14
15 #include <sound/hdmi-codec.h>
16
17 #include "dw-hdmi-qp.h"
18 #include "dw-hdmi-qp-audio.h"
19
20 #define DRIVER_NAME "dw-hdmi-qp-i2s-audio"
21
hdmi_write(struct dw_hdmi_qp_i2s_audio_data * audio,u32 val,int offset)22 static inline void hdmi_write(struct dw_hdmi_qp_i2s_audio_data *audio,
23 u32 val, int offset)
24 {
25 struct dw_hdmi_qp *hdmi = audio->hdmi;
26
27 audio->write(hdmi, val, offset);
28 }
29
hdmi_read(struct dw_hdmi_qp_i2s_audio_data * audio,int offset)30 static inline u32 hdmi_read(struct dw_hdmi_qp_i2s_audio_data *audio, int offset)
31 {
32 struct dw_hdmi_qp *hdmi = audio->hdmi;
33
34 return audio->read(hdmi, offset);
35 }
36
hdmi_mod(struct dw_hdmi_qp_i2s_audio_data * audio,u32 data,u32 mask,u32 reg)37 static inline void hdmi_mod(struct dw_hdmi_qp_i2s_audio_data *audio,
38 u32 data, u32 mask, u32 reg)
39 {
40 struct dw_hdmi_qp *hdmi = audio->hdmi;
41
42 return audio->mod(hdmi, data, mask, reg);
43 }
44
is_dw_hdmi_qp_clk_off(struct dw_hdmi_qp_i2s_audio_data * audio)45 static inline bool is_dw_hdmi_qp_clk_off(struct dw_hdmi_qp_i2s_audio_data *audio)
46 {
47 u32 sta = hdmi_read(audio, CMU_STATUS);
48
49 return (sta & (AUDCLK_OFF | LINKQPCLK_OFF | VIDQPCLK_OFF));
50 }
51
dw_hdmi_qp_i2s_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * fmt,struct hdmi_codec_params * hparms)52 static int dw_hdmi_qp_i2s_hw_params(struct device *dev, void *data,
53 struct hdmi_codec_daifmt *fmt,
54 struct hdmi_codec_params *hparms)
55 {
56 struct dw_hdmi_qp_i2s_audio_data *audio = data;
57 struct dw_hdmi_qp *hdmi = audio->hdmi;
58 u32 conf0 = 0;
59 bool ref2stream = false;
60
61 if (is_dw_hdmi_qp_clk_off(audio))
62 return 0;
63
64 if (fmt->bit_clk_master | fmt->frame_clk_master) {
65 dev_err(dev, "unsupported clock settings\n");
66 return -EINVAL;
67 }
68
69 /* Reset the audio data path of the AVP */
70 hdmi_write(audio, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST);
71
72 /* Clear the audio FIFO */
73 hdmi_write(audio, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0);
74
75 /* Select I2S interface as the audio source */
76 hdmi_mod(audio, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0);
77
78 /* Enable the active i2s lanes */
79 switch (hparms->channels) {
80 case 7 ... 8:
81 conf0 |= I2S_LINES_EN(3);
82 fallthrough;
83 case 5 ... 6:
84 conf0 |= I2S_LINES_EN(2);
85 fallthrough;
86 case 3 ... 4:
87 conf0 |= I2S_LINES_EN(1);
88 fallthrough;
89 default:
90 conf0 |= I2S_LINES_EN(0);
91 break;
92 }
93
94 hdmi_mod(audio, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0);
95
96 /*
97 * Enable bpcuv generated internally for L-PCM, or received
98 * from stream for NLPCM/HBR.
99 */
100 switch (fmt->bit_fmt) {
101 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
102 conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP;
103 conf0 |= I2S_BPCUV_RCV_EN;
104 ref2stream = true;
105 break;
106 default:
107 conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS;
108 ref2stream = false;
109 break;
110 }
111
112 hdmi_mod(audio, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK,
113 AUDIO_INTERFACE_CONFIG0);
114
115 /* Enable audio FIFO auto clear when overflow */
116 hdmi_mod(audio, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK,
117 AUDIO_INTERFACE_CONFIG0);
118
119 dw_hdmi_qp_set_sample_rate(hdmi, hparms->sample_rate);
120 dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream);
121 dw_hdmi_qp_set_channel_count(hdmi, hparms->channels);
122 dw_hdmi_qp_set_channel_allocation(hdmi, hparms->cea.channel_allocation);
123 dw_hdmi_qp_set_audio_infoframe(hdmi, hparms);
124
125 return 0;
126 }
127
dw_hdmi_qp_i2s_audio_startup(struct device * dev,void * data)128 static int dw_hdmi_qp_i2s_audio_startup(struct device *dev, void *data)
129 {
130 struct dw_hdmi_qp_i2s_audio_data *audio = data;
131 struct dw_hdmi_qp *hdmi = audio->hdmi;
132
133 if (is_dw_hdmi_qp_clk_off(audio))
134 return 0;
135
136 dw_hdmi_qp_audio_enable(hdmi);
137
138 return 0;
139 }
140
dw_hdmi_qp_i2s_audio_shutdown(struct device * dev,void * data)141 static void dw_hdmi_qp_i2s_audio_shutdown(struct device *dev, void *data)
142 {
143 struct dw_hdmi_qp_i2s_audio_data *audio = data;
144 struct dw_hdmi_qp *hdmi = audio->hdmi;
145
146 if (is_dw_hdmi_qp_clk_off(audio))
147 return;
148
149 dw_hdmi_qp_audio_disable(hdmi);
150 }
151
dw_hdmi_qp_i2s_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)152 static int dw_hdmi_qp_i2s_get_eld(struct device *dev, void *data, uint8_t *buf,
153 size_t len)
154 {
155 struct dw_hdmi_qp_i2s_audio_data *audio = data;
156
157 memcpy(buf, audio->eld, min_t(size_t, MAX_ELD_BYTES, len));
158
159 return 0;
160 }
161
dw_hdmi_qp_i2s_get_dai_id(struct snd_soc_component * component,struct device_node * endpoint)162 static int dw_hdmi_qp_i2s_get_dai_id(struct snd_soc_component *component,
163 struct device_node *endpoint)
164 {
165 struct of_endpoint of_ep;
166 int ret;
167
168 ret = of_graph_parse_endpoint(endpoint, &of_ep);
169 if (ret < 0)
170 return ret;
171
172 /*
173 * HDMI sound should be located as reg = <2>
174 * Then, it is sound port 0
175 */
176 if (of_ep.port == 2)
177 return 0;
178
179 return -EINVAL;
180 }
181
dw_hdmi_qp_i2s_hook_plugged_cb(struct device * dev,void * data,hdmi_codec_plugged_cb fn,struct device * codec_dev)182 static int dw_hdmi_qp_i2s_hook_plugged_cb(struct device *dev, void *data,
183 hdmi_codec_plugged_cb fn,
184 struct device *codec_dev)
185 {
186 struct dw_hdmi_qp_i2s_audio_data *audio = data;
187 struct dw_hdmi_qp *hdmi = audio->hdmi;
188
189 return dw_hdmi_qp_set_plugged_cb(hdmi, fn, codec_dev);
190 }
191
192 static struct hdmi_codec_ops dw_hdmi_qp_i2s_ops = {
193 .hw_params = dw_hdmi_qp_i2s_hw_params,
194 .audio_startup = dw_hdmi_qp_i2s_audio_startup,
195 .audio_shutdown = dw_hdmi_qp_i2s_audio_shutdown,
196 .get_eld = dw_hdmi_qp_i2s_get_eld,
197 .get_dai_id = dw_hdmi_qp_i2s_get_dai_id,
198 .hook_plugged_cb = dw_hdmi_qp_i2s_hook_plugged_cb,
199 };
200
snd_dw_hdmi_qp_probe(struct platform_device * pdev)201 static int snd_dw_hdmi_qp_probe(struct platform_device *pdev)
202 {
203 struct dw_hdmi_qp_i2s_audio_data *audio = pdev->dev.platform_data;
204 struct platform_device_info pdevinfo;
205 struct hdmi_codec_pdata pdata;
206 struct platform_device *platform;
207
208 pdata.ops = &dw_hdmi_qp_i2s_ops;
209 pdata.i2s = 1;
210 pdata.max_i2s_channels = 8;
211 pdata.data = audio;
212
213 memset(&pdevinfo, 0, sizeof(pdevinfo));
214 pdevinfo.parent = pdev->dev.parent;
215 pdevinfo.id = PLATFORM_DEVID_AUTO;
216 pdevinfo.name = HDMI_CODEC_DRV_NAME;
217 pdevinfo.data = &pdata;
218 pdevinfo.size_data = sizeof(pdata);
219 pdevinfo.dma_mask = DMA_BIT_MASK(32);
220
221 platform = platform_device_register_full(&pdevinfo);
222 if (IS_ERR(platform))
223 return PTR_ERR(platform);
224
225 dev_set_drvdata(&pdev->dev, platform);
226
227 return 0;
228 }
229
snd_dw_hdmi_qp_remove(struct platform_device * pdev)230 static int snd_dw_hdmi_qp_remove(struct platform_device *pdev)
231 {
232 struct platform_device *platform = dev_get_drvdata(&pdev->dev);
233
234 platform_device_unregister(platform);
235
236 return 0;
237 }
238
239 static struct platform_driver snd_dw_hdmi_qp_driver = {
240 .probe = snd_dw_hdmi_qp_probe,
241 .remove = snd_dw_hdmi_qp_remove,
242 .driver = {
243 .name = DRIVER_NAME,
244 },
245 };
246 module_platform_driver(snd_dw_hdmi_qp_driver);
247
248 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>");
249 MODULE_DESCRIPTION("Synopsis Designware HDMI QP I2S ALSA SoC interface");
250 MODULE_LICENSE("GPL v2");
251 MODULE_ALIAS("platform:" DRIVER_NAME);
252