1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Synopsys DesignWare Cores DisplayPort Transmitter Controller
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 *
7 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
8 * Zhang Yubing <yubing.zhang@rock-chips.com>
9 */
10
11 #include <asm/unaligned.h>
12
13 #include <drm/drm_atomic_helper.h>
14 #include <drm/drm_bridge.h>
15 #include <drm/drm_dp_helper.h>
16 #include <drm/drm_of.h>
17 #include <drm/drm_print.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_simple_kms_helper.h>
20
21 #include <linux/bitfield.h>
22 #include <linux/clk.h>
23 #include <linux/component.h>
24 #include <linux/extcon-provider.h>
25 #include <linux/iopoll.h>
26 #include <linux/irq.h>
27 #include <linux/of_device.h>
28 #include <linux/of_graph.h>
29 #include <linux/regmap.h>
30 #include <linux/reset.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/phy/phy.h>
33 #include <linux/mfd/syscon.h>
34
35 #include <sound/hdmi-codec.h>
36
37 #include <uapi/linux/videodev2.h>
38
39 #include "rockchip_drm_drv.h"
40 #include "rockchip_drm_vop.h"
41
42 #define DPTX_VERSION_NUMBER 0x0000
43 #define DPTX_VERSION_TYPE 0x0004
44 #define DPTX_ID 0x0008
45
46 #define DPTX_CONFIG_REG1 0x0100
47 #define DPTX_CONFIG_REG2 0x0104
48 #define DPTX_CONFIG_REG3 0x0108
49
50 #define DPTX_CCTL 0x0200
51 #define FORCE_HPD BIT(4)
52 #define DEFAULT_FAST_LINK_TRAIN_EN BIT(2)
53 #define ENHANCE_FRAMING_EN BIT(1)
54 #define SCRAMBLE_DIS BIT(0)
55 #define DPTX_SOFT_RESET_CTRL 0x0204
56 #define VIDEO_RESET BIT(5)
57 #define AUX_RESET BIT(4)
58 #define AUDIO_SAMPLER_RESET BIT(3)
59 #define PHY_SOFT_RESET BIT(1)
60 #define CONTROLLER_RESET BIT(0)
61
62 #define DPTX_VSAMPLE_CTRL 0x0300
63 #define PIXEL_MODE_SELECT GENMASK(22, 21)
64 #define VIDEO_MAPPING GENMASK(20, 16)
65 #define VIDEO_STREAM_ENABLE BIT(5)
66 #define DPTX_VSAMPLE_STUFF_CTRL1 0x0304
67 #define DPTX_VSAMPLE_STUFF_CTRL2 0x0308
68 #define DPTX_VINPUT_POLARITY_CTRL 0x030c
69 #define DE_IN_POLARITY BIT(2)
70 #define HSYNC_IN_POLARITY BIT(1)
71 #define VSYNC_IN_POLARITY BIT(0)
72 #define DPTX_VIDEO_CONFIG1 0x0310
73 #define HACTIVE GENMASK(31, 16)
74 #define HBLANK GENMASK(15, 2)
75 #define I_P BIT(1)
76 #define R_V_BLANK_IN_OSC BIT(0)
77 #define DPTX_VIDEO_CONFIG2 0x0314
78 #define VBLANK GENMASK(31, 16)
79 #define VACTIVE GENMASK(15, 0)
80 #define DPTX_VIDEO_CONFIG3 0x0318
81 #define H_SYNC_WIDTH GENMASK(31, 16)
82 #define H_FRONT_PORCH GENMASK(15, 0)
83 #define DPTX_VIDEO_CONFIG4 0x031c
84 #define V_SYNC_WIDTH GENMASK(31, 16)
85 #define V_FRONT_PORCH GENMASK(15, 0)
86 #define DPTX_VIDEO_CONFIG5 0x0320
87 #define INIT_THRESHOLD_HI GENMASK(22, 21)
88 #define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16)
89 #define INIT_THRESHOLD GENMASK(13, 7)
90 #define AVERAGE_BYTES_PER_TU GENMASK(6, 0)
91 #define DPTX_VIDEO_MSA1 0x0324
92 #define VSTART GENMASK(31, 16)
93 #define HSTART GENMASK(15, 0)
94 #define DPTX_VIDEO_MSA2 0x0328
95 #define MISC0 GENMASK(31, 24)
96 #define DPTX_VIDEO_MSA3 0x032c
97 #define MISC1 GENMASK(31, 24)
98 #define DPTX_VIDEO_HBLANK_INTERVAL 0x0330
99 #define HBLANK_INTERVAL_EN BIT(16)
100 #define HBLANK_INTERVAL GENMASK(15, 0)
101
102 #define DPTX_AUD_CONFIG1 0x0400
103 #define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24)
104 #define AUDIO_PACKET_ID GENMASK(23, 16)
105 #define AUDIO_MUTE BIT(15)
106 #define NUM_CHANNELS GENMASK(14, 12)
107 #define HBR_MODE_ENABLE BIT(10)
108 #define AUDIO_DATA_WIDTH GENMASK(9, 5)
109 #define AUDIO_DATA_IN_EN GENMASK(4, 1)
110 #define AUDIO_INF_SELECT BIT(0)
111
112 #define DPTX_SDP_VERTICAL_CTRL 0x0500
113 #define EN_VERTICAL_SDP BIT(2)
114 #define EN_AUDIO_STREAM_SDP BIT(1)
115 #define EN_AUDIO_TIMESTAMP_SDP BIT(0)
116 #define DPTX_SDP_HORIZONTAL_CTRL 0x0504
117 #define EN_HORIZONTAL_SDP BIT(2)
118 #define DPTX_SDP_STATUS_REGISTER 0x0508
119 #define DPTX_SDP_MANUAL_CTRL 0x050c
120 #define DPTX_SDP_STATUS_EN 0x0510
121
122 #define DPTX_SDP_REGISTER_BANK 0x0600
123 #define SDP_REGS GENMASK(31, 0)
124
125 #define DPTX_PHYIF_CTRL 0x0a00
126 #define PHY_WIDTH BIT(25)
127 #define PHY_POWERDOWN GENMASK(20, 17)
128 #define PHY_BUSY GENMASK(15, 12)
129 #define SSC_DIS BIT(16)
130 #define XMIT_ENABLE GENMASK(11, 8)
131 #define PHY_LANES GENMASK(7, 6)
132 #define PHY_RATE GENMASK(5, 4)
133 #define TPS_SEL GENMASK(3, 0)
134 #define DPTX_PHY_TX_EQ 0x0a04
135 #define DPTX_CUSTOMPAT0 0x0a08
136 #define DPTX_CUSTOMPAT1 0x0a0c
137 #define DPTX_CUSTOMPAT2 0x0a10
138 #define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14
139 #define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18
140
141 #define DPTX_AUX_CMD 0x0b00
142 #define AUX_CMD_TYPE GENMASK(31, 28)
143 #define AUX_ADDR GENMASK(27, 8)
144 #define I2C_ADDR_ONLY BIT(4)
145 #define AUX_LEN_REQ GENMASK(3, 0)
146 #define DPTX_AUX_STATUS 0x0b04
147 #define AUX_TIMEOUT BIT(17)
148 #define AUX_BYTES_READ GENMASK(23, 19)
149 #define AUX_STATUS GENMASK(7, 4)
150 #define DPTX_AUX_DATA0 0x0b08
151 #define DPTX_AUX_DATA1 0x0b0c
152 #define DPTX_AUX_DATA2 0x0b10
153 #define DPTX_AUX_DATA3 0x0b14
154
155 #define DPTX_GENERAL_INTERRUPT 0x0d00
156 #define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6)
157 #define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5)
158 #define SDP_EVENT_STREAM0 BIT(4)
159 #define AUX_CMD_INVALID BIT(3)
160 #define AUX_REPLY_EVENT BIT(1)
161 #define HPD_EVENT BIT(0)
162 #define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04
163 #define AUX_REPLY_EVENT_EN BIT(1)
164 #define HPD_EVENT_EN BIT(0)
165 #define DPTX_HPD_STATUS 0x0d08
166 #define HPD_STATE GENMASK(11, 9)
167 #define HPD_STATUS BIT(8)
168 #define HPD_HOT_UNPLUG BIT(2)
169 #define HPD_HOT_PLUG BIT(1)
170 #define HPD_IRQ BIT(0)
171 #define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c
172 #define HPD_UNPLUG_ERR_EN BIT(3)
173 #define HPD_UNPLUG_EN BIT(2)
174 #define HPD_PLUG_EN BIT(1)
175 #define HPD_IRQ_EN BIT(0)
176
177 #define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE
178
179 #define SDP_REG_BANK_SIZE 16
180
181 struct drm_dp_link_caps {
182 bool enhanced_framing;
183 bool tps3_supported;
184 bool tps4_supported;
185 bool fast_training;
186 bool channel_coding;
187 bool ssc;
188 };
189
190 struct drm_dp_link_train_set {
191 unsigned int voltage_swing[4];
192 unsigned int pre_emphasis[4];
193 };
194
195 struct drm_dp_link_train {
196 struct drm_dp_link_train_set request;
197 struct drm_dp_link_train_set adjust;
198 bool clock_recovered;
199 bool channel_equalized;
200 };
201
202 struct dw_dp_link {
203 u8 dpcd[DP_RECEIVER_CAP_SIZE];
204 unsigned char revision;
205 unsigned int rate;
206 unsigned int lanes;
207 struct drm_dp_link_caps caps;
208 struct drm_dp_link_train train;
209 struct drm_dp_desc desc;
210 u8 sink_count;
211 u8 vsc_sdp_extension_for_colorimetry_supported;
212 };
213
214 struct dw_dp_video {
215 struct drm_display_mode mode;
216 u32 bus_format;
217 u8 video_mapping;
218 u8 pixel_mode;
219 u8 color_format;
220 u8 bpc;
221 u8 bpp;
222 };
223
224 enum audio_format {
225 AFMT_I2S = 0,
226 AFMT_SPDIF = 1,
227 AFMT_UNUSED,
228 };
229
230 struct dw_dp_audio {
231 struct platform_device *pdev;
232 hdmi_codec_plugged_cb plugged_cb;
233 struct device *codec_dev;
234 enum audio_format format;
235 u8 channels;
236 };
237
238 struct dw_dp_sdp {
239 struct dp_sdp_header header;
240 u8 db[32];
241 unsigned long flags;
242 };
243
244 struct dw_dp_hotplug {
245 bool long_hpd;
246 bool status;
247 };
248
249 struct dw_dp {
250 struct device *dev;
251 struct regmap *regmap;
252 struct phy *phy;
253 struct clk *apb_clk;
254 struct clk *aux_clk;
255 struct clk *hclk;
256 struct clk *i2s_clk;
257 struct clk *spdif_clk;
258 struct reset_control *rstc;
259 struct regmap *grf;
260 struct completion complete;
261 int irq;
262 int id;
263 struct work_struct hpd_work;
264 struct gpio_desc *hpd_gpio;
265 struct dw_dp_hotplug hotplug;
266 struct mutex irq_lock;
267 struct extcon_dev *extcon;
268
269 struct drm_bridge bridge;
270 struct drm_connector connector;
271 struct drm_encoder encoder;
272 struct drm_dp_aux aux;
273
274 struct dw_dp_link link;
275 struct dw_dp_video video;
276 struct dw_dp_audio audio;
277
278 DECLARE_BITMAP(sdp_reg_bank, SDP_REG_BANK_SIZE);
279
280 bool split_mode;
281 struct dw_dp *left;
282 struct dw_dp *right;
283
284 struct drm_property *color_depth_property;
285 struct drm_property *color_format_property;
286 struct drm_property *color_depth_capacity;
287 struct drm_property *color_format_capacity;
288
289 struct rockchip_drm_sub_dev sub_dev;
290 };
291
292 struct dw_dp_state {
293 struct drm_connector_state state;
294
295 int bpc;
296 int color_format;
297 };
298
299 enum {
300 DPTX_VM_RGB_6BIT,
301 DPTX_VM_RGB_8BIT,
302 DPTX_VM_RGB_10BIT,
303 DPTX_VM_RGB_12BIT,
304 DPTX_VM_RGB_16BIT,
305 DPTX_VM_YCBCR444_8BIT,
306 DPTX_VM_YCBCR444_10BIT,
307 DPTX_VM_YCBCR444_12BIT,
308 DPTX_VM_YCBCR444_16BIT,
309 DPTX_VM_YCBCR422_8BIT,
310 DPTX_VM_YCBCR422_10BIT,
311 DPTX_VM_YCBCR422_12BIT,
312 DPTX_VM_YCBCR422_16BIT,
313 DPTX_VM_YCBCR420_8BIT,
314 DPTX_VM_YCBCR420_10BIT,
315 DPTX_VM_YCBCR420_12BIT,
316 DPTX_VM_YCBCR420_16BIT,
317 };
318
319 enum {
320 DPTX_MP_SINGLE_PIXEL,
321 DPTX_MP_DUAL_PIXEL,
322 DPTX_MP_QUAD_PIXEL,
323 };
324
325 enum {
326 DPTX_SDP_VERTICAL_INTERVAL = BIT(0),
327 DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1),
328 };
329
330 enum {
331 SOURCE_STATE_IDLE,
332 SOURCE_STATE_UNPLUG,
333 SOURCE_STATE_HPD_TIMEOUT = 4,
334 SOURCE_STATE_PLUG = 7
335 };
336
337 enum {
338 DPTX_PHY_PATTERN_NONE,
339 DPTX_PHY_PATTERN_TPS_1,
340 DPTX_PHY_PATTERN_TPS_2,
341 DPTX_PHY_PATTERN_TPS_3,
342 DPTX_PHY_PATTERN_TPS_4,
343 DPTX_PHY_PATTERN_SERM,
344 DPTX_PHY_PATTERN_PBRS7,
345 DPTX_PHY_PATTERN_CUSTOM_80BIT,
346 DPTX_PHY_PATTERN_CP2520_1,
347 DPTX_PHY_PATTERN_CP2520_2,
348 };
349
350 static const unsigned int dw_dp_cable[] = {
351 EXTCON_DISP_DP,
352 EXTCON_NONE,
353 };
354
355 struct dw_dp_output_format {
356 u32 bus_format;
357 u32 color_format;
358 u8 video_mapping;
359 u8 bpc;
360 u8 bpp;
361 };
362
363 static const struct dw_dp_output_format possible_output_fmts[] = {
364 { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444,
365 DPTX_VM_RGB_10BIT, 10, 30 },
366 { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444,
367 DPTX_VM_RGB_8BIT, 8, 24 },
368 { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444,
369 DPTX_VM_YCBCR444_10BIT, 10, 30 },
370 { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444,
371 DPTX_VM_YCBCR444_8BIT, 8, 24},
372 { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422,
373 DPTX_VM_YCBCR422_10BIT, 10, 20 },
374 { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422,
375 DPTX_VM_YCBCR422_8BIT, 8, 16 },
376 { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420,
377 DPTX_VM_YCBCR420_10BIT, 10, 15 },
378 { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420,
379 DPTX_VM_YCBCR420_8BIT, 8, 12 },
380 { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444,
381 DPTX_VM_RGB_6BIT, 6, 18 },
382 };
383
384 static const struct drm_prop_enum_list color_depth_enum_list[] = {
385 { 0, "Automatic" },
386 { 6, "18bit" },
387 { 8, "24bit" },
388 { 10, "30bit" },
389 };
390
391 static const struct drm_prop_enum_list color_format_enum_list[] = {
392 { RK_IF_FORMAT_RGB, "rgb" },
393 { RK_IF_FORMAT_YCBCR444, "ycbcr444" },
394 { RK_IF_FORMAT_YCBCR422, "ycbcr422" },
395 { RK_IF_FORMAT_YCBCR420, "ycbcr420" },
396 };
397
dw_dp_get_output_format(u32 bus_format)398 static const struct dw_dp_output_format *dw_dp_get_output_format(u32 bus_format)
399 {
400 unsigned int i;
401
402 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++)
403 if (possible_output_fmts[i].bus_format == bus_format)
404 return &possible_output_fmts[i];
405
406 return &possible_output_fmts[1];
407 }
408
connector_to_dp(struct drm_connector * c)409 static inline struct dw_dp *connector_to_dp(struct drm_connector *c)
410 {
411 return container_of(c, struct dw_dp, connector);
412 }
413
encoder_to_dp(struct drm_encoder * e)414 static inline struct dw_dp *encoder_to_dp(struct drm_encoder *e)
415 {
416 return container_of(e, struct dw_dp, encoder);
417 }
418
bridge_to_dp(struct drm_bridge * b)419 static inline struct dw_dp *bridge_to_dp(struct drm_bridge *b)
420 {
421 return container_of(b, struct dw_dp, bridge);
422 }
423
connector_to_dp_state(struct drm_connector_state * cstate)424 static inline struct dw_dp_state *connector_to_dp_state(struct drm_connector_state *cstate)
425 {
426 return container_of(cstate, struct dw_dp_state, state);
427 }
428
dw_dp_match_by_id(struct device * dev,const void * data)429 static int dw_dp_match_by_id(struct device *dev, const void *data)
430 {
431 struct dw_dp *dp = dev_get_drvdata(dev);
432 const unsigned int *id = data;
433
434 return dp->id == *id;
435 }
436
dw_dp_find_by_id(struct device_driver * drv,unsigned int id)437 static struct dw_dp *dw_dp_find_by_id(struct device_driver *drv,
438 unsigned int id)
439 {
440 struct device *dev;
441
442 dev = driver_find_device(drv, NULL, &id, dw_dp_match_by_id);
443 if (!dev)
444 return NULL;
445
446 return dev_get_drvdata(dev);
447 }
448
dw_dp_phy_set_pattern(struct dw_dp * dp,u32 pattern)449 static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern)
450 {
451 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL,
452 FIELD_PREP(TPS_SEL, pattern));
453 }
454
dw_dp_phy_xmit_enable(struct dw_dp * dp,u32 lanes)455 static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes)
456 {
457 u32 xmit_enable;
458
459 switch (lanes) {
460 case 4:
461 case 2:
462 case 1:
463 xmit_enable = GENMASK(lanes - 1, 0);
464 break;
465 case 0:
466 default:
467 xmit_enable = 0;
468 break;
469 }
470
471 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE,
472 FIELD_PREP(XMIT_ENABLE, xmit_enable));
473 }
474
dw_dp_bandwidth_ok(struct dw_dp * dp,const struct drm_display_mode * mode,u32 bpp,unsigned int lanes,unsigned int rate)475 static bool dw_dp_bandwidth_ok(struct dw_dp *dp,
476 const struct drm_display_mode *mode, u32 bpp,
477 unsigned int lanes, unsigned int rate)
478 {
479 u32 max_bw, req_bw;
480
481 req_bw = mode->clock * bpp / 8;
482 max_bw = lanes * rate;
483 if (req_bw > max_bw)
484 return false;
485
486 return true;
487 }
488
dw_dp_detect(struct dw_dp * dp)489 static bool dw_dp_detect(struct dw_dp *dp)
490 {
491 u32 value;
492
493 if (dp->hpd_gpio)
494 return gpiod_get_value_cansleep(dp->hpd_gpio);
495
496 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);
497
498 return FIELD_GET(HPD_STATE, value) == SOURCE_STATE_PLUG;
499 }
500
501 static enum drm_connector_status
dw_dp_connector_detect(struct drm_connector * connector,bool force)502 dw_dp_connector_detect(struct drm_connector *connector, bool force)
503 {
504 struct dw_dp *dp = connector_to_dp(connector);
505
506 if (dp->right && drm_bridge_detect(&dp->right->bridge) != connector_status_connected)
507 return connector_status_disconnected;
508
509 return drm_bridge_detect(&dp->bridge);
510 }
511
dw_dp_audio_handle_plugged_change(struct dw_dp_audio * audio,bool plugged)512 static void dw_dp_audio_handle_plugged_change(struct dw_dp_audio *audio, bool plugged)
513 {
514 if (audio->plugged_cb && audio->codec_dev)
515 audio->plugged_cb(audio->codec_dev, plugged);
516 }
517
dw_dp_connector_force(struct drm_connector * connector)518 static void dw_dp_connector_force(struct drm_connector *connector)
519 {
520 struct dw_dp *dp = connector_to_dp(connector);
521
522 if (connector->status == connector_status_connected) {
523 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
524 dw_dp_audio_handle_plugged_change(&dp->audio, true);
525 } else {
526 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
527 dw_dp_audio_handle_plugged_change(&dp->audio, false);
528 }
529 }
530
dw_dp_atomic_connector_reset(struct drm_connector * connector)531 static void dw_dp_atomic_connector_reset(struct drm_connector *connector)
532 {
533 struct dw_dp_state *dp_state = connector_to_dp_state(connector->state);
534
535 if (connector->state) {
536 __drm_atomic_helper_connector_destroy_state(connector->state);
537 kfree(dp_state);
538 }
539
540 dp_state = kzalloc(sizeof(*dp_state), GFP_KERNEL);
541 if (!dp_state)
542 return;
543
544 __drm_atomic_helper_connector_reset(connector, &dp_state->state);
545 dp_state->bpc = 0;
546 dp_state->color_format = RK_IF_FORMAT_RGB;
547 }
548
549 static struct drm_connector_state *
dw_dp_atomic_connector_duplicate_state(struct drm_connector * connector)550 dw_dp_atomic_connector_duplicate_state(struct drm_connector *connector)
551 {
552 struct dw_dp_state *cstate, *old_cstate;
553
554 if (WARN_ON(!connector->state))
555 return NULL;
556
557 old_cstate = connector_to_dp_state(connector->state);
558 cstate = kmalloc(sizeof(*cstate), GFP_KERNEL);
559 if (!cstate)
560 return NULL;
561
562 __drm_atomic_helper_connector_duplicate_state(connector, &cstate->state);
563 cstate->bpc = old_cstate->bpc;
564 cstate->color_format = old_cstate->color_format;
565
566 return &cstate->state;
567 }
568
dw_dp_atomic_connector_destroy_state(struct drm_connector * connector,struct drm_connector_state * state)569 static void dw_dp_atomic_connector_destroy_state(struct drm_connector *connector,
570 struct drm_connector_state *state)
571 {
572 struct dw_dp_state *cstate = connector_to_dp_state(state);
573
574 __drm_atomic_helper_connector_destroy_state(&cstate->state);
575 kfree(cstate);
576 }
577
dw_dp_atomic_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)578 static int dw_dp_atomic_connector_get_property(struct drm_connector *connector,
579 const struct drm_connector_state *state,
580 struct drm_property *property,
581 uint64_t *val)
582 {
583 struct dw_dp *dp = connector_to_dp(connector);
584 struct dw_dp_state *dp_state = connector_to_dp_state((struct drm_connector_state *)state);
585 struct drm_display_info *info = &connector->display_info;
586
587 if (property == dp->color_depth_property) {
588 *val = dp_state->bpc;
589 return 0;
590 } else if (property == dp->color_format_property) {
591 *val = dp_state->color_format;
592 return 0;
593 } else if (property == dp->color_depth_capacity) {
594 *val = BIT(RK_IF_DEPTH_8);
595 switch (info->bpc) {
596 case 16:
597 fallthrough;
598 case 12:
599 fallthrough;
600 case 10:
601 *val |= BIT(RK_IF_DEPTH_10);
602 fallthrough;
603 case 8:
604 *val |= BIT(RK_IF_DEPTH_8);
605 fallthrough;
606 case 6:
607 *val |= BIT(RK_IF_DEPTH_6);
608 fallthrough;
609 default:
610 break;
611 }
612 return 0;
613 } else if (property == dp->color_format_capacity) {
614 *val = info->color_formats;
615 return 0;
616 }
617
618 dev_err(dp->dev, "Unknown property [PROP:%d:%s]\n",
619 property->base.id, property->name);
620
621 return 0;
622 }
623
dw_dp_atomic_connector_set_property(struct drm_connector * connector,struct drm_connector_state * state,struct drm_property * property,uint64_t val)624 static int dw_dp_atomic_connector_set_property(struct drm_connector *connector,
625 struct drm_connector_state *state,
626 struct drm_property *property,
627 uint64_t val)
628 {
629 struct dw_dp *dp = connector_to_dp(connector);
630 struct dw_dp_state *dp_state = connector_to_dp_state(state);
631
632 if (property == dp->color_depth_property) {
633 dp_state->bpc = val;
634 return 0;
635 } else if (property == dp->color_format_property) {
636 dp_state->color_format = val;
637 return 0;
638 } else if (property == dp->color_depth_capacity) {
639 return 0;
640 } else if (property == dp->color_format_capacity) {
641 return 0;
642 }
643
644 dev_err(dp->dev, "Unknown property [PROP:%d:%s]\n",
645 property->base.id, property->name);
646
647 return -EINVAL;
648 }
649
650 static const struct drm_connector_funcs dw_dp_connector_funcs = {
651 .detect = dw_dp_connector_detect,
652 .fill_modes = drm_helper_probe_single_connector_modes,
653 .destroy = drm_connector_cleanup,
654 .force = dw_dp_connector_force,
655 .reset = dw_dp_atomic_connector_reset,
656 .atomic_duplicate_state = dw_dp_atomic_connector_duplicate_state,
657 .atomic_destroy_state = dw_dp_atomic_connector_destroy_state,
658 .atomic_get_property = dw_dp_atomic_connector_get_property,
659 .atomic_set_property = dw_dp_atomic_connector_set_property,
660 };
661
dw_dp_connector_get_modes(struct drm_connector * connector)662 static int dw_dp_connector_get_modes(struct drm_connector *connector)
663 {
664 struct dw_dp *dp = connector_to_dp(connector);
665 struct drm_display_info *di = &connector->display_info;
666 struct edid *edid;
667 int num_modes = 0;
668
669 edid = drm_bridge_get_edid(&dp->bridge, connector);
670 if (edid) {
671 drm_connector_update_edid_property(connector, edid);
672 num_modes = drm_add_edid_modes(connector, edid);
673 kfree(edid);
674 }
675
676 if (!di->color_formats)
677 di->color_formats = DRM_COLOR_FORMAT_RGB444;
678
679 if (!di->bpc)
680 di->bpc = 8;
681
682 if (num_modes > 0 && dp->split_mode) {
683 struct drm_display_mode *mode;
684
685 di->width_mm *= 2;
686
687 list_for_each_entry(mode, &connector->probed_modes, head)
688 drm_mode_convert_to_split_mode(mode);
689 }
690
691 return num_modes;
692 }
693
dw_dp_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * state)694 static int dw_dp_connector_atomic_check(struct drm_connector *conn,
695 struct drm_atomic_state *state)
696 {
697 struct drm_connector_state *old_state, *new_state;
698 struct dw_dp_state *dp_old_state, *dp_new_state;
699 struct drm_crtc_state *crtc_state;
700 struct dw_dp *dp = connector_to_dp(conn);
701
702 old_state = drm_atomic_get_old_connector_state(state, conn);
703 new_state = drm_atomic_get_new_connector_state(state, conn);
704 dp_old_state = connector_to_dp_state(old_state);
705 dp_new_state = connector_to_dp_state(new_state);
706
707 if (!new_state->crtc)
708 return 0;
709
710 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
711
712 if ((dp_new_state->bpc != 0) && (dp_new_state->bpc != 6) && (dp_new_state->bpc != 8) &&
713 (dp_new_state->bpc != 10)) {
714 dev_err(dp->dev, "set invalid bpc:%d\n", dp_new_state->bpc);
715 return -EINVAL;
716 }
717
718 if ((dp_new_state->color_format < RK_IF_FORMAT_RGB) ||
719 (dp_new_state->color_format > RK_IF_FORMAT_YCBCR420)) {
720 dev_err(dp->dev, "set invalid color format:%d\n", dp_new_state->color_format);
721 return -EINVAL;
722 }
723
724 if ((dp_old_state->bpc != dp_new_state->bpc) ||
725 (dp_old_state->color_format != dp_new_state->color_format)) {
726 if ((dp_old_state->bpc == 0) && (dp_new_state->bpc == 0))
727 dev_info(dp->dev, "still auto set color mode\n");
728 else
729 crtc_state->mode_changed = true;
730 }
731
732 return 0;
733 }
734
735 static const struct drm_connector_helper_funcs dw_dp_connector_helper_funcs = {
736 .get_modes = dw_dp_connector_get_modes,
737 .atomic_check = dw_dp_connector_atomic_check,
738 };
739
dw_dp_link_caps_reset(struct drm_dp_link_caps * caps)740 static void dw_dp_link_caps_reset(struct drm_dp_link_caps *caps)
741 {
742 caps->enhanced_framing = false;
743 caps->tps3_supported = false;
744 caps->tps4_supported = false;
745 caps->fast_training = false;
746 caps->channel_coding = false;
747 }
748
dw_dp_link_reset(struct dw_dp_link * link)749 static void dw_dp_link_reset(struct dw_dp_link *link)
750 {
751 link->vsc_sdp_extension_for_colorimetry_supported = 0;
752 link->sink_count = 0;
753 link->revision = 0;
754
755 dw_dp_link_caps_reset(&link->caps);
756 memset(link->dpcd, 0, sizeof(link->dpcd));
757
758 link->rate = 0;
759 link->lanes = 0;
760 }
761
dw_dp_link_power_up(struct dw_dp * dp)762 static int dw_dp_link_power_up(struct dw_dp *dp)
763 {
764 struct dw_dp_link *link = &dp->link;
765 u8 value;
766 int ret;
767
768 if (link->revision < 0x11)
769 return 0;
770
771 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
772 if (ret < 0)
773 return ret;
774
775 value &= ~DP_SET_POWER_MASK;
776 value |= DP_SET_POWER_D0;
777
778 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
779 if (ret < 0)
780 return ret;
781
782 usleep_range(1000, 2000);
783
784 return 0;
785 }
786
dw_dp_link_power_down(struct dw_dp * dp)787 static int dw_dp_link_power_down(struct dw_dp *dp)
788 {
789 struct dw_dp_link *link = &dp->link;
790 u8 value;
791 int ret;
792
793 if (link->revision < 0x11)
794 return 0;
795
796 ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value);
797 if (ret < 0)
798 return ret;
799
800 value &= ~DP_SET_POWER_MASK;
801 value |= DP_SET_POWER_D3;
802
803 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value);
804 if (ret < 0)
805 return ret;
806
807 return 0;
808 }
809
dw_dp_has_sink_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE],const struct drm_dp_desc * desc)810 static bool dw_dp_has_sink_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
811 const struct drm_dp_desc *desc)
812 {
813 return dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
814 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
815 !drm_dp_has_quirk(desc, 0, DP_DPCD_QUIRK_NO_SINK_COUNT);
816 }
817
dw_dp_link_probe(struct dw_dp * dp)818 static int dw_dp_link_probe(struct dw_dp *dp)
819 {
820 struct dw_dp_link *link = &dp->link;
821 u8 dpcd;
822 int ret;
823
824 dw_dp_link_reset(link);
825
826 ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd);
827 if (ret < 0)
828 return ret;
829
830 drm_dp_read_desc(&dp->aux, &link->desc, drm_dp_is_branch(link->dpcd));
831
832 if (dw_dp_has_sink_count(link->dpcd, &link->desc)) {
833 ret = drm_dp_read_sink_count(&dp->aux);
834 if (ret < 0)
835 return ret;
836
837 link->sink_count = ret;
838
839 /* Dongle connected, but no display */
840 if (!link->sink_count)
841 return -ENODEV;
842 }
843
844 ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
845 &dpcd);
846 if (ret < 0)
847 return ret;
848
849 link->vsc_sdp_extension_for_colorimetry_supported =
850 !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
851
852 link->revision = link->dpcd[DP_DPCD_REV];
853 link->rate = drm_dp_max_link_rate(link->dpcd);
854 link->lanes = min_t(u8, phy_get_bus_width(dp->phy),
855 drm_dp_max_lane_count(link->dpcd));
856
857 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd);
858 link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd);
859 link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd);
860 link->caps.fast_training = drm_dp_fast_training_cap(link->dpcd);
861 link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd);
862 link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
863
864 return 0;
865 }
866
dw_dp_link_train_update_vs_emph(struct dw_dp * dp)867 static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp)
868 {
869 struct dw_dp_link *link = &dp->link;
870 struct drm_dp_link_train_set *request = &link->train.request;
871 union phy_configure_opts phy_cfg;
872 unsigned int lanes = link->lanes, *vs, *pe;
873 u8 buf[4];
874 int i, ret;
875
876 vs = request->voltage_swing;
877 pe = request->pre_emphasis;
878
879 for (i = 0; i < lanes; i++) {
880 phy_cfg.dp.voltage[i] = vs[i];
881 phy_cfg.dp.pre[i] = pe[i];
882 }
883 phy_cfg.dp.lanes = lanes;
884 phy_cfg.dp.link_rate = link->rate / 100;
885 phy_cfg.dp.set_lanes = false;
886 phy_cfg.dp.set_rate = false;
887 phy_cfg.dp.set_voltages = true;
888 ret = phy_configure(dp->phy, &phy_cfg);
889 if (ret)
890 return ret;
891
892 for (i = 0; i < lanes; i++)
893 buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) |
894 (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT);
895 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes);
896 if (ret < 0)
897 return ret;
898
899 return 0;
900 }
901
dw_dp_link_configure(struct dw_dp * dp)902 static int dw_dp_link_configure(struct dw_dp *dp)
903 {
904 struct dw_dp_link *link = &dp->link;
905 union phy_configure_opts phy_cfg;
906 u8 buf[2];
907 int ret;
908
909 /* Move PHY to P3 */
910 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,
911 FIELD_PREP(PHY_POWERDOWN, 0x3));
912
913 phy_cfg.dp.lanes = link->lanes;
914 phy_cfg.dp.link_rate = link->rate / 100;
915 phy_cfg.dp.ssc = link->caps.ssc;
916 phy_cfg.dp.set_lanes = true;
917 phy_cfg.dp.set_rate = true;
918 phy_cfg.dp.set_voltages = false;
919 ret = phy_configure(dp->phy, &phy_cfg);
920 if (ret)
921 return ret;
922
923 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES,
924 FIELD_PREP(PHY_LANES, link->lanes / 2));
925
926 /* Move PHY to P0 */
927 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN,
928 FIELD_PREP(PHY_POWERDOWN, 0x0));
929
930 dw_dp_phy_xmit_enable(dp, link->lanes);
931
932 buf[0] = drm_dp_link_rate_to_bw_code(link->rate);
933 buf[1] = link->lanes;
934
935 if (link->caps.enhanced_framing) {
936 buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
937 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,
938 FIELD_PREP(ENHANCE_FRAMING_EN, 1));
939 } else {
940 regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN,
941 FIELD_PREP(ENHANCE_FRAMING_EN, 0));
942 }
943
944 ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));
945 if (ret < 0)
946 return ret;
947
948 buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0;
949 buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0;
950
951 ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf,
952 sizeof(buf));
953 if (ret < 0)
954 return ret;
955
956 return 0;
957 }
958
dw_dp_link_train_init(struct drm_dp_link_train * train)959 static void dw_dp_link_train_init(struct drm_dp_link_train *train)
960 {
961 struct drm_dp_link_train_set *request = &train->request;
962 struct drm_dp_link_train_set *adjust = &train->adjust;
963 unsigned int i;
964
965 for (i = 0; i < 4; i++) {
966 request->voltage_swing[i] = 0;
967 adjust->voltage_swing[i] = 0;
968
969 request->pre_emphasis[i] = 0;
970 adjust->pre_emphasis[i] = 0;
971 }
972
973 train->clock_recovered = false;
974 train->channel_equalized = false;
975 }
976
dw_dp_link_train_valid(const struct drm_dp_link_train * train)977 static bool dw_dp_link_train_valid(const struct drm_dp_link_train *train)
978 {
979 return train->clock_recovered && train->channel_equalized;
980 }
981
dw_dp_link_train_set_pattern(struct dw_dp * dp,u32 pattern)982 static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern)
983 {
984 u8 buf = 0;
985 int ret;
986
987 if (pattern && pattern != DP_TRAINING_PATTERN_4) {
988 buf |= DP_LINK_SCRAMBLING_DISABLE;
989
990 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS,
991 FIELD_PREP(SCRAMBLE_DIS, 1));
992 } else {
993 regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS,
994 FIELD_PREP(SCRAMBLE_DIS, 0));
995 }
996
997 switch (pattern) {
998 case DP_TRAINING_PATTERN_DISABLE:
999 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE);
1000 break;
1001 case DP_TRAINING_PATTERN_1:
1002 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1);
1003 break;
1004 case DP_TRAINING_PATTERN_2:
1005 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2);
1006 break;
1007 case DP_TRAINING_PATTERN_3:
1008 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3);
1009 break;
1010 case DP_TRAINING_PATTERN_4:
1011 dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4);
1012 break;
1013 default:
1014 return -EINVAL;
1015 }
1016
1017 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
1018 buf | pattern);
1019 if (ret < 0)
1020 return ret;
1021
1022 return 0;
1023 }
1024
dw_dp_link_get_adjustments(struct dw_dp_link * link,u8 status[DP_LINK_STATUS_SIZE])1025 static void dw_dp_link_get_adjustments(struct dw_dp_link *link,
1026 u8 status[DP_LINK_STATUS_SIZE])
1027 {
1028 struct drm_dp_link_train_set *adjust = &link->train.adjust;
1029 unsigned int i;
1030
1031 for (i = 0; i < link->lanes; i++) {
1032 adjust->voltage_swing[i] =
1033 drm_dp_get_adjust_request_voltage(status, i) >>
1034 DP_TRAIN_VOLTAGE_SWING_SHIFT;
1035
1036 adjust->pre_emphasis[i] =
1037 drm_dp_get_adjust_request_pre_emphasis(status, i) >>
1038 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1039 }
1040 }
1041
dw_dp_link_train_adjust(struct drm_dp_link_train * train)1042 static void dw_dp_link_train_adjust(struct drm_dp_link_train *train)
1043 {
1044 struct drm_dp_link_train_set *request = &train->request;
1045 struct drm_dp_link_train_set *adjust = &train->adjust;
1046 unsigned int i;
1047
1048 for (i = 0; i < 4; i++)
1049 if (request->voltage_swing[i] != adjust->voltage_swing[i])
1050 request->voltage_swing[i] = adjust->voltage_swing[i];
1051
1052 for (i = 0; i < 4; i++)
1053 if (request->pre_emphasis[i] != adjust->pre_emphasis[i])
1054 request->pre_emphasis[i] = adjust->pre_emphasis[i];
1055 }
1056
dw_dp_link_clock_recovery(struct dw_dp * dp)1057 static int dw_dp_link_clock_recovery(struct dw_dp *dp)
1058 {
1059 struct dw_dp_link *link = &dp->link;
1060 u8 status[DP_LINK_STATUS_SIZE];
1061 unsigned int tries = 0;
1062 int ret;
1063
1064 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
1065 if (ret)
1066 return ret;
1067
1068 for (;;) {
1069 ret = dw_dp_link_train_update_vs_emph(dp);
1070 if (ret)
1071 return ret;
1072
1073 drm_dp_link_train_clock_recovery_delay(link->dpcd);
1074
1075 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
1076 if (ret < 0) {
1077 dev_err(dp->dev, "failed to read link status: %d\n", ret);
1078 return ret;
1079 }
1080
1081 if (drm_dp_clock_recovery_ok(status, link->lanes)) {
1082 link->train.clock_recovered = true;
1083 break;
1084 }
1085
1086 dw_dp_link_get_adjustments(link, status);
1087
1088 if (link->train.request.voltage_swing[0] ==
1089 link->train.adjust.voltage_swing[0])
1090 tries++;
1091 else
1092 tries = 0;
1093
1094 if (tries == 5)
1095 break;
1096
1097 dw_dp_link_train_adjust(&link->train);
1098 }
1099
1100 return 0;
1101 }
1102
dw_dp_link_channel_equalization(struct dw_dp * dp)1103 static int dw_dp_link_channel_equalization(struct dw_dp *dp)
1104 {
1105 struct dw_dp_link *link = &dp->link;
1106 u8 status[DP_LINK_STATUS_SIZE], pattern;
1107 unsigned int tries;
1108 int ret;
1109
1110 if (link->caps.tps4_supported)
1111 pattern = DP_TRAINING_PATTERN_4;
1112 else if (link->caps.tps3_supported)
1113 pattern = DP_TRAINING_PATTERN_3;
1114 else
1115 pattern = DP_TRAINING_PATTERN_2;
1116 ret = dw_dp_link_train_set_pattern(dp, pattern);
1117 if (ret)
1118 return ret;
1119
1120 for (tries = 1; tries < 5; tries++) {
1121 ret = dw_dp_link_train_update_vs_emph(dp);
1122 if (ret)
1123 return ret;
1124
1125 drm_dp_link_train_channel_eq_delay(link->dpcd);
1126
1127 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
1128 if (ret < 0)
1129 return ret;
1130
1131 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
1132 dev_err(dp->dev, "clock recovery lost while equalizing channel\n");
1133 link->train.clock_recovered = false;
1134 break;
1135 }
1136
1137 if (drm_dp_channel_eq_ok(status, link->lanes)) {
1138 link->train.channel_equalized = true;
1139 break;
1140 }
1141
1142 dw_dp_link_get_adjustments(link, status);
1143 dw_dp_link_train_adjust(&link->train);
1144 }
1145
1146 return 0;
1147 }
1148
dw_dp_link_downgrade(struct dw_dp * dp)1149 static int dw_dp_link_downgrade(struct dw_dp *dp)
1150 {
1151 struct dw_dp_link *link = &dp->link;
1152 struct dw_dp_video *video = &dp->video;
1153
1154 switch (link->rate) {
1155 case 162000:
1156 return -EINVAL;
1157 case 270000:
1158 link->rate = 162000;
1159 break;
1160 case 540000:
1161 link->rate = 270000;
1162 break;
1163 case 810000:
1164 link->rate = 540000;
1165 break;
1166 }
1167
1168 if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes,
1169 link->rate))
1170 return -E2BIG;
1171
1172 return 0;
1173 }
1174
dw_dp_link_train_full(struct dw_dp * dp)1175 static int dw_dp_link_train_full(struct dw_dp *dp)
1176 {
1177 struct dw_dp_link *link = &dp->link;
1178 int ret;
1179
1180 retry:
1181 dw_dp_link_train_init(&link->train);
1182
1183 dev_info(dp->dev, "full-training link: %u lane%s at %u MHz\n",
1184 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100);
1185
1186 ret = dw_dp_link_configure(dp);
1187 if (ret < 0) {
1188 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
1189 return ret;
1190 }
1191
1192 ret = dw_dp_link_clock_recovery(dp);
1193 if (ret < 0) {
1194 dev_err(dp->dev, "clock recovery failed: %d\n", ret);
1195 goto out;
1196 }
1197
1198 if (!link->train.clock_recovered) {
1199 dev_err(dp->dev, "clock recovery failed, downgrading link\n");
1200
1201 ret = dw_dp_link_downgrade(dp);
1202 if (ret < 0)
1203 goto out;
1204 else
1205 goto retry;
1206 }
1207
1208 dev_info(dp->dev, "clock recovery succeeded\n");
1209
1210 ret = dw_dp_link_channel_equalization(dp);
1211 if (ret < 0) {
1212 dev_err(dp->dev, "channel equalization failed: %d\n", ret);
1213 goto out;
1214 }
1215
1216 if (!link->train.channel_equalized) {
1217 dev_err(dp->dev, "channel equalization failed, downgrading link\n");
1218
1219 ret = dw_dp_link_downgrade(dp);
1220 if (ret < 0)
1221 goto out;
1222 else
1223 goto retry;
1224 }
1225
1226 dev_info(dp->dev, "channel equalization succeeded\n");
1227
1228 out:
1229 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1230 return ret;
1231 }
1232
dw_dp_link_train_fast(struct dw_dp * dp)1233 static int dw_dp_link_train_fast(struct dw_dp *dp)
1234 {
1235 struct dw_dp_link *link = &dp->link;
1236 u8 status[DP_LINK_STATUS_SIZE], pattern;
1237 int ret;
1238
1239 dw_dp_link_train_init(&link->train);
1240
1241 dev_info(dp->dev, "fast-training link: %u lane%s at %u MHz\n",
1242 link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100);
1243
1244 ret = dw_dp_link_configure(dp);
1245 if (ret < 0) {
1246 dev_err(dp->dev, "failed to configure DP link: %d\n", ret);
1247 return ret;
1248 }
1249
1250 ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
1251 if (ret)
1252 goto out;
1253
1254 usleep_range(500, 1000);
1255
1256 if (link->caps.tps4_supported)
1257 pattern = DP_TRAINING_PATTERN_4;
1258 else if (link->caps.tps3_supported)
1259 pattern = DP_TRAINING_PATTERN_3;
1260 else
1261 pattern = DP_TRAINING_PATTERN_2;
1262 ret = dw_dp_link_train_set_pattern(dp, pattern);
1263 if (ret)
1264 goto out;
1265
1266 usleep_range(500, 1000);
1267
1268 ret = drm_dp_dpcd_read_link_status(&dp->aux, status);
1269 if (ret < 0) {
1270 dev_err(dp->dev, "failed to read link status: %d\n", ret);
1271 goto out;
1272 }
1273
1274 if (!drm_dp_clock_recovery_ok(status, link->lanes)) {
1275 dev_err(dp->dev, "clock recovery failed\n");
1276 ret = -EIO;
1277 goto out;
1278 }
1279
1280 if (!drm_dp_channel_eq_ok(status, link->lanes)) {
1281 dev_err(dp->dev, "channel equalization failed\n");
1282 ret = -EIO;
1283 goto out;
1284 }
1285
1286 out:
1287 dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE);
1288 return ret;
1289 }
1290
dw_dp_link_train(struct dw_dp * dp)1291 static int dw_dp_link_train(struct dw_dp *dp)
1292 {
1293 struct dw_dp_link *link = &dp->link;
1294 int ret;
1295
1296 if (link->caps.fast_training) {
1297 if (dw_dp_link_train_valid(&link->train)) {
1298 ret = dw_dp_link_train_fast(dp);
1299 if (ret < 0)
1300 dev_err(dp->dev,
1301 "fast link training failed: %d\n", ret);
1302 else
1303 return 0;
1304 }
1305 }
1306
1307 ret = dw_dp_link_train_full(dp);
1308 if (ret < 0) {
1309 dev_err(dp->dev, "full link training failed: %d\n", ret);
1310 return ret;
1311 }
1312
1313 return 0;
1314 }
1315
dw_dp_send_sdp(struct dw_dp * dp,struct dw_dp_sdp * sdp)1316 static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp)
1317 {
1318 const u8 *payload = sdp->db;
1319 u32 reg;
1320 int i, nr;
1321
1322 nr = find_first_zero_bit(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
1323 if (nr < SDP_REG_BANK_SIZE)
1324 set_bit(nr, dp->sdp_reg_bank);
1325 else
1326 return -EBUSY;
1327
1328 reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4;
1329
1330 /* SDP header */
1331 regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header));
1332
1333 /* SDP data payload */
1334 for (i = 1; i < 9; i++, payload += 4)
1335 regmap_write(dp->regmap, reg + i * 4,
1336 FIELD_PREP(SDP_REGS, get_unaligned_le32(payload)));
1337
1338 if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL)
1339 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,
1340 EN_VERTICAL_SDP << nr,
1341 EN_VERTICAL_SDP << nr);
1342
1343 if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL)
1344 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL,
1345 EN_HORIZONTAL_SDP << nr,
1346 EN_HORIZONTAL_SDP << nr);
1347
1348 return 0;
1349 }
1350
dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp * vsc,struct dw_dp_sdp * sdp)1351 static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
1352 struct dw_dp_sdp *sdp)
1353 {
1354 sdp->header.HB0 = 0;
1355 sdp->header.HB1 = DP_SDP_VSC;
1356 sdp->header.HB2 = vsc->revision;
1357 sdp->header.HB3 = vsc->length;
1358
1359 sdp->db[16] = (vsc->pixelformat & 0xf) << 4;
1360 sdp->db[16] |= vsc->colorimetry & 0xf;
1361
1362 switch (vsc->bpc) {
1363 case 8:
1364 sdp->db[17] = 0x1;
1365 break;
1366 case 10:
1367 sdp->db[17] = 0x2;
1368 break;
1369 case 12:
1370 sdp->db[17] = 0x3;
1371 break;
1372 case 16:
1373 sdp->db[17] = 0x4;
1374 break;
1375 case 6:
1376 default:
1377 break;
1378 }
1379
1380 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
1381 sdp->db[17] |= 0x80;
1382
1383 sdp->db[18] = vsc->content_type & 0x7;
1384
1385 sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL;
1386 }
1387
dw_dp_send_vsc_sdp(struct dw_dp * dp)1388 static int dw_dp_send_vsc_sdp(struct dw_dp *dp)
1389 {
1390 struct dw_dp_video *video = &dp->video;
1391 struct drm_dp_vsc_sdp vsc = {};
1392 struct dw_dp_sdp sdp = {};
1393
1394 vsc.revision = 0x5;
1395 vsc.length = 0x13;
1396
1397 switch (video->color_format) {
1398 case DRM_COLOR_FORMAT_YCRCB444:
1399 vsc.pixelformat = DP_PIXELFORMAT_YUV444;
1400 break;
1401 case DRM_COLOR_FORMAT_YCRCB420:
1402 vsc.pixelformat = DP_PIXELFORMAT_YUV420;
1403 break;
1404 case DRM_COLOR_FORMAT_YCRCB422:
1405 vsc.pixelformat = DP_PIXELFORMAT_YUV422;
1406 break;
1407 case DRM_COLOR_FORMAT_RGB444:
1408 default:
1409 vsc.pixelformat = DP_PIXELFORMAT_RGB;
1410 break;
1411 }
1412
1413 if (video->color_format == DRM_COLOR_FORMAT_RGB444) {
1414 vsc.colorimetry = DP_COLORIMETRY_DEFAULT;
1415 vsc.dynamic_range = DP_DYNAMIC_RANGE_VESA;
1416 } else {
1417 vsc.colorimetry = DP_COLORIMETRY_BT709_YCC;
1418 vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA;
1419 }
1420
1421 vsc.bpc = video->bpc;
1422 vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED;
1423
1424 dw_dp_vsc_sdp_pack(&vsc, &sdp);
1425
1426 return dw_dp_send_sdp(dp, &sdp);
1427 }
1428
dw_dp_video_set_pixel_mode(struct dw_dp * dp,u8 pixel_mode)1429 static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode)
1430 {
1431 switch (pixel_mode) {
1432 case DPTX_MP_SINGLE_PIXEL:
1433 case DPTX_MP_DUAL_PIXEL:
1434 case DPTX_MP_QUAD_PIXEL:
1435 break;
1436 default:
1437 return -EINVAL;
1438 }
1439
1440 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT,
1441 FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode));
1442
1443 return 0;
1444 }
1445
dw_dp_video_set_msa(struct dw_dp * dp,u8 color_format,u8 bpc,u16 vstart,u16 hstart)1446 static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc,
1447 u16 vstart, u16 hstart)
1448 {
1449 struct dw_dp_link *link = &dp->link;
1450 u16 misc = 0;
1451
1452 if (link->vsc_sdp_extension_for_colorimetry_supported)
1453 misc |= DP_MSA_MISC_COLOR_VSC_SDP;
1454
1455 switch (color_format) {
1456 case DRM_COLOR_FORMAT_RGB444:
1457 misc |= DP_MSA_MISC_COLOR_RGB;
1458 break;
1459 case DRM_COLOR_FORMAT_YCRCB444:
1460 misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1461 break;
1462 case DRM_COLOR_FORMAT_YCRCB422:
1463 misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709;
1464 break;
1465 case DRM_COLOR_FORMAT_YCRCB420:
1466 break;
1467 default:
1468 return -EINVAL;
1469 }
1470
1471 switch (bpc) {
1472 case 6:
1473 misc |= DP_MSA_MISC_6_BPC;
1474 break;
1475 case 8:
1476 misc |= DP_MSA_MISC_8_BPC;
1477 break;
1478 case 10:
1479 misc |= DP_MSA_MISC_10_BPC;
1480 break;
1481 case 12:
1482 misc |= DP_MSA_MISC_12_BPC;
1483 break;
1484 case 16:
1485 misc |= DP_MSA_MISC_16_BPC;
1486 break;
1487 default:
1488 return -EINVAL;
1489 }
1490
1491 regmap_write(dp->regmap, DPTX_VIDEO_MSA1,
1492 FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart));
1493 regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc));
1494 regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8));
1495
1496 return 0;
1497 }
1498
dw_dp_video_disable(struct dw_dp * dp)1499 static void dw_dp_video_disable(struct dw_dp *dp)
1500 {
1501 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,
1502 FIELD_PREP(VIDEO_STREAM_ENABLE, 0));
1503 }
1504
dw_dp_video_enable(struct dw_dp * dp)1505 static int dw_dp_video_enable(struct dw_dp *dp)
1506 {
1507 struct dw_dp_video *video = &dp->video;
1508 struct dw_dp_link *link = &dp->link;
1509 struct drm_display_mode *mode = &video->mode;
1510 u8 color_format = video->color_format;
1511 u8 bpc = video->bpc;
1512 u8 pixel_mode = video->pixel_mode;
1513 u8 bpp = video->bpp, init_threshold, vic;
1514 u32 hactive, hblank, h_sync_width, h_front_porch;
1515 u32 vactive, vblank, v_sync_width, v_front_porch;
1516 u32 vstart = mode->vtotal - mode->vsync_start;
1517 u32 hstart = mode->htotal - mode->hsync_start;
1518 u32 peak_stream_bandwidth, link_bandwidth;
1519 u32 average_bytes_per_tu, average_bytes_per_tu_frac;
1520 u32 ts, hblank_interval;
1521 u32 value;
1522 int ret;
1523
1524 ret = dw_dp_video_set_pixel_mode(dp, pixel_mode);
1525 if (ret)
1526 return ret;
1527
1528 ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart);
1529 if (ret)
1530 return ret;
1531
1532 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING,
1533 FIELD_PREP(VIDEO_MAPPING, video->video_mapping));
1534
1535 /* Configure DPTX_VINPUT_POLARITY_CTRL register */
1536 value = 0;
1537 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1538 value |= FIELD_PREP(HSYNC_IN_POLARITY, 1);
1539 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1540 value |= FIELD_PREP(VSYNC_IN_POLARITY, 1);
1541 regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value);
1542
1543 /* Configure DPTX_VIDEO_CONFIG1 register */
1544 hactive = mode->hdisplay;
1545 hblank = mode->htotal - mode->hdisplay;
1546 value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank);
1547 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1548 value |= FIELD_PREP(I_P, 1);
1549 vic = drm_match_cea_mode(mode);
1550 if (vic == 5 || vic == 6 || vic == 7 ||
1551 vic == 10 || vic == 11 || vic == 20 ||
1552 vic == 21 || vic == 22 || vic == 39 ||
1553 vic == 25 || vic == 26 || vic == 40 ||
1554 vic == 44 || vic == 45 || vic == 46 ||
1555 vic == 50 || vic == 51 || vic == 54 ||
1556 vic == 55 || vic == 58 || vic == 59)
1557 value |= R_V_BLANK_IN_OSC;
1558 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value);
1559
1560 /* Configure DPTX_VIDEO_CONFIG2 register */
1561 vblank = mode->vtotal - mode->vdisplay;
1562 vactive = mode->vdisplay;
1563 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2,
1564 FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive));
1565
1566 /* Configure DPTX_VIDEO_CONFIG3 register */
1567 h_sync_width = mode->hsync_end - mode->hsync_start;
1568 h_front_porch = mode->hsync_start - mode->hdisplay;
1569 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3,
1570 FIELD_PREP(H_SYNC_WIDTH, h_sync_width) |
1571 FIELD_PREP(H_FRONT_PORCH, h_front_porch));
1572
1573 /* Configure DPTX_VIDEO_CONFIG4 register */
1574 v_sync_width = mode->vsync_end - mode->vsync_start;
1575 v_front_porch = mode->vsync_start - mode->vdisplay;
1576 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4,
1577 FIELD_PREP(V_SYNC_WIDTH, v_sync_width) |
1578 FIELD_PREP(V_FRONT_PORCH, v_front_porch));
1579
1580 /* Configure DPTX_VIDEO_CONFIG5 register */
1581 peak_stream_bandwidth = mode->clock * bpp / 8;
1582 link_bandwidth = (link->rate / 1000) * link->lanes;
1583 ts = peak_stream_bandwidth * 64 / link_bandwidth;
1584 average_bytes_per_tu = ts / 1000;
1585 average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10;
1586 if (pixel_mode == DPTX_MP_SINGLE_PIXEL) {
1587 if (average_bytes_per_tu < 6)
1588 init_threshold = 32;
1589 else if (hblank <= 80 && color_format != DRM_COLOR_FORMAT_YCRCB420)
1590 init_threshold = 12;
1591 else if (hblank <= 40 && color_format == DRM_COLOR_FORMAT_YCRCB420)
1592 init_threshold = 3;
1593 else
1594 init_threshold = 16;
1595 } else {
1596 u32 t1 = 0, t2 = 0, t3 = 0;
1597
1598 switch (bpc) {
1599 case 6:
1600 t1 = (4 * 1000 / 9) * link->lanes;
1601 break;
1602 case 8:
1603 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1604 t1 = (1000 / 2) * link->lanes;
1605 } else {
1606 if (pixel_mode == DPTX_MP_DUAL_PIXEL)
1607 t1 = (1000 / 3) * link->lanes;
1608 else
1609 t1 = (3000 / 16) * link->lanes;
1610 }
1611 break;
1612 case 10:
1613 if (color_format == DRM_COLOR_FORMAT_YCRCB422)
1614 t1 = (2000 / 5) * link->lanes;
1615 else
1616 t1 = (4000 / 15) * link->lanes;
1617 break;
1618 case 12:
1619 if (color_format == DRM_COLOR_FORMAT_YCRCB422) {
1620 if (pixel_mode == DPTX_MP_DUAL_PIXEL)
1621 t1 = (1000 / 6) * link->lanes;
1622 else
1623 t1 = (1000 / 3) * link->lanes;
1624 } else {
1625 t1 = (2000 / 9) * link->lanes;
1626 }
1627 break;
1628 case 16:
1629 if (color_format != DRM_COLOR_FORMAT_YCRCB422 &&
1630 pixel_mode == DPTX_MP_DUAL_PIXEL)
1631 t1 = (1000 / 6) * link->lanes;
1632 else
1633 t1 = (1000 / 4) * link->lanes;
1634 break;
1635 default:
1636 return -EINVAL;
1637 }
1638
1639 if (color_format == DRM_COLOR_FORMAT_YCRCB420)
1640 t2 = (link->rate / 4) * 1000 / (mode->clock / 2);
1641 else
1642 t2 = (link->rate / 4) * 1000 / mode->clock;
1643
1644 if (average_bytes_per_tu_frac)
1645 t3 = average_bytes_per_tu + 1;
1646 else
1647 t3 = average_bytes_per_tu;
1648 init_threshold = t1 * t2 * t3 / (1000 * 1000);
1649 if (init_threshold <= 16 || average_bytes_per_tu < 10)
1650 init_threshold = 40;
1651 }
1652
1653 regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5,
1654 FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) |
1655 FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, average_bytes_per_tu_frac) |
1656 FIELD_PREP(INIT_THRESHOLD, init_threshold) |
1657 FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu));
1658
1659 /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */
1660 hblank_interval = hblank * (link->rate / 4) / mode->clock;
1661 regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL,
1662 FIELD_PREP(HBLANK_INTERVAL_EN, 1) |
1663 FIELD_PREP(HBLANK_INTERVAL, hblank_interval));
1664
1665 /* Video stream enable */
1666 regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE,
1667 FIELD_PREP(VIDEO_STREAM_ENABLE, 1));
1668
1669 if (link->vsc_sdp_extension_for_colorimetry_supported)
1670 dw_dp_send_vsc_sdp(dp);
1671
1672 return 0;
1673 }
1674
dw_dp_hpd_irq_handler(int irq,void * arg)1675 static irqreturn_t dw_dp_hpd_irq_handler(int irq, void *arg)
1676 {
1677 struct dw_dp *dp = arg;
1678 bool hpd = dw_dp_detect(dp);
1679
1680 mutex_lock(&dp->irq_lock);
1681
1682 dp->hotplug.long_hpd = true;
1683
1684 if (dp->hotplug.status && !hpd) {
1685 usleep_range(2000, 2001);
1686
1687 hpd = dw_dp_detect(dp);
1688 if (hpd)
1689 dp->hotplug.long_hpd = false;
1690 }
1691
1692 dp->hotplug.status = hpd;
1693
1694 mutex_unlock(&dp->irq_lock);
1695
1696 schedule_work(&dp->hpd_work);
1697
1698 return IRQ_HANDLED;
1699 }
1700
dw_dp_hpd_init(struct dw_dp * dp)1701 static void dw_dp_hpd_init(struct dw_dp *dp)
1702 {
1703 dp->hotplug.status = dw_dp_detect(dp);
1704
1705 if (dp->hpd_gpio) {
1706 regmap_update_bits(dp->regmap, DPTX_CCTL, FORCE_HPD,
1707 FIELD_PREP(FORCE_HPD, 1));
1708 return;
1709 }
1710
1711 /* Enable all HPD interrupts */
1712 regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE,
1713 HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN,
1714 FIELD_PREP(HPD_UNPLUG_EN, 1) |
1715 FIELD_PREP(HPD_PLUG_EN, 1) |
1716 FIELD_PREP(HPD_IRQ_EN, 1));
1717
1718 /* Enable all top-level interrupts */
1719 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,
1720 HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1));
1721 }
1722
dw_dp_aux_init(struct dw_dp * dp)1723 static void dw_dp_aux_init(struct dw_dp *dp)
1724 {
1725 regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE,
1726 AUX_REPLY_EVENT_EN,
1727 FIELD_PREP(AUX_REPLY_EVENT_EN, 1));
1728 }
1729
dw_dp_init(struct dw_dp * dp)1730 static void dw_dp_init(struct dw_dp *dp)
1731 {
1732 regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN,
1733 FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0));
1734
1735 dw_dp_hpd_init(dp);
1736 dw_dp_aux_init(dp);
1737 }
1738
dw_dp_encoder_enable(struct drm_encoder * encoder)1739 static void dw_dp_encoder_enable(struct drm_encoder *encoder)
1740 {
1741
1742 }
1743
dw_dp_encoder_disable(struct drm_encoder * encoder)1744 static void dw_dp_encoder_disable(struct drm_encoder *encoder)
1745 {
1746 struct dw_dp *dp = encoder_to_dp(encoder);
1747 struct drm_crtc *crtc = encoder->crtc;
1748 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1749
1750 if (!crtc->state->active_changed)
1751 return;
1752
1753 if (dp->split_mode)
1754 s->output_if &= ~(VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1);
1755 else
1756 s->output_if &= ~(dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0);
1757 }
1758
dw_dp_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)1759 static int dw_dp_encoder_atomic_check(struct drm_encoder *encoder,
1760 struct drm_crtc_state *crtc_state,
1761 struct drm_connector_state *conn_state)
1762 {
1763 struct dw_dp *dp = encoder_to_dp(encoder);
1764 struct dw_dp_video *video = &dp->video;
1765 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1766 struct drm_display_info *di = &conn_state->connector->display_info;
1767
1768 switch (video->color_format) {
1769 case DRM_COLOR_FORMAT_YCRCB420:
1770 s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
1771 break;
1772 case DRM_COLOR_FORMAT_YCRCB422:
1773 s->output_mode = ROCKCHIP_OUT_MODE_S888_DUMMY;
1774 break;
1775 case DRM_COLOR_FORMAT_RGB444:
1776 case DRM_COLOR_FORMAT_YCRCB444:
1777 default:
1778 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
1779 break;
1780 }
1781
1782 if (dp->split_mode) {
1783 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
1784 s->output_flags |= dp->id ? ROCKCHIP_OUTPUT_DATA_SWAP : 0;
1785 s->output_if |= VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1;
1786 } else {
1787 s->output_if |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0;
1788 }
1789
1790 s->output_type = DRM_MODE_CONNECTOR_DisplayPort;
1791 s->bus_format = video->bus_format;
1792 s->bus_flags = di->bus_flags;
1793 s->tv_state = &conn_state->tv;
1794 s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
1795 s->color_space = V4L2_COLORSPACE_DEFAULT;
1796
1797 return 0;
1798 }
1799
1800 static const struct drm_encoder_helper_funcs dw_dp_encoder_helper_funcs = {
1801 .enable = dw_dp_encoder_enable,
1802 .disable = dw_dp_encoder_disable,
1803 .atomic_check = dw_dp_encoder_atomic_check,
1804 };
1805
dw_dp_aux_write_data(struct dw_dp * dp,const u8 * buffer,size_t size)1806 static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size)
1807 {
1808 size_t i, j;
1809
1810 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
1811 size_t num = min_t(size_t, size - i * 4, 4);
1812 u32 value = 0;
1813
1814 for (j = 0; j < num; j++)
1815 value |= buffer[i * 4 + j] << (j * 8);
1816
1817 regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value);
1818 }
1819
1820 return size;
1821 }
1822
dw_dp_aux_read_data(struct dw_dp * dp,u8 * buffer,size_t size)1823 static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size)
1824 {
1825 size_t i, j;
1826
1827 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
1828 size_t num = min_t(size_t, size - i * 4, 4);
1829 u32 value;
1830
1831 regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value);
1832
1833 for (j = 0; j < num; j++)
1834 buffer[i * 4 + j] = value >> (j * 8);
1835 }
1836
1837 return size;
1838 }
1839
dw_dp_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1840 static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux,
1841 struct drm_dp_aux_msg *msg)
1842 {
1843 struct dw_dp *dp = container_of(aux, struct dw_dp, aux);
1844 unsigned long timeout = msecs_to_jiffies(250);
1845 u32 status, value;
1846 ssize_t ret = 0;
1847
1848 if (WARN_ON(msg->size > 16))
1849 return -E2BIG;
1850
1851 switch (msg->request & ~DP_AUX_I2C_MOT) {
1852 case DP_AUX_NATIVE_WRITE:
1853 case DP_AUX_I2C_WRITE:
1854 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1855 ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size);
1856 if (ret < 0)
1857 return ret;
1858 break;
1859 case DP_AUX_NATIVE_READ:
1860 case DP_AUX_I2C_READ:
1861 break;
1862 default:
1863 return -EINVAL;
1864 }
1865
1866 if (msg->size > 0)
1867 value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1);
1868 else
1869 value = FIELD_PREP(I2C_ADDR_ONLY, 1);
1870 value |= FIELD_PREP(AUX_CMD_TYPE, msg->request);
1871 value |= FIELD_PREP(AUX_ADDR, msg->address);
1872 regmap_write(dp->regmap, DPTX_AUX_CMD, value);
1873
1874 status = wait_for_completion_timeout(&dp->complete, timeout);
1875 if (!status) {
1876 dev_err(dp->dev, "timeout waiting for AUX reply\n");
1877 return -ETIMEDOUT;
1878 }
1879
1880 regmap_read(dp->regmap, DPTX_AUX_STATUS, &value);
1881 if (value & AUX_TIMEOUT)
1882 return -ETIMEDOUT;
1883
1884 msg->reply = FIELD_GET(AUX_STATUS, value);
1885
1886 if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) {
1887 if (msg->request & DP_AUX_I2C_READ) {
1888 size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1;
1889
1890 if (count != msg->size)
1891 return -EBUSY;
1892
1893 ret = dw_dp_aux_read_data(dp, msg->buffer, count);
1894 if (ret < 0)
1895 return ret;
1896 }
1897 }
1898
1899 return ret;
1900 }
1901
dw_dp_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1902 static int dw_dp_bridge_mode_valid(struct drm_bridge *bridge,
1903 const struct drm_display_info *info,
1904 const struct drm_display_mode *mode)
1905 {
1906 struct dw_dp *dp = bridge_to_dp(bridge);
1907 struct dw_dp_link *link = &dp->link;
1908 struct drm_display_mode m;
1909 u32 min_bpp;
1910
1911 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB420 &&
1912 link->vsc_sdp_extension_for_colorimetry_supported)
1913 min_bpp = 12;
1914 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1915 min_bpp = 16;
1916 else if (info->color_formats & DRM_COLOR_FORMAT_RGB444)
1917 min_bpp = 18;
1918 else
1919 min_bpp = 24;
1920
1921 drm_mode_copy(&m, mode);
1922
1923 if (dp->split_mode)
1924 drm_mode_convert_to_origin_mode(&m);
1925
1926 if (!dw_dp_bandwidth_ok(dp, &m, min_bpp, link->lanes, link->rate))
1927 return MODE_CLOCK_HIGH;
1928
1929 return MODE_OK;
1930 }
1931
dw_dp_loader_protect(struct drm_encoder * encoder,bool on)1932 static void dw_dp_loader_protect(struct drm_encoder *encoder, bool on)
1933 {
1934 struct dw_dp *dp = encoder_to_dp(encoder);
1935 struct dw_dp_link *link = &dp->link;
1936 struct drm_connector *conn = &dp->connector;
1937 struct drm_display_info *di = &conn->display_info;
1938
1939 u32 value;
1940
1941 if (on) {
1942 di->color_formats = DRM_COLOR_FORMAT_RGB444;
1943 di->bpc = 8;
1944
1945 regmap_read(dp->regmap, DPTX_PHYIF_CTRL, &value);
1946 switch (FIELD_GET(PHY_LANES, value)) {
1947 case 2:
1948 link->lanes = 4;
1949 break;
1950 case 1:
1951 link->lanes = 2;
1952 break;
1953 case 0:
1954 fallthrough;
1955 default:
1956 link->lanes = 1;
1957 break;
1958 }
1959
1960 switch (FIELD_GET(PHY_RATE, value)) {
1961 case 3:
1962 link->rate = 810000;
1963 break;
1964 case 2:
1965 link->rate = 540000;
1966 break;
1967 case 1:
1968 link->rate = 270000;
1969 break;
1970 case 0:
1971 fallthrough;
1972 default:
1973 link->rate = 162000;
1974 break;
1975 }
1976
1977 phy_power_on(dp->phy);
1978 } else {
1979 phy_power_off(dp->phy);
1980 }
1981 }
1982
dw_dp_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)1983 static int dw_dp_bridge_attach(struct drm_bridge *bridge,
1984 enum drm_bridge_attach_flags flags)
1985 {
1986 struct dw_dp *dp = bridge_to_dp(bridge);
1987 struct drm_connector *connector = &dp->connector;
1988 int ret;
1989
1990 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
1991 return 0;
1992
1993 if (!bridge->encoder) {
1994 DRM_DEV_ERROR(dp->dev, "Parent encoder object not found");
1995 return -ENODEV;
1996 }
1997
1998 connector->polled = DRM_CONNECTOR_POLL_HPD;
1999 connector->ycbcr_420_allowed = true;
2000
2001 ret = drm_connector_init(bridge->dev, connector,
2002 &dw_dp_connector_funcs,
2003 DRM_MODE_CONNECTOR_DisplayPort);
2004 if (ret) {
2005 DRM_DEV_ERROR(dp->dev, "Failed to initialize connector\n");
2006 return ret;
2007 }
2008
2009 drm_connector_helper_add(connector,
2010 &dw_dp_connector_helper_funcs);
2011
2012 drm_connector_attach_encoder(connector, bridge->encoder);
2013
2014 dp->sub_dev.connector = connector;
2015 dp->sub_dev.of_node = dp->dev->of_node;
2016 dp->sub_dev.loader_protect = dw_dp_loader_protect;
2017 rockchip_drm_register_sub_dev(&dp->sub_dev);
2018
2019 return 0;
2020 }
2021
dw_dp_bridge_detach(struct drm_bridge * bridge)2022 static void dw_dp_bridge_detach(struct drm_bridge *bridge)
2023 {
2024 struct dw_dp *dp = bridge_to_dp(bridge);
2025
2026 drm_connector_cleanup(&dp->connector);
2027 }
2028
dw_dp_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state)2029 static void dw_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
2030 struct drm_bridge_state *bridge_state)
2031 {
2032 struct dw_dp *dp = bridge_to_dp(bridge);
2033 struct dw_dp_video *video = &dp->video;
2034 struct drm_crtc_state *crtc_state = bridge->encoder->crtc->state;
2035 struct drm_display_mode *m = &video->mode;
2036
2037 drm_mode_copy(m, &crtc_state->adjusted_mode);
2038
2039 if (dp->split_mode)
2040 drm_mode_convert_to_origin_mode(m);
2041 }
2042
dw_dp_needs_link_retrain(struct dw_dp * dp)2043 static bool dw_dp_needs_link_retrain(struct dw_dp *dp)
2044 {
2045 struct dw_dp_link *link = &dp->link;
2046 u8 link_status[DP_LINK_STATUS_SIZE];
2047
2048 if (!dw_dp_link_train_valid(&link->train))
2049 return false;
2050
2051 if (drm_dp_dpcd_read_link_status(&dp->aux, link_status) < 0)
2052 return false;
2053
2054 /* Retrain if Channel EQ or CR not ok */
2055 return !drm_dp_channel_eq_ok(link_status, dp->link.lanes);
2056 }
2057
dw_dp_link_disable(struct dw_dp * dp)2058 static void dw_dp_link_disable(struct dw_dp *dp)
2059 {
2060 struct dw_dp_link *link = &dp->link;
2061
2062 if (dw_dp_detect(dp))
2063 dw_dp_link_power_down(dp);
2064
2065 dw_dp_phy_xmit_enable(dp, 0);
2066
2067 phy_power_off(dp->phy);
2068
2069 link->train.clock_recovered = false;
2070 link->train.channel_equalized = false;
2071 }
2072
dw_dp_link_enable(struct dw_dp * dp)2073 static int dw_dp_link_enable(struct dw_dp *dp)
2074 {
2075 int ret;
2076
2077 ret = phy_power_on(dp->phy);
2078 if (ret)
2079 return ret;
2080
2081 ret = dw_dp_link_power_up(dp);
2082 if (ret < 0)
2083 return ret;
2084
2085 ret = dw_dp_link_train(dp);
2086 if (ret < 0) {
2087 dev_err(dp->dev, "link training failed: %d\n", ret);
2088 return ret;
2089 }
2090
2091 return 0;
2092 }
2093
dw_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_state)2094 static void dw_dp_bridge_atomic_enable(struct drm_bridge *bridge,
2095 struct drm_bridge_state *old_state)
2096 {
2097 struct dw_dp *dp = bridge_to_dp(bridge);
2098 int ret;
2099
2100 set_bit(0, dp->sdp_reg_bank);
2101
2102 ret = dw_dp_link_enable(dp);
2103 if (ret < 0) {
2104 dev_err(dp->dev, "failed to enable link: %d\n", ret);
2105 return;
2106 }
2107
2108 ret = dw_dp_video_enable(dp);
2109 if (ret < 0) {
2110 dev_err(dp->dev, "failed to enable video: %d\n", ret);
2111 return;
2112 }
2113 }
2114
dw_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)2115 static void dw_dp_bridge_atomic_disable(struct drm_bridge *bridge,
2116 struct drm_bridge_state *old_bridge_state)
2117 {
2118 struct dw_dp *dp = bridge_to_dp(bridge);
2119
2120 dw_dp_video_disable(dp);
2121 dw_dp_link_disable(dp);
2122 bitmap_zero(dp->sdp_reg_bank, SDP_REG_BANK_SIZE);
2123 }
2124
dw_dp_detect_dpcd(struct dw_dp * dp)2125 static enum drm_connector_status dw_dp_detect_dpcd(struct dw_dp *dp)
2126 {
2127 int ret;
2128
2129 ret = phy_power_on(dp->phy);
2130 if (ret)
2131 return ret;
2132
2133 ret = dw_dp_link_probe(dp);
2134 if (ret) {
2135 phy_power_off(dp->phy);
2136 dev_err(dp->dev, "failed to probe DP link: %d\n", ret);
2137 return connector_status_disconnected;
2138 }
2139
2140 phy_power_off(dp->phy);
2141
2142 return connector_status_connected;
2143 }
2144
dw_dp_bridge_detect(struct drm_bridge * bridge)2145 static enum drm_connector_status dw_dp_bridge_detect(struct drm_bridge *bridge)
2146 {
2147 struct dw_dp *dp = bridge_to_dp(bridge);
2148 enum drm_connector_status status;
2149
2150 if (dw_dp_detect(dp))
2151 status = dw_dp_detect_dpcd(dp);
2152 else
2153 status = connector_status_disconnected;
2154
2155 if (status == connector_status_connected) {
2156 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, true);
2157 dw_dp_audio_handle_plugged_change(&dp->audio, true);
2158 } else {
2159 extcon_set_state_sync(dp->extcon, EXTCON_DISP_DP, false);
2160 dw_dp_audio_handle_plugged_change(&dp->audio, false);
2161 }
2162
2163 return status;
2164 }
2165
dw_dp_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)2166 static struct edid *dw_dp_bridge_get_edid(struct drm_bridge *bridge,
2167 struct drm_connector *connector)
2168 {
2169 struct dw_dp *dp = bridge_to_dp(bridge);
2170 struct edid *edid;
2171 int ret;
2172
2173 ret = phy_power_on(dp->phy);
2174 if (ret)
2175 return NULL;
2176
2177 edid = drm_get_edid(connector, &dp->aux.ddc);
2178
2179 phy_power_off(dp->phy);
2180
2181 return edid;
2182 }
2183
dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,unsigned int * num_output_fmts)2184 static u32 *dw_dp_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2185 struct drm_bridge_state *bridge_state,
2186 struct drm_crtc_state *crtc_state,
2187 struct drm_connector_state *conn_state,
2188 unsigned int *num_output_fmts)
2189 {
2190 struct dw_dp *dp = bridge_to_dp(bridge);
2191 struct dw_dp_state *dp_state = connector_to_dp_state(conn_state);
2192 struct dw_dp_link *link = &dp->link;
2193 struct drm_display_info *di = &conn_state->connector->display_info;
2194 struct drm_display_mode mode = crtc_state->mode;
2195 u32 *output_fmts;
2196 unsigned int i, j = 0;
2197
2198 if (dp->split_mode)
2199 drm_mode_convert_to_origin_mode(&mode);
2200
2201 *num_output_fmts = 0;
2202
2203 output_fmts = kcalloc(ARRAY_SIZE(possible_output_fmts),
2204 sizeof(*output_fmts), GFP_KERNEL);
2205 if (!output_fmts)
2206 return NULL;
2207
2208 for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) {
2209 const struct dw_dp_output_format *fmt = &possible_output_fmts[i];
2210
2211 if (fmt->bpc > conn_state->max_bpc)
2212 continue;
2213
2214 if (!(di->color_formats & fmt->color_format))
2215 continue;
2216
2217 if (fmt->color_format == DRM_COLOR_FORMAT_YCRCB420 &&
2218 !link->vsc_sdp_extension_for_colorimetry_supported)
2219 continue;
2220
2221 if (drm_mode_is_420_only(di, &mode) &&
2222 fmt->color_format != DRM_COLOR_FORMAT_YCRCB420)
2223 continue;
2224
2225 if (!dw_dp_bandwidth_ok(dp, &mode, fmt->bpp, link->lanes, link->rate))
2226 continue;
2227
2228 if (dp_state->bpc != 0) {
2229 if ((fmt->bpc != dp_state->bpc) ||
2230 (fmt->color_format != BIT(dp_state->color_format)))
2231 continue;
2232 }
2233 output_fmts[j++] = fmt->bus_format;
2234 }
2235
2236 *num_output_fmts = j;
2237
2238 return output_fmts;
2239 }
2240
dw_dp_bridge_atomic_check(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)2241 static int dw_dp_bridge_atomic_check(struct drm_bridge *bridge,
2242 struct drm_bridge_state *bridge_state,
2243 struct drm_crtc_state *crtc_state,
2244 struct drm_connector_state *conn_state)
2245 {
2246 struct dw_dp *dp = bridge_to_dp(bridge);
2247 struct dw_dp_video *video = &dp->video;
2248 const struct dw_dp_output_format *fmt =
2249 dw_dp_get_output_format(bridge_state->output_bus_cfg.format);
2250
2251 dev_dbg(dp->dev, "input format 0x%04x, output format 0x%04x\n",
2252 bridge_state->input_bus_cfg.format,
2253 bridge_state->output_bus_cfg.format);
2254
2255 video->video_mapping = fmt->video_mapping;
2256 video->color_format = fmt->color_format;
2257 video->bus_format = fmt->bus_format;
2258 video->bpc = fmt->bpc;
2259 video->bpp = fmt->bpp;
2260
2261 return 0;
2262 }
2263
2264 static const struct drm_bridge_funcs dw_dp_bridge_funcs = {
2265 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2266 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2267 .atomic_reset = drm_atomic_helper_bridge_reset,
2268 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt,
2269 .atomic_get_output_bus_fmts = dw_dp_bridge_atomic_get_output_bus_fmts,
2270 .attach = dw_dp_bridge_attach,
2271 .detach = dw_dp_bridge_detach,
2272 .mode_valid = dw_dp_bridge_mode_valid,
2273 .atomic_check = dw_dp_bridge_atomic_check,
2274 .atomic_pre_enable = dw_dp_bridge_atomic_pre_enable,
2275 .atomic_enable = dw_dp_bridge_atomic_enable,
2276 .atomic_disable = dw_dp_bridge_atomic_disable,
2277 .detect = dw_dp_bridge_detect,
2278 .get_edid = dw_dp_bridge_get_edid,
2279 };
2280
dw_dp_link_retrain(struct dw_dp * dp)2281 static int dw_dp_link_retrain(struct dw_dp *dp)
2282 {
2283 struct drm_device *dev = dp->bridge.dev;
2284 struct drm_modeset_acquire_ctx ctx;
2285 int ret;
2286
2287 if (!dw_dp_needs_link_retrain(dp))
2288 return 0;
2289
2290 dev_dbg(dp->dev, "Retraining link\n");
2291
2292 drm_modeset_acquire_init(&ctx, 0);
2293 for (;;) {
2294 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
2295 if (ret != -EDEADLK)
2296 break;
2297
2298 drm_modeset_backoff(&ctx);
2299 }
2300
2301 ret = dw_dp_link_train(dp);
2302 drm_modeset_drop_locks(&ctx);
2303 drm_modeset_acquire_fini(&ctx);
2304
2305 return ret;
2306 }
2307
dw_dp_hpd_work(struct work_struct * work)2308 static void dw_dp_hpd_work(struct work_struct *work)
2309 {
2310 struct dw_dp *dp = container_of(work, struct dw_dp, hpd_work);
2311 bool long_hpd;
2312 int ret;
2313
2314 mutex_lock(&dp->irq_lock);
2315 long_hpd = dp->hotplug.long_hpd;
2316 mutex_unlock(&dp->irq_lock);
2317
2318 dev_dbg(dp->dev, "got hpd irq - %s\n", long_hpd ? "long" : "short");
2319
2320 if (!long_hpd) {
2321 ret = dw_dp_link_retrain(dp);
2322 if (ret)
2323 dev_warn(dp->dev, "Retrain link failed\n");
2324 } else {
2325 drm_helper_hpd_irq_event(dp->bridge.dev);
2326 }
2327 }
2328
dw_dp_handle_hpd_event(struct dw_dp * dp)2329 static void dw_dp_handle_hpd_event(struct dw_dp *dp)
2330 {
2331 u32 value;
2332
2333 mutex_lock(&dp->irq_lock);
2334
2335 regmap_read(dp->regmap, DPTX_HPD_STATUS, &value);
2336
2337 if (value & HPD_IRQ) {
2338 dev_dbg(dp->dev, "IRQ from the HPD\n");
2339 dp->hotplug.long_hpd = false;
2340 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_IRQ);
2341 }
2342
2343 if (value & HPD_HOT_PLUG) {
2344 dev_dbg(dp->dev, "Hot plug detected\n");
2345 dp->hotplug.long_hpd = true;
2346 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_PLUG);
2347 }
2348
2349 if (value & HPD_HOT_UNPLUG) {
2350 dev_dbg(dp->dev, "Unplug detected\n");
2351 dp->hotplug.long_hpd = true;
2352 regmap_write(dp->regmap, DPTX_HPD_STATUS, HPD_HOT_UNPLUG);
2353 }
2354
2355 mutex_unlock(&dp->irq_lock);
2356
2357 schedule_work(&dp->hpd_work);
2358 }
2359
dw_dp_irq_handler(int irq,void * data)2360 static irqreturn_t dw_dp_irq_handler(int irq, void *data)
2361 {
2362 struct dw_dp *dp = data;
2363 u32 value;
2364
2365 regmap_read(dp->regmap, DPTX_GENERAL_INTERRUPT, &value);
2366 if (!value)
2367 return IRQ_NONE;
2368
2369 if (value & HPD_EVENT)
2370 dw_dp_handle_hpd_event(dp);
2371
2372 if (value & AUX_REPLY_EVENT) {
2373 regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT,
2374 AUX_REPLY_EVENT);
2375 complete(&dp->complete);
2376 }
2377
2378 return IRQ_HANDLED;
2379 }
2380
dw_dp_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)2381 static int dw_dp_audio_hw_params(struct device *dev, void *data,
2382 struct hdmi_codec_daifmt *daifmt,
2383 struct hdmi_codec_params *params)
2384 {
2385 struct dw_dp *dp = dev_get_drvdata(dev);
2386 struct dw_dp_audio *audio = &dp->audio;
2387 u8 audio_data_in_en, num_channels, audio_inf_select;
2388
2389 audio->channels = params->cea.channels;
2390
2391 switch (params->cea.channels) {
2392 case 1:
2393 audio_data_in_en = 0x1;
2394 num_channels = 0x0;
2395 break;
2396 case 2:
2397 audio_data_in_en = 0x1;
2398 num_channels = 0x1;
2399 break;
2400 case 8:
2401 audio_data_in_en = 0xf;
2402 num_channels = 0x7;
2403 break;
2404 default:
2405 dev_err(dp->dev, "invalid channels %d\n", params->cea.channels);
2406 return -EINVAL;
2407 }
2408
2409 switch (daifmt->fmt) {
2410 case HDMI_SPDIF:
2411 audio_inf_select = 0x1;
2412 audio->format = AFMT_SPDIF;
2413 break;
2414 case HDMI_I2S:
2415 audio_inf_select = 0x0;
2416 audio->format = AFMT_I2S;
2417 break;
2418 default:
2419 dev_err(dp->dev, "invalid daifmt %d\n", daifmt->fmt);
2420 return -EINVAL;
2421 }
2422
2423 clk_prepare_enable(dp->spdif_clk);
2424 clk_prepare_enable(dp->i2s_clk);
2425
2426 regmap_update_bits(dp->regmap, DPTX_AUD_CONFIG1,
2427 AUDIO_DATA_IN_EN | NUM_CHANNELS | AUDIO_DATA_WIDTH |
2428 AUDIO_INF_SELECT,
2429 FIELD_PREP(AUDIO_DATA_IN_EN, audio_data_in_en) |
2430 FIELD_PREP(NUM_CHANNELS, num_channels) |
2431 FIELD_PREP(AUDIO_DATA_WIDTH, params->sample_width) |
2432 FIELD_PREP(AUDIO_INF_SELECT, audio_inf_select));
2433
2434 /* Wait for inf switch */
2435 usleep_range(20, 40);
2436 if (audio->format == AFMT_I2S)
2437 clk_disable_unprepare(dp->spdif_clk);
2438 else if (audio->format == AFMT_SPDIF)
2439 clk_disable_unprepare(dp->i2s_clk);
2440
2441 return 0;
2442 }
2443
dw_dp_audio_infoframe_send(struct dw_dp * dp)2444 static int dw_dp_audio_infoframe_send(struct dw_dp *dp)
2445 {
2446 struct dw_dp_audio *audio = &dp->audio;
2447 struct hdmi_audio_infoframe frame;
2448 struct dp_sdp_header header;
2449 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
2450 u8 size = sizeof(buffer);
2451 int i, j, ret;
2452
2453 header.HB0 = 0;
2454 header.HB1 = HDMI_INFOFRAME_TYPE_AUDIO;
2455 header.HB2 = 0x1b;
2456 header.HB3 = 0x48;
2457
2458 ret = hdmi_audio_infoframe_init(&frame);
2459 if (ret < 0)
2460 return ret;
2461
2462 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
2463 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
2464 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
2465 frame.channels = audio->channels;
2466
2467 ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2468 if (ret < 0)
2469 return ret;
2470
2471 regmap_write(dp->regmap, DPTX_SDP_REGISTER_BANK,
2472 get_unaligned_le32(&header));
2473
2474 for (i = 1; i < DIV_ROUND_UP(size, 4); i++) {
2475 size_t num = min_t(size_t, size - i * 4, 4);
2476 u32 value = 0;
2477
2478 for (j = 0; j < num; j++)
2479 value |= buffer[i * 4 + j] << (j * 8);
2480
2481 regmap_write(dp->regmap, DPTX_SDP_REGISTER_BANK + 4 * i, value);
2482 }
2483
2484 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,
2485 EN_VERTICAL_SDP, FIELD_PREP(EN_VERTICAL_SDP, 1));
2486
2487 return 0;
2488 }
2489
dw_dp_audio_startup(struct device * dev,void * data)2490 static int dw_dp_audio_startup(struct device *dev, void *data)
2491 {
2492 struct dw_dp *dp = dev_get_drvdata(dev);
2493
2494 regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL,
2495 EN_AUDIO_STREAM_SDP | EN_AUDIO_TIMESTAMP_SDP,
2496 FIELD_PREP(EN_AUDIO_STREAM_SDP, 1) |
2497 FIELD_PREP(EN_AUDIO_TIMESTAMP_SDP, 1));
2498 regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL,
2499 EN_AUDIO_STREAM_SDP,
2500 FIELD_PREP(EN_AUDIO_STREAM_SDP, 1));
2501
2502 return dw_dp_audio_infoframe_send(dp);
2503 }
2504
dw_dp_audio_shutdown(struct device * dev,void * data)2505 static void dw_dp_audio_shutdown(struct device *dev, void *data)
2506 {
2507 struct dw_dp *dp = dev_get_drvdata(dev);
2508 struct dw_dp_audio *audio = &dp->audio;
2509
2510 regmap_update_bits(dp->regmap, DPTX_AUD_CONFIG1, AUDIO_DATA_IN_EN,
2511 FIELD_PREP(AUDIO_DATA_IN_EN, 0));
2512
2513 if (audio->format == AFMT_SPDIF)
2514 clk_disable_unprepare(dp->spdif_clk);
2515 else if (audio->format == AFMT_I2S)
2516 clk_disable_unprepare(dp->i2s_clk);
2517
2518 audio->format = AFMT_UNUSED;
2519 }
2520
dw_dp_audio_hook_plugged_cb(struct device * dev,void * data,hdmi_codec_plugged_cb fn,struct device * codec_dev)2521 static int dw_dp_audio_hook_plugged_cb(struct device *dev, void *data,
2522 hdmi_codec_plugged_cb fn,
2523 struct device *codec_dev)
2524 {
2525 struct dw_dp *dp = dev_get_drvdata(dev);
2526 struct dw_dp_audio *audio = &dp->audio;
2527
2528 audio->plugged_cb = fn;
2529 audio->codec_dev = codec_dev;
2530 dw_dp_audio_handle_plugged_change(audio, dw_dp_detect(dp));
2531 return 0;
2532 }
2533
dw_dp_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)2534 static int dw_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf,
2535 size_t len)
2536 {
2537 struct dw_dp *dp = dev_get_drvdata(dev);
2538 struct drm_connector *connector = &dp->connector;
2539
2540 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2541
2542 return 0;
2543 }
2544
2545 static const struct hdmi_codec_ops dw_dp_audio_codec_ops = {
2546 .hw_params = dw_dp_audio_hw_params,
2547 .audio_startup = dw_dp_audio_startup,
2548 .audio_shutdown = dw_dp_audio_shutdown,
2549 .get_eld = dw_dp_audio_get_eld,
2550 .hook_plugged_cb = dw_dp_audio_hook_plugged_cb
2551 };
2552
dw_dp_register_audio_driver(struct dw_dp * dp)2553 static int dw_dp_register_audio_driver(struct dw_dp *dp)
2554 {
2555 struct dw_dp_audio *audio = &dp->audio;
2556 struct hdmi_codec_pdata codec_data = {
2557 .ops = &dw_dp_audio_codec_ops,
2558 .spdif = 1,
2559 .i2s = 1,
2560 .max_i2s_channels = 8,
2561 };
2562
2563 audio->format = AFMT_UNUSED;
2564 audio->pdev = platform_device_register_data(dp->dev,
2565 HDMI_CODEC_DRV_NAME,
2566 PLATFORM_DEVID_AUTO,
2567 &codec_data,
2568 sizeof(codec_data));
2569
2570 return PTR_ERR_OR_ZERO(audio->pdev);
2571 }
2572
dw_dp_unregister_audio_driver(void * data)2573 static void dw_dp_unregister_audio_driver(void *data)
2574 {
2575 struct dw_dp *dp = data;
2576 struct dw_dp_audio *audio = &dp->audio;
2577
2578 if (audio->pdev) {
2579 platform_device_unregister(audio->pdev);
2580 audio->pdev = NULL;
2581 }
2582 }
2583
dw_dp_aux_unregister(void * data)2584 static void dw_dp_aux_unregister(void *data)
2585 {
2586 struct dw_dp *dp = data;
2587
2588 drm_dp_aux_unregister(&dp->aux);
2589 }
2590
dw_dp_attach_properties(struct drm_connector * connector,struct dw_dp * dp)2591 static int dw_dp_attach_properties(struct drm_connector *connector, struct dw_dp *dp)
2592 {
2593 struct drm_property *prop;
2594
2595 prop = drm_property_create_enum(connector->dev, 0, RK_IF_PROP_COLOR_DEPTH,
2596 color_depth_enum_list,
2597 ARRAY_SIZE(color_depth_enum_list));
2598 if (!prop) {
2599 dev_err(dp->dev, "create color depth prop for dp%d failed\n", dp->id);
2600 return -ENOMEM;
2601 }
2602 dp->color_depth_property = prop;
2603 drm_object_attach_property(&connector->base, prop, 0);
2604
2605 prop = drm_property_create_enum(connector->dev, 0, RK_IF_PROP_COLOR_FORMAT,
2606 color_format_enum_list,
2607 ARRAY_SIZE(color_format_enum_list));
2608 if (!prop) {
2609 dev_err(dp->dev, "create color format prop for dp%d failed\n", dp->id);
2610 return -ENOMEM;
2611 }
2612 dp->color_format_property = prop;
2613 drm_object_attach_property(&connector->base, prop, 0);
2614
2615 prop = drm_property_create_range(connector->dev, 0, RK_IF_PROP_COLOR_DEPTH_CAPS,
2616 0, 1 << RK_IF_DEPTH_MAX);
2617 if (!prop) {
2618 dev_err(dp->dev, "create color depth caps prop for dp%d failed\n", dp->id);
2619 return -ENOMEM;
2620 }
2621 dp->color_depth_capacity = prop;
2622 drm_object_attach_property(&connector->base, prop, 0);
2623
2624 prop = drm_property_create_range(connector->dev, 0, RK_IF_PROP_COLOR_FORMAT_CAPS,
2625 0, 1 << RK_IF_FORMAT_MAX);
2626 if (!prop) {
2627 dev_err(dp->dev, "create color format caps prop for dp%d failed\n", dp->id);
2628 return -ENOMEM;
2629 }
2630 dp->color_format_capacity = prop;
2631 drm_object_attach_property(&connector->base, prop, 0);
2632
2633 return 0;
2634 }
2635
dw_dp_bind(struct device * dev,struct device * master,void * data)2636 static int dw_dp_bind(struct device *dev, struct device *master, void *data)
2637 {
2638 struct dw_dp *dp = dev_get_drvdata(dev);
2639 struct drm_device *drm_dev = data;
2640 struct drm_encoder *encoder = &dp->encoder;
2641 struct drm_bridge *bridge = &dp->bridge;
2642 int ret;
2643
2644 if (!dp->left) {
2645 drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
2646 drm_encoder_helper_add(encoder, &dw_dp_encoder_helper_funcs);
2647
2648 encoder->possible_crtcs =
2649 rockchip_drm_of_find_possible_crtcs(drm_dev, dev->of_node);
2650
2651 ret = drm_bridge_attach(encoder, bridge, NULL, 0);
2652 if (ret) {
2653 dev_err(dev, "failed to attach bridge: %d\n", ret);
2654 return ret;
2655 }
2656
2657 ret = dw_dp_attach_properties(&dp->connector, dp);
2658 if (ret)
2659 return ret;
2660 }
2661
2662 if (dp->right) {
2663 struct dw_dp *secondary = dp->right;
2664
2665 ret = drm_bridge_attach(encoder, &secondary->bridge, bridge,
2666 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
2667 if (ret)
2668 return ret;
2669 }
2670
2671 pm_runtime_enable(dp->dev);
2672 pm_runtime_get_sync(dp->dev);
2673
2674 enable_irq(dp->irq);
2675
2676 return 0;
2677 }
2678
dw_dp_unbind(struct device * dev,struct device * master,void * data)2679 static void dw_dp_unbind(struct device *dev, struct device *master, void *data)
2680 {
2681 struct dw_dp *dp = dev_get_drvdata(dev);
2682
2683 disable_irq(dp->irq);
2684
2685 pm_runtime_put(dp->dev);
2686 pm_runtime_disable(dp->dev);
2687
2688 drm_encoder_cleanup(&dp->encoder);
2689 }
2690
2691 static const struct component_ops dw_dp_component_ops = {
2692 .bind = dw_dp_bind,
2693 .unbind = dw_dp_unbind,
2694 };
2695
2696 static const struct regmap_range dw_dp_readable_ranges[] = {
2697 regmap_reg_range(DPTX_VERSION_NUMBER, DPTX_ID),
2698 regmap_reg_range(DPTX_CONFIG_REG1, DPTX_CONFIG_REG3),
2699 regmap_reg_range(DPTX_CCTL, DPTX_SOFT_RESET_CTRL),
2700 regmap_reg_range(DPTX_VSAMPLE_CTRL, DPTX_VIDEO_HBLANK_INTERVAL),
2701 regmap_reg_range(DPTX_AUD_CONFIG1, DPTX_AUD_CONFIG1),
2702 regmap_reg_range(DPTX_SDP_VERTICAL_CTRL, DPTX_SDP_STATUS_EN),
2703 regmap_reg_range(DPTX_PHYIF_CTRL, DPTX_PHYIF_PWRDOWN_CTRL),
2704 regmap_reg_range(DPTX_AUX_CMD, DPTX_AUX_DATA3),
2705 regmap_reg_range(DPTX_GENERAL_INTERRUPT, DPTX_HPD_INTERRUPT_ENABLE),
2706 };
2707
2708 static const struct regmap_access_table dw_dp_readable_table = {
2709 .yes_ranges = dw_dp_readable_ranges,
2710 .n_yes_ranges = ARRAY_SIZE(dw_dp_readable_ranges),
2711 };
2712
2713 static const struct regmap_config dw_dp_regmap_config = {
2714 .reg_bits = 32,
2715 .reg_stride = 4,
2716 .val_bits = 32,
2717 .fast_io = true,
2718 .max_register = DPTX_MAX_REGISTER,
2719 .rd_table = &dw_dp_readable_table,
2720 };
2721
dw_dp_probe(struct platform_device * pdev)2722 static int dw_dp_probe(struct platform_device *pdev)
2723 {
2724 struct device *dev = &pdev->dev;
2725 struct dw_dp *dp;
2726 void __iomem *base;
2727 int id, ret;
2728
2729 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
2730 if (!dp)
2731 return -ENOMEM;
2732
2733 id = of_alias_get_id(dev->of_node, "dp");
2734 if (id < 0)
2735 id = 0;
2736
2737 dp->id = id;
2738 dp->dev = dev;
2739 dp->video.pixel_mode = DPTX_MP_QUAD_PIXEL;
2740
2741 mutex_init(&dp->irq_lock);
2742 INIT_WORK(&dp->hpd_work, dw_dp_hpd_work);
2743 init_completion(&dp->complete);
2744
2745 base = devm_platform_ioremap_resource(pdev, 0);
2746 if (IS_ERR(base))
2747 return PTR_ERR(base);
2748
2749 dp->regmap = devm_regmap_init_mmio(dev, base, &dw_dp_regmap_config);
2750 if (IS_ERR(dp->regmap))
2751 return dev_err_probe(dev, PTR_ERR(dp->regmap),
2752 "failed to create regmap\n");
2753
2754 dp->phy = devm_of_phy_get(dev, dev->of_node, NULL);
2755 if (IS_ERR(dp->phy))
2756 return dev_err_probe(dev, PTR_ERR(dp->phy),
2757 "failed to get phy\n");
2758
2759 dp->apb_clk = devm_clk_get(dev, "apb");
2760 if (IS_ERR(dp->apb_clk))
2761 return dev_err_probe(dev, PTR_ERR(dp->apb_clk),
2762 "failed to get apb clock\n");
2763
2764 dp->aux_clk = devm_clk_get(dev, "aux");
2765 if (IS_ERR(dp->aux_clk))
2766 return dev_err_probe(dev, PTR_ERR(dp->aux_clk),
2767 "failed to get aux clock\n");
2768
2769 dp->i2s_clk = devm_clk_get(dev, "i2s");
2770 if (IS_ERR(dp->i2s_clk))
2771 return dev_err_probe(dev, PTR_ERR(dp->i2s_clk),
2772 "failed to get i2s clock\n");
2773
2774 dp->spdif_clk = devm_clk_get(dev, "spdif");
2775 if (IS_ERR(dp->spdif_clk))
2776 return dev_err_probe(dev, PTR_ERR(dp->spdif_clk),
2777 "failed to get spdif clock\n");
2778
2779 dp->hclk = devm_clk_get_optional(dev, "hclk");
2780 if (IS_ERR(dp->hclk))
2781 return dev_err_probe(dev, PTR_ERR(dp->hclk),
2782 "failed to get hclk\n");
2783
2784 dp->rstc = devm_reset_control_get(dev, NULL);
2785 if (IS_ERR(dp->rstc))
2786 return dev_err_probe(dev, PTR_ERR(dp->rstc),
2787 "failed to get reset control\n");
2788
2789 dp->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2790 if (IS_ERR(dp->hpd_gpio))
2791 return dev_err_probe(dev, PTR_ERR(dp->hpd_gpio),
2792 "failed to get hpd GPIO\n");
2793 if (dp->hpd_gpio) {
2794 int hpd_irq = gpiod_to_irq(dp->hpd_gpio);
2795
2796 ret = devm_request_threaded_irq(dev, hpd_irq, NULL,
2797 dw_dp_hpd_irq_handler,
2798 IRQF_TRIGGER_RISING |
2799 IRQF_TRIGGER_FALLING |
2800 IRQF_ONESHOT, "dw-dp-hpd", dp);
2801 if (ret) {
2802 dev_err(dev, "failed to request HPD interrupt\n");
2803 return ret;
2804 }
2805 }
2806
2807 dp->irq = platform_get_irq(pdev, 0);
2808 if (dp->irq < 0)
2809 return dp->irq;
2810
2811 irq_set_status_flags(dp->irq, IRQ_NOAUTOEN);
2812 ret = devm_request_threaded_irq(dev, dp->irq, NULL, dw_dp_irq_handler,
2813 IRQF_ONESHOT, dev_name(dev), dp);
2814 if (ret) {
2815 dev_err(dev, "failed to request irq: %d\n", ret);
2816 return ret;
2817 }
2818
2819 dp->extcon = devm_extcon_dev_allocate(dev, dw_dp_cable);
2820 if (IS_ERR(dp->extcon))
2821 return dev_err_probe(dev, PTR_ERR(dp->extcon),
2822 "failed to allocate extcon device\n");
2823
2824 ret = devm_extcon_dev_register(dev, dp->extcon);
2825 if (ret)
2826 return dev_err_probe(dev, ret,
2827 "failed to register extcon device\n");
2828
2829 ret = dw_dp_register_audio_driver(dp);
2830 if (ret)
2831 return ret;
2832
2833 ret = devm_add_action_or_reset(dev, dw_dp_unregister_audio_driver, dp);
2834 if (ret)
2835 return ret;
2836
2837 dp->aux.dev = dev;
2838 dp->aux.name = dev_name(dev);
2839 dp->aux.transfer = dw_dp_aux_transfer;
2840 ret = drm_dp_aux_register(&dp->aux);
2841 if (ret)
2842 return ret;
2843
2844 ret = devm_add_action_or_reset(dev, dw_dp_aux_unregister, dp);
2845 if (ret)
2846 return ret;
2847
2848 dp->bridge.of_node = dev->of_node;
2849 dp->bridge.funcs = &dw_dp_bridge_funcs;
2850 dp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
2851 DRM_BRIDGE_OP_HPD;
2852 dp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2853
2854 platform_set_drvdata(pdev, dp);
2855
2856 if (device_property_read_bool(dev, "split-mode")) {
2857 struct dw_dp *secondary = dw_dp_find_by_id(dev->driver, !dp->id);
2858
2859 if (!secondary)
2860 return -EPROBE_DEFER;
2861
2862 dp->right = secondary;
2863 dp->split_mode = true;
2864 secondary->left = dp;
2865 secondary->split_mode = true;
2866 }
2867
2868 return component_add(dev, &dw_dp_component_ops);
2869 }
2870
dw_dp_remove(struct platform_device * pdev)2871 static int dw_dp_remove(struct platform_device *pdev)
2872 {
2873 struct dw_dp *dp = platform_get_drvdata(pdev);
2874
2875 component_del(dp->dev, &dw_dp_component_ops);
2876 cancel_work_sync(&dp->hpd_work);
2877
2878 return 0;
2879 }
2880
dw_dp_runtime_suspend(struct device * dev)2881 static int __maybe_unused dw_dp_runtime_suspend(struct device *dev)
2882 {
2883 struct dw_dp *dp = dev_get_drvdata(dev);
2884
2885 clk_disable_unprepare(dp->aux_clk);
2886 clk_disable_unprepare(dp->apb_clk);
2887 clk_disable_unprepare(dp->hclk);
2888
2889 return 0;
2890 }
2891
dw_dp_runtime_resume(struct device * dev)2892 static int __maybe_unused dw_dp_runtime_resume(struct device *dev)
2893 {
2894 struct dw_dp *dp = dev_get_drvdata(dev);
2895
2896 clk_prepare_enable(dp->hclk);
2897 clk_prepare_enable(dp->apb_clk);
2898 clk_prepare_enable(dp->aux_clk);
2899
2900 dw_dp_init(dp);
2901
2902 return 0;
2903 }
2904
2905 static const struct dev_pm_ops dw_dp_pm_ops = {
2906 SET_RUNTIME_PM_OPS(dw_dp_runtime_suspend, dw_dp_runtime_resume, NULL)
2907 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2908 pm_runtime_force_resume)
2909 };
2910
2911 static const struct of_device_id dw_dp_of_match[] = {
2912 { .compatible = "rockchip,rk3588-dp", },
2913 {}
2914 };
2915 MODULE_DEVICE_TABLE(of, dw_dp_of_match);
2916
2917 struct platform_driver dw_dp_driver = {
2918 .probe = dw_dp_probe,
2919 .remove = dw_dp_remove,
2920 .driver = {
2921 .name = "dw-dp",
2922 .of_match_table = dw_dp_of_match,
2923 .pm = &dw_dp_pm_ops,
2924 },
2925 };
2926