1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Rockchip Electronics Co.Ltd
4 * Author:
5 * Guochun Huang <hero.huang@rock-chips.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/gpio.h>
11 #include <linux/iopoll.h>
12 #include <linux/math64.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_gpio.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/phy/phy.h>
21
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_crtc.h>
24 #include <drm/drm_crtc_helper.h>
25 #include <drm/drm_dsc.h>
26 #include <drm/drm_mipi_dsi.h>
27 #include <drm/drm_of.h>
28 #include <drm/drm_panel.h>
29 #include <video/mipi_display.h>
30 #include <video/videomode.h>
31 #include <asm/unaligned.h>
32 #include <uapi/linux/videodev2.h>
33 #include <drm/drm_panel.h>
34 #include <drm/drm_connector.h>
35 #include <drm/drm_probe_helper.h>
36 #include <drm/drm_simple_kms_helper.h>
37
38 #include "rockchip_drm_drv.h"
39 #include "rockchip_drm_vop.h"
40
41 #define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l)))
42
43 #define DSI2_PWR_UP 0x000c
44 #define RESET 0
45 #define POWER_UP BIT(0)
46 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
47 #define DSI2_SOFT_RESET 0x0010
48 #define SYS_RSTN BIT(2)
49 #define PHY_RSTN BIT(1)
50 #define IPI_RSTN BIT(0)
51 #define INT_ST_MAIN 0x0014
52 #define DSI2_MODE_CTRL 0x0018
53 #define DSI2_MODE_STATUS 0x001c
54 #define DSI2_CORE_STATUS 0x0020
55 #define PRI_RD_DATA_AVAIL BIT(26)
56 #define PRI_FIFOS_NOT_EMPTY BIT(25)
57 #define PRI_BUSY BIT(24)
58 #define CRI_RD_DATA_AVAIL BIT(18)
59 #define CRT_FIFOS_NOT_EMPTY BIT(17)
60 #define CRI_BUSY BIT(16)
61 #define IPI_FIFOS_NOT_EMPTY BIT(9)
62 #define IPI_BUSY BIT(8)
63 #define CORE_FIFOS_NOT_EMPTY BIT(1)
64 #define CORE_BUSY BIT(0)
65 #define MANUAL_MODE_CFG 0x0024
66 #define MANUAL_MODE_EN BIT(0)
67 #define DSI2_TIMEOUT_HSTX_CFG 0x0048
68 #define TO_HSTX(x) UPDATE(x, 15, 0)
69 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c
70 #define TO_HSTXRDY(x) UPDATE(x, 15, 0)
71 #define DSI2_TIMEOUT_LPRX_CFG 0x0050
72 #define TO_LPRXRDY(x) UPDATE(x, 15, 0)
73 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054
74 #define TO_LPTXRDY(x) UPDATE(x, 15, 0)
75 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058
76 #define TO_LPTXTRIG(x) UPDATE(x, 15, 0)
77 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c
78 #define TO_LPTXULPS(x) UPDATE(x, 15, 0)
79 #define DSI2_TIMEOUT_BTA_CFG 0x60
80 #define TO_BTA(x) UPDATE(x, 15, 0)
81
82 #define DSI2_PHY_MODE_CFG 0x0100
83 #define PPI_WIDTH(x) UPDATE(x, 9, 8)
84 #define PHY_LANES(x) UPDATE(x - 1, 5, 4)
85 #define PHY_TYPE(x) UPDATE(x, 0, 0)
86 #define DSI2_PHY_CLK_CFG 0X0104
87 #define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8)
88 #define CLK_TYPE_MASK BIT(0)
89 #define NON_CONTINUOUS_CLK BIT(0)
90 #define CONTIUOUS_CLK 0
91 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c
92 #define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0)
93 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114
94 #define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0)
95 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c
96 #define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0)
97 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124
98 #define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0)
99 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c
100 #define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0)
101
102 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134
103 #define PHY_IPI_RATIO(x) UPDATE(x, 21, 0)
104 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C
105 #define PHY_SYS_RATIO(x) UPDATE(x, 16, 0)
106
107 #define DSI2_DSI_GENERAL_CFG 0x0200
108 #define BTA_EN BIT(1)
109 #define EOTP_TX_EN BIT(0)
110 #define DSI2_DSI_VCID_CFG 0x0204
111 #define TX_VCID(x) UPDATE(x, 1, 0)
112 #define DSI2_DSI_SCRAMBLING_CFG 0x0208
113 #define SCRAMBLING_SEED(x) UPDATE(x, 31, 16)
114 #define SCRAMBLING_EN BIT(0)
115 #define DSI2_DSI_VID_TX_CFG 0x020c
116 #define LPDT_DISPLAY_CMD_EN BIT(20)
117 #define BLK_VFP_HS_EN BIT(14)
118 #define BLK_VBP_HS_EN BIT(13)
119 #define BLK_VSA_HS_EN BIT(12)
120 #define BLK_HFP_HS_EN BIT(6)
121 #define BLK_HBP_HS_EN BIT(5)
122 #define BLK_HSA_HS_EN BIT(4)
123 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
124 #define DSI2_CRI_TX_HDR 0x02c0
125 #define CMD_TX_MODE(x) UPDATE(x, 24, 24)
126 #define DSI2_CRI_TX_PLD 0x02c4
127 #define DSI2_CRI_RX_HDR 0x02c8
128 #define DSI2_CRI_RX_PLD 0x02cc
129
130 #define DSI2_IPI_COLOR_MAN_CFG 0x0300
131 #define IPI_DEPTH(x) UPDATE(x, 7, 4)
132 #define IPI_DEPTH_5_6_5_BITS 0x02
133 #define IPI_DEPTH_6_BITS 0x03
134 #define IPI_DEPTH_8_BITS 0x05
135 #define IPI_DEPTH_10_BITS 0x06
136 #define IPI_FORMAT(x) UPDATE(x, 3, 0)
137 #define IPI_FORMAT_RGB 0x0
138 #define IPI_FORMAT_DSC 0x0b
139 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304
140 #define VID_HSA_TIME(x) UPDATE(x, 29, 0)
141 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c
142 #define VID_HBP_TIME(x) UPDATE(x, 29, 0)
143 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314
144 #define VID_HACT_TIME(x) UPDATE(x, 29, 0)
145 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c
146 #define VID_HLINE_TIME(x) UPDATE(x, 29, 0)
147 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324
148 #define VID_VSA_LINES(x) UPDATE(x, 9, 0)
149 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C
150 #define VID_VBP_LINES(x) UPDATE(x, 9, 0)
151 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334
152 #define VID_VACT_LINES(x) UPDATE(x, 13, 0)
153 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C
154 #define VID_VFP_LINES(x) UPDATE(x, 9, 0)
155 #define DSI2_IPI_PIX_PKT_CFG 0x0344
156 #define MAX_PIX_PKT(x) UPDATE(x, 15, 0)
157
158 #define DSI2_INT_ST_PHY 0x0400
159 #define DSI2_INT_MASK_PHY 0x0404
160 #define DSI2_INT_ST_TO 0x0410
161 #define DSI2_INT_MASK_TO 0x0414
162 #define DSI2_INT_ST_ACK 0x0420
163 #define DSI2_INT_MASK_ACK 0x0424
164 #define DSI2_INT_ST_IPI 0x0430
165 #define DSI2_INT_MASK_IPI 0x0434
166 #define DSI2_INT_ST_FIFO 0x0440
167 #define DSI2_INT_MASK_FIFO 0x0444
168 #define DSI2_INT_ST_PRI 0x0450
169 #define DSI2_INT_MASK_PRI 0x0454
170 #define DSI2_INT_ST_CRI 0x0460
171 #define DSI2_INT_MASK_CRI 0x0464
172 #define DSI2_INT_FORCE_CRI 0x0468
173 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI
174
175 #define MODE_STATUS_TIMEOUT_US 10000
176 #define CMD_PKT_STATUS_TIMEOUT_US 20000
177 #define PSEC_PER_SEC 1000000000000LL
178
179 #define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb))
180
181 enum vid_mode_type {
182 VID_MODE_TYPE_NON_BURST_SYNC_PULSES,
183 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS,
184 VID_MODE_TYPE_BURST,
185 };
186
187 enum mode_ctrl {
188 IDLE_MODE,
189 AUTOCALC_MODE,
190 COMMAND_MODE,
191 VIDEO_MODE,
192 DATA_STREAM_MODE,
193 VIDE_TEST_MODE,
194 DATA_STREAM_TEST_MODE,
195 };
196
197 enum grf_reg_fields {
198 TXREQCLKHS_EN,
199 GATING_EN,
200 IPI_SHUTDN,
201 IPI_COLORM,
202 IPI_COLOR_DEPTH,
203 IPI_FORMAT,
204 MAX_FIELDS,
205 };
206
207 enum phy_type {
208 DPHY,
209 CPHY,
210 };
211
212 enum ppi_width {
213 PPI_WIDTH_8_BITS,
214 PPI_WIDTH_16_BITS,
215 PPI_WIDTH_32_BITS,
216 };
217
218 struct cmd_header {
219 u8 cmd_type;
220 u8 delay;
221 u8 payload_length;
222 };
223
224 struct dw_mipi_dsi2_plat_data {
225 const u32 *dsi0_grf_reg_fields;
226 const u32 *dsi1_grf_reg_fields;
227 unsigned long long dphy_max_bit_rate_per_lane;
228 unsigned long long cphy_max_symbol_rate_per_lane;
229
230 };
231
232 struct dw_mipi_dsi2 {
233 struct drm_encoder encoder;
234 struct drm_connector connector;
235 struct drm_bridge *bridge;
236 struct mipi_dsi_host host;
237 struct drm_panel *panel;
238 struct drm_display_mode mode;
239 struct device *dev;
240 struct device_node *client;
241 struct regmap *grf;
242 struct clk *pclk;
243 struct clk *sys_clk;
244 bool phy_enabled;
245 struct phy *dcphy;
246 union phy_configure_opts phy_opts;
247
248 bool c_option;
249 bool scrambling_en;
250 unsigned int slice_width;
251 unsigned int slice_height;
252 bool dsc_enable;
253 u8 version_major;
254 u8 version_minor;
255
256 struct drm_dsc_picture_parameter_set *pps;
257 struct regmap *regmap;
258 struct reset_control *apb_rst;
259 int irq;
260 int id;
261
262 /* dual-channel */
263 struct dw_mipi_dsi2 *master;
264 struct dw_mipi_dsi2 *slave;
265 bool data_swap;
266
267 unsigned int lane_hs_rate; /* Mbps or Msps per lane */
268 u32 channel;
269 u32 lanes;
270 u32 format;
271 unsigned long mode_flags;
272
273 const struct dw_mipi_dsi2_plat_data *pdata;
274 struct rockchip_drm_sub_dev sub_dev;
275
276 struct gpio_desc *te_gpio;
277 bool user_split_mode;
278 struct drm_property *user_split_mode_prop;
279 };
280
host_to_dsi2(struct mipi_dsi_host * host)281 static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host)
282 {
283 return container_of(host, struct dw_mipi_dsi2, host);
284 }
285
con_to_dsi2(struct drm_connector * con)286 static inline struct dw_mipi_dsi2 *con_to_dsi2(struct drm_connector *con)
287 {
288 return container_of(con, struct dw_mipi_dsi2, connector);
289 }
290
encoder_to_dsi2(struct drm_encoder * encoder)291 static inline struct dw_mipi_dsi2 *encoder_to_dsi2(struct drm_encoder *encoder)
292 {
293 return container_of(encoder, struct dw_mipi_dsi2, encoder);
294 }
295
grf_field_write(struct dw_mipi_dsi2 * dsi2,enum grf_reg_fields index,unsigned int val)296 static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index,
297 unsigned int val)
298 {
299 const u32 field = dsi2->id ?
300 dsi2->pdata->dsi1_grf_reg_fields[index] :
301 dsi2->pdata->dsi0_grf_reg_fields[index];
302 u16 reg;
303 u8 msb, lsb;
304
305 if (!field)
306 return;
307
308 reg = (field >> 16) & 0xffff;
309 lsb = (field >> 8) & 0xff;
310 msb = (field >> 0) & 0xff;
311
312 regmap_write(dsi2->grf, reg, (val << lsb) | (GENMASK(msb, lsb) << 16));
313 }
314
cri_fifos_wait_avail(struct dw_mipi_dsi2 * dsi2)315 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2)
316 {
317 u32 sts, mask;
318 int ret;
319
320 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY;
321 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts,
322 !(sts & mask), 0,
323 CMD_PKT_STATUS_TIMEOUT_US);
324 if (ret < 0) {
325 DRM_DEV_ERROR(dsi2->dev, "command interface is busy\n");
326 return ret;
327 }
328
329 return 0;
330 }
331
dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 * dsi2,bool enable)332 static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable)
333 {
334 if (enable) {
335 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x1);
336 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0xf);
337 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x1);
338 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x1);
339 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x1);
340 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x1);
341 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x1);
342 } else {
343 regmap_write(dsi2->regmap, DSI2_INT_MASK_PHY, 0x0);
344 regmap_write(dsi2->regmap, DSI2_INT_MASK_TO, 0x0);
345 regmap_write(dsi2->regmap, DSI2_INT_MASK_ACK, 0x0);
346 regmap_write(dsi2->regmap, DSI2_INT_MASK_IPI, 0x0);
347 regmap_write(dsi2->regmap, DSI2_INT_MASK_FIFO, 0x0);
348 regmap_write(dsi2->regmap, DSI2_INT_MASK_PRI, 0x0);
349 regmap_write(dsi2->regmap, DSI2_INT_MASK_CRI, 0x0);
350 };
351 }
352
mipi_dcphy_power_on(struct dw_mipi_dsi2 * dsi2)353 static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2)
354 {
355 if (dsi2->phy_enabled)
356 return;
357
358 if (dsi2->dcphy)
359 phy_power_on(dsi2->dcphy);
360
361 dsi2->phy_enabled = true;
362 }
363
mipi_dcphy_power_off(struct dw_mipi_dsi2 * dsi2)364 static void mipi_dcphy_power_off(struct dw_mipi_dsi2 *dsi2)
365 {
366 if (!dsi2->phy_enabled)
367 return;
368
369 if (dsi2->dcphy)
370 phy_power_off(dsi2->dcphy);
371
372 dsi2->phy_enabled = false;
373 }
374
dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 * dsi2)375 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2)
376 {
377 u32 val = 0, mode;
378 int ret;
379
380 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
381 val |= VID_MODE_TYPE_BURST;
382 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
383 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
384
385 else
386 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
387
388 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val);
389
390
391 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE);
392 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
393 mode, mode & VIDEO_MODE,
394 1000, MODE_STATUS_TIMEOUT_US);
395 if (ret < 0)
396 dev_err(dsi2->dev, "failed to enter video mode\n");
397 }
398
dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 * dsi2)399 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2)
400 {
401 u32 mode;
402 int ret;
403
404 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, DATA_STREAM_MODE);
405 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
406 mode, mode & DATA_STREAM_MODE,
407 1000, MODE_STATUS_TIMEOUT_US);
408 if (ret < 0)
409 dev_err(dsi2->dev, "failed to enter data stream mode\n");
410 }
411
dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 * dsi2)412 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2)
413 {
414 u32 mode;
415 int ret;
416
417 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, COMMAND_MODE);
418 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS,
419 mode, mode & COMMAND_MODE,
420 1000, MODE_STATUS_TIMEOUT_US);
421 if (ret < 0)
422 dev_err(dsi2->dev, "failed to enter data stream mode\n");
423 }
424
dw_mipi_dsi2_disable(struct dw_mipi_dsi2 * dsi2)425 static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2)
426 {
427 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, 0);
428 dw_mipi_dsi2_set_cmd_mode(dsi2);
429
430 if (dsi2->slave)
431 dw_mipi_dsi2_disable(dsi2->slave);
432 }
433
dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 * dsi2)434 static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2)
435 {
436 dw_mipi_dsi2_irq_enable(dsi2, 0);
437 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
438 mipi_dcphy_power_off(dsi2);
439 pm_runtime_put(dsi2->dev);
440
441 if (dsi2->slave)
442 dw_mipi_dsi2_post_disable(dsi2->slave);
443 }
444
dw_mipi_dsi2_encoder_disable(struct drm_encoder * encoder)445 static void dw_mipi_dsi2_encoder_disable(struct drm_encoder *encoder)
446 {
447 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
448 struct drm_crtc *crtc = encoder->crtc;
449 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
450
451 if (dsi2->panel)
452 drm_panel_disable(dsi2->panel);
453
454 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
455 rockchip_drm_crtc_standby(encoder->crtc, 1);
456
457 dw_mipi_dsi2_disable(dsi2);
458
459 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
460 rockchip_drm_crtc_standby(encoder->crtc, 0);
461
462 if (dsi2->panel)
463 drm_panel_unprepare(dsi2->panel);
464
465 dw_mipi_dsi2_post_disable(dsi2);
466
467 if (!crtc->state->active_changed)
468 return;
469
470 s->output_if &= ~(dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0);
471 }
472
dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 * dsi2)473 static void dw_mipi_dsi2_set_lane_rate(struct dw_mipi_dsi2 *dsi2)
474 {
475 struct device *dev = dsi2->dev;
476 const struct drm_display_mode *mode = &dsi2->mode;
477 unsigned long max_lane_rate;
478 unsigned long lane_rate, hs_clk_rate, target_pclk;
479 unsigned int value;
480 int bpp, lanes;
481 u64 tmp;
482
483 max_lane_rate = (dsi2->c_option) ?
484 dsi2->pdata->cphy_max_symbol_rate_per_lane :
485 dsi2->pdata->dphy_max_bit_rate_per_lane;
486
487 lanes = (dsi2->slave || dsi2->master) ? dsi2->lanes * 2 : dsi2->lanes;
488 bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format);
489 if (bpp < 0)
490 bpp = 24;
491
492 /* optional override of the desired bandwidth */
493 if (!of_property_read_u32(dev->of_node, "rockchip,lane-rate", &value)) {
494 lane_rate = value * MSEC_PER_SEC;
495 } else {
496 tmp = (u64)mode->clock * 1000 * bpp;
497 do_div(tmp, lanes);
498
499 /*
500 * Multiple bits are encoded into each symbol epoch,
501 * the data rate is ~2.28x the symbol rate.
502 */
503 if (dsi2->c_option)
504 tmp = DIV_ROUND_CLOSEST_ULL(tmp * 100, 228);
505
506 /* set BW a little larger only in video burst mode in
507 * consideration of the protocol overhead and HS mode
508 * switching to BLLP mode, take 1 / 0.9, since Mbps must
509 * big than bandwidth of RGB
510 */
511 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
512 tmp *= 10;
513 do_div(tmp, 9);
514 }
515
516 if (tmp > max_lane_rate)
517 lane_rate = max_lane_rate;
518 else
519 lane_rate = tmp;
520 }
521
522 target_pclk = DIV_ROUND_CLOSEST_ULL(lane_rate * lanes, bpp);
523 phy_mipi_dphy_get_default_config(target_pclk, bpp, lanes,
524 &dsi2->phy_opts.mipi_dphy);
525
526 if (dsi2->dcphy)
527 if (!dsi2->c_option)
528 phy_set_mode(dsi2->dcphy, PHY_MODE_MIPI_DPHY);
529
530 phy_configure(dsi2->dcphy, &dsi2->phy_opts);
531 hs_clk_rate = dsi2->phy_opts.mipi_dphy.hs_clk_rate;
532 dsi2->lane_hs_rate = DIV_ROUND_UP(hs_clk_rate, MSEC_PER_SEC);
533 }
534
dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 * dsi2)535 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2)
536 {
537 if (dsi2->apb_rst) {
538 reset_control_assert(dsi2->apb_rst);
539 usleep_range(10, 20);
540 reset_control_deassert(dsi2->apb_rst);
541 }
542
543 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 0x0);
544 udelay(100);
545 regmap_write(dsi2->regmap, DSI2_SOFT_RESET,
546 SYS_RSTN | PHY_RSTN | IPI_RSTN);
547
548 }
549
dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 * dsi2)550 static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2)
551 {
552 u32 val = 0;
553
554 /* PPI width is fixed to 16 bits in DCPHY */
555 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes);
556 val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY);
557 regmap_write(dsi2->regmap, DSI2_PHY_MODE_CFG, val);
558 }
559
dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 * dsi2)560 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2)
561 {
562 u32 sys_clk, esc_clk_div;
563 u32 val = 0;
564
565 /*
566 * clk_type should be NON_CONTINUOUS_CLK before
567 * initial deskew calibration be sent.
568 */
569 val |= NON_CONTINUOUS_CLK;
570
571 /* The Escape clock ranges from 1MHz to 20MHz. */
572 sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC;
573 esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2);
574 val |= PHY_LPTX_CLK_DIV(esc_clk_div);
575
576 regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val);
577 }
578
dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 * dsi2)579 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2)
580 {
581 struct drm_display_mode *mode = &dsi2->mode;
582 u64 sys_clk = clk_get_rate(dsi2->sys_clk);
583 u64 pixel_clk, ipi_clk, phy_hsclk;
584 u64 tmp;
585
586 /*
587 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed
588 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio
589 * high speed symbol rate.
590 */
591 if (dsi2->c_option)
592 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);
593 else
594 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
595
596 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */
597 pixel_clk = mode->clock * MSEC_PER_SEC;
598 ipi_clk = pixel_clk / 4;
599
600 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk);
601 regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG,
602 PHY_IPI_RATIO(tmp));
603
604 /*
605 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq
606 */
607 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk);
608 regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG,
609 PHY_SYS_RATIO(tmp));
610 }
611
dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 * dsi2)612 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2)
613 {
614 struct phy_configure_opts_mipi_dphy *cfg = &dsi2->phy_opts.mipi_dphy;
615 unsigned long long tmp, ui;
616 unsigned long long hstx_clk;
617
618 hstx_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
619
620 ui = ALIGN(PSEC_PER_SEC, hstx_clk);
621 do_div(ui, hstx_clk);
622
623 /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */
624 tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero;
625 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
626 regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp));
627
628 /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */
629 tmp = cfg->hs_trail + cfg->hs_exit;
630 tmp = DIV_ROUND_CLOSEST_ULL(tmp << 16, ui);
631 regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp));
632 }
633
dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 * dsi2)634 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2)
635 {
636 dw_mipi_dsi2_phy_mode_cfg(dsi2);
637 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2);
638 dw_mipi_dsi2_phy_ratio_cfg(dsi2);
639 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2);
640
641 /* phy configuration 8 - 10 */
642 }
643
dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 * dsi2)644 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2)
645 {
646 u32 val;
647
648 val = BTA_EN | EOTP_TX_EN;
649
650 if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
651 val &= ~EOTP_TX_EN;
652
653 regmap_write(dsi2->regmap, DSI2_DSI_GENERAL_CFG, val);
654 regmap_write(dsi2->regmap, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel));
655
656 if (dsi2->scrambling_en)
657 regmap_write(dsi2->regmap, DSI2_DSI_SCRAMBLING_CFG,
658 SCRAMBLING_EN);
659
660 val = 0;
661 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
662 val |= BLK_HFP_HS_EN;
663
664 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
665 val |= BLK_HBP_HS_EN;
666
667 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)
668 val |= BLK_HSA_HS_EN;
669
670 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val);
671
672 /* configure the maximum return packet size that periphera can send */
673 }
674
dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 * dsi2)675 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2)
676 {
677 u32 val, color_depth;
678
679 switch (dsi2->format) {
680 case MIPI_DSI_FMT_RGB666:
681 case MIPI_DSI_FMT_RGB666_PACKED:
682 color_depth = IPI_DEPTH_6_BITS;
683 break;
684 case MIPI_DSI_FMT_RGB565:
685 color_depth = IPI_DEPTH_5_6_5_BITS;
686 break;
687 case MIPI_DSI_FMT_RGB888:
688 default:
689 color_depth = IPI_DEPTH_8_BITS;
690 break;
691 }
692
693 val = IPI_DEPTH(color_depth) |
694 IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB);
695 regmap_write(dsi2->regmap, DSI2_IPI_COLOR_MAN_CFG, val);
696 grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth);
697
698 if (dsi2->dsc_enable)
699 grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC);
700 }
701
dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 * dsi2)702 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2)
703 {
704 struct drm_display_mode *mode = &dsi2->mode;
705 u32 hline, hsa, hbp, hact;
706 u64 hline_time, hsa_time, hbp_time, hact_time, tmp;
707 u64 pixel_clk, phy_hs_clk;
708 u32 vact, vsa, vfp, vbp;
709 u16 val;
710
711 if (dsi2->slave || dsi2->master)
712 val = mode->hdisplay / 2;
713 else
714 val = mode->hdisplay;
715
716 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val));
717
718 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2);
719
720 /*
721 * if the controller is intended to operate in data stream mode,
722 * no more steps are required.
723 */
724 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO))
725 return;
726
727 vact = mode->vdisplay;
728 vsa = mode->vsync_end - mode->vsync_start;
729 vfp = mode->vsync_start - mode->vdisplay;
730 vbp = mode->vtotal - mode->vsync_end;
731 hact = mode->hdisplay;
732 hsa = mode->hsync_end - mode->hsync_start;
733 hbp = mode->htotal - mode->hsync_end;
734 hline = mode->htotal;
735
736 pixel_clk = mode->clock * MSEC_PER_SEC;
737
738 if (dsi2->c_option)
739 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 7);
740 else
741 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_hs_rate * MSEC_PER_SEC, 16);
742
743 tmp = hsa * phy_hs_clk;
744 hsa_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
745 regmap_write(dsi2->regmap, DSI2_IPI_VID_HSA_MAN_CFG,
746 VID_HSA_TIME(hsa_time));
747
748 tmp = hbp * phy_hs_clk;
749 hbp_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
750 regmap_write(dsi2->regmap, DSI2_IPI_VID_HBP_MAN_CFG,
751 VID_HBP_TIME(hbp_time));
752
753 tmp = hact * phy_hs_clk;
754 hact_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
755 regmap_write(dsi2->regmap, DSI2_IPI_VID_HACT_MAN_CFG,
756 VID_HACT_TIME(hact_time));
757
758 tmp = hline * phy_hs_clk;
759 hline_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk);
760 regmap_write(dsi2->regmap, DSI2_IPI_VID_HLINE_MAN_CFG,
761 VID_HLINE_TIME(hline_time));
762
763 regmap_write(dsi2->regmap, DSI2_IPI_VID_VSA_MAN_CFG,
764 VID_VSA_LINES(vsa));
765 regmap_write(dsi2->regmap, DSI2_IPI_VID_VBP_MAN_CFG,
766 VID_VBP_LINES(vbp));
767 regmap_write(dsi2->regmap, DSI2_IPI_VID_VACT_MAN_CFG,
768 VID_VACT_LINES(vact));
769 regmap_write(dsi2->regmap, DSI2_IPI_VID_VFP_MAN_CFG,
770 VID_VFP_LINES(vfp));
771 }
772
773 static void
dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 * dsi2,u32 mode)774 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode)
775 {
776 /*
777 * select controller work in Manual mode
778 * Manual: MANUAL_MODE_EN
779 * Automatic: 0
780 */
781 regmap_write(dsi2->regmap, MANUAL_MODE_CFG, mode);
782 }
783
dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 * dsi2)784 static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2)
785 {
786 pm_runtime_get_sync(dsi2->dev);
787
788 dw_mipi_dsi2_host_softrst(dsi2);
789 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET);
790
791 /* there may be some timeout registers may be configured if desired */
792
793 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN);
794 dw_mipi_dsi2_phy_init(dsi2);
795 dw_mipi_dsi2_tx_option_set(dsi2);
796 dw_mipi_dsi2_irq_enable(dsi2, 1);
797 mipi_dcphy_power_on(dsi2);
798
799 /*
800 * initial deskew calibration is send after phy_power_on,
801 * then we can configure clk_type.
802 */
803 if (!(dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
804 regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG,
805 CLK_TYPE_MASK, CONTIUOUS_CLK);
806
807 regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP);
808 dw_mipi_dsi2_set_cmd_mode(dsi2);
809
810 if (dsi2->slave)
811 dw_mipi_dsi2_pre_enable(dsi2->slave);
812 }
813
dw_mipi_dsi2_enable(struct dw_mipi_dsi2 * dsi2)814 static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2)
815 {
816 dw_mipi_dsi2_ipi_set(dsi2);
817
818 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)
819 dw_mipi_dsi2_set_vid_mode(dsi2);
820 else
821 dw_mipi_dsi2_set_data_stream_mode(dsi2);
822
823 if (dsi2->slave)
824 dw_mipi_dsi2_enable(dsi2->slave);
825 }
826
dw_mipi_dsi2_encoder_enable(struct drm_encoder * encoder)827 static void dw_mipi_dsi2_encoder_enable(struct drm_encoder *encoder)
828 {
829 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
830
831 if (dsi2->dcphy)
832 dw_mipi_dsi2_set_lane_rate(dsi2);
833
834 if (dsi2->slave && dsi2->slave->dcphy)
835 dw_mipi_dsi2_set_lane_rate(dsi2->slave);
836
837 dw_mipi_dsi2_pre_enable(dsi2);
838
839 if (dsi2->panel)
840 drm_panel_prepare(dsi2->panel);
841
842 dw_mipi_dsi2_enable(dsi2);
843
844 if (dsi2->panel)
845 drm_panel_enable(dsi2->panel);
846
847 DRM_DEV_INFO(dsi2->dev, "final DSI-Link bandwidth: %u x %d %s\n",
848 dsi2->lane_hs_rate,
849 dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes,
850 dsi2->c_option ? "Ksps" : "Kbps");
851 }
852
853 static int
dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)854 dw_mipi_dsi2_encoder_atomic_check(struct drm_encoder *encoder,
855 struct drm_crtc_state *crtc_state,
856 struct drm_connector_state *conn_state)
857 {
858
859 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
860 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
861 struct drm_connector *connector = conn_state->connector;
862 struct drm_display_info *info = &connector->display_info;
863
864 switch (dsi2->format) {
865 case MIPI_DSI_FMT_RGB888:
866 s->output_mode = ROCKCHIP_OUT_MODE_P888;
867 break;
868 case MIPI_DSI_FMT_RGB666:
869 s->output_mode = ROCKCHIP_OUT_MODE_P666;
870 break;
871 case MIPI_DSI_FMT_RGB565:
872 s->output_mode = ROCKCHIP_OUT_MODE_P565;
873 break;
874 default:
875 WARN_ON(1);
876 return -EINVAL;
877 }
878
879 if (info->num_bus_formats)
880 s->bus_format = info->bus_formats[0];
881 else
882 s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
883
884 s->output_type = DRM_MODE_CONNECTOR_DSI;
885 s->output_if |= dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0;
886 s->bus_flags = info->bus_flags;
887
888 s->tv_state = &conn_state->tv;
889 s->color_space = V4L2_COLORSPACE_DEFAULT;
890
891 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) {
892 s->output_flags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE;
893 s->hold_mode = true;
894 }
895
896 if (dsi2->slave) {
897 s->output_flags |= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
898 if (dsi2->data_swap)
899 s->output_flags |= ROCKCHIP_OUTPUT_DATA_SWAP;
900
901 s->output_if |= VOP_OUTPUT_IF_MIPI1;
902 }
903
904 if (dsi2->dsc_enable) {
905 s->dsc_enable = 1;
906 s->dsc_sink_cap.version_major = dsi2->version_major;
907 s->dsc_sink_cap.version_minor = dsi2->version_minor;
908 s->dsc_sink_cap.slice_width = dsi2->slice_width;
909 s->dsc_sink_cap.slice_height = dsi2->slice_height;
910 /* only can support rgb888 panel now */
911 s->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4;
912 s->dsc_sink_cap.native_420 = 0;
913
914 memcpy(&s->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set));
915 }
916
917 return 0;
918 }
919
920 static void
dw_mipi_dsi2_encoder_atomic_mode_set(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * connector_state)921 dw_mipi_dsi2_encoder_atomic_mode_set(struct drm_encoder *encoder,
922 struct drm_crtc_state *crtc_state,
923 struct drm_connector_state *connector_state)
924 {
925 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
926
927 drm_mode_copy(&dsi2->mode, &crtc_state->adjusted_mode);
928 if (dsi2->slave)
929 drm_mode_copy(&dsi2->slave->mode, &crtc_state->adjusted_mode);
930 }
931
dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 * dsi2,bool on)932 static void dw_mipi_dsi2_loader_protect(struct dw_mipi_dsi2 *dsi2, bool on)
933 {
934 if (on) {
935 pm_runtime_get_sync(dsi2->dev);
936 phy_init(dsi2->dcphy);
937 dsi2->phy_enabled = true;
938 if (dsi2->dcphy)
939 dsi2->dcphy->power_count++;
940 } else {
941 pm_runtime_put(dsi2->dev);
942 phy_exit(dsi2->dcphy);
943 dsi2->phy_enabled = false;
944 if (dsi2->dcphy)
945 dsi2->dcphy->power_count--;
946 }
947
948 if (dsi2->slave)
949 dw_mipi_dsi2_loader_protect(dsi2->slave, on);
950 }
951
dw_mipi_dsi2_encoder_loader_protect(struct drm_encoder * encoder,bool on)952 static void dw_mipi_dsi2_encoder_loader_protect(struct drm_encoder *encoder,
953 bool on)
954 {
955 struct dw_mipi_dsi2 *dsi2 = encoder_to_dsi2(encoder);
956
957 if (dsi2->panel)
958 panel_simple_loader_protect(dsi2->panel);
959
960 dw_mipi_dsi2_loader_protect(dsi2, on);
961 }
962
963 static const struct drm_encoder_helper_funcs
964 dw_mipi_dsi2_encoder_helper_funcs = {
965 .enable = dw_mipi_dsi2_encoder_enable,
966 .disable = dw_mipi_dsi2_encoder_disable,
967 .atomic_check = dw_mipi_dsi2_encoder_atomic_check,
968 .atomic_mode_set = dw_mipi_dsi2_encoder_atomic_mode_set,
969 };
970
dw_mipi_dsi2_connector_get_modes(struct drm_connector * connector)971 static int dw_mipi_dsi2_connector_get_modes(struct drm_connector *connector)
972 {
973 struct dw_mipi_dsi2 *dsi2 = con_to_dsi2(connector);
974
975 return drm_panel_get_modes(dsi2->panel, connector);
976 }
977
dw_mipi_dsi2_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)978 static int dw_mipi_dsi2_connector_mode_valid(struct drm_connector *connector,
979 struct drm_display_mode *mode)
980 {
981 struct videomode vm;
982
983 drm_display_mode_to_videomode(mode, &vm);
984
985 /*
986 * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels
987 * which is the ip known issues and limitations.
988 */
989 if (!(vm.hsync_len < 4 || vm.hback_porch < 4 ||
990 vm.hfront_porch < 4 || vm.hactive < 4))
991 return MODE_OK;
992
993 if (vm.hsync_len < 4)
994 vm.hsync_len = 4;
995
996 if (vm.hback_porch < 4)
997 vm.hback_porch = 4;
998
999 if (vm.hfront_porch < 4)
1000 vm.hfront_porch = 4;
1001
1002 if (vm.hactive < 4)
1003 vm.hactive = 4;
1004
1005 drm_display_mode_from_videomode(&vm, mode);
1006
1007 return MODE_OK;
1008 }
1009
1010 static struct drm_connector_helper_funcs dw_mipi_dsi2_connector_helper_funcs = {
1011 .get_modes = dw_mipi_dsi2_connector_get_modes,
1012 .mode_valid = dw_mipi_dsi2_connector_mode_valid,
1013 };
1014
dw_mipi_dsi2_drm_connector_destroy(struct drm_connector * connector)1015 static void dw_mipi_dsi2_drm_connector_destroy(struct drm_connector *connector)
1016 {
1017 drm_connector_unregister(connector);
1018 drm_connector_cleanup(connector);
1019 }
1020
1021 static const struct drm_connector_funcs dw_mipi_dsi2_atomic_connector_funcs = {
1022 .fill_modes = drm_helper_probe_single_connector_modes,
1023 .destroy = dw_mipi_dsi2_drm_connector_destroy,
1024 .reset = drm_atomic_helper_connector_reset,
1025 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1026 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1027 };
1028
dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 * dsi2)1029 static int dw_mipi_dsi2_dual_channel_probe(struct dw_mipi_dsi2 *dsi2)
1030 {
1031 struct device_node *np;
1032 struct platform_device *secondary;
1033
1034 np = of_parse_phandle(dsi2->dev->of_node, "rockchip,dual-channel", 0);
1035 if (np) {
1036 dsi2->data_swap = of_property_read_bool(dsi2->dev->of_node,
1037 "rockchip,data-swap");
1038 secondary = of_find_device_by_node(np);
1039 dsi2->slave = platform_get_drvdata(secondary);
1040 of_node_put(np);
1041
1042 if (!dsi2->slave)
1043 return -EPROBE_DEFER;
1044
1045 dsi2->slave->master = dsi2;
1046 dsi2->lanes /= 2;
1047
1048 dsi2->slave->lanes = dsi2->lanes;
1049 dsi2->slave->channel = dsi2->channel;
1050 dsi2->slave->format = dsi2->format;
1051 dsi2->slave->mode_flags = dsi2->mode_flags;
1052 }
1053
1054 return 0;
1055 }
1056
dw_mipi_dsi2_te_irq_handler(int irq,void * dev_id)1057 static irqreturn_t dw_mipi_dsi2_te_irq_handler(int irq, void *dev_id)
1058 {
1059 struct dw_mipi_dsi2 *dsi2 = (struct dw_mipi_dsi2 *)dev_id;
1060 struct drm_encoder *encoder = &dsi2->encoder;
1061
1062 rockchip_drm_te_handle(encoder->crtc);
1063
1064 return IRQ_HANDLED;
1065 }
1066
dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 * dsi2,struct drm_panel * panel,struct drm_bridge * bridge)1067 static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2,
1068 struct drm_panel *panel,
1069 struct drm_bridge *bridge)
1070 {
1071 struct drm_dsc_picture_parameter_set *pps = NULL;
1072 struct device_node *np = NULL;
1073 struct cmd_header *header;
1074 const void *data;
1075 char *d;
1076 uint8_t *dsc_packed_pps;
1077 int len;
1078
1079 if (!panel && !bridge)
1080 return -ENODEV;
1081
1082 if (panel)
1083 np = panel->dev->of_node;
1084 else
1085 np = bridge->of_node;
1086
1087 dsi2->c_option = of_property_read_bool(np, "phy-c-option");
1088 dsi2->scrambling_en = of_property_read_bool(np, "scrambling-enable");
1089 dsi2->dsc_enable = of_property_read_bool(np, "compressed-data");
1090
1091 if (dsi2->slave) {
1092 dsi2->slave->c_option = dsi2->c_option;
1093 dsi2->slave->scrambling_en = dsi2->scrambling_en;
1094 dsi2->slave->dsc_enable = dsi2->dsc_enable;
1095 }
1096
1097 of_property_read_u32(np, "slice-width", &dsi2->slice_width);
1098 of_property_read_u32(np, "slice-height", &dsi2->slice_height);
1099 of_property_read_u8(np, "version-major", &dsi2->version_major);
1100 of_property_read_u8(np, "version-minor", &dsi2->version_minor);
1101
1102 data = of_get_property(np, "panel-init-sequence", &len);
1103 if (!data)
1104 return -EINVAL;
1105
1106 d = devm_kmemdup(dsi2->dev, data, len, GFP_KERNEL);
1107 if (!d)
1108 return -ENOMEM;
1109
1110 while (len > sizeof(*header)) {
1111 header = (struct cmd_header *)d;
1112 d += sizeof(*header);
1113 len -= sizeof(*header);
1114
1115 if (header->payload_length > len)
1116 return -EINVAL;
1117
1118 if (header->cmd_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
1119 dsc_packed_pps = devm_kmemdup(dsi2->dev, d,
1120 header->payload_length, GFP_KERNEL);
1121 if (!dsc_packed_pps)
1122 return -ENOMEM;
1123
1124 pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
1125 break;
1126 }
1127
1128 d += header->payload_length;
1129 len -= header->payload_length;
1130 }
1131
1132 dsi2->pps = pps;
1133
1134 return 0;
1135 }
1136
dw_mipi_dsi2_bind(struct device * dev,struct device * master,void * data)1137 static int dw_mipi_dsi2_bind(struct device *dev, struct device *master,
1138 void *data)
1139 {
1140 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1141 struct drm_device *drm_dev = data;
1142 struct drm_encoder *encoder = &dsi2->encoder;
1143 struct drm_connector *connector = &dsi2->connector;
1144 struct device_node *of_node = dsi2->dev->of_node;
1145 struct drm_property *prop;
1146 int ret;
1147
1148 ret = dw_mipi_dsi2_dual_channel_probe(dsi2);
1149 if (ret)
1150 return ret;
1151
1152 if (dsi2->master)
1153 return 0;
1154
1155 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, -1,
1156 &dsi2->panel, &dsi2->bridge);
1157 if (ret) {
1158 DRM_DEV_ERROR(dev, "Failed to find panel or bridge: %d\n", ret);
1159 return ret;
1160 }
1161
1162 dw_mipi_dsi2_get_dsc_params_from_sink(dsi2, dsi2->panel, dsi2->bridge);
1163 encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
1164 of_node);
1165
1166 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI);
1167 if (ret) {
1168 DRM_ERROR("Failed to initialize encoder with drm\n");
1169 return ret;
1170 }
1171
1172 drm_encoder_helper_add(encoder, &dw_mipi_dsi2_encoder_helper_funcs);
1173
1174 if (dsi2->panel) {
1175 ret = drm_connector_init(drm_dev, connector,
1176 &dw_mipi_dsi2_atomic_connector_funcs,
1177 DRM_MODE_CONNECTOR_DSI);
1178 if (ret) {
1179 DRM_DEV_ERROR(dev, "Failed to initialize connector\n");
1180 goto encoder_cleanup;
1181 }
1182
1183 drm_connector_helper_add(connector,
1184 &dw_mipi_dsi2_connector_helper_funcs);
1185 ret = drm_connector_attach_encoder(connector, encoder);
1186 if (ret < 0) {
1187 DRM_DEV_ERROR(dev, "Failed to attach encoder: %d\n", ret);
1188 goto connector_cleanup;
1189 }
1190
1191 prop = drm_property_create_bool(drm_dev, DRM_MODE_PROP_IMMUTABLE,
1192 "USER_SPLIT_MODE");
1193 if (!prop) {
1194 ret = -EINVAL;
1195 DRM_DEV_ERROR(dev, "create user split mode prop failed\n");
1196 goto connector_cleanup;
1197 }
1198
1199 dsi2->user_split_mode_prop = prop;
1200 drm_object_attach_property(&dsi2->connector.base,
1201 dsi2->user_split_mode_prop,
1202 dsi2->user_split_mode ? 1 : 0);
1203
1204 dsi2->sub_dev.connector = &dsi2->connector;
1205 dsi2->sub_dev.of_node = dev->of_node;
1206 dsi2->sub_dev.loader_protect = dw_mipi_dsi2_encoder_loader_protect;
1207 rockchip_drm_register_sub_dev(&dsi2->sub_dev);
1208 } else {
1209 dsi2->bridge->driver_private = &dsi2->host;
1210 dsi2->bridge->encoder = encoder;
1211
1212 ret = drm_bridge_attach(encoder, dsi2->bridge, NULL, 0);
1213 if (ret) {
1214 DRM_DEV_ERROR(dev,
1215 "Failed to attach bridge: %d\n", ret);
1216 goto encoder_cleanup;
1217 }
1218
1219 }
1220
1221 pm_runtime_enable(dsi2->dev);
1222 if (dsi2->slave)
1223 pm_runtime_enable(dsi2->slave->dev);
1224
1225 return 0;
1226
1227 connector_cleanup:
1228 connector->funcs->destroy(connector);
1229 encoder_cleanup:
1230 encoder->funcs->destroy(encoder);
1231
1232 return ret;
1233 }
1234
dw_mipi_dsi2_unbind(struct device * dev,struct device * master,void * data)1235 static void dw_mipi_dsi2_unbind(struct device *dev, struct device *master,
1236 void *data)
1237 {
1238 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1239
1240 if (dsi2->sub_dev.connector)
1241 rockchip_drm_unregister_sub_dev(&dsi2->sub_dev);
1242
1243 pm_runtime_disable(dsi2->dev);
1244 if (dsi2->slave)
1245 pm_runtime_disable(dsi2->slave->dev);
1246
1247 dsi2->connector.funcs->destroy(&dsi2->connector);
1248 dsi2->encoder.funcs->destroy(&dsi2->encoder);
1249 }
1250
1251 static const struct component_ops dw_mipi_dsi2_ops = {
1252 .bind = dw_mipi_dsi2_bind,
1253 .unbind = dw_mipi_dsi2_unbind,
1254 };
1255
1256 struct dsi2_irq_data {
1257 u32 offeset;
1258 char *irq_src;
1259 };
1260
1261 static const struct dsi2_irq_data dw_mipi_dsi2_irq_data[] = {
1262 {DSI2_INT_ST_PHY, "int_st_phy"},
1263 {DSI2_INT_ST_TO, "int_st_to"},
1264 {DSI2_INT_ST_ACK, "int_st_ack"},
1265 {DSI2_INT_ST_IPI, "int_st_ipi"},
1266 {DSI2_INT_ST_FIFO, "int_st_fifo"},
1267 {DSI2_INT_ST_PRI, "int_st_pri"},
1268 {DSI2_INT_ST_CRI, "int_st_cri"},
1269 };
1270
dw_mipi_dsi2_irq_handler(int irq,void * dev_id)1271 static irqreturn_t dw_mipi_dsi2_irq_handler(int irq, void *dev_id)
1272 {
1273
1274 struct dw_mipi_dsi2 *dsi2 = dev_id;
1275 u32 int_st;
1276 unsigned int i;
1277
1278 regmap_read(dsi2->regmap, INT_ST_MAIN, &int_st);
1279
1280 for (i = 0; i < ARRAY_SIZE(dw_mipi_dsi2_irq_data); i++)
1281 if (int_st & BIT(i))
1282 DRM_DEV_DEBUG(dsi2->dev, "%s\n",
1283 dw_mipi_dsi2_irq_data[i].irq_src);
1284
1285 return IRQ_HANDLED;
1286 }
1287
1288 static const struct regmap_config dw_mipi_dsi2_regmap_config = {
1289 .name = "host",
1290 .reg_bits = 32,
1291 .val_bits = 32,
1292 .reg_stride = 4,
1293 .fast_io = true,
1294 .max_register = DSI2_MAX_REGISGER,
1295 };
1296
dw_mipi_dsi2_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1297 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host,
1298 struct mipi_dsi_device *device)
1299 {
1300 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host);
1301
1302 if (dsi2->master)
1303 return 0;
1304
1305 if (device->lanes < 1 || device->lanes > 8)
1306 return -EINVAL;
1307
1308 dsi2->client = device->dev.of_node;
1309 dsi2->lanes = device->lanes;
1310 dsi2->channel = device->channel;
1311 dsi2->format = device->format;
1312 dsi2->mode_flags = device->mode_flags;
1313
1314 return 0;
1315 }
1316
dw_mipi_dsi2_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)1317 static int dw_mipi_dsi2_host_detach(struct mipi_dsi_host *host,
1318 struct mipi_dsi_device *device)
1319 {
1320 return 0;
1321 }
1322
dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 * dsi2,const struct mipi_dsi_msg * msg)1323 static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2,
1324 const struct mipi_dsi_msg *msg)
1325 {
1326 u8 *payload = msg->rx_buf;
1327 u8 data_type;
1328 u16 wc;
1329 int i, j, ret, len = msg->rx_len;
1330 unsigned int vrefresh = drm_mode_vrefresh(&dsi2->mode);
1331 u32 val;
1332
1333 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS,
1334 val, val & CRI_RD_DATA_AVAIL,
1335 0, DIV_ROUND_UP(1000000, vrefresh));
1336 if (ret) {
1337 DRM_DEV_ERROR(dsi2->dev, "CRI has no available read data\n");
1338 return ret;
1339 }
1340
1341 regmap_read(dsi2->regmap, DSI2_CRI_RX_HDR, &val);
1342 data_type = val & 0x3f;
1343
1344 if (mipi_dsi_packet_format_is_short(data_type)) {
1345 for (i = 0; i < len && i < 2; i++)
1346 payload[i] = (val >> (8 * (i + 1))) & 0xff;
1347
1348 return 0;
1349 }
1350
1351 wc = (val >> 8) & 0xffff;
1352 /* Receive payload */
1353 for (i = 0; i < len && i < wc; i += 4) {
1354 regmap_read(dsi2->regmap, DSI2_CRI_RX_PLD, &val);
1355 for (j = 0; j < 4 && j + i < len && j + i < wc; j++)
1356 payload[i + j] = val >> (8 * j);
1357 }
1358
1359 return 0;
1360 }
1361
dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 * dsi2,const struct mipi_dsi_msg * msg)1362 static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2,
1363 const struct mipi_dsi_msg *msg)
1364 {
1365 struct mipi_dsi_packet packet;
1366 int ret;
1367 u32 val;
1368 u32 mode;
1369
1370 regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG,
1371 LPDT_DISPLAY_CMD_EN,
1372 msg->flags & MIPI_DSI_MSG_USE_LPM ?
1373 LPDT_DISPLAY_CMD_EN : 0);
1374
1375 /* create a packet to the DSI protocol */
1376 ret = mipi_dsi_create_packet(&packet, msg);
1377 if (ret) {
1378 DRM_DEV_ERROR(dsi2->dev, "failed to create packet: %d\n", ret);
1379 return ret;
1380 }
1381
1382 ret = cri_fifos_wait_avail(dsi2);
1383 if (ret)
1384 return ret;
1385
1386 /* Send payload */
1387 while (DIV_ROUND_UP(packet.payload_length, 4)) {
1388 /* check cri interface is not busy */
1389 if (packet.payload_length < 4) {
1390 /* send residu payload */
1391 val = 0;
1392 memcpy(&val, packet.payload, packet.payload_length);
1393 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val);
1394 packet.payload_length = 0;
1395 } else {
1396 val = get_unaligned_le32(packet.payload);
1397 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, val);
1398 packet.payload += 4;
1399 packet.payload_length -= 4;
1400 }
1401 }
1402
1403 /* Send packet header */
1404 mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0);
1405 val = get_unaligned_le32(packet.header);
1406
1407 regmap_write(dsi2->regmap, DSI2_CRI_TX_HDR, mode | val);
1408
1409 ret = cri_fifos_wait_avail(dsi2);
1410 if (ret)
1411 return ret;
1412
1413 if (msg->rx_len) {
1414 ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg);
1415 if (ret < 0)
1416 return ret;
1417 }
1418
1419 if (dsi2->slave)
1420 dw_mipi_dsi2_transfer(dsi2->slave, msg);
1421
1422 return msg->tx_len;
1423 }
1424
dw_mipi_dsi2_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1425 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host,
1426 const struct mipi_dsi_msg *msg)
1427 {
1428 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host);
1429
1430 return dw_mipi_dsi2_transfer(dsi2, msg);
1431 }
1432
1433 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = {
1434 .attach = dw_mipi_dsi2_host_attach,
1435 .detach = dw_mipi_dsi2_host_detach,
1436 .transfer = dw_mipi_dsi2_host_transfer,
1437 };
1438
dw_mipi_dsi2_probe(struct platform_device * pdev)1439 static int dw_mipi_dsi2_probe(struct platform_device *pdev)
1440 {
1441 struct device *dev = &pdev->dev;
1442 struct dw_mipi_dsi2 *dsi2;
1443 struct resource *res;
1444 void __iomem *regs;
1445 int id;
1446 int ret;
1447
1448 dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL);
1449 if (!dsi2)
1450 return -ENOMEM;
1451
1452 id = of_alias_get_id(dev->of_node, "dsi");
1453 if (id < 0)
1454 id = 0;
1455
1456 dsi2->dev = dev;
1457 dsi2->id = id;
1458 dsi2->pdata = of_device_get_match_data(dev);
1459 platform_set_drvdata(pdev, dsi2);
1460 dsi2->user_split_mode = device_property_read_bool(dev, "user-split-mode");
1461
1462 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1463 regs = devm_ioremap_resource(dev, res);
1464 if (IS_ERR(regs))
1465 return PTR_ERR(regs);
1466
1467 dsi2->irq = platform_get_irq(pdev, 0);
1468 if (dsi2->irq < 0)
1469 return dsi2->irq;
1470
1471 dsi2->pclk = devm_clk_get(dev, "pclk");
1472 if (IS_ERR(dsi2->pclk)) {
1473 ret = PTR_ERR(dsi2->pclk);
1474 DRM_DEV_ERROR(dev, "Unable to get pclk: %d\n", ret);
1475 return ret;
1476 }
1477
1478 dsi2->sys_clk = devm_clk_get(dev, "sys_clk");
1479 if (IS_ERR(dsi2->sys_clk)) {
1480 ret = PTR_ERR(dsi2->sys_clk);
1481 DRM_DEV_ERROR(dev, "Unable to get sys_clk: %d\n", ret);
1482 return ret;
1483 }
1484
1485 dsi2->regmap = devm_regmap_init_mmio(dev, regs,
1486 &dw_mipi_dsi2_regmap_config);
1487 if (IS_ERR(dsi2->regmap)) {
1488 ret = PTR_ERR(dsi2->regmap);
1489 DRM_DEV_ERROR(dev, "failed to init register map: %d\n", ret);
1490 return ret;
1491 }
1492
1493 dsi2->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1494 "rockchip,grf");
1495 if (IS_ERR(dsi2->grf)) {
1496 ret = PTR_ERR(dsi2->grf);
1497 DRM_DEV_ERROR(dsi2->dev, "Unable to get grf: %d\n", ret);
1498 return ret;
1499 }
1500
1501 dsi2->apb_rst = devm_reset_control_get(dev, "apb");
1502 if (IS_ERR(dsi2->apb_rst)) {
1503 ret = PTR_ERR(dsi2->apb_rst);
1504 DRM_DEV_ERROR(dev,
1505 "Unable to get reset control: %d\n", ret);
1506 return ret;
1507 }
1508
1509 dsi2->dcphy = devm_phy_optional_get(dev, "dcphy");
1510 if (IS_ERR(dsi2->dcphy)) {
1511 ret = PTR_ERR(dsi2->dcphy);
1512 DRM_DEV_ERROR(dev, "failed to get mipi dcphy: %d\n", ret);
1513 return ret;
1514 }
1515
1516 dsi2->te_gpio = devm_gpiod_get_optional(dsi2->dev, "te", GPIOD_IN);
1517 if (IS_ERR(dsi2->te_gpio))
1518 dsi2->te_gpio = NULL;
1519
1520 if (dsi2->te_gpio) {
1521 ret = devm_request_threaded_irq(dsi2->dev, gpiod_to_irq(dsi2->te_gpio),
1522 NULL, dw_mipi_dsi2_te_irq_handler,
1523 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1524 "PANEL-TE", dsi2);
1525 if (ret) {
1526 dev_err(dsi2->dev, "failed to request TE IRQ: %d\n", ret);
1527 return ret;
1528 }
1529 }
1530
1531 ret = devm_request_irq(dev, dsi2->irq, dw_mipi_dsi2_irq_handler,
1532 IRQF_SHARED, dev_name(dev), dsi2);
1533 if (ret) {
1534 DRM_DEV_ERROR(dev, "failed to request irq: %d\n", ret);
1535 return ret;
1536 }
1537
1538 dsi2->host.ops = &dw_mipi_dsi2_host_ops;
1539 dsi2->host.dev = dev;
1540 ret = mipi_dsi_host_register(&dsi2->host);
1541 if (ret) {
1542 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1543 return ret;
1544 }
1545
1546 return component_add(&pdev->dev, &dw_mipi_dsi2_ops);
1547 }
1548
dw_mipi_dsi2_remove(struct platform_device * pdev)1549 static int dw_mipi_dsi2_remove(struct platform_device *pdev)
1550 {
1551 return 0;
1552 }
1553
dw_mipi_dsi2_runtime_suspend(struct device * dev)1554 static __maybe_unused int dw_mipi_dsi2_runtime_suspend(struct device *dev)
1555 {
1556 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1557
1558 clk_disable_unprepare(dsi2->pclk);
1559 clk_disable_unprepare(dsi2->sys_clk);
1560
1561 return 0;
1562 }
1563
dw_mipi_dsi2_runtime_resume(struct device * dev)1564 static __maybe_unused int dw_mipi_dsi2_runtime_resume(struct device *dev)
1565 {
1566 struct dw_mipi_dsi2 *dsi2 = dev_get_drvdata(dev);
1567
1568 clk_prepare_enable(dsi2->pclk);
1569 clk_prepare_enable(dsi2->sys_clk);
1570
1571 return 0;
1572 }
1573
1574 static const struct dev_pm_ops dw_mipi_dsi2_rockchip_pm_ops = {
1575 SET_RUNTIME_PM_OPS(dw_mipi_dsi2_runtime_suspend,
1576 dw_mipi_dsi2_runtime_resume, NULL)
1577 };
1578
1579 static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = {
1580 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11),
1581 [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10),
1582 [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9),
1583 [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8),
1584 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7),
1585 [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3),
1586 };
1587
1588 static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = {
1589 [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11),
1590 [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10),
1591 [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9),
1592 [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8),
1593 [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7),
1594 [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3),
1595 };
1596
1597 static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = {
1598 .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields,
1599 .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields,
1600 .dphy_max_bit_rate_per_lane = 4500000000ULL,
1601 .cphy_max_symbol_rate_per_lane = 2000000000ULL,
1602 };
1603
1604 static const struct of_device_id dw_mipi_dsi2_dt_ids[] = {
1605 {
1606 .compatible = "rockchip,rk3588-mipi-dsi2",
1607 .data = &rk3588_mipi_dsi2_plat_data,
1608 },
1609 {}
1610 };
1611 MODULE_DEVICE_TABLE(of, dw_mipi_dsi2_dt_ids);
1612
1613 struct platform_driver dw_mipi_dsi2_rockchip_driver = {
1614 .probe = dw_mipi_dsi2_probe,
1615 .remove = dw_mipi_dsi2_remove,
1616 .driver = {
1617 .of_match_table = dw_mipi_dsi2_dt_ids,
1618 .pm = &dw_mipi_dsi2_rockchip_pm_ops,
1619 .name = "dw-mipi-dsi2",
1620 },
1621 };
1622