1 /* 2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 3 * Author: 4 * algea cao <algea.cao@rock-chips.com> 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #ifndef __ROCKCHIP_DRM_TVE_H__ 16 #define __ROCKCHIP_DRM_TVE_H__ 17 18 #define TV_CTRL (0x00) 19 #define m_CVBS_MODE BIT(24) 20 #define m_CLK_UPSTREAM_EN (3 << 18) 21 #define m_TIMING_EN (3 << 16) 22 #define m_LUMA_FILTER_GAIN (3 << 9) 23 #define m_LUMA_FILTER_BW BIT(8) 24 #define m_CSC_PATH (3 << 1) 25 26 #define v_CVBS_MODE(x) (((x) & 1) << 24) 27 #define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18) 28 #define v_TIMING_EN(x) (((x) & 3) << 16) 29 #define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9) 30 #define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8) 31 #define v_CSC_PATH(x) (((x) & 3) << 1) 32 33 #define TV_SYNC_TIMING (0x04) 34 #define TV_ACT_TIMING (0x08) 35 #define TV_ADJ_TIMING (0x0c) 36 #define TV_FREQ_SC (0x10) 37 #define TV_LUMA_FILTER0 (0x14) 38 #define TV_LUMA_FILTER1 (0x18) 39 #define TV_LUMA_FILTER2 (0x1C) 40 #define TV_ACT_ST (0x34) 41 #define TV_ROUTING (0x38) 42 #define m_DAC_SENSE_EN BIT(27) 43 #define m_Y_IRE_7_5 BIT(19) 44 #define m_Y_AGC_PULSE_ON BIT(15) 45 #define m_Y_VIDEO_ON BIT(11) 46 #define m_Y_SYNC_ON BIT(7) 47 #define m_YPP_MODE BIT(3) 48 #define m_MONO_EN BIT(2) 49 #define m_PIC_MODE BIT(1) 50 51 #define v_DAC_SENSE_EN(x) (((x) & 1) << 27) 52 #define v_Y_IRE_7_5(x) (((x) & 1) << 19) 53 #define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15) 54 #define v_Y_VIDEO_ON(x) (((x) & 1) << 11) 55 #define v_Y_SYNC_ON(x) (((x) & 1) << 7) 56 #define v_YPP_MODE(x) (((x) & 1) << 3) 57 #define v_MONO_EN(x) (((x) & 1) << 2) 58 #define v_PIC_MODE(x) (((x) & 1) << 1) 59 60 #define TV_SYNC_ADJUST (0x50) 61 #define TV_STATUS (0x54) 62 #define TV_RESET (0x68) 63 #define m_RESET BIT(1) 64 #define v_RESET(x) (((x) & 1) << 1) 65 #define TV_SATURATION (0x78) 66 #define TV_BW_CTRL (0x8C) 67 #define m_CHROMA_BW (3 << 4) 68 #define m_COLOR_DIFF_BW (0xf) 69 70 enum { 71 BP_FILTER_PASS = 0, 72 BP_FILTER_NTSC, 73 BP_FILTER_PAL, 74 }; 75 enum { 76 COLOR_DIFF_FILTER_OFF = 0, 77 COLOR_DIFF_FILTER_BW_0_6, 78 COLOR_DIFF_FILTER_BW_1_3, 79 COLOR_DIFF_FILTER_BW_2_0 80 }; 81 82 #define v_CHROMA_BW(x) ((3 & (x)) << 4) 83 #define v_COLOR_DIFF_BW(x) (0xF & (x)) 84 85 #define TV_BRIGHTNESS_CONTRAST (0x90) 86 87 #define m_EXTREF_EN BIT(0) 88 #define m_VBG_EN BIT(1) 89 #define m_DAC_EN BIT(2) 90 #define m_SENSE_EN BIT(3) 91 #define m_BIAS_EN (7 << 4) 92 #define m_DAC_GAIN (0x3f << 7) 93 #define v_DAC_GAIN(x) (((x) & 0x3f) << 7) 94 95 #define VDAC_VDAC0 (0x00) 96 #define m_RST_ANA BIT(7) 97 #define m_RST_DIG BIT(6) 98 99 #define v_RST_ANA(x) (((x) & 1) << 7) 100 #define v_RST_DIG(x) (((x) & 1) << 6) 101 #define VDAC_VDAC1 (0x280) 102 #define m_CUR_REG (0xf << 4) 103 #define m_DR_PWR_DOWN BIT(1) 104 #define m_BG_PWR_DOWN BIT(0) 105 106 #define v_CUR_REG(x) (((x) & 0xf) << 4) 107 #define v_DR_PWR_DOWN(x) (((x) & 1) << 1) 108 #define v_BG_PWR_DOWN(x) (((x) & 1) << 0) 109 #define VDAC_VDAC2 (0x284) 110 #define m_CUR_CTR (0X3f) 111 112 #define v_CUR_CTR(x) (((x) & 0x3f)) 113 #define VDAC_VDAC3 (0x288) 114 #define m_CAB_EN BIT(5) 115 #define m_CAB_REF BIT(4) 116 #define m_CAB_FLAG BIT(0) 117 118 #define v_CAB_EN(x) (((x) & 1) << 5) 119 #define v_CAB_REF(x) (((x) & 1) << 4) 120 #define v_CAB_FLAG(x) (((x) & 1) << 0) 121 122 enum { 123 TVOUT_CVBS_NTSC = 0, 124 TVOUT_CVBS_PAL, 125 }; 126 127 enum { 128 INPUT_FORMAT_RGB = 0, 129 INPUT_FORMAT_YUV 130 }; 131 132 #define grf_writel(offset, v) do { \ 133 writel_relaxed(v, RK_GRF_VIRT + (offset)); \ 134 dsb(sy); \ 135 } while (0) 136 137 struct rockchip_tve { 138 struct device *dev; 139 struct drm_device *drm_dev; 140 struct drm_connector connector; 141 struct drm_encoder encoder; 142 143 u32 tv_format; 144 void __iomem *regbase; 145 void __iomem *vdacbase; 146 struct clk *dac_clk; 147 u32 reg_phy_base; 148 u32 len; 149 int inputformat; 150 bool enable; 151 u32 test_mode; 152 u32 saturation; 153 u32 brightcontrast; 154 u32 adjtiming; 155 u32 lumafilter0; 156 u32 lumafilter1; 157 u32 lumafilter2; 158 u32 daclevel; 159 u32 dac1level; 160 u32 preferred_mode; 161 struct mutex suspend_lock; /* mutex for tve resume operation*/ 162 struct rockchip_drm_sub_dev sub_dev; 163 }; 164 165 #endif /* _ROCKCHIP_DRM_TVE_ */ 166