1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip CIF Driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/reset.h>
11 #include <linux/iommu.h>
12 #include <media/v4l2-common.h>
13 #include <media/v4l2-event.h>
14 #include <media/v4l2-fh.h>
15 #include <media/v4l2-fwnode.h>
16 #include <media/v4l2-ioctl.h>
17 #include <media/v4l2-subdev.h>
18 #include <media/videobuf2-dma-contig.h>
19 #include <media/videobuf2-dma-sg.h>
20 #include <soc/rockchip/rockchip-system-status.h>
21 #include <dt-bindings/soc/rockchip-system-status.h>
22 #include <soc/rockchip/rockchip_iommu.h>
23
24 #include "dev.h"
25 #include "mipi-csi2.h"
26 #include "common.h"
27
28 #define CIF_REQ_BUFS_MIN 3
29 #define CIF_MIN_WIDTH 64
30 #define CIF_MIN_HEIGHT 64
31 #define CIF_MAX_WIDTH 8192
32 #define CIF_MAX_HEIGHT 8192
33
34 #define OUTPUT_STEP_WISE 8
35
36 #define RKCIF_PLANE_Y 0
37 #define RKCIF_PLANE_CBCR 1
38 #define RKCIF_MAX_PLANE 3
39
40 #define STREAM_PAD_SINK 0
41 #define STREAM_PAD_SOURCE 1
42
43 #define CIF_TIMEOUT_FRAME_NUM (2)
44
45 #define CIF_DVP_PCLK_DUAL_EDGE (V4L2_MBUS_PCLK_SAMPLE_RISING |\
46 V4L2_MBUS_PCLK_SAMPLE_FALLING)
47
48 /*
49 * Round up height when allocate memory so that Rockchip encoder can
50 * use DMA buffer directly, though this may waste a bit of memory.
51 */
52 #define MEMORY_ALIGN_ROUND_UP_HEIGHT 16
53
54 /* Get xsubs and ysubs for fourcc formats
55 *
56 * @xsubs: horizontal color samples in a 4*4 matrix, for yuv
57 * @ysubs: vertical color samples in a 4*4 matrix, for yuv
58 */
fcc_xysubs(u32 fcc,u32 * xsubs,u32 * ysubs)59 static int fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
60 {
61 switch (fcc) {
62 case V4L2_PIX_FMT_NV16:
63 case V4L2_PIX_FMT_NV61:
64 case V4L2_PIX_FMT_UYVY:
65 case V4L2_PIX_FMT_VYUY:
66 case V4L2_PIX_FMT_YUYV:
67 case V4L2_PIX_FMT_YVYU:
68 *xsubs = 2;
69 *ysubs = 1;
70 break;
71 case V4L2_PIX_FMT_NV21:
72 case V4L2_PIX_FMT_NV12:
73 *xsubs = 2;
74 *ysubs = 2;
75 break;
76 default:
77 return -EINVAL;
78 }
79
80 return 0;
81 }
82
83 static const struct cif_output_fmt out_fmts[] = {
84 {
85 .fourcc = V4L2_PIX_FMT_NV16,
86 .cplanes = 2,
87 .mplanes = 1,
88 .fmt_val = YUV_OUTPUT_422 | UV_STORAGE_ORDER_UVUV,
89 .bpp = { 8, 16 },
90 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
91 .fmt_type = CIF_FMT_TYPE_YUV,
92 }, {
93 .fourcc = V4L2_PIX_FMT_NV61,
94 .fmt_val = YUV_OUTPUT_422 | UV_STORAGE_ORDER_VUVU,
95 .cplanes = 2,
96 .mplanes = 1,
97 .bpp = { 8, 16 },
98 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
99 .fmt_type = CIF_FMT_TYPE_YUV,
100 }, {
101 .fourcc = V4L2_PIX_FMT_NV12,
102 .fmt_val = YUV_OUTPUT_420 | UV_STORAGE_ORDER_UVUV,
103 .cplanes = 2,
104 .mplanes = 1,
105 .bpp = { 8, 16 },
106 .csi_fmt_val = CSI_WRDDR_TYPE_YUV420SP,
107 .fmt_type = CIF_FMT_TYPE_YUV,
108 }, {
109 .fourcc = V4L2_PIX_FMT_NV21,
110 .fmt_val = YUV_OUTPUT_420 | UV_STORAGE_ORDER_VUVU,
111 .cplanes = 2,
112 .mplanes = 1,
113 .bpp = { 8, 16 },
114 .csi_fmt_val = CSI_WRDDR_TYPE_YUV420SP,
115 .fmt_type = CIF_FMT_TYPE_YUV,
116 }, {
117 .fourcc = V4L2_PIX_FMT_YUYV,
118 .cplanes = 2,
119 .mplanes = 1,
120 .bpp = { 8, 16 },
121 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
122 .fmt_type = CIF_FMT_TYPE_YUV,
123 }, {
124 .fourcc = V4L2_PIX_FMT_YVYU,
125 .cplanes = 2,
126 .mplanes = 1,
127 .bpp = { 8, 16 },
128 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
129 .fmt_type = CIF_FMT_TYPE_YUV,
130 }, {
131 .fourcc = V4L2_PIX_FMT_UYVY,
132 .cplanes = 2,
133 .mplanes = 1,
134 .bpp = { 8, 16 },
135 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
136 .fmt_type = CIF_FMT_TYPE_YUV,
137 }, {
138 .fourcc = V4L2_PIX_FMT_VYUY,
139 .cplanes = 2,
140 .mplanes = 1,
141 .bpp = { 8, 16 },
142 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
143 .fmt_type = CIF_FMT_TYPE_YUV,
144 }, {
145 .fourcc = V4L2_PIX_FMT_RGB24,
146 .cplanes = 1,
147 .mplanes = 1,
148 .bpp = { 24 },
149 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
150 .fmt_type = CIF_FMT_TYPE_RAW,
151 }, {
152 .fourcc = V4L2_PIX_FMT_RGB565,
153 .cplanes = 1,
154 .mplanes = 1,
155 .bpp = { 16 },
156 .fmt_type = CIF_FMT_TYPE_RAW,
157 }, {
158 .fourcc = V4L2_PIX_FMT_BGR666,
159 .cplanes = 1,
160 .mplanes = 1,
161 .bpp = { 18 },
162 .fmt_type = CIF_FMT_TYPE_RAW,
163 }, {
164 .fourcc = V4L2_PIX_FMT_SRGGB8,
165 .cplanes = 1,
166 .mplanes = 1,
167 .bpp = { 8 },
168 .raw_bpp = 8,
169 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
170 .fmt_type = CIF_FMT_TYPE_RAW,
171 }, {
172 .fourcc = V4L2_PIX_FMT_SGRBG8,
173 .cplanes = 1,
174 .mplanes = 1,
175 .bpp = { 8 },
176 .raw_bpp = 8,
177 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
178 .fmt_type = CIF_FMT_TYPE_RAW,
179 }, {
180 .fourcc = V4L2_PIX_FMT_SGBRG8,
181 .cplanes = 1,
182 .mplanes = 1,
183 .bpp = { 8 },
184 .raw_bpp = 8,
185 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
186 .fmt_type = CIF_FMT_TYPE_RAW,
187 }, {
188 .fourcc = V4L2_PIX_FMT_SBGGR8,
189 .cplanes = 1,
190 .mplanes = 1,
191 .bpp = { 8 },
192 .raw_bpp = 8,
193 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
194 .fmt_type = CIF_FMT_TYPE_RAW,
195 }, {
196 .fourcc = V4L2_PIX_FMT_SRGGB10,
197 .cplanes = 1,
198 .mplanes = 1,
199 .bpp = { 16 },
200 .raw_bpp = 10,
201 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
202 .fmt_type = CIF_FMT_TYPE_RAW,
203 }, {
204 .fourcc = V4L2_PIX_FMT_SGRBG10,
205 .cplanes = 1,
206 .mplanes = 1,
207 .bpp = { 16 },
208 .raw_bpp = 10,
209 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
210 .fmt_type = CIF_FMT_TYPE_RAW,
211 }, {
212 .fourcc = V4L2_PIX_FMT_SGBRG10,
213 .cplanes = 1,
214 .mplanes = 1,
215 .bpp = { 16 },
216 .raw_bpp = 10,
217 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
218 .fmt_type = CIF_FMT_TYPE_RAW,
219 }, {
220 .fourcc = V4L2_PIX_FMT_SBGGR10,
221 .cplanes = 1,
222 .mplanes = 1,
223 .bpp = { 16 },
224 .raw_bpp = 10,
225 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
226 .fmt_type = CIF_FMT_TYPE_RAW,
227 }, {
228 .fourcc = V4L2_PIX_FMT_SRGGB12,
229 .cplanes = 1,
230 .mplanes = 1,
231 .bpp = { 16 },
232 .raw_bpp = 12,
233 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
234 .fmt_type = CIF_FMT_TYPE_RAW,
235 }, {
236 .fourcc = V4L2_PIX_FMT_SGRBG12,
237 .cplanes = 1,
238 .mplanes = 1,
239 .bpp = { 16 },
240 .raw_bpp = 12,
241 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
242 .fmt_type = CIF_FMT_TYPE_RAW,
243 }, {
244 .fourcc = V4L2_PIX_FMT_SGBRG12,
245 .cplanes = 1,
246 .mplanes = 1,
247 .bpp = { 16 },
248 .raw_bpp = 12,
249 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
250 .fmt_type = CIF_FMT_TYPE_RAW,
251 }, {
252 .fourcc = V4L2_PIX_FMT_SBGGR12,
253 .cplanes = 1,
254 .mplanes = 1,
255 .bpp = { 16 },
256 .raw_bpp = 12,
257 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
258 .fmt_type = CIF_FMT_TYPE_RAW,
259 }, {
260 .fourcc = V4L2_PIX_FMT_SBGGR16,
261 .cplanes = 1,
262 .mplanes = 1,
263 .bpp = { 16 },
264 .raw_bpp = 16,
265 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
266 .fmt_type = CIF_FMT_TYPE_RAW,
267 }, {
268 .fourcc = V4L2_PIX_FMT_SGBRG16,
269 .cplanes = 1,
270 .mplanes = 1,
271 .bpp = { 16 },
272 .raw_bpp = 16,
273 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
274 .fmt_type = CIF_FMT_TYPE_RAW,
275 }, {
276 .fourcc = V4L2_PIX_FMT_SGRBG16,
277 .cplanes = 1,
278 .mplanes = 1,
279 .bpp = { 16 },
280 .raw_bpp = 16,
281 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
282 .fmt_type = CIF_FMT_TYPE_RAW,
283 }, {
284 .fourcc = V4L2_PIX_FMT_SRGGB16,
285 .cplanes = 1,
286 .mplanes = 1,
287 .bpp = { 16 },
288 .raw_bpp = 16,
289 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
290 .fmt_type = CIF_FMT_TYPE_RAW,
291 }, {
292 .fourcc = V4L2_PIX_FMT_Y16,
293 .cplanes = 1,
294 .mplanes = 1,
295 .bpp = { 16 },
296 .raw_bpp = 16,
297 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
298 .fmt_type = CIF_FMT_TYPE_RAW,
299 }, {
300 .fourcc = V4L2_PIX_FMT_GREY,
301 .cplanes = 1,
302 .mplanes = 1,
303 .bpp = {8},
304 .raw_bpp = 8,
305 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
306 .fmt_type = CIF_FMT_TYPE_RAW,
307 }, {
308 .fourcc = V4l2_PIX_FMT_EBD8,
309 .cplanes = 1,
310 .mplanes = 1,
311 .bpp = {8},
312 .raw_bpp = 8,
313 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
314 .fmt_type = CIF_FMT_TYPE_RAW,
315 }, {
316 .fourcc = V4l2_PIX_FMT_SPD16,
317 .cplanes = 1,
318 .mplanes = 1,
319 .bpp = {16},
320 .raw_bpp = 16,
321 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
322 .fmt_type = CIF_FMT_TYPE_RAW,
323 }, {
324 .fourcc = V4L2_PIX_FMT_Y12,
325 .cplanes = 1,
326 .mplanes = 1,
327 .bpp = { 16 },
328 .raw_bpp = 12,
329 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
330 .fmt_type = CIF_FMT_TYPE_RAW,
331 }, {
332 .fourcc = V4L2_PIX_FMT_Y10,
333 .cplanes = 1,
334 .mplanes = 1,
335 .bpp = { 16 },
336 .raw_bpp = 10,
337 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
338 .fmt_type = CIF_FMT_TYPE_RAW,
339 }
340
341 /* TODO: We can support NV12M/NV21M/NV16M/NV61M too */
342 };
343
344 static const struct cif_input_fmt in_fmts[] = {
345 {
346 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
347 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YUYV,
348 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
349 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YUYV,
350 .fmt_type = CIF_FMT_TYPE_YUV,
351 .field = V4L2_FIELD_NONE,
352 }, {
353 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
354 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YUYV,
355 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
356 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YUYV,
357 .fmt_type = CIF_FMT_TYPE_YUV,
358 .field = V4L2_FIELD_INTERLACED,
359 }, {
360 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
361 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YVYU,
362 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
363 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YVYU,
364 .fmt_type = CIF_FMT_TYPE_YUV,
365 .field = V4L2_FIELD_NONE,
366 }, {
367 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
368 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_YVYU,
369 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
370 .csi_yuv_order = CSI_YUV_INPUT_ORDER_YVYU,
371 .fmt_type = CIF_FMT_TYPE_YUV,
372 .field = V4L2_FIELD_INTERLACED,
373 }, {
374 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
375 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_UYVY,
376 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
377 .csi_yuv_order = CSI_YUV_INPUT_ORDER_UYVY,
378 .fmt_type = CIF_FMT_TYPE_YUV,
379 .field = V4L2_FIELD_NONE,
380 }, {
381 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
382 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_UYVY,
383 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
384 .csi_yuv_order = CSI_YUV_INPUT_ORDER_UYVY,
385 .fmt_type = CIF_FMT_TYPE_YUV,
386 .field = V4L2_FIELD_INTERLACED,
387 }, {
388 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
389 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_VYUY,
390 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
391 .csi_yuv_order = CSI_YUV_INPUT_ORDER_VYUY,
392 .fmt_type = CIF_FMT_TYPE_YUV,
393 .field = V4L2_FIELD_NONE,
394 }, {
395 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
396 .dvp_fmt_val = YUV_INPUT_422 | YUV_INPUT_ORDER_VYUY,
397 .csi_fmt_val = CSI_WRDDR_TYPE_YUV422,
398 .csi_yuv_order = CSI_YUV_INPUT_ORDER_VYUY,
399 .fmt_type = CIF_FMT_TYPE_YUV,
400 .field = V4L2_FIELD_INTERLACED,
401 }, {
402 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
403 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
404 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
405 .fmt_type = CIF_FMT_TYPE_RAW,
406 .field = V4L2_FIELD_NONE,
407 }, {
408 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
409 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
410 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
411 .fmt_type = CIF_FMT_TYPE_RAW,
412 .field = V4L2_FIELD_NONE,
413 }, {
414 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
415 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
416 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
417 .fmt_type = CIF_FMT_TYPE_RAW,
418 .field = V4L2_FIELD_NONE,
419 }, {
420 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
421 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
422 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
423 .fmt_type = CIF_FMT_TYPE_RAW,
424 .field = V4L2_FIELD_NONE,
425 }, {
426 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
427 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
428 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
429 .fmt_type = CIF_FMT_TYPE_RAW,
430 .field = V4L2_FIELD_NONE,
431 }, {
432 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
433 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
434 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
435 .fmt_type = CIF_FMT_TYPE_RAW,
436 .field = V4L2_FIELD_NONE,
437 }, {
438 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
439 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
440 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
441 .fmt_type = CIF_FMT_TYPE_RAW,
442 .field = V4L2_FIELD_NONE,
443 }, {
444 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
445 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
446 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
447 .fmt_type = CIF_FMT_TYPE_RAW,
448 .field = V4L2_FIELD_NONE,
449 }, {
450 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
451 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
452 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
453 .fmt_type = CIF_FMT_TYPE_RAW,
454 .field = V4L2_FIELD_NONE,
455 }, {
456 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
457 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
458 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
459 .fmt_type = CIF_FMT_TYPE_RAW,
460 .field = V4L2_FIELD_NONE,
461 }, {
462 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
463 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
464 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
465 .fmt_type = CIF_FMT_TYPE_RAW,
466 .field = V4L2_FIELD_NONE,
467 }, {
468 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
469 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
470 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
471 .fmt_type = CIF_FMT_TYPE_RAW,
472 .field = V4L2_FIELD_NONE,
473 }, {
474 .mbus_code = MEDIA_BUS_FMT_RGB888_1X24,
475 .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
476 .field = V4L2_FIELD_NONE,
477 }, {
478 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
479 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
480 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
481 .fmt_type = CIF_FMT_TYPE_RAW,
482 .field = V4L2_FIELD_NONE,
483 }, {
484 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
485 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_10,
486 .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
487 .fmt_type = CIF_FMT_TYPE_RAW,
488 .field = V4L2_FIELD_NONE,
489 }, {
490 .mbus_code = MEDIA_BUS_FMT_Y12_1X12,
491 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
492 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
493 .fmt_type = CIF_FMT_TYPE_RAW,
494 .field = V4L2_FIELD_NONE,
495 }, {
496 .mbus_code = MEDIA_BUS_FMT_EBD_1X8,
497 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_8,
498 .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
499 .fmt_type = CIF_FMT_TYPE_RAW,
500 .field = V4L2_FIELD_NONE,
501 }, {
502 .mbus_code = MEDIA_BUS_FMT_SPD_2X8,
503 .dvp_fmt_val = INPUT_MODE_RAW | RAW_DATA_WIDTH_12,
504 .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
505 .fmt_type = CIF_FMT_TYPE_RAW,
506 .field = V4L2_FIELD_NONE,
507 }
508 };
509
510 static inline
to_cif_rx_buf(struct rkisp_rx_buf * dbufs)511 struct rkcif_rx_buffer *to_cif_rx_buf(struct rkisp_rx_buf *dbufs)
512 {
513 return container_of(dbufs, struct rkcif_rx_buffer, dbufs);
514 }
515
get_remote_sensor(struct rkcif_stream * stream,u16 * index)516 static struct v4l2_subdev *get_remote_sensor(struct rkcif_stream *stream, u16 *index)
517 {
518 struct media_pad *local, *remote;
519 struct media_entity *sensor_me;
520 struct v4l2_subdev *sub = NULL;
521
522 local = &stream->vnode.vdev.entity.pads[0];
523 if (!local) {
524 v4l2_err(&stream->cifdev->v4l2_dev,
525 "%s: video pad[0] is null\n", __func__);
526 return NULL;
527 }
528
529 remote = media_entity_remote_pad(local);
530 if (!remote) {
531 v4l2_err(&stream->cifdev->v4l2_dev,
532 "%s: remote pad is null\n", __func__);
533 return NULL;
534 }
535
536 if (index)
537 *index = remote->index;
538
539 sensor_me = remote->entity;
540
541 sub = media_entity_to_v4l2_subdev(sensor_me);
542
543 return sub;
544
545 }
546
get_remote_terminal_sensor(struct rkcif_stream * stream,struct v4l2_subdev ** sensor_sd)547 static void get_remote_terminal_sensor(struct rkcif_stream *stream,
548 struct v4l2_subdev **sensor_sd)
549 {
550 struct media_graph graph;
551 struct media_entity *entity = &stream->vnode.vdev.entity;
552 struct media_device *mdev = entity->graph_obj.mdev;
553 int ret;
554
555 /* Walk the graph to locate sensor nodes. */
556 mutex_lock(&mdev->graph_mutex);
557 ret = media_graph_walk_init(&graph, mdev);
558 if (ret) {
559 mutex_unlock(&mdev->graph_mutex);
560 *sensor_sd = NULL;
561 return;
562 }
563
564 media_graph_walk_start(&graph, entity);
565 while ((entity = media_graph_walk_next(&graph))) {
566 if (entity->function == MEDIA_ENT_F_CAM_SENSOR)
567 break;
568 }
569 mutex_unlock(&mdev->graph_mutex);
570 media_graph_walk_cleanup(&graph);
571
572 if (entity)
573 *sensor_sd = media_entity_to_v4l2_subdev(entity);
574 else
575 *sensor_sd = NULL;
576 }
577
sd_to_sensor(struct rkcif_device * dev,struct v4l2_subdev * sd)578 static struct rkcif_sensor_info *sd_to_sensor(struct rkcif_device *dev,
579 struct v4l2_subdev *sd)
580 {
581 u32 i;
582
583 for (i = 0; i < dev->num_sensors; ++i)
584 if (dev->sensors[i].sd == sd)
585 return &dev->sensors[i];
586
587 if (i == dev->num_sensors) {
588 for (i = 0; i < dev->num_sensors; ++i) {
589 if (dev->sensors[i].mbus.type == V4L2_MBUS_CCP2)
590 return &dev->lvds_subdev.sensor_self;
591 }
592 }
593
594 return NULL;
595 }
596
get_data_type(u32 pixelformat,u8 cmd_mode_en)597 static unsigned char get_data_type(u32 pixelformat, u8 cmd_mode_en)
598 {
599 switch (pixelformat) {
600 /* csi raw8 */
601 case MEDIA_BUS_FMT_SBGGR8_1X8:
602 case MEDIA_BUS_FMT_SGBRG8_1X8:
603 case MEDIA_BUS_FMT_SGRBG8_1X8:
604 case MEDIA_BUS_FMT_SRGGB8_1X8:
605 return 0x2a;
606 /* csi raw10 */
607 case MEDIA_BUS_FMT_SBGGR10_1X10:
608 case MEDIA_BUS_FMT_SGBRG10_1X10:
609 case MEDIA_BUS_FMT_SGRBG10_1X10:
610 case MEDIA_BUS_FMT_SRGGB10_1X10:
611 return 0x2b;
612 /* csi raw12 */
613 case MEDIA_BUS_FMT_SBGGR12_1X12:
614 case MEDIA_BUS_FMT_SGBRG12_1X12:
615 case MEDIA_BUS_FMT_SGRBG12_1X12:
616 case MEDIA_BUS_FMT_SRGGB12_1X12:
617 return 0x2c;
618 /* csi uyvy 422 */
619 case MEDIA_BUS_FMT_UYVY8_2X8:
620 case MEDIA_BUS_FMT_VYUY8_2X8:
621 case MEDIA_BUS_FMT_YUYV8_2X8:
622 case MEDIA_BUS_FMT_YVYU8_2X8:
623 return 0x1e;
624 case MEDIA_BUS_FMT_RGB888_1X24: {
625 if (cmd_mode_en) /* dsi command mode*/
626 return 0x39;
627 else /* dsi video mode */
628 return 0x3e;
629 }
630 case MEDIA_BUS_FMT_EBD_1X8:
631 return 0x12;
632 case MEDIA_BUS_FMT_SPD_2X8:
633 return 0x2f;
634
635 default:
636 return 0x2b;
637 }
638 }
639
get_csi_crop_align(const struct cif_input_fmt * fmt_in)640 static int get_csi_crop_align(const struct cif_input_fmt *fmt_in)
641 {
642 switch (fmt_in->csi_fmt_val) {
643 case CSI_WRDDR_TYPE_RGB888:
644 return 24;
645 case CSI_WRDDR_TYPE_RAW10:
646 case CSI_WRDDR_TYPE_RAW12:
647 return 4;
648 case CSI_WRDDR_TYPE_RAW8:
649 case CSI_WRDDR_TYPE_YUV422:
650 return 8;
651 default:
652 return -1;
653 }
654 }
655
656 const struct
get_input_fmt(struct v4l2_subdev * sd,struct v4l2_rect * rect,u32 pad_id,struct csi_channel_info * csi_info)657 cif_input_fmt *get_input_fmt(struct v4l2_subdev *sd, struct v4l2_rect *rect,
658 u32 pad_id, struct csi_channel_info *csi_info)
659 {
660 struct v4l2_subdev_format fmt;
661 struct rkmodule_channel_info ch_info = {0};
662 int ret;
663 u32 i;
664
665 fmt.pad = 0;
666 fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
667 fmt.reserved[0] = 0;
668 fmt.format.field = V4L2_FIELD_NONE;
669 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
670 if (ret < 0) {
671 v4l2_warn(sd->v4l2_dev,
672 "sensor fmt invalid, set to default size\n");
673 goto set_default;
674 }
675 ch_info.index = pad_id;
676 ret = v4l2_subdev_call(sd,
677 core, ioctl,
678 RKMODULE_GET_CHANNEL_INFO,
679 &ch_info);
680 if (!ret) {
681 fmt.format.width = ch_info.width;
682 fmt.format.height = ch_info.height;
683 fmt.format.code = ch_info.bus_fmt;
684 switch (ch_info.vc) {
685 case V4L2_MBUS_CSI2_CHANNEL_3:
686 csi_info->vc = 3;
687 break;
688 case V4L2_MBUS_CSI2_CHANNEL_2:
689 csi_info->vc = 2;
690 break;
691 case V4L2_MBUS_CSI2_CHANNEL_1:
692 csi_info->vc = 1;
693 break;
694 case V4L2_MBUS_CSI2_CHANNEL_0:
695 csi_info->vc = 0;
696 break;
697 default:
698 csi_info->vc = -1;
699 }
700 if (ch_info.bus_fmt == MEDIA_BUS_FMT_SPD_2X8 ||
701 ch_info.bus_fmt == MEDIA_BUS_FMT_EBD_1X8) {
702 if (ch_info.data_type > 0)
703 csi_info->data_type = ch_info.data_type;
704 if (ch_info.data_bit > 0)
705 csi_info->data_bit = ch_info.data_bit;
706 }
707 }
708
709 v4l2_dbg(1, rkcif_debug, sd->v4l2_dev,
710 "remote fmt: mbus code:0x%x, size:%dx%d, field: %d\n",
711 fmt.format.code, fmt.format.width,
712 fmt.format.height, fmt.format.field);
713 rect->left = 0;
714 rect->top = 0;
715 rect->width = fmt.format.width;
716 rect->height = fmt.format.height;
717
718 for (i = 0; i < ARRAY_SIZE(in_fmts); i++)
719 if (fmt.format.code == in_fmts[i].mbus_code &&
720 fmt.format.field == in_fmts[i].field)
721 return &in_fmts[i];
722
723 v4l2_err(sd->v4l2_dev, "remote sensor mbus code not supported\n");
724
725 set_default:
726 rect->left = 0;
727 rect->top = 0;
728 rect->width = RKCIF_DEFAULT_WIDTH;
729 rect->height = RKCIF_DEFAULT_HEIGHT;
730
731 return NULL;
732 }
733
734 static const struct
find_output_fmt(struct rkcif_stream * stream,u32 pixelfmt)735 cif_output_fmt *find_output_fmt(struct rkcif_stream *stream, u32 pixelfmt)
736 {
737 const struct cif_output_fmt *fmt;
738 u32 i;
739
740 for (i = 0; i < ARRAY_SIZE(out_fmts); i++) {
741 fmt = &out_fmts[i];
742 if (fmt->fourcc == pixelfmt)
743 return fmt;
744 }
745
746 return NULL;
747 }
748
get_reg_index_of_id_ctrl0(int channel_id)749 static enum cif_reg_index get_reg_index_of_id_ctrl0(int channel_id)
750 {
751 enum cif_reg_index index;
752
753 switch (channel_id) {
754 case 0:
755 index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
756 break;
757 case 1:
758 index = CIF_REG_MIPI_LVDS_ID1_CTRL0;
759 break;
760 case 2:
761 index = CIF_REG_MIPI_LVDS_ID2_CTRL0;
762 break;
763 case 3:
764 index = CIF_REG_MIPI_LVDS_ID3_CTRL0;
765 break;
766 default:
767 index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
768 break;
769 }
770
771 return index;
772 }
773
get_reg_index_of_id_ctrl1(int channel_id)774 static enum cif_reg_index get_reg_index_of_id_ctrl1(int channel_id)
775 {
776 enum cif_reg_index index;
777
778 switch (channel_id) {
779 case 0:
780 index = CIF_REG_MIPI_LVDS_ID0_CTRL1;
781 break;
782 case 1:
783 index = CIF_REG_MIPI_LVDS_ID1_CTRL1;
784 break;
785 case 2:
786 index = CIF_REG_MIPI_LVDS_ID2_CTRL1;
787 break;
788 case 3:
789 index = CIF_REG_MIPI_LVDS_ID3_CTRL1;
790 break;
791 default:
792 index = CIF_REG_MIPI_LVDS_ID0_CTRL1;
793 break;
794 }
795
796 return index;
797 }
798
get_reg_index_of_frm0_y_addr(int channel_id)799 static enum cif_reg_index get_reg_index_of_frm0_y_addr(int channel_id)
800 {
801 enum cif_reg_index index;
802
803 switch (channel_id) {
804 case 0:
805 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0;
806 break;
807 case 1:
808 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1;
809 break;
810 case 2:
811 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2;
812 break;
813 case 3:
814 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3;
815 break;
816 default:
817 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0;
818 break;
819 }
820
821 return index;
822 }
823
get_reg_index_of_frm1_y_addr(int channel_id)824 static enum cif_reg_index get_reg_index_of_frm1_y_addr(int channel_id)
825 {
826 enum cif_reg_index index;
827
828 switch (channel_id) {
829 case 0:
830 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0;
831 break;
832 case 1:
833 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1;
834 break;
835 case 2:
836 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2;
837 break;
838 case 3:
839 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3;
840 break;
841 default:
842 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0;
843 break;
844 }
845
846 return index;
847 }
848
get_reg_index_of_frm0_uv_addr(int channel_id)849 static enum cif_reg_index get_reg_index_of_frm0_uv_addr(int channel_id)
850 {
851 enum cif_reg_index index;
852
853 switch (channel_id) {
854 case 0:
855 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0;
856 break;
857 case 1:
858 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1;
859 break;
860 case 2:
861 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2;
862 break;
863 case 3:
864 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3;
865 break;
866 default:
867 index = CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0;
868 break;
869 }
870
871 return index;
872 }
873
get_reg_index_of_frm1_uv_addr(int channel_id)874 static enum cif_reg_index get_reg_index_of_frm1_uv_addr(int channel_id)
875 {
876 enum cif_reg_index index;
877
878 switch (channel_id) {
879 case 0:
880 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0;
881 break;
882 case 1:
883 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1;
884 break;
885 case 2:
886 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2;
887 break;
888 case 3:
889 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3;
890 break;
891 default:
892 index = CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0;
893 break;
894 }
895
896 return index;
897 }
898
get_reg_index_of_frm0_y_vlw(int channel_id)899 static enum cif_reg_index get_reg_index_of_frm0_y_vlw(int channel_id)
900 {
901 enum cif_reg_index index;
902
903 switch (channel_id) {
904 case 0:
905 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0;
906 break;
907 case 1:
908 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1;
909 break;
910 case 2:
911 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2;
912 break;
913 case 3:
914 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3;
915 break;
916 default:
917 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0;
918 break;
919 }
920
921 return index;
922 }
923
get_reg_index_of_frm1_y_vlw(int channel_id)924 static enum cif_reg_index get_reg_index_of_frm1_y_vlw(int channel_id)
925 {
926 enum cif_reg_index index;
927
928 switch (channel_id) {
929 case 0:
930 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0;
931 break;
932 case 1:
933 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1;
934 break;
935 case 2:
936 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2;
937 break;
938 case 3:
939 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3;
940 break;
941 default:
942 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0;
943 break;
944 }
945
946 return index;
947 }
948
get_reg_index_of_frm0_uv_vlw(int channel_id)949 static enum cif_reg_index get_reg_index_of_frm0_uv_vlw(int channel_id)
950 {
951 enum cif_reg_index index;
952
953 switch (channel_id) {
954 case 0:
955 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0;
956 break;
957 case 1:
958 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1;
959 break;
960 case 2:
961 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2;
962 break;
963 case 3:
964 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3;
965 break;
966 default:
967 index = CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0;
968 break;
969 }
970
971 return index;
972 }
973
get_reg_index_of_frm1_uv_vlw(int channel_id)974 static enum cif_reg_index get_reg_index_of_frm1_uv_vlw(int channel_id)
975 {
976 enum cif_reg_index index;
977
978 switch (channel_id) {
979 case 0:
980 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0;
981 break;
982 case 1:
983 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1;
984 break;
985 case 2:
986 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2;
987 break;
988 case 3:
989 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3;
990 break;
991 default:
992 index = CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0;
993 break;
994 }
995
996 return index;
997 }
998
get_reg_index_of_id_crop_start(int channel_id)999 static enum cif_reg_index get_reg_index_of_id_crop_start(int channel_id)
1000 {
1001 enum cif_reg_index index;
1002
1003 switch (channel_id) {
1004 case 0:
1005 index = CIF_REG_MIPI_LVDS_ID0_CROP_START;
1006 break;
1007 case 1:
1008 index = CIF_REG_MIPI_LVDS_ID1_CROP_START;
1009 break;
1010 case 2:
1011 index = CIF_REG_MIPI_LVDS_ID2_CROP_START;
1012 break;
1013 case 3:
1014 index = CIF_REG_MIPI_LVDS_ID3_CROP_START;
1015 break;
1016 default:
1017 index = CIF_REG_MIPI_LVDS_ID0_CROP_START;
1018 break;
1019 }
1020
1021 return index;
1022 }
1023
get_reg_index_of_lvds_sav_eav_act0(int channel_id)1024 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_act0(int channel_id)
1025 {
1026 enum cif_reg_index index;
1027
1028 switch (channel_id) {
1029 case 0:
1030 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID0;
1031 break;
1032 case 1:
1033 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID1;
1034 break;
1035 case 2:
1036 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID2;
1037 break;
1038 case 3:
1039 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID3;
1040 break;
1041 default:
1042 index = CIF_REG_LVDS_SAV_EAV_ACT0_ID0;
1043 break;
1044 }
1045
1046 return index;
1047 }
1048
get_reg_index_of_lvds_sav_eav_act1(int channel_id)1049 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_act1(int channel_id)
1050 {
1051 enum cif_reg_index index;
1052
1053 switch (channel_id) {
1054 case 0:
1055 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID0;
1056 break;
1057 case 1:
1058 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID1;
1059 break;
1060 case 2:
1061 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID2;
1062 break;
1063 case 3:
1064 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID3;
1065 break;
1066 default:
1067 index = CIF_REG_LVDS_SAV_EAV_ACT1_ID0;
1068 break;
1069 }
1070
1071 return index;
1072 }
1073
get_reg_index_of_lvds_sav_eav_blk0(int channel_id)1074 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_blk0(int channel_id)
1075 {
1076 enum cif_reg_index index;
1077
1078 switch (channel_id) {
1079 case 0:
1080 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID0;
1081 break;
1082 case 1:
1083 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID1;
1084 break;
1085 case 2:
1086 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID2;
1087 break;
1088 case 3:
1089 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID3;
1090 break;
1091 default:
1092 index = CIF_REG_LVDS_SAV_EAV_BLK0_ID0;
1093 break;
1094 }
1095
1096 return index;
1097 }
1098
get_reg_index_of_lvds_sav_eav_blk1(int channel_id)1099 static enum cif_reg_index get_reg_index_of_lvds_sav_eav_blk1(int channel_id)
1100 {
1101 enum cif_reg_index index;
1102
1103 switch (channel_id) {
1104 case 0:
1105 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID0;
1106 break;
1107 case 1:
1108 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID1;
1109 break;
1110 case 2:
1111 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID2;
1112 break;
1113 case 3:
1114 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID3;
1115 break;
1116 default:
1117 index = CIF_REG_LVDS_SAV_EAV_BLK1_ID0;
1118 break;
1119 }
1120
1121 return index;
1122 }
1123
get_dvp_reg_index_of_frm0_y_addr(int channel_id)1124 static enum cif_reg_index get_dvp_reg_index_of_frm0_y_addr(int channel_id)
1125 {
1126 enum cif_reg_index index;
1127
1128 switch (channel_id) {
1129 case 0:
1130 index = CIF_REG_DVP_FRM0_ADDR_Y;
1131 break;
1132 case 1:
1133 index = CIF_REG_DVP_FRM0_ADDR_Y_ID1;
1134 break;
1135 case 2:
1136 index = CIF_REG_DVP_FRM0_ADDR_Y_ID2;
1137 break;
1138 case 3:
1139 index = CIF_REG_DVP_FRM0_ADDR_Y_ID3;
1140 break;
1141 default:
1142 index = CIF_REG_DVP_FRM0_ADDR_Y;
1143 break;
1144 }
1145
1146 return index;
1147 }
1148
get_dvp_reg_index_of_frm1_y_addr(int channel_id)1149 static enum cif_reg_index get_dvp_reg_index_of_frm1_y_addr(int channel_id)
1150 {
1151 enum cif_reg_index index;
1152
1153 switch (channel_id) {
1154 case 0:
1155 index = CIF_REG_DVP_FRM1_ADDR_Y;
1156 break;
1157 case 1:
1158 index = CIF_REG_DVP_FRM1_ADDR_Y_ID1;
1159 break;
1160 case 2:
1161 index = CIF_REG_DVP_FRM1_ADDR_Y_ID2;
1162 break;
1163 case 3:
1164 index = CIF_REG_DVP_FRM1_ADDR_Y_ID3;
1165 break;
1166 default:
1167 index = CIF_REG_DVP_FRM0_ADDR_Y;
1168 break;
1169 }
1170
1171 return index;
1172 }
1173
get_dvp_reg_index_of_frm0_uv_addr(int channel_id)1174 static enum cif_reg_index get_dvp_reg_index_of_frm0_uv_addr(int channel_id)
1175 {
1176 enum cif_reg_index index;
1177
1178 switch (channel_id) {
1179 case 0:
1180 index = CIF_REG_DVP_FRM0_ADDR_UV;
1181 break;
1182 case 1:
1183 index = CIF_REG_DVP_FRM0_ADDR_UV_ID1;
1184 break;
1185 case 2:
1186 index = CIF_REG_DVP_FRM0_ADDR_UV_ID2;
1187 break;
1188 case 3:
1189 index = CIF_REG_DVP_FRM0_ADDR_UV_ID3;
1190 break;
1191 default:
1192 index = CIF_REG_DVP_FRM0_ADDR_UV;
1193 break;
1194 }
1195
1196 return index;
1197 }
1198
get_dvp_reg_index_of_frm1_uv_addr(int channel_id)1199 static enum cif_reg_index get_dvp_reg_index_of_frm1_uv_addr(int channel_id)
1200 {
1201 enum cif_reg_index index;
1202
1203 switch (channel_id) {
1204 case 0:
1205 index = CIF_REG_DVP_FRM1_ADDR_UV;
1206 break;
1207 case 1:
1208 index = CIF_REG_DVP_FRM1_ADDR_UV_ID1;
1209 break;
1210 case 2:
1211 index = CIF_REG_DVP_FRM1_ADDR_UV_ID2;
1212 break;
1213 case 3:
1214 index = CIF_REG_DVP_FRM1_ADDR_UV_ID3;
1215 break;
1216 default:
1217 index = CIF_REG_DVP_FRM1_ADDR_UV;
1218 break;
1219 }
1220
1221 return index;
1222 }
1223
1224 /***************************** stream operations ******************************/
rkcif_assign_new_buffer_oneframe(struct rkcif_stream * stream,enum rkcif_yuvaddr_state stat)1225 static int rkcif_assign_new_buffer_oneframe(struct rkcif_stream *stream,
1226 enum rkcif_yuvaddr_state stat)
1227 {
1228 struct rkcif_device *dev = stream->cifdev;
1229 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
1230 struct rkcif_buffer *buffer = NULL;
1231 u32 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1232 u32 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
1233 unsigned long flags;
1234 int ret = 0;
1235
1236 spin_lock_irqsave(&stream->vbq_lock, flags);
1237 if (stat == RKCIF_YUV_ADDR_STATE_INIT) {
1238 if (!stream->curr_buf) {
1239 if (!list_empty(&stream->buf_head)) {
1240 stream->curr_buf = list_first_entry(&stream->buf_head,
1241 struct rkcif_buffer,
1242 queue);
1243 list_del(&stream->curr_buf->queue);
1244 }
1245 }
1246
1247 if (stream->curr_buf) {
1248 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_Y,
1249 stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
1250 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_UV,
1251 stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
1252 } else {
1253 if (dummy_buf->vaddr) {
1254 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_Y,
1255 dummy_buf->dma_addr);
1256 rkcif_write_register(dev, CIF_REG_DVP_FRM0_ADDR_UV,
1257 dummy_buf->dma_addr);
1258 }
1259 }
1260
1261 if (!stream->next_buf) {
1262 if (!list_empty(&stream->buf_head)) {
1263 stream->next_buf = list_first_entry(&stream->buf_head,
1264 struct rkcif_buffer, queue);
1265 list_del(&stream->next_buf->queue);
1266 }
1267 }
1268
1269 if (stream->next_buf) {
1270 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_Y,
1271 stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
1272 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_UV,
1273 stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
1274 } else {
1275 if (dummy_buf->vaddr) {
1276 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_Y,
1277 dummy_buf->dma_addr);
1278 rkcif_write_register(dev, CIF_REG_DVP_FRM1_ADDR_UV,
1279 dummy_buf->dma_addr);
1280 }
1281 }
1282 } else if (stat == RKCIF_YUV_ADDR_STATE_UPDATE) {
1283 if (!list_empty(&stream->buf_head)) {
1284 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1285 stream->curr_buf = list_first_entry(&stream->buf_head,
1286 struct rkcif_buffer, queue);
1287 list_del(&stream->curr_buf->queue);
1288 buffer = stream->curr_buf;
1289 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1290 stream->next_buf = list_first_entry(&stream->buf_head,
1291 struct rkcif_buffer, queue);
1292 list_del(&stream->next_buf->queue);
1293 buffer = stream->next_buf;
1294 }
1295 } else {
1296 if (dummy_buf->vaddr && stream->frame_phase == CIF_CSI_FRAME0_READY)
1297 stream->curr_buf = NULL;
1298 if (dummy_buf->vaddr && stream->frame_phase == CIF_CSI_FRAME1_READY)
1299 stream->next_buf = NULL;
1300 buffer = NULL;
1301 }
1302 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1303 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1304 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
1305 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1306 frm_addr_y = CIF_REG_DVP_FRM1_ADDR_Y;
1307 frm_addr_uv = CIF_REG_DVP_FRM1_ADDR_UV;
1308 }
1309
1310 if (buffer) {
1311 rkcif_write_register(dev, frm_addr_y,
1312 buffer->buff_addr[RKCIF_PLANE_Y]);
1313 rkcif_write_register(dev, frm_addr_uv,
1314 buffer->buff_addr[RKCIF_PLANE_CBCR]);
1315 } else {
1316 if (dummy_buf->vaddr) {
1317 rkcif_write_register(dev, frm_addr_y,
1318 dummy_buf->dma_addr);
1319 rkcif_write_register(dev, frm_addr_uv,
1320 dummy_buf->dma_addr);
1321 } else {
1322 ret = -EINVAL;
1323 }
1324 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1325 "not active buffer, frame Drop\n");
1326 }
1327 }
1328 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1329 return ret;
1330 }
1331
rkcif_s_rx_buffer(struct rkcif_device * dev,struct rkisp_rx_buf * dbufs)1332 static void rkcif_s_rx_buffer(struct rkcif_device *dev, struct rkisp_rx_buf *dbufs)
1333 {
1334 struct media_pad *pad = media_entity_remote_pad(&dev->sditf->pads);
1335 struct v4l2_subdev *sd;
1336
1337 if (pad)
1338 sd = media_entity_to_v4l2_subdev(pad->entity);
1339 else
1340 return;
1341
1342 v4l2_subdev_call(sd, video, s_rx_buffer, dbufs, NULL);
1343 }
1344
rkcif_assign_new_buffer_init_toisp(struct rkcif_stream * stream,int channel_id)1345 static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
1346 int channel_id)
1347 {
1348 struct rkcif_device *dev = stream->cifdev;
1349 struct rkisp_rx_buf *dbufs;
1350 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1351 u32 frm0_addr_y;
1352 u32 frm1_addr_y;
1353 unsigned long flags;
1354
1355 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1356 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1357 mbus_cfg->type == V4L2_MBUS_CCP2) {
1358 frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
1359 frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
1360 } else {
1361 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
1362 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
1363 }
1364
1365 spin_lock_irqsave(&stream->vbq_lock, flags);
1366
1367 if (!stream->curr_buf_toisp) {
1368 if (!list_empty(&stream->rx_buf_head)) {
1369 dbufs = list_first_entry(&stream->rx_buf_head,
1370 struct rkisp_rx_buf,
1371 list);
1372 if (dbufs)
1373 list_del(&dbufs->list);
1374 stream->curr_buf_toisp = to_cif_rx_buf(dbufs);
1375 }
1376 }
1377
1378 if (stream->curr_buf_toisp)
1379 rkcif_write_register(dev, frm0_addr_y,
1380 stream->curr_buf_toisp->dummy.dma_addr);
1381
1382 if (!stream->next_buf_toisp) {
1383 if (!list_empty(&stream->rx_buf_head)) {
1384 dbufs = list_first_entry(&stream->rx_buf_head,
1385 struct rkisp_rx_buf, list);
1386 if (dbufs) {
1387 list_del(&dbufs->list);
1388 stream->next_buf_toisp = to_cif_rx_buf(dbufs);
1389 } else {
1390 stream->next_buf_toisp = stream->curr_buf_toisp;
1391 }
1392 } else {
1393 stream->next_buf_toisp = stream->curr_buf_toisp;
1394 }
1395 }
1396
1397 if (stream->next_buf_toisp)
1398 rkcif_write_register(dev, frm1_addr_y,
1399 stream->next_buf_toisp->dummy.dma_addr);
1400
1401 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1402 }
1403
rkcif_assign_new_buffer_update_toisp(struct rkcif_stream * stream,int channel_id)1404 static int rkcif_assign_new_buffer_update_toisp(struct rkcif_stream *stream,
1405 int channel_id)
1406 {
1407 struct rkcif_device *dev = stream->cifdev;
1408 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1409 struct rkcif_rx_buffer *buffer = NULL;
1410 struct rkisp_rx_buf *dbufs;
1411 u32 frm_addr_y;
1412 int ret = 0;
1413 unsigned long flags;
1414
1415 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1416 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1417 mbus_cfg->type == V4L2_MBUS_CCP2) {
1418 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1419 get_reg_index_of_frm0_y_addr(channel_id) :
1420 get_reg_index_of_frm1_y_addr(channel_id);
1421 } else {
1422 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1423 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
1424 get_dvp_reg_index_of_frm1_y_addr(channel_id);
1425 }
1426 spin_lock_irqsave(&stream->vbq_lock, flags);
1427 if (!list_empty(&stream->rx_buf_head)) {
1428 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1429
1430 dbufs = list_first_entry(&stream->rx_buf_head,
1431 struct rkisp_rx_buf, list);
1432 if (dbufs) {
1433 list_del(&dbufs->list);
1434 stream->curr_buf_toisp = to_cif_rx_buf(dbufs);
1435 buffer = stream->curr_buf_toisp;
1436 }
1437 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1438 dbufs = list_first_entry(&stream->rx_buf_head,
1439 struct rkisp_rx_buf, list);
1440 if (dbufs) {
1441 list_del(&dbufs->list);
1442 stream->next_buf_toisp = to_cif_rx_buf(dbufs);
1443 buffer = stream->next_buf_toisp;
1444 }
1445 }
1446 } else {
1447 buffer = NULL;
1448 }
1449 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1450
1451 if (buffer) {
1452 rkcif_write_register(dev, frm_addr_y,
1453 buffer->dummy.dma_addr);
1454 }
1455 return ret;
1456 }
1457
rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream * stream,int init,int channel_id)1458 static int rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream *stream,
1459 int init, int channel_id)
1460 {
1461 int ret = 0;
1462
1463 if (init)
1464 rkcif_assign_new_buffer_init_toisp(stream, channel_id);
1465 else
1466 ret = rkcif_assign_new_buffer_update_toisp(stream, channel_id);
1467 return ret;
1468 }
1469
rkcif_assign_new_buffer_init(struct rkcif_stream * stream,int channel_id)1470 static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
1471 int channel_id)
1472 {
1473 struct rkcif_device *dev = stream->cifdev;
1474 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1475 u32 frm0_addr_y, frm0_addr_uv;
1476 u32 frm1_addr_y, frm1_addr_uv;
1477 unsigned long flags;
1478 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
1479 struct csi_channel_info *channel = &dev->channels[channel_id];
1480
1481 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1482 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1483 mbus_cfg->type == V4L2_MBUS_CCP2) {
1484 frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
1485 frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
1486 frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
1487 frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
1488 } else {
1489 frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
1490 frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
1491 frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
1492 frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
1493 }
1494
1495 spin_lock_irqsave(&stream->vbq_lock, flags);
1496
1497 if (!stream->curr_buf) {
1498 if (!list_empty(&stream->buf_head)) {
1499 stream->curr_buf = list_first_entry(&stream->buf_head,
1500 struct rkcif_buffer,
1501 queue);
1502 list_del(&stream->curr_buf->queue);
1503 }
1504 }
1505
1506 if (stream->curr_buf) {
1507 rkcif_write_register(dev, frm0_addr_y,
1508 stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
1509 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1510 rkcif_write_register(dev, frm0_addr_uv,
1511 stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
1512 } else {
1513 if (dummy_buf->vaddr) {
1514 rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
1515 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1516 rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
1517 }
1518 }
1519
1520 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1521 stream->next_buf = stream->curr_buf;
1522 if (stream->next_buf) {
1523 rkcif_write_register(dev, frm1_addr_y,
1524 stream->next_buf->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
1525 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1526 rkcif_write_register(dev, frm1_addr_uv,
1527 stream->next_buf->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
1528 }
1529 } else {
1530 if (!stream->next_buf) {
1531 if (!list_empty(&stream->buf_head)) {
1532 stream->next_buf = list_first_entry(&stream->buf_head,
1533 struct rkcif_buffer, queue);
1534 list_del(&stream->next_buf->queue);
1535 }
1536 }
1537
1538 if (stream->next_buf) {
1539 rkcif_write_register(dev, frm1_addr_y,
1540 stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
1541 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1542 rkcif_write_register(dev, frm1_addr_uv,
1543 stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
1544 } else {
1545 if (dummy_buf->vaddr) {
1546 rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
1547 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1548 rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
1549 }
1550 }
1551 }
1552 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1553
1554 stream->is_dvp_yuv_addr_init = true;
1555
1556 /* for BT.656/BT.1120 multi channels function,
1557 * yuv addr of unused channel must be set
1558 */
1559 if (mbus_cfg->type == V4L2_MBUS_BT656) {
1560 int ch_id;
1561
1562 for (ch_id = 0; ch_id < RKCIF_MAX_STREAM_DVP; ch_id++) {
1563 if (dev->stream[ch_id].is_dvp_yuv_addr_init)
1564 continue;
1565 if (dummy_buf->dma_addr) {
1566 rkcif_write_register(dev,
1567 get_dvp_reg_index_of_frm0_y_addr(ch_id),
1568 dummy_buf->dma_addr);
1569 rkcif_write_register(dev,
1570 get_dvp_reg_index_of_frm0_uv_addr(ch_id),
1571 dummy_buf->dma_addr);
1572 rkcif_write_register(dev,
1573 get_dvp_reg_index_of_frm1_y_addr(ch_id),
1574 dummy_buf->dma_addr);
1575 rkcif_write_register(dev,
1576 get_dvp_reg_index_of_frm1_uv_addr(ch_id),
1577 dummy_buf->dma_addr);
1578 }
1579 }
1580 }
1581
1582 }
1583
rkcif_assign_new_buffer_update(struct rkcif_stream * stream,int channel_id)1584 static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
1585 int channel_id)
1586 {
1587 struct rkcif_device *dev = stream->cifdev;
1588 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
1589 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1590 struct rkcif_buffer *buffer = NULL;
1591 u32 frm_addr_y, frm_addr_uv;
1592 struct csi_channel_info *channel = &dev->channels[channel_id];
1593 int ret = 0;
1594 unsigned long flags;
1595
1596 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1597 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1598 mbus_cfg->type == V4L2_MBUS_CCP2) {
1599 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1600 get_reg_index_of_frm0_y_addr(channel_id) :
1601 get_reg_index_of_frm1_y_addr(channel_id);
1602 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1603 get_reg_index_of_frm0_uv_addr(channel_id) :
1604 get_reg_index_of_frm1_uv_addr(channel_id);
1605 } else {
1606 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1607 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
1608 get_dvp_reg_index_of_frm1_y_addr(channel_id);
1609 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1610 get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
1611 get_dvp_reg_index_of_frm1_uv_addr(channel_id);
1612 }
1613
1614 spin_lock_irqsave(&stream->vbq_lock, flags);
1615 if (!list_empty(&stream->buf_head)) {
1616 if (!dummy_buf->vaddr &&
1617 stream->curr_buf == stream->next_buf &&
1618 stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
1619 ret = -EINVAL;
1620 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1621 stream->curr_buf = list_first_entry(&stream->buf_head,
1622 struct rkcif_buffer, queue);
1623 if (stream->curr_buf) {
1624 list_del(&stream->curr_buf->queue);
1625 buffer = stream->curr_buf;
1626 }
1627 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1628 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1629 if (stream->next_buf != stream->curr_buf) {
1630 stream->next_buf = stream->curr_buf;
1631 buffer = stream->next_buf;
1632 } else {
1633 buffer = NULL;
1634 }
1635
1636 } else {
1637 stream->next_buf = list_first_entry(&stream->buf_head,
1638 struct rkcif_buffer, queue);
1639 if (stream->next_buf) {
1640 list_del(&stream->next_buf->queue);
1641 buffer = stream->next_buf;
1642 }
1643 }
1644 }
1645 } else {
1646 buffer = NULL;
1647 if (dummy_buf->vaddr) {
1648 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1649 stream->curr_buf = NULL;
1650 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1651 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1652 stream->next_buf = stream->curr_buf;
1653 buffer = stream->next_buf;
1654 } else {
1655 stream->next_buf = NULL;
1656 }
1657 }
1658 } else if (stream->curr_buf != stream->next_buf) {
1659 if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1660 stream->curr_buf = stream->next_buf;
1661 buffer = stream->next_buf;
1662 } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1663 stream->next_buf = stream->curr_buf;
1664 buffer = stream->curr_buf;
1665 }
1666
1667 }
1668
1669 }
1670 stream->frame_phase_cache = stream->frame_phase;
1671 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1672
1673 if (buffer) {
1674 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
1675 stream->frame_phase == CIF_CSI_FRAME1_READY) {
1676 rkcif_write_register(dev, frm_addr_y,
1677 buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
1678 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1679 rkcif_write_register(dev, frm_addr_uv,
1680 buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
1681 } else {
1682 rkcif_write_register(dev, frm_addr_y,
1683 buffer->buff_addr[RKCIF_PLANE_Y]);
1684 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1685 rkcif_write_register(dev, frm_addr_uv,
1686 buffer->buff_addr[RKCIF_PLANE_CBCR]);
1687 }
1688 } else {
1689 if (dummy_buf->vaddr) {
1690 rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1691 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1692 rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
1693 } else {
1694 ret = -EINVAL;
1695 }
1696 v4l2_info(&dev->v4l2_dev,
1697 "not active buffer, skip current frame, %s stream[%d]\n",
1698 (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1699 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1700 mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1701 stream->id);
1702 }
1703 return ret;
1704 }
1705
rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream * stream)1706 static int rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1707 {
1708 struct rkcif_device *dev = stream->cifdev;
1709 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
1710 int ret = 0;
1711 unsigned long flags;
1712
1713 spin_lock_irqsave(&stream->vbq_lock, flags);
1714 if (!list_empty(&stream->buf_head)) {
1715 if (!dummy_buf->vaddr &&
1716 stream->curr_buf == stream->next_buf)
1717 ret = -EINVAL;
1718 if (stream->line_int_cnt % 2) {
1719 stream->curr_buf = list_first_entry(&stream->buf_head,
1720 struct rkcif_buffer, queue);
1721 if (stream->curr_buf)
1722 list_del(&stream->curr_buf->queue);
1723 } else {
1724 stream->next_buf = list_first_entry(&stream->buf_head,
1725 struct rkcif_buffer, queue);
1726 if (stream->next_buf)
1727 list_del(&stream->next_buf->queue);
1728 }
1729 stream->is_buf_active = true;
1730 } else {
1731 stream->is_buf_active = false;
1732 if (dummy_buf->vaddr) {
1733 if (stream->line_int_cnt % 2)
1734 stream->curr_buf = NULL;
1735 else
1736 stream->next_buf = NULL;
1737 } else if (stream->curr_buf != stream->next_buf) {
1738 if (stream->line_int_cnt % 2) {
1739 stream->curr_buf = stream->next_buf;
1740 stream->frame_phase_cache = CIF_CSI_FRAME0_READY;
1741 } else {
1742 stream->next_buf = stream->curr_buf;
1743 stream->frame_phase_cache = CIF_CSI_FRAME1_READY;
1744 }
1745 stream->is_buf_active = true;
1746 } else {
1747 ret = -EINVAL;
1748 }
1749 }
1750 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1751
1752 return ret;
1753 }
1754
rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream * stream)1755 static int rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1756 {
1757 struct rkcif_device *dev = stream->cifdev;
1758 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
1759 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1760 struct rkcif_buffer *buffer = NULL;
1761 u32 frm_addr_y, frm_addr_uv;
1762 int channel_id = stream->id;
1763 int ret = 0;
1764 unsigned long flags;
1765
1766 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1767 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1768 mbus_cfg->type == V4L2_MBUS_CCP2) {
1769 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1770 get_reg_index_of_frm0_y_addr(channel_id) :
1771 get_reg_index_of_frm1_y_addr(channel_id);
1772 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1773 get_reg_index_of_frm0_uv_addr(channel_id) :
1774 get_reg_index_of_frm1_uv_addr(channel_id);
1775 } else {
1776 frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1777 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
1778 get_dvp_reg_index_of_frm1_y_addr(channel_id);
1779 frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1780 get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
1781 get_dvp_reg_index_of_frm1_uv_addr(channel_id);
1782 }
1783 spin_lock_irqsave(&stream->vbq_lock, flags);
1784 if (stream->is_buf_active) {
1785 if (stream->frame_phase == CIF_CSI_FRAME0_READY)
1786 buffer = stream->curr_buf;
1787 else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
1788 buffer = stream->next_buf;
1789 }
1790 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1791 if (buffer) {
1792 rkcif_write_register(dev, frm_addr_y,
1793 buffer->buff_addr[RKCIF_PLANE_Y]);
1794 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1795 rkcif_write_register(dev, frm_addr_uv,
1796 buffer->buff_addr[RKCIF_PLANE_CBCR]);
1797 } else {
1798 if (dummy_buf->vaddr) {
1799 rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1800 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1801 rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
1802 } else {
1803 ret = -EINVAL;
1804 }
1805 v4l2_info(&dev->v4l2_dev,
1806 "not active buffer, skip current frame, %s stream[%d]\n",
1807 (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
1808 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
1809 mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1810 stream->id);
1811 }
1812
1813 return ret;
1814 }
1815
rkcif_assign_dummy_buffer(struct rkcif_stream * stream)1816 static void rkcif_assign_dummy_buffer(struct rkcif_stream *stream)
1817 {
1818 struct rkcif_device *dev = stream->cifdev;
1819 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1820 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
1821 unsigned long flags;
1822
1823 spin_lock_irqsave(&stream->vbq_lock, flags);
1824
1825 /* for BT.656/BT.1120 multi channels function,
1826 * yuv addr of unused channel must be set
1827 */
1828 if (mbus_cfg->type == V4L2_MBUS_BT656 && dummy_buf->vaddr) {
1829 rkcif_write_register(dev,
1830 get_dvp_reg_index_of_frm0_y_addr(stream->id),
1831 dummy_buf->dma_addr);
1832 rkcif_write_register(dev,
1833 get_dvp_reg_index_of_frm0_uv_addr(stream->id),
1834 dummy_buf->dma_addr);
1835 rkcif_write_register(dev,
1836 get_dvp_reg_index_of_frm1_y_addr(stream->id),
1837 dummy_buf->dma_addr);
1838 rkcif_write_register(dev,
1839 get_dvp_reg_index_of_frm1_uv_addr(stream->id),
1840 dummy_buf->dma_addr);
1841 }
1842
1843 spin_unlock_irqrestore(&stream->vbq_lock, flags);
1844 }
1845
rkcif_assign_new_buffer_pingpong(struct rkcif_stream * stream,int init,int channel_id)1846 static int rkcif_assign_new_buffer_pingpong(struct rkcif_stream *stream,
1847 int init, int channel_id)
1848 {
1849 int ret = 0;
1850
1851 if (init)
1852 rkcif_assign_new_buffer_init(stream, channel_id);
1853 else
1854 ret = rkcif_assign_new_buffer_update(stream, channel_id);
1855 return ret;
1856 }
1857
rkcif_csi_get_vc_num(struct rkcif_device * dev,unsigned int mbus_flags)1858 static void rkcif_csi_get_vc_num(struct rkcif_device *dev,
1859 unsigned int mbus_flags)
1860 {
1861 int i, vc_num = 0;
1862
1863 for (i = 0; i < RKCIF_MAX_CSI_CHANNEL; i++) {
1864 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_0) {
1865 dev->channels[vc_num].vc = vc_num;
1866 vc_num++;
1867 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_0;
1868 continue;
1869 }
1870 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_1) {
1871 dev->channels[vc_num].vc = vc_num;
1872 vc_num++;
1873 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_1;
1874 continue;
1875 }
1876
1877 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_2) {
1878 dev->channels[vc_num].vc = vc_num;
1879 vc_num++;
1880 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_2;
1881 continue;
1882 }
1883
1884 if (mbus_flags & V4L2_MBUS_CSI2_CHANNEL_3) {
1885 dev->channels[vc_num].vc = vc_num;
1886 vc_num++;
1887 mbus_flags ^= V4L2_MBUS_CSI2_CHANNEL_3;
1888 continue;
1889 }
1890 }
1891
1892 dev->num_channels = vc_num ? vc_num : 1;
1893 if (dev->num_channels == 1)
1894 dev->channels[0].vc = 0;
1895 }
1896
rkcif_csi_set_lvds_sav_eav(struct rkcif_stream * stream,struct csi_channel_info * channel)1897 static void rkcif_csi_set_lvds_sav_eav(struct rkcif_stream *stream,
1898 struct csi_channel_info *channel)
1899 {
1900 struct rkcif_device *dev = stream->cifdev;
1901 struct rkmodule_lvds_cfg *lvds_cfg = &channel->lvds_cfg;
1902 struct rkmodule_lvds_frame_sync_code *frm_sync_code = NULL;
1903 struct rkmodule_lvds_frm_sync_code *odd_sync_code = NULL;
1904 struct rkmodule_lvds_frm_sync_code *even_sync_code = NULL;
1905
1906 if (dev->hdr.hdr_mode == NO_HDR) {
1907 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LINEAR];
1908 odd_sync_code = &frm_sync_code->odd_sync_code;
1909 even_sync_code = odd_sync_code;
1910 } else {
1911 if (channel->id == RKCIF_STREAM_MIPI_ID0)
1912 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1913
1914 if (dev->hdr.hdr_mode == HDR_X2) {
1915 if (channel->id == RKCIF_STREAM_MIPI_ID1)
1916 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
1917 else
1918 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1919 } else if (dev->hdr.hdr_mode == HDR_X3) {
1920 if (channel->id == RKCIF_STREAM_MIPI_ID1)
1921 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_MEDIUM];
1922 else if (channel->id == RKCIF_STREAM_MIPI_ID2)
1923 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
1924 else
1925 frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1926 }
1927
1928 odd_sync_code = &frm_sync_code->odd_sync_code;
1929 even_sync_code = &frm_sync_code->even_sync_code;
1930 }
1931
1932 if (odd_sync_code && even_sync_code) {
1933 rkcif_write_register(stream->cifdev,
1934 get_reg_index_of_lvds_sav_eav_act0(channel->id),
1935 SW_LVDS_EAV_ACT(odd_sync_code->act.eav) |
1936 SW_LVDS_SAV_ACT(odd_sync_code->act.sav));
1937
1938 rkcif_write_register(stream->cifdev,
1939 get_reg_index_of_lvds_sav_eav_blk0(channel->id),
1940 SW_LVDS_EAV_BLK(odd_sync_code->blk.eav) |
1941 SW_LVDS_SAV_BLK(odd_sync_code->blk.sav));
1942
1943 rkcif_write_register(stream->cifdev,
1944 get_reg_index_of_lvds_sav_eav_act1(channel->id),
1945 SW_LVDS_EAV_ACT(even_sync_code->act.eav) |
1946 SW_LVDS_SAV_ACT(even_sync_code->act.sav));
1947
1948 rkcif_write_register(stream->cifdev,
1949 get_reg_index_of_lvds_sav_eav_blk1(channel->id),
1950 SW_LVDS_EAV_BLK(even_sync_code->blk.eav) |
1951 SW_LVDS_SAV_BLK(even_sync_code->blk.sav));
1952 }
1953 }
1954
get_csi_fmt_val(const struct cif_input_fmt * cif_fmt_in,struct csi_channel_info * csi_info)1955 static unsigned char get_csi_fmt_val(const struct cif_input_fmt *cif_fmt_in,
1956 struct csi_channel_info *csi_info)
1957 {
1958 unsigned char csi_fmt_val = 0;
1959
1960 if (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 ||
1961 cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8) {
1962 switch (csi_info->data_bit) {
1963 case 8:
1964 csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
1965 break;
1966 case 10:
1967 csi_fmt_val = CSI_WRDDR_TYPE_RAW10;
1968 break;
1969 case 12:
1970 csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
1971 break;
1972 default:
1973 csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
1974 break;
1975 }
1976 } else if (cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB888) {
1977 csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
1978 } else {
1979 csi_fmt_val = cif_fmt_in->csi_fmt_val;
1980 }
1981 return csi_fmt_val;
1982 }
1983
rkcif_csi_channel_init(struct rkcif_stream * stream,struct csi_channel_info * channel)1984 static int rkcif_csi_channel_init(struct rkcif_stream *stream,
1985 struct csi_channel_info *channel)
1986 {
1987 struct rkcif_device *dev = stream->cifdev;
1988 const struct cif_output_fmt *fmt;
1989 u32 fourcc;
1990 int vc = dev->channels[stream->id].vc;
1991
1992 channel->enable = 1;
1993 channel->width = stream->pixm.width;
1994 channel->height = stream->pixm.height;
1995
1996 channel->fmt_val = stream->cif_fmt_out->csi_fmt_val;
1997
1998 channel->cmd_mode_en = 0; /* default use DSI Video Mode */
1999
2000 if (stream->crop_enable) {
2001 channel->crop_en = 1;
2002
2003 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
2004 channel->crop_st_x = 3 * stream->crop[CROP_SRC_ACT].left;
2005 else
2006 channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
2007
2008 channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
2009 channel->width = stream->crop[CROP_SRC_ACT].width;
2010 channel->height = stream->crop[CROP_SRC_ACT].height;
2011 } else {
2012 channel->width = stream->pixm.width;
2013 channel->height = stream->pixm.height;
2014 channel->crop_en = 0;
2015 }
2016
2017 fmt = find_output_fmt(stream, stream->pixm.pixelformat);
2018 if (!fmt) {
2019 v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
2020 stream->pixm.pixelformat);
2021 return -EINVAL;
2022 }
2023
2024 /*
2025 * for mipi or lvds, when enable compact, the virtual width of raw10/raw12
2026 * needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
2027 * needs aligned with :ALIGN(bits_per_pixel * width * 2, 8), to optimize reading and
2028 * writing of ddr, aliged with 256
2029 */
2030 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact) {
2031 channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
2032 } else {
2033 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && fmt->csi_fmt_val != CSI_WRDDR_TYPE_RAW8)
2034 channel->virtual_width = ALIGN(channel->width * 2, 8);
2035 else
2036 channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
2037 }
2038
2039 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
2040 channel->width = channel->width * fmt->bpp[0] / 8;
2041 /*
2042 * rk cif don't support output yuyv fmt data
2043 * if user request yuyv fmt, the input mode must be RAW8
2044 * and the width is double Because the real input fmt is
2045 * yuyv
2046 */
2047 fourcc = stream->cif_fmt_out->fourcc;
2048 if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
2049 fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY) {
2050 channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
2051 channel->width *= 2;
2052 channel->virtual_width *= 2;
2053 }
2054 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
2055 channel->virtual_width *= 2;
2056 channel->height /= 2;
2057 }
2058 if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
2059 stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
2060 if (dev->channels[stream->id].data_type)
2061 channel->data_type = dev->channels[stream->id].data_type;
2062 else
2063 channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
2064 channel->cmd_mode_en);
2065 } else {
2066 channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
2067 channel->cmd_mode_en);
2068 }
2069 channel->csi_fmt_val = get_csi_fmt_val(stream->cif_fmt_in,
2070 &dev->channels[stream->id]);
2071
2072 if (dev->hdr.hdr_mode == NO_HDR ||
2073 (dev->hdr.hdr_mode == HDR_X2 && stream->id > 1) ||
2074 (dev->hdr.hdr_mode == HDR_X3 && stream->id > 2))
2075 channel->vc = vc >= 0 ? vc : channel->id;
2076 else
2077 channel->vc = channel->id;
2078 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2079 "%s: channel width %d, height %d, virtual_width %d, vc %d\n", __func__,
2080 channel->width, channel->height, channel->virtual_width, channel->vc);
2081 return 0;
2082 }
2083
rkcif_csi_channel_set(struct rkcif_stream * stream,struct csi_channel_info * channel,enum v4l2_mbus_type mbus_type)2084 static int rkcif_csi_channel_set(struct rkcif_stream *stream,
2085 struct csi_channel_info *channel,
2086 enum v4l2_mbus_type mbus_type)
2087 {
2088 unsigned int val = 0x0;
2089 struct rkcif_device *dev = stream->cifdev;
2090 struct rkcif_stream *detect_stream = &dev->stream[0];
2091 unsigned int wait_line = 0x3fff;
2092
2093 if (channel->id >= 4)
2094 return -EINVAL;
2095
2096 if (!channel->enable) {
2097 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
2098 CSI_DISABLE_CAPTURE);
2099 return 0;
2100 }
2101
2102 rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
2103 ~(CSI_START_INTSTAT(channel->id) |
2104 CSI_DMA_END_INTSTAT(channel->id) |
2105 CSI_LINE_INTSTAT(channel->id)));
2106
2107 /* enable id0 frame start int for sof(long frame, for hdr) */
2108 if (channel->id == RKCIF_STREAM_MIPI_ID0)
2109 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2110 CSI_START_INTEN(channel->id));
2111 if (detect_stream->is_line_wake_up) {
2112 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2113 CSI_LINE_INTEN(channel->id));
2114 wait_line = dev->wait_line;
2115 }
2116 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
2117 wait_line << 16 | wait_line);
2118 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
2119 wait_line << 16 | wait_line);
2120
2121 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2122 CSI_DMA_END_INTEN(channel->id));
2123 rkcif_write_register(dev, CIF_REG_MIPI_WATER_LINE,
2124 CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 |
2125 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808 |
2126 CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(0x3) |
2127 CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808);
2128
2129 val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x3) |
2130 CIF_MIPI_LVDS_SW_PRESS_ENABLE |
2131 CIF_MIPI_LVDS_SW_HURRY_VALUE(0x3) |
2132 CIF_MIPI_LVDS_SW_HURRY_ENABLE |
2133 CIF_MIPI_LVDS_SW_WATER_LINE_25 |
2134 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
2135 if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
2136 val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
2137 } else if (mbus_type == V4L2_MBUS_CCP2) {
2138 if (channel->fmt_val == CSI_WRDDR_TYPE_RAW12)
2139 val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS;
2140 else if (channel->fmt_val == CSI_WRDDR_TYPE_RAW10)
2141 val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS;
2142 else
2143 val |= CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS;
2144 val |= CIF_MIPI_LVDS_SW_SEL_LVDS;
2145 }
2146 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
2147
2148 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2149 CSI_ALL_ERROR_INTEN);
2150
2151 rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
2152 channel->width | (channel->height << 16));
2153
2154 rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
2155 channel->virtual_width);
2156 rkcif_write_register(dev, get_reg_index_of_frm1_y_vlw(channel->id),
2157 channel->virtual_width);
2158 rkcif_write_register(dev, get_reg_index_of_frm0_uv_vlw(channel->id),
2159 channel->virtual_width);
2160 rkcif_write_register(dev, get_reg_index_of_frm1_uv_vlw(channel->id),
2161 channel->virtual_width);
2162
2163 if (channel->crop_en)
2164 rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
2165 channel->crop_st_y << 16 | channel->crop_st_x);
2166
2167 /* Set up an buffer for the next frame */
2168 rkcif_assign_new_buffer_pingpong(stream,
2169 RKCIF_YUV_ADDR_STATE_INIT,
2170 channel->id);
2171
2172 if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
2173 //need always enable crop
2174 val = CSI_ENABLE_CAPTURE | channel->fmt_val |
2175 channel->cmd_mode_en << 4 | CSI_ENABLE_CROP |
2176 channel->vc << 8 | channel->data_type << 10;
2177 if (stream->is_compact)
2178 val |= CSI_ENABLE_MIPI_COMPACT;
2179 else
2180 val &= ~CSI_ENABLE_MIPI_COMPACT;
2181
2182 if (stream->cifdev->chip_id >= CHIP_RK3568_CIF)
2183 val |= stream->cif_fmt_in->csi_yuv_order;
2184 } else if (mbus_type == V4L2_MBUS_CCP2) {
2185 rkcif_csi_set_lvds_sav_eav(stream, channel);
2186 val = LVDS_ENABLE_CAPTURE | LVDS_MODE(channel->lvds_cfg.mode) |
2187 LVDS_MAIN_LANE(0) | LVDS_FID(0) |
2188 LVDS_LANES_ENABLED(dev->active_sensor->lanes);
2189
2190 if (stream->is_compact)
2191 val |= LVDS_COMPACT;
2192 else
2193 val &= ~LVDS_COMPACT;
2194 }
2195 if (stream->is_high_align)
2196 val |= CSI_HIGH_ALIGN;
2197 else
2198 val &= ~CSI_HIGH_ALIGN;
2199 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
2200
2201 return 0;
2202 }
2203
rkcif_dvp_get_input_yuv_order(struct rkcif_stream * stream)2204 static int rkcif_dvp_get_input_yuv_order(struct rkcif_stream *stream)
2205 {
2206 unsigned int mask;
2207 const struct cif_input_fmt *fmt = stream->cif_fmt_in;
2208
2209 switch (fmt->mbus_code) {
2210 case MEDIA_BUS_FMT_UYVY8_2X8:
2211 mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
2212 break;
2213 case MEDIA_BUS_FMT_VYUY8_2X8:
2214 mask = CSI_YUV_INPUT_ORDER_VYUY >> 11;
2215 break;
2216 case MEDIA_BUS_FMT_YUYV8_2X8:
2217 mask = CSI_YUV_INPUT_ORDER_YUYV >> 11;
2218 break;
2219 case MEDIA_BUS_FMT_YVYU8_2X8:
2220 mask = CSI_YUV_INPUT_ORDER_YVYU >> 11;
2221 break;
2222 default:
2223 mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
2224 break;
2225 }
2226 return mask;
2227 }
2228
rkcif_csi_get_output_type_mask(struct rkcif_stream * stream)2229 static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
2230 {
2231 unsigned int mask;
2232 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
2233
2234 switch (fmt->fourcc) {
2235 case V4L2_PIX_FMT_NV16:
2236 mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 | CSI_YUV_OUTPUT_ORDER_UYVY;
2237 break;
2238 case V4L2_PIX_FMT_NV61:
2239 mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 | CSI_YUV_OUTPUT_ORDER_VYUY;
2240 break;
2241 case V4L2_PIX_FMT_NV12:
2242 mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 | CSI_YUV_OUTPUT_ORDER_UYVY;
2243 break;
2244 case V4L2_PIX_FMT_NV21:
2245 mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 | CSI_YUV_OUTPUT_ORDER_VYUY;
2246 break;
2247 case V4L2_PIX_FMT_YUYV:
2248 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_YUYV;
2249 break;
2250 case V4L2_PIX_FMT_YVYU:
2251 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_YVYU;
2252 break;
2253 case V4L2_PIX_FMT_UYVY:
2254 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_UYVY;
2255 break;
2256 case V4L2_PIX_FMT_VYUY:
2257 mask = CSI_WRDDR_TYPE_YUV_PACKET | CSI_YUV_OUTPUT_ORDER_VYUY;
2258 break;
2259 case V4L2_PIX_FMT_RGB24:
2260 case V4L2_PIX_FMT_RGB565:
2261 case V4L2_PIX_FMT_BGR666:
2262 mask = CSI_WRDDR_TYPE_RAW_COMPACT;
2263 break;
2264 case V4L2_PIX_FMT_SRGGB8:
2265 case V4L2_PIX_FMT_SGRBG8:
2266 case V4L2_PIX_FMT_SGBRG8:
2267 case V4L2_PIX_FMT_SBGGR8:
2268 case V4L2_PIX_FMT_SRGGB10:
2269 case V4L2_PIX_FMT_SGRBG10:
2270 case V4L2_PIX_FMT_SGBRG10:
2271 case V4L2_PIX_FMT_SBGGR10:
2272 case V4L2_PIX_FMT_SRGGB12:
2273 case V4L2_PIX_FMT_SGRBG12:
2274 case V4L2_PIX_FMT_SGBRG12:
2275 case V4L2_PIX_FMT_SBGGR12:
2276 case V4L2_PIX_FMT_GREY:
2277 case V4L2_PIX_FMT_Y10:
2278 case V4L2_PIX_FMT_Y12:
2279 if (stream->is_compact)
2280 mask = CSI_WRDDR_TYPE_RAW_COMPACT;
2281 else
2282 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
2283 break;
2284 case V4L2_PIX_FMT_SBGGR16:
2285 case V4L2_PIX_FMT_SGBRG16:
2286 case V4L2_PIX_FMT_SGRBG16:
2287 case V4L2_PIX_FMT_SRGGB16:
2288 case V4L2_PIX_FMT_Y16:
2289 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
2290 break;
2291 default:
2292 mask = CSI_WRDDR_TYPE_RAW_COMPACT;
2293 break;
2294 }
2295 return mask;
2296 }
2297
2298 /*config reg for rk3588*/
rkcif_csi_channel_set_v1(struct rkcif_stream * stream,struct csi_channel_info * channel,enum v4l2_mbus_type mbus_type,unsigned int mode)2299 static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
2300 struct csi_channel_info *channel,
2301 enum v4l2_mbus_type mbus_type, unsigned int mode)
2302 {
2303 unsigned int val = 0x0;
2304 struct rkcif_device *dev = stream->cifdev;
2305 struct rkcif_stream *detect_stream = &dev->stream[0];
2306 struct sditf_priv *priv = dev->sditf;
2307 unsigned int wait_line = 0x3fff;
2308 unsigned int dma_en = 0;
2309
2310 if (channel->id >= 4)
2311 return -EINVAL;
2312
2313 if (!channel->enable) {
2314 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
2315 CSI_DISABLE_CAPTURE);
2316 return 0;
2317 }
2318
2319 rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
2320 ~(CSI_START_INTSTAT(channel->id) |
2321 CSI_DMA_END_INTSTAT(channel->id) |
2322 CSI_LINE_INTSTAT_V1(channel->id)));
2323
2324 /* enable id0 frame start int for sof(long frame, for hdr) */
2325 if (channel->id == RKCIF_STREAM_MIPI_ID0)
2326 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2327 CSI_START_INTEN(channel->id));
2328
2329 if (priv && priv->toisp_inf.link_mode == TOISP_NONE && detect_stream->is_line_wake_up) {
2330 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2331 CSI_LINE_INTEN_RK3588(channel->id));
2332 wait_line = dev->wait_line;
2333 }
2334 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
2335 wait_line << 16 | wait_line);
2336 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
2337 wait_line << 16 | wait_line);
2338
2339 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2340 CSI_DMA_END_INTEN(channel->id));
2341 if (stream->cifdev->id_use_cnt == 0) {
2342 val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) |
2343 CIF_MIPI_LVDS_SW_PRESS_ENABLE |
2344 CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(0x3) |
2345 CIF_MIPI_LVDS_SW_HURRY_ENABLE |
2346 CIF_MIPI_LVDS_SW_WATER_LINE_25 |
2347 CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
2348 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
2349
2350 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
2351 CSI_ALL_ERROR_INTEN_V1);
2352 }
2353 rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
2354 channel->width | (channel->height << 16));
2355
2356 rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
2357 channel->virtual_width);
2358
2359 if (channel->crop_en)
2360 rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
2361 channel->crop_st_y << 16 | channel->crop_st_x);
2362 if (stream->dma_en)
2363 dma_en = CSI_DMA_ENABLE;
2364 if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
2365 rkcif_assign_new_buffer_pingpong(stream,
2366 RKCIF_YUV_ADDR_STATE_INIT,
2367 channel->id);
2368 else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
2369 rkcif_assign_new_buffer_pingpong_toisp(stream,
2370 RKCIF_YUV_ADDR_STATE_INIT,
2371 channel->id);
2372 if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
2373 mbus_type == V4L2_MBUS_CSI2_CPHY) {
2374 val = CSI_ENABLE_CAPTURE | dma_en |
2375 channel->cmd_mode_en << 26 | CSI_ENABLE_CROP_V1 |
2376 channel->vc << 8 | channel->data_type << 10 |
2377 channel->csi_fmt_val;
2378
2379 val |= stream->cif_fmt_in->csi_yuv_order;
2380 val |= rkcif_csi_get_output_type_mask(stream);
2381 if (stream->cifdev->hdr.hdr_mode == NO_HDR)
2382 val |= CSI_NO_HDR;
2383 else if (stream->cifdev->hdr.hdr_mode == HDR_X2)
2384 val |= CSI_HDR2;
2385 else if (stream->cifdev->hdr.hdr_mode == HDR_X3)
2386 val |= CSI_HDR3;
2387 if (stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
2388 val |= CSI_HDR_MODE_VC;
2389 else if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT)
2390 val |= CSI_HDR_MODE_LINE_CNT;
2391 else if (stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
2392 val |= CSI_HDR_MODE_LINE_INFO;
2393 if (stream->cifdev->hdr.hdr_mode != NO_HDR &&
2394 stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
2395 val |= CSI_HDR_VC_MODE_PROTECT;
2396 if (stream->is_high_align)
2397 val |= CSI_HIGH_ALIGN_RK3588;
2398 else
2399 val &= ~CSI_HIGH_ALIGN_RK3588;
2400 } else if (mbus_type == V4L2_MBUS_CCP2) {
2401 //not used
2402 rkcif_csi_set_lvds_sav_eav(stream, channel);
2403 val = LVDS_ENABLE_CAPTURE | LVDS_MODE(channel->lvds_cfg.mode) |
2404 LVDS_MAIN_LANE(0) | LVDS_FID(0) |
2405 LVDS_LANES_ENABLED(dev->active_sensor->lanes);
2406
2407 if (stream->is_compact)
2408 val |= LVDS_COMPACT;
2409 else
2410 val &= ~LVDS_COMPACT;
2411 }
2412
2413 rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
2414 rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
2415 rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
2416 stream->cifdev->id_use_cnt++;
2417 return 0;
2418 }
2419
rkcif_csi_stream_start(struct rkcif_stream * stream,unsigned int mode)2420 static int rkcif_csi_stream_start(struct rkcif_stream *stream, unsigned int mode)
2421 {
2422 struct rkcif_device *dev = stream->cifdev;
2423 struct rkcif_sensor_info *active_sensor = dev->active_sensor;
2424 unsigned int flags = active_sensor->mbus.flags;
2425 enum v4l2_mbus_type mbus_type = active_sensor->mbus.type;
2426 struct csi_channel_info *channel;
2427 u32 ret = 0;
2428
2429 if (stream->state < RKCIF_STATE_STREAMING)
2430 stream->frame_idx = 0;
2431
2432 if (mbus_type == V4L2_MBUS_CSI2_DPHY ||
2433 mbus_type == V4L2_MBUS_CSI2_CPHY) {
2434 rkcif_csi_get_vc_num(dev, flags);
2435
2436 channel = &dev->channels[stream->id];
2437 channel->id = stream->id;
2438 rkcif_csi_channel_init(stream, channel);
2439 if (stream->state != RKCIF_STATE_STREAMING) {
2440 if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
2441 stream->dma_en |= RKCIF_DMAEN_BY_VICAP;
2442 } else if ((mode & RKCIF_STREAM_MODE_TOISP) == RKCIF_STREAM_MODE_TOISP) {
2443 if (dev->hdr.hdr_mode == HDR_X2 &&
2444 stream->id == 0)
2445 stream->dma_en |= RKCIF_DMAEN_BY_ISP;
2446 else if (dev->hdr.hdr_mode == HDR_X3 && (stream->id == 0 || stream->id == 1))
2447 stream->dma_en |= RKCIF_DMAEN_BY_ISP;
2448 }
2449 if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
2450 rkcif_csi_channel_set(stream, channel, mbus_type);
2451 else
2452 rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode);
2453 } else {
2454 if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
2455 if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE &&
2456 (!stream->dma_en)) {
2457 stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
2458 } else if ((mode & RKCIF_STREAM_MODE_TOISP) == RKCIF_STREAM_MODE_TOISP) {
2459 if (dev->hdr.hdr_mode == HDR_X2 &&
2460 stream->id == 0 &&
2461 (!stream->dma_en))
2462 stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
2463 else if (dev->hdr.hdr_mode == HDR_X3 &&
2464 (stream->id == 0 || stream->id == 1) &&
2465 (!stream->dma_en))
2466 stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
2467 }
2468 }
2469 }
2470 } else if (mbus_type == V4L2_MBUS_CCP2) {
2471 rkcif_csi_get_vc_num(dev, flags);
2472
2473 channel = &dev->channels[stream->id];
2474 channel->id = stream->id;
2475
2476 ret = v4l2_subdev_call(dev->terminal_sensor.sd, core,
2477 ioctl, RKMODULE_GET_LVDS_CFG,
2478 &channel->lvds_cfg);
2479 if (ret) {
2480 v4l2_err(&dev->v4l2_dev, "Err: get lvds config failed!!\n");
2481 return ret;
2482 }
2483
2484 rkcif_csi_channel_init(stream, channel);
2485 rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CCP2);
2486 }
2487 if (stream->state != RKCIF_STATE_STREAMING) {
2488 stream->line_int_cnt = 0;
2489 if (stream->is_line_wake_up)
2490 stream->is_can_stop = false;
2491 else
2492 stream->is_can_stop = true;
2493 stream->state = RKCIF_STATE_STREAMING;
2494 dev->workmode = RKCIF_WORKMODE_PINGPONG;
2495 }
2496
2497 return 0;
2498 }
2499
rkcif_stream_stop(struct rkcif_stream * stream)2500 static void rkcif_stream_stop(struct rkcif_stream *stream)
2501 {
2502 struct rkcif_device *cif_dev = stream->cifdev;
2503 struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
2504 u32 val;
2505 int id;
2506
2507 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2508 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2509 mbus_cfg->type == V4L2_MBUS_CCP2) {
2510 id = stream->id;
2511 val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(id));
2512 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2513 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
2514 val &= ~(CSI_ENABLE_CAPTURE | CSI_DMA_ENABLE);
2515 else
2516 val &= ~LVDS_ENABLE_CAPTURE;
2517
2518 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
2519
2520 rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT,
2521 CSI_START_INTSTAT(id) |
2522 CSI_DMA_END_INTSTAT(id) |
2523 CSI_LINE_INTSTAT(id));
2524
2525 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
2526 ~(CSI_START_INTEN(id) |
2527 CSI_DMA_END_INTEN(id) |
2528 CSI_LINE_INTEN(id)));
2529
2530 if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
2531 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
2532 ~CSI_ALL_ERROR_INTEN);
2533 } else {
2534 if (stream->cifdev->id_use_cnt == 0) {
2535 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
2536 ~CSI_ALL_ERROR_INTEN_V1);
2537 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
2538 ~CSI_ENABLE_CAPTURE);
2539 }
2540 }
2541
2542 } else {
2543 if (atomic_read(&cif_dev->pipe.stream_cnt) == 1) {
2544 val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
2545 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL,
2546 val & (~ENABLE_CAPTURE));
2547 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, 0x0);
2548 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, 0x3ff);
2549 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS, 0x0);
2550 }
2551 }
2552 stream->cifdev->id_use_cnt--;
2553 stream->state = RKCIF_STATE_READY;
2554 stream->dma_en = 0;
2555 }
2556
rkcif_is_extending_line_for_height(struct rkcif_device * dev,struct rkcif_stream * stream,const struct cif_input_fmt * fmt)2557 static bool rkcif_is_extending_line_for_height(struct rkcif_device *dev,
2558 struct rkcif_stream *stream,
2559 const struct cif_input_fmt *fmt)
2560 {
2561 bool is_extended = false;
2562 struct rkmodule_hdr_cfg hdr_cfg;
2563 int ret;
2564
2565 if (dev->chip_id == CHIP_RV1126_CIF ||
2566 dev->chip_id == CHIP_RV1126_CIF_LITE) {
2567 if (dev->terminal_sensor.sd) {
2568 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
2569 core, ioctl,
2570 RKMODULE_GET_HDR_CFG,
2571 &hdr_cfg);
2572 if (!ret)
2573 dev->hdr = hdr_cfg;
2574 else
2575 dev->hdr.hdr_mode = NO_HDR;
2576 }
2577
2578 if (fmt && fmt->fmt_type == CIF_FMT_TYPE_RAW) {
2579 if ((dev->hdr.hdr_mode == HDR_X2 &&
2580 stream->id == RKCIF_STREAM_MIPI_ID1) ||
2581 (dev->hdr.hdr_mode == HDR_X3 &&
2582 stream->id == RKCIF_STREAM_MIPI_ID2) ||
2583 (dev->hdr.hdr_mode == NO_HDR)) {
2584 is_extended = true;
2585 }
2586 }
2587 }
2588
2589 return is_extended;
2590 }
2591
rkcif_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])2592 static int rkcif_queue_setup(struct vb2_queue *queue,
2593 unsigned int *num_buffers,
2594 unsigned int *num_planes,
2595 unsigned int sizes[],
2596 struct device *alloc_ctxs[])
2597 {
2598 struct rkcif_stream *stream = queue->drv_priv;
2599 struct rkcif_extend_info *extend_line = &stream->extend_line;
2600 struct rkcif_device *dev = stream->cifdev;
2601 const struct v4l2_pix_format_mplane *pixm = NULL;
2602 const struct cif_output_fmt *cif_fmt;
2603 const struct cif_input_fmt *in_fmt;
2604 bool is_extended = false;
2605 u32 i, height;
2606
2607 pixm = &stream->pixm;
2608 cif_fmt = stream->cif_fmt_out;
2609 in_fmt = stream->cif_fmt_in;
2610
2611 *num_planes = cif_fmt->mplanes;
2612
2613 if (stream->crop_enable)
2614 height = stream->crop[CROP_SRC_ACT].height;
2615 else
2616 height = pixm->height;
2617
2618 is_extended = rkcif_is_extending_line_for_height(dev, stream, in_fmt);
2619 if (is_extended && extend_line->is_extended) {
2620 height = extend_line->pixm.height;
2621 pixm = &extend_line->pixm;
2622 }
2623
2624 for (i = 0; i < cif_fmt->mplanes; i++) {
2625 const struct v4l2_plane_pix_format *plane_fmt;
2626 int h = round_up(height, MEMORY_ALIGN_ROUND_UP_HEIGHT);
2627
2628 plane_fmt = &pixm->plane_fmt[i];
2629 sizes[i] = plane_fmt->sizeimage / height * h;
2630 }
2631
2632 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s count %d, size %d, extended(%d, %d)\n",
2633 v4l2_type_names[queue->type], *num_buffers, sizes[0],
2634 is_extended, extend_line->is_extended);
2635
2636 return 0;
2637 }
2638
rkcif_check_buffer_update_pingpong(struct rkcif_stream * stream,int channel_id)2639 static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
2640 int channel_id)
2641 {
2642 struct rkcif_device *dev = stream->cifdev;
2643 struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2644 struct rkcif_buffer *buffer = NULL;
2645 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2646 u32 frm_addr_y, frm_addr_uv;
2647 unsigned long flags;
2648
2649 if (stream->state == RKCIF_STATE_STREAMING &&
2650 stream->curr_buf == stream->next_buf &&
2651 stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
2652 (!dummy_buf->vaddr)) {
2653 if (!stream->is_line_wake_up) {
2654 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
2655 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
2656 mbus_cfg->type == V4L2_MBUS_CCP2) {
2657 frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2658 get_reg_index_of_frm0_y_addr(channel_id) :
2659 get_reg_index_of_frm1_y_addr(channel_id);
2660 frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2661 get_reg_index_of_frm0_uv_addr(channel_id) :
2662 get_reg_index_of_frm1_uv_addr(channel_id);
2663 } else {
2664 frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2665 get_dvp_reg_index_of_frm0_y_addr(channel_id) :
2666 get_dvp_reg_index_of_frm1_y_addr(channel_id);
2667 frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2668 get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
2669 get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2670 }
2671 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2672 "stream[%d] update buf in %s, stream->frame_phase_cache %d\n",
2673 stream->id, __func__, stream->frame_phase_cache);
2674 spin_lock_irqsave(&stream->vbq_lock, flags);
2675 if (!list_empty(&stream->buf_head)) {
2676 if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
2677 stream->curr_buf = list_first_entry(&stream->buf_head,
2678 struct rkcif_buffer, queue);
2679 if (stream->curr_buf) {
2680 list_del(&stream->curr_buf->queue);
2681 buffer = stream->curr_buf;
2682 }
2683 } else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2684 stream->next_buf = list_first_entry(&stream->buf_head,
2685 struct rkcif_buffer, queue);
2686 if (stream->next_buf) {
2687 list_del(&stream->next_buf->queue);
2688 buffer = stream->next_buf;
2689 }
2690 }
2691 }
2692 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2693 if (buffer) {
2694 rkcif_write_register(dev, frm_addr_y,
2695 buffer->buff_addr[RKCIF_PLANE_Y]);
2696 if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2697 rkcif_write_register(dev, frm_addr_uv,
2698 buffer->buff_addr[RKCIF_PLANE_CBCR]);
2699 }
2700 } else {
2701 spin_lock_irqsave(&stream->vbq_lock, flags);
2702 if (stream->curr_buf == stream->next_buf) {
2703 if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
2704 stream->curr_buf = list_first_entry(&stream->buf_head,
2705 struct rkcif_buffer, queue);
2706 if (stream->curr_buf)
2707 list_del(&stream->curr_buf->queue);
2708 } else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2709 stream->next_buf = list_first_entry(&stream->buf_head,
2710 struct rkcif_buffer, queue);
2711 if (stream->next_buf)
2712 list_del(&stream->next_buf->queue);
2713 }
2714 stream->is_buf_active = true;
2715 }
2716 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2717 }
2718 }
2719 }
2720
2721 /*
2722 * The vb2_buffer are stored in rkcif_buffer, in order to unify
2723 * mplane buffer and none-mplane buffer.
2724 */
rkcif_buf_queue(struct vb2_buffer * vb)2725 static void rkcif_buf_queue(struct vb2_buffer *vb)
2726 {
2727 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2728 struct rkcif_buffer *cifbuf = to_rkcif_buffer(vbuf);
2729 struct vb2_queue *queue = vb->vb2_queue;
2730 struct rkcif_stream *stream = queue->drv_priv;
2731 struct v4l2_pix_format_mplane *pixm = &stream->pixm;
2732 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
2733 struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
2734 unsigned long flags;
2735 int i;
2736
2737 memset(cifbuf->buff_addr, 0, sizeof(cifbuf->buff_addr));
2738 /* If mplanes > 1, every c-plane has its own m-plane,
2739 * otherwise, multiple c-planes are in the same m-plane
2740 */
2741 for (i = 0; i < fmt->mplanes; i++) {
2742 void *addr = vb2_plane_vaddr(vb, i);
2743
2744 if (hw_dev->iommu_en) {
2745 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, i);
2746
2747 cifbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
2748 } else {
2749 cifbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
2750 }
2751 if (rkcif_debug && addr && !hw_dev->iommu_en) {
2752 memset(addr, 0, pixm->plane_fmt[i].sizeimage);
2753 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2754 "Clear buffer, size: 0x%08x\n",
2755 pixm->plane_fmt[i].sizeimage);
2756 }
2757 }
2758
2759 if (fmt->mplanes == 1) {
2760 for (i = 0; i < fmt->cplanes - 1; i++)
2761 cifbuf->buff_addr[i + 1] = cifbuf->buff_addr[i] +
2762 pixm->plane_fmt[i].bytesperline * pixm->height;
2763 }
2764 spin_lock_irqsave(&stream->vbq_lock, flags);
2765 list_add_tail(&cifbuf->queue, &stream->buf_head);
2766 spin_unlock_irqrestore(&stream->vbq_lock, flags);
2767 if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG)
2768 rkcif_check_buffer_update_pingpong(stream, stream->id);
2769 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2770 "stream[%d] buf queue, index: %d\n",
2771 stream->id, vb->index);
2772 }
2773
rkcif_free_rx_buf(struct rkcif_stream * stream,int buf_num)2774 void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
2775 {
2776 struct rkisp_rx_buf *dbufs;
2777 struct rkcif_rx_buffer *buf;
2778 struct rkcif_device *dev = stream->cifdev;
2779 int i = 0;
2780
2781 if (stream->curr_buf_toisp) {
2782 list_add_tail(&stream->curr_buf_toisp->dbufs.list, &stream->rx_buf_head);
2783 if (stream->curr_buf_toisp == stream->next_buf_toisp)
2784 stream->next_buf_toisp = NULL;
2785 stream->curr_buf_toisp = NULL;
2786 }
2787 if (stream->next_buf_toisp) {
2788 list_add_tail(&stream->next_buf_toisp->dbufs.list, &stream->rx_buf_head);
2789 stream->next_buf_toisp = NULL;
2790 }
2791 while (!list_empty(&stream->rx_buf_head)) {
2792 dbufs = list_first_entry(&stream->rx_buf_head,
2793 struct rkisp_rx_buf, list);
2794 list_del(&dbufs->list);
2795 }
2796 for (i = 0; i < buf_num; i++) {
2797 buf = &stream->rx_buf[i];
2798 rkcif_free_buffer(dev, &buf->dummy);
2799 }
2800 stream->dma_en &= ~RKCIF_DMAEN_BY_ISP;
2801 v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
2802 "free rx_buf, buf_num %d\n", buf_num);
2803 }
2804
rkcif_init_rx_buf(struct rkcif_stream * stream,int buf_num)2805 int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num)
2806 {
2807 struct rkcif_device *dev = stream->cifdev;
2808 struct v4l2_pix_format_mplane *pixm = &stream->pixm;
2809 struct rkcif_dummy_buffer *dummy;
2810 struct rkcif_rx_buffer *buf;
2811 int frm_type = 0;
2812 int i = 0;
2813 int ret = 0;
2814
2815 if (buf_num > RKCIF_RX_BUF_MAX)
2816 return -EINVAL;
2817 if (dev->hdr.hdr_mode == HDR_X2 && stream->id == 0)
2818 frm_type = BUF_MIDDLE;
2819 else if (dev->hdr.hdr_mode == HDR_X3 && stream->id == 0)
2820 frm_type = BUF_LONG;
2821 else if (dev->hdr.hdr_mode == HDR_X3 && stream->id == 1)
2822 frm_type = BUF_MIDDLE;
2823 for (i = 0; i < buf_num; i++) {
2824 buf = &stream->rx_buf[i];
2825 memset(buf, 0, sizeof(*buf));
2826 dummy = &buf->dummy;
2827 dummy->size = pixm->plane_fmt[0].sizeimage;
2828 dummy->is_need_vaddr = true;
2829 dummy->is_need_dbuf = true;
2830 ret = rkcif_alloc_buffer(dev, dummy);
2831 if (ret)
2832 goto alloc_rx_buf_err;
2833 buf->dbufs.is_init = false;
2834 buf->dbufs.type = frm_type;
2835 buf->dbufs.dbuf = dummy->dbuf;
2836 list_add_tail(&buf->dbufs.list, &stream->rx_buf_head);
2837 rkcif_s_rx_buffer(dev, &buf->dbufs);
2838 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2839 "init rx_buf,dma_addr 0x%llx size: 0x%x\n",
2840 (u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
2841 }
2842 return 0;
2843 alloc_rx_buf_err:
2844 rkcif_free_rx_buf(stream, buf_num);
2845 v4l2_err(&dev->v4l2_dev, "%s fail:%d\n", __func__, ret);
2846 return ret;
2847
2848 }
2849
rkcif_create_dummy_buf(struct rkcif_stream * stream)2850 static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
2851 {
2852 u32 fourcc;
2853 struct rkcif_device *dev = stream->cifdev;
2854 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2855 int ret = 0;
2856
2857 /* get a maximum plane size */
2858 dummy_buf->size = max3(stream->pixm.plane_fmt[0].bytesperline *
2859 stream->pixm.height,
2860 stream->pixm.plane_fmt[1].sizeimage,
2861 stream->pixm.plane_fmt[2].sizeimage);
2862 /*
2863 * rk cif don't support output yuyv fmt data
2864 * if user request yuyv fmt, the input mode must be RAW8
2865 * and the width is double Because the real input fmt is
2866 * yuyv
2867 */
2868 fourcc = stream->cif_fmt_out->fourcc;
2869 if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
2870 fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY)
2871 dummy_buf->size *= 2;
2872
2873 dummy_buf->is_need_vaddr = true;
2874 dummy_buf->is_need_dbuf = true;
2875 ret = rkcif_alloc_common_dummy_buf(dev, dummy_buf);
2876 if (ret) {
2877 v4l2_err(&dev->v4l2_dev,
2878 "Failed to allocate the memory for dummy buffer\n");
2879 return -ENOMEM;
2880 }
2881
2882 v4l2_info(&dev->v4l2_dev, "Allocate dummy buffer, size: 0x%08x\n",
2883 dummy_buf->size);
2884
2885 return ret;
2886 }
2887
rkcif_destroy_dummy_buf(struct rkcif_stream * stream)2888 static void rkcif_destroy_dummy_buf(struct rkcif_stream *stream)
2889 {
2890 struct rkcif_device *dev = stream->cifdev;
2891 struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2892
2893 if (dummy_buf->vaddr)
2894 rkcif_free_common_dummy_buf(dev, dummy_buf);
2895 dummy_buf->dma_addr = 0;
2896 dummy_buf->vaddr = NULL;
2897 }
2898
rkcif_do_cru_reset(struct rkcif_device * dev)2899 static void rkcif_do_cru_reset(struct rkcif_device *dev)
2900 {
2901 struct rkcif_hw *cif_hw = dev->hw_dev;
2902
2903 unsigned int val, i;
2904
2905 if (dev->luma_vdev.enable)
2906 rkcif_stop_luma(&dev->luma_vdev);
2907
2908 if (dev->hdr.hdr_mode != NO_HDR) {
2909 if (dev->chip_id == CHIP_RK1808_CIF) {
2910 val = rkcif_read_register(dev, CIF_REG_MIPI_WATER_LINE);
2911 val |= CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808;
2912 rkcif_write_register(dev, CIF_REG_MIPI_WATER_LINE, val);
2913 } else {
2914 val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
2915 val |= CIF_MIPI_LVDS_SW_DMA_IDLE;
2916 rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
2917 }
2918 udelay(5);
2919 }
2920
2921 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
2922 if (cif_hw->cif_rst[i])
2923 reset_control_assert(cif_hw->cif_rst[i]);
2924
2925 udelay(10);
2926
2927 for (i = 0; i < ARRAY_SIZE(cif_hw->cif_rst); i++)
2928 if (cif_hw->cif_rst[i])
2929 reset_control_deassert(cif_hw->cif_rst[i]);
2930
2931 if (cif_hw->iommu_en) {
2932 rockchip_iommu_disable(cif_hw->dev);
2933 rockchip_iommu_enable(cif_hw->dev);
2934 }
2935 }
2936
rkcif_do_soft_reset(struct rkcif_device * dev)2937 static void rkcif_do_soft_reset(struct rkcif_device *dev)
2938 {
2939 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
2940 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
2941 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
2942 rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
2943 else
2944 rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x000A0000);
2945 usleep_range(10, 20);
2946 v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
2947 "vicap do soft reset 0x%x\n", 0x000A0000);
2948 }
2949
rkcif_release_rdbk_buf(struct rkcif_stream * stream)2950 static void rkcif_release_rdbk_buf(struct rkcif_stream *stream)
2951 {
2952 struct rkcif_device *dev = stream->cifdev;
2953 struct rkcif_buffer *rdbk_buf;
2954 struct rkcif_buffer *tmp_buf;
2955 unsigned long flags;
2956 bool has_added;
2957 int index = 0;
2958
2959 if (stream->id == RKCIF_STREAM_MIPI_ID0)
2960 index = RDBK_L;
2961 else if (stream->id == RKCIF_STREAM_MIPI_ID1)
2962 index = RDBK_M;
2963 else if (stream->id == RKCIF_STREAM_MIPI_ID2)
2964 index = RDBK_S;
2965 else
2966 return;
2967
2968 spin_lock_irqsave(&dev->hdr_lock, flags);
2969 rdbk_buf = dev->rdbk_buf[index];
2970 if (rdbk_buf) {
2971 if (rdbk_buf != stream->curr_buf &&
2972 rdbk_buf != stream->next_buf) {
2973
2974 has_added = false;
2975
2976 list_for_each_entry(tmp_buf, &stream->buf_head, queue) {
2977 if (tmp_buf == rdbk_buf) {
2978 has_added = true;
2979 break;
2980 }
2981 }
2982
2983 if (!has_added)
2984 list_add_tail(&rdbk_buf->queue, &stream->buf_head);
2985 }
2986 dev->rdbk_buf[index] = NULL;
2987 }
2988 spin_unlock_irqrestore(&dev->hdr_lock, flags);
2989
2990 }
2991
rkcif_detach_sync_mode(struct rkcif_device * cif_dev)2992 static void rkcif_detach_sync_mode(struct rkcif_device *cif_dev)
2993 {
2994 int i = 0;
2995 struct rkcif_hw *hw = cif_dev->hw_dev;
2996 struct rkcif_device *tmp_dev;
2997
2998 if ((!cif_dev->sync_type) ||
2999 (atomic_read(&cif_dev->pipe.stream_cnt) != 0))
3000 return;
3001
3002 hw->sync_config.streaming_cnt--;
3003 if (cif_dev->sync_type == EXTERNAL_MASTER_MODE) {
3004 for (i = 0; i < hw->sync_config.ext_master.count; i++) {
3005 tmp_dev = hw->sync_config.ext_master.cif_dev[i];
3006 if (tmp_dev == cif_dev) {
3007 hw->sync_config.ext_master.is_streaming[i] = false;
3008 break;
3009 }
3010 }
3011 }
3012 if (cif_dev->sync_type == INTERNAL_MASTER_MODE)
3013 hw->sync_config.int_master.is_streaming[0] = false;
3014 if (cif_dev->sync_type == SLAVE_MODE) {
3015 for (i = 0; i < hw->sync_config.slave.count; i++) {
3016 tmp_dev = hw->sync_config.slave.cif_dev[i];
3017 if (tmp_dev == cif_dev) {
3018 hw->sync_config.slave.is_streaming[i] = false;
3019 break;
3020 }
3021 }
3022 }
3023
3024 if (!hw->sync_config.streaming_cnt && hw->sync_config.is_attach) {
3025 hw->sync_config.is_attach = false;
3026 hw->sync_config.mode = RKCIF_NOSYNC_MODE;
3027 hw->sync_config.dev_cnt = 0;
3028 for (i = 0; i < hw->dev_num; i++)
3029 hw->cif_dev[i]->sync_type = NO_SYNC_MODE;
3030 }
3031 }
3032
rkcif_do_stop_stream(struct rkcif_stream * stream,unsigned int mode)3033 void rkcif_do_stop_stream(struct rkcif_stream *stream,
3034 unsigned int mode)
3035 {
3036 struct rkcif_vdev_node *node = &stream->vnode;
3037 struct rkcif_device *dev = stream->cifdev;
3038 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3039 struct rkcif_buffer *buf = NULL;
3040 int ret;
3041 struct rkcif_hw *hw_dev = dev->hw_dev;
3042 bool can_reset = true;
3043 int i;
3044
3045 mutex_lock(&dev->stream_lock);
3046
3047 v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping, total mode 0x%x, cur 0x%x\n",
3048 stream->id, stream->cur_stream_mode, mode);
3049
3050 if (mode == stream->cur_stream_mode) {
3051 stream->stopping = true;
3052
3053 ret = wait_event_timeout(stream->wq_stopped,
3054 stream->state != RKCIF_STATE_STREAMING,
3055 msecs_to_jiffies(1000));
3056 if (!ret) {
3057 rkcif_stream_stop(stream);
3058 stream->stopping = false;
3059 }
3060
3061 media_pipeline_stop(&node->vdev.entity);
3062 ret = dev->pipe.set_stream(&dev->pipe, false);
3063 if (ret < 0)
3064 v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
3065 ret);
3066
3067 dev->is_start_hdr = false;
3068 stream->is_dvp_yuv_addr_init = false;
3069 } else if (mode == RKCIF_STREAM_MODE_CAPTURE) {
3070 //only stop dma
3071 stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
3072 wait_event_timeout(stream->wq_stopped,
3073 stream->to_stop_dma != RKCIF_DMAEN_BY_VICAP,
3074 msecs_to_jiffies(1000));
3075 } else if (mode == RKCIF_STREAM_MODE_TOISP) {
3076 //only stop dma
3077 stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
3078 wait_event_timeout(stream->wq_stopped,
3079 stream->to_stop_dma != RKCIF_DMAEN_BY_ISP,
3080 msecs_to_jiffies(1000));
3081 }
3082 if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
3083 /* release buffers */
3084 if (stream->curr_buf)
3085 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
3086
3087 if (stream->next_buf &&
3088 stream->next_buf != stream->curr_buf)
3089 list_add_tail(&stream->next_buf->queue, &stream->buf_head);
3090
3091 if (dev->hdr.hdr_mode != NO_HDR)
3092 rkcif_release_rdbk_buf(stream);
3093
3094 stream->curr_buf = NULL;
3095 stream->next_buf = NULL;
3096
3097 while (!list_empty(&stream->buf_head)) {
3098 buf = list_first_entry(&stream->buf_head,
3099 struct rkcif_buffer, queue);
3100 list_del(&buf->queue);
3101 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
3102 }
3103 stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
3104 }
3105
3106 if (mode == stream->cur_stream_mode) {
3107 ret = dev->pipe.close(&dev->pipe);
3108 if (ret < 0)
3109 v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
3110 pm_runtime_put_sync(dev->dev);
3111 v4l2_pipeline_pm_put(&node->vdev.entity);
3112 if (dev->hdr.hdr_mode == HDR_X2) {
3113 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
3114 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
3115 dev->can_be_reset = true;
3116 }
3117 } else if (dev->hdr.hdr_mode == HDR_X3) {
3118 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
3119 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
3120 dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
3121 dev->can_be_reset = true;
3122 }
3123 } else {
3124 dev->can_be_reset = true;
3125 }
3126
3127 for (i = 0; i < hw_dev->dev_num; i++) {
3128 if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
3129 can_reset = false;
3130 break;
3131 }
3132 }
3133 if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF)
3134 rkcif_do_soft_reset(dev);
3135 if (dev->can_be_reset && can_reset) {
3136 rkcif_do_cru_reset(dev);
3137 dev->can_be_reset = false;
3138 dev->reset_work_cancel = true;
3139 }
3140 }
3141 if (!atomic_read(&dev->pipe.stream_cnt) && dev->dummy_buf.vaddr)
3142 rkcif_destroy_dummy_buf(stream);
3143 stream->cur_stream_mode &= ~mode;
3144 v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished\n", stream->id);
3145 rkcif_detach_sync_mode(dev);
3146 mutex_unlock(&dev->stream_lock);
3147 }
3148
rkcif_stop_streaming(struct vb2_queue * queue)3149 static void rkcif_stop_streaming(struct vb2_queue *queue)
3150 {
3151 struct rkcif_stream *stream = queue->drv_priv;
3152
3153 rkcif_do_stop_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
3154 }
3155
3156 /*
3157 * CIF supports the following input modes,
3158 * YUV, the default mode
3159 * PAL,
3160 * NTSC,
3161 * RAW, if the input format is raw bayer
3162 * JPEG, TODO
3163 * MIPI, TODO
3164 */
rkcif_determine_input_mode(struct rkcif_stream * stream)3165 static u32 rkcif_determine_input_mode(struct rkcif_stream *stream)
3166 {
3167 struct rkcif_device *dev = stream->cifdev;
3168 struct rkcif_sensor_info *sensor_info = dev->active_sensor;
3169 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
3170 __u32 intf = BT656_STD_RAW;
3171 u32 mode = INPUT_MODE_YUV;
3172 v4l2_std_id std;
3173 int ret;
3174
3175 ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
3176 if (ret == 0) {
3177 /* retrieve std from sensor if exist */
3178 switch (std) {
3179 case V4L2_STD_NTSC:
3180 mode = INPUT_MODE_NTSC;
3181 break;
3182 case V4L2_STD_PAL:
3183 mode = INPUT_MODE_PAL;
3184 break;
3185 case V4L2_STD_ATSC:
3186 mode = INPUT_MODE_BT1120;
3187 break;
3188 default:
3189 v4l2_err(&dev->v4l2_dev,
3190 "std: %lld is not supported", std);
3191 }
3192 } else {
3193 /* determine input mode by mbus_code (fmt_type) */
3194 switch (stream->cif_fmt_in->fmt_type) {
3195 case CIF_FMT_TYPE_YUV:
3196 if (dev->chip_id >= CHIP_RK3568_CIF) {
3197 if (sensor_info->mbus.type == V4L2_MBUS_BT656)
3198 mode = INPUT_MODE_BT656_YUV422;
3199 else
3200 mode = INPUT_MODE_YUV;
3201 } else {
3202 mode = INPUT_MODE_YUV;
3203 }
3204 break;
3205 case CIF_FMT_TYPE_RAW:
3206 if (dev->chip_id >= CHIP_RK3568_CIF) {
3207 ret = v4l2_subdev_call(terminal_sensor->sd,
3208 core, ioctl,
3209 RKMODULE_GET_BT656_INTF_TYPE,
3210 &intf);
3211 if (!ret) {
3212 if (intf == BT656_SONY_RAW)
3213 mode = INPUT_MODE_SONY_RAW;
3214 else
3215 mode = INPUT_MODE_RAW;
3216 } else {
3217 mode = INPUT_MODE_RAW;
3218 }
3219 } else {
3220 mode = INPUT_MODE_RAW;
3221 }
3222 break;
3223 }
3224 }
3225
3226 return mode;
3227 }
3228
rkcif_determine_input_mode_rk3588(struct rkcif_stream * stream)3229 static u32 rkcif_determine_input_mode_rk3588(struct rkcif_stream *stream)
3230 {
3231 struct rkcif_device *dev = stream->cifdev;
3232 struct rkcif_sensor_info *sensor_info = dev->active_sensor;
3233 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
3234 __u32 intf = BT656_STD_RAW;
3235 u32 mode = INPUT_MODE_YUV;
3236 v4l2_std_id std;
3237 int ret;
3238
3239 ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
3240 if (ret == 0) {
3241 /* retrieve std from sensor if exist */
3242 switch (std) {
3243 case V4L2_STD_NTSC:
3244 case V4L2_STD_PAL:
3245 mode = INPUT_BT656_YUV422;
3246 break;
3247 case V4L2_STD_ATSC:
3248 mode = INPUT_BT1120_YUV422;
3249 break;
3250 default:
3251 v4l2_err(&dev->v4l2_dev,
3252 "std: %lld is not supported", std);
3253 }
3254 mode |= CSI_WRDDR_TYPE_RAW8 << 6;
3255 } else {
3256 /* determine input mode by mbus_code (fmt_type) */
3257 switch (stream->cif_fmt_in->fmt_type) {
3258 case CIF_FMT_TYPE_YUV:
3259 if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
3260 if ((sensor_info->mbus.flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE)
3261 mode = INPUT_BT1120_YUV422;
3262 else
3263 mode = INPUT_BT656_YUV422;
3264 } else {
3265 mode = INPUT_BT601_YUV422;
3266 }
3267 mode |= CSI_WRDDR_TYPE_RAW8 << 6;
3268 break;
3269 case CIF_FMT_TYPE_RAW:
3270 ret = v4l2_subdev_call(terminal_sensor->sd,
3271 core, ioctl,
3272 RKMODULE_GET_BT656_INTF_TYPE,
3273 &intf);
3274 if (!ret) {
3275 if (intf == BT656_SONY_RAW)
3276 mode = INPUT_SONY_RAW;
3277 else
3278 mode = INPUT_BT601_RAW;
3279 } else {
3280 mode = INPUT_BT601_RAW;
3281 }
3282 mode |= stream->cif_fmt_in->csi_fmt_val << 6;
3283 break;
3284 }
3285 }
3286 if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
3287 mode |= TRANSMIT_PROGRESS_RK3588;
3288 else
3289 mode |= TRANSMIT_INTERFACE_RK3588;
3290 return mode;
3291 }
3292
rkcif_scl_ctl(struct rkcif_stream * stream)3293 static inline u32 rkcif_scl_ctl(struct rkcif_stream *stream)
3294 {
3295 u32 fmt_type = stream->cif_fmt_in->fmt_type;
3296
3297 return (fmt_type == CIF_FMT_TYPE_YUV) ?
3298 ENABLE_YUV_16BIT_BYPASS : ENABLE_RAW_16BIT_BYPASS;
3299 }
3300
3301 /**
3302 * rkcif_align_bits_per_pixel() - return the bit width of per pixel for stored
3303 * In raw or jpeg mode, data is stored by 16-bits,so need to align it.
3304 */
rkcif_align_bits_per_pixel(struct rkcif_stream * stream,const struct cif_output_fmt * fmt,int plane_index)3305 static u32 rkcif_align_bits_per_pixel(struct rkcif_stream *stream,
3306 const struct cif_output_fmt *fmt,
3307 int plane_index)
3308 {
3309 u32 bpp = 0, i, cal = 0;
3310
3311 if (fmt) {
3312 switch (fmt->fourcc) {
3313 case V4L2_PIX_FMT_NV16:
3314 case V4L2_PIX_FMT_NV61:
3315 case V4L2_PIX_FMT_NV12:
3316 case V4L2_PIX_FMT_NV21:
3317 case V4L2_PIX_FMT_GREY:
3318 case V4L2_PIX_FMT_Y16:
3319 bpp = fmt->bpp[plane_index];
3320 break;
3321 case V4L2_PIX_FMT_YUYV:
3322 case V4L2_PIX_FMT_YVYU:
3323 case V4L2_PIX_FMT_UYVY:
3324 case V4L2_PIX_FMT_VYUY:
3325 if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
3326 bpp = fmt->bpp[plane_index];
3327 else
3328 bpp = fmt->bpp[plane_index + 1];
3329 break;
3330 case V4L2_PIX_FMT_RGB24:
3331 case V4L2_PIX_FMT_RGB565:
3332 case V4L2_PIX_FMT_BGR666:
3333 case V4L2_PIX_FMT_SRGGB8:
3334 case V4L2_PIX_FMT_SGRBG8:
3335 case V4L2_PIX_FMT_SGBRG8:
3336 case V4L2_PIX_FMT_SBGGR8:
3337 case V4L2_PIX_FMT_SRGGB10:
3338 case V4L2_PIX_FMT_SGRBG10:
3339 case V4L2_PIX_FMT_SGBRG10:
3340 case V4L2_PIX_FMT_SBGGR10:
3341 case V4L2_PIX_FMT_SRGGB12:
3342 case V4L2_PIX_FMT_SGRBG12:
3343 case V4L2_PIX_FMT_SGBRG12:
3344 case V4L2_PIX_FMT_SBGGR12:
3345 case V4L2_PIX_FMT_SBGGR16:
3346 case V4L2_PIX_FMT_SGBRG16:
3347 case V4L2_PIX_FMT_SGRBG16:
3348 case V4L2_PIX_FMT_SRGGB16:
3349 case V4l2_PIX_FMT_SPD16:
3350 case V4l2_PIX_FMT_EBD8:
3351 if (stream->cifdev->chip_id < CHIP_RV1126_CIF) {
3352 bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH);
3353 cal = CIF_RAW_STORED_BIT_WIDTH;
3354 } else {
3355 bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH_RV1126);
3356 cal = CIF_RAW_STORED_BIT_WIDTH_RV1126;
3357 }
3358 for (i = 1; i < 5; i++) {
3359 if (i * cal >= bpp) {
3360 bpp = i * cal;
3361 break;
3362 }
3363 }
3364 break;
3365 default:
3366 v4l2_err(&stream->cifdev->v4l2_dev, "fourcc: %d is not supported!\n",
3367 fmt->fourcc);
3368 break;
3369 }
3370 }
3371
3372 return bpp;
3373 }
3374
3375 /**
3376 * rkcif_cal_raw_vir_line_ratio() - return ratio for virtual line width setting
3377 * In raw or jpeg mode, data is stored by 16-bits,
3378 * so need to align virtual line width.
3379 */
rkcif_cal_raw_vir_line_ratio(struct rkcif_stream * stream,const struct cif_output_fmt * fmt)3380 static u32 rkcif_cal_raw_vir_line_ratio(struct rkcif_stream *stream,
3381 const struct cif_output_fmt *fmt)
3382 {
3383 u32 ratio = 0, bpp = 0;
3384
3385 if (fmt) {
3386 bpp = rkcif_align_bits_per_pixel(stream, fmt, 0);
3387 ratio = bpp / CIF_YUV_STORED_BIT_WIDTH;
3388 }
3389
3390 return ratio;
3391 }
3392
rkcif_sync_crop_info(struct rkcif_stream * stream)3393 static void rkcif_sync_crop_info(struct rkcif_stream *stream)
3394 {
3395 struct rkcif_device *dev = stream->cifdev;
3396 struct v4l2_subdev_selection input_sel;
3397 int ret;
3398
3399 if (dev->terminal_sensor.sd) {
3400 input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
3401 input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
3402 input_sel.pad = 0;
3403 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
3404 pad, get_selection, NULL,
3405 &input_sel);
3406 if (!ret) {
3407 stream->crop[CROP_SRC_SENSOR] = input_sel.r;
3408 stream->crop_enable = true;
3409 stream->crop_mask |= CROP_SRC_SENSOR_MASK;
3410 dev->terminal_sensor.selection = input_sel;
3411 } else {
3412 dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
3413 }
3414 }
3415
3416 if ((stream->crop_mask & 0x3) == (CROP_SRC_USR_MASK | CROP_SRC_SENSOR_MASK)) {
3417 if (stream->crop[CROP_SRC_USR].left + stream->crop[CROP_SRC_USR].width >
3418 stream->crop[CROP_SRC_SENSOR].width ||
3419 stream->crop[CROP_SRC_USR].top + stream->crop[CROP_SRC_USR].height >
3420 stream->crop[CROP_SRC_SENSOR].height)
3421 stream->crop[CROP_SRC_USR] = stream->crop[CROP_SRC_SENSOR];
3422 }
3423
3424 if (stream->crop_mask & CROP_SRC_USR_MASK) {
3425 stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
3426 if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
3427 stream->crop[CROP_SRC_ACT].left = stream->crop[CROP_SRC_USR].left +
3428 stream->crop[CROP_SRC_SENSOR].left;
3429 stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
3430 stream->crop[CROP_SRC_SENSOR].top;
3431 }
3432 } else {
3433 stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
3434 }
3435 }
3436
3437 /**rkcif_sanity_check_fmt - check fmt for setting
3438 * @stream - the stream for setting
3439 * @s_crop - the crop information
3440 */
rkcif_sanity_check_fmt(struct rkcif_stream * stream,const struct v4l2_rect * s_crop)3441 static int rkcif_sanity_check_fmt(struct rkcif_stream *stream,
3442 const struct v4l2_rect *s_crop)
3443 {
3444 struct rkcif_device *dev = stream->cifdev;
3445 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3446 struct v4l2_rect input, *crop;
3447
3448 stream->cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
3449 &input, stream->id, &dev->channels[stream->id]);
3450 if (!stream->cif_fmt_in) {
3451 v4l2_err(v4l2_dev, "Input fmt is invalid\n");
3452 return -EINVAL;
3453 }
3454
3455 if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
3456 stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
3457 stream->crop_enable = false;
3458 return 0;
3459 }
3460
3461 if (s_crop)
3462 crop = (struct v4l2_rect *)s_crop;
3463 else
3464 crop = &stream->crop[CROP_SRC_ACT];
3465
3466 if (crop->width + crop->left > input.width ||
3467 crop->height + crop->top > input.height) {
3468 v4l2_err(v4l2_dev, "crop size is bigger than input\n");
3469 return -EINVAL;
3470 }
3471
3472 if (dev->active_sensor &&
3473 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
3474 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY)) {
3475 if (crop->left > 0) {
3476 int align_x = get_csi_crop_align(stream->cif_fmt_in);
3477
3478 if (align_x > 0 && crop->left % align_x != 0) {
3479 v4l2_err(v4l2_dev,
3480 "ERROR: crop left must align %d\n",
3481 align_x);
3482 return -EINVAL;
3483 }
3484 }
3485 } else if (dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
3486 if (crop->left % 4 != 0 && crop->width % 4 != 0) {
3487 v4l2_err(v4l2_dev,
3488 "ERROR: lvds crop left and width must align %d\n", 4);
3489 return -EINVAL;
3490 }
3491 }
3492
3493 return 0;
3494 }
3495
rkcif_update_sensor_info(struct rkcif_stream * stream)3496 int rkcif_update_sensor_info(struct rkcif_stream *stream)
3497 {
3498 struct rkcif_sensor_info *sensor, *terminal_sensor;
3499 struct v4l2_subdev *sensor_sd;
3500 int ret = 0;
3501
3502 sensor_sd = get_remote_sensor(stream, NULL);
3503 if (!sensor_sd) {
3504 v4l2_err(&stream->cifdev->v4l2_dev,
3505 "%s: stream[%d] get remote sensor_sd failed!\n",
3506 __func__, stream->id);
3507 return -ENODEV;
3508 }
3509
3510 sensor = sd_to_sensor(stream->cifdev, sensor_sd);
3511 if (!sensor) {
3512 v4l2_err(&stream->cifdev->v4l2_dev,
3513 "%s: stream[%d] get remote sensor failed!\n",
3514 __func__, stream->id);
3515 return -ENODEV;
3516 }
3517 ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
3518 0, &sensor->mbus);
3519 if (ret && ret != -ENOIOCTLCMD) {
3520 v4l2_err(&stream->cifdev->v4l2_dev,
3521 "%s: get remote %s mbus failed!\n", __func__, sensor->sd->name);
3522 return ret;
3523 }
3524
3525 stream->cifdev->active_sensor = sensor;
3526
3527 terminal_sensor = &stream->cifdev->terminal_sensor;
3528 get_remote_terminal_sensor(stream, &terminal_sensor->sd);
3529 if (terminal_sensor->sd) {
3530 ret = v4l2_subdev_call(terminal_sensor->sd, pad, get_mbus_config,
3531 0, &terminal_sensor->mbus);
3532 if (ret && ret != -ENOIOCTLCMD) {
3533 v4l2_err(&stream->cifdev->v4l2_dev,
3534 "%s: get terminal %s mbus failed!\n",
3535 __func__, terminal_sensor->sd->name);
3536 return ret;
3537 }
3538 } else {
3539 v4l2_err(&stream->cifdev->v4l2_dev,
3540 "%s: stream[%d] get remote terminal sensor failed!\n",
3541 __func__, stream->id);
3542 return -ENODEV;
3543 }
3544
3545 if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
3546 terminal_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
3547 terminal_sensor->mbus.type == V4L2_MBUS_CCP2) {
3548 switch (terminal_sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
3549 case V4L2_MBUS_CSI2_1_LANE:
3550 terminal_sensor->lanes = 1;
3551 break;
3552 case V4L2_MBUS_CSI2_2_LANE:
3553 terminal_sensor->lanes = 2;
3554 break;
3555 case V4L2_MBUS_CSI2_3_LANE:
3556 terminal_sensor->lanes = 3;
3557 break;
3558 case V4L2_MBUS_CSI2_4_LANE:
3559 terminal_sensor->lanes = 4;
3560 break;
3561 default:
3562 v4l2_err(&stream->cifdev->v4l2_dev, "%s:get sd:%s lane num failed!\n",
3563 __func__,
3564 terminal_sensor->sd ?
3565 terminal_sensor->sd->name : "null");
3566 return -EINVAL;
3567 }
3568 }
3569
3570 return ret;
3571 }
3572
rkcif_dvp_get_output_type_mask(struct rkcif_stream * stream)3573 static int rkcif_dvp_get_output_type_mask(struct rkcif_stream *stream)
3574 {
3575 unsigned int mask;
3576 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
3577
3578 switch (fmt->fourcc) {
3579 case V4L2_PIX_FMT_NV16:
3580 mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) |
3581 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
3582 break;
3583 case V4L2_PIX_FMT_NV61:
3584 mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) |
3585 (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
3586 break;
3587 case V4L2_PIX_FMT_NV12:
3588 mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) |
3589 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
3590 break;
3591 case V4L2_PIX_FMT_NV21:
3592 mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) |
3593 (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
3594 break;
3595 case V4L2_PIX_FMT_YUYV:
3596 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
3597 (CSI_YUV_OUTPUT_ORDER_YUYV << 1);
3598 break;
3599 case V4L2_PIX_FMT_YVYU:
3600 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
3601 (CSI_YUV_OUTPUT_ORDER_YVYU << 1);
3602 break;
3603 case V4L2_PIX_FMT_UYVY:
3604 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
3605 (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
3606 break;
3607 case V4L2_PIX_FMT_VYUY:
3608 mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) |
3609 (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
3610 break;
3611 case V4L2_PIX_FMT_RGB24:
3612 case V4L2_PIX_FMT_RGB565:
3613 case V4L2_PIX_FMT_BGR666:
3614 mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
3615 break;
3616 case V4L2_PIX_FMT_SRGGB8:
3617 case V4L2_PIX_FMT_SGRBG8:
3618 case V4L2_PIX_FMT_SGBRG8:
3619 case V4L2_PIX_FMT_SBGGR8:
3620 case V4L2_PIX_FMT_SRGGB10:
3621 case V4L2_PIX_FMT_SGRBG10:
3622 case V4L2_PIX_FMT_SGBRG10:
3623 case V4L2_PIX_FMT_SBGGR10:
3624 case V4L2_PIX_FMT_SRGGB12:
3625 case V4L2_PIX_FMT_SGRBG12:
3626 case V4L2_PIX_FMT_SGBRG12:
3627 case V4L2_PIX_FMT_SBGGR12:
3628 case V4L2_PIX_FMT_GREY:
3629 case V4L2_PIX_FMT_Y10:
3630 case V4L2_PIX_FMT_Y12:
3631 if (stream->is_compact)
3632 mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
3633 else
3634 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
3635 break;
3636 case V4L2_PIX_FMT_SBGGR16:
3637 case V4L2_PIX_FMT_SGBRG16:
3638 case V4L2_PIX_FMT_SGRBG16:
3639 case V4L2_PIX_FMT_SRGGB16:
3640 case V4L2_PIX_FMT_Y16:
3641 mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
3642 break;
3643 default:
3644 mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
3645 break;
3646 }
3647 return mask;
3648 }
3649
rkcif_stream_start(struct rkcif_stream * stream,unsigned int mode)3650 static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
3651 {
3652 u32 val, mbus_flags, href_pol, vsync_pol,
3653 xfer_mode = 0, yc_swap = 0, inputmode = 0,
3654 mipimode = 0, workmode = 0, multi_id = 0,
3655 multi_id_en = BT656_1120_MULTI_ID_DISABLE,
3656 multi_id_mode = BT656_1120_MULTI_ID_MODE_1,
3657 multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB,
3658 bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES,
3659 bt1120_flags = 0,
3660 out_fmt_mask = 0,
3661 in_fmt_yuv_order = 0;
3662 struct rkmodule_bt656_mbus_info bt1120_info;
3663 struct rkcif_device *dev = stream->cifdev;
3664 struct rkcif_sensor_info *sensor_info;
3665 struct v4l2_mbus_config *mbus;
3666 struct rkcif_dvp_sof_subdev *sof_sd = &dev->dvp_sof_subdev;
3667 const struct cif_output_fmt *fmt;
3668 unsigned int dma_en = 0;
3669 int i = 0;
3670 u32 sav_detect = BT656_DETECT_SAV;
3671
3672 if (stream->state < RKCIF_STATE_STREAMING)
3673 stream->frame_idx = 0;
3674
3675 sensor_info = dev->active_sensor;
3676 mbus = &sensor_info->mbus;
3677
3678 if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
3679 dma_en = DVP_DMA_EN;
3680 stream->dma_en = RKCIF_DMAEN_BY_VICAP;
3681 }
3682
3683 if (sensor_info->sd && mbus->type == V4L2_MBUS_BT656) {
3684 int ret;
3685
3686 multi_id_en = BT656_1120_MULTI_ID_ENABLE;
3687
3688 ret = v4l2_subdev_call(sensor_info->sd,
3689 core, ioctl,
3690 RKMODULE_GET_BT656_MBUS_INFO,
3691 &bt1120_info);
3692 if (ret) {
3693 v4l2_warn(&dev->v4l2_dev,
3694 "waring: no muti channel info for BT.656\n");
3695 } else {
3696 bt1120_flags = bt1120_info.flags;
3697 if (bt1120_flags & RKMODULE_CAMERA_BT656_PARSE_ID_LSB)
3698 multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB;
3699 else
3700 multi_id_sel = BT656_1120_MULTI_ID_SEL_MSB;
3701
3702 if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 3)
3703 multi_id_mode = BT656_1120_MULTI_ID_MODE_4;
3704 else if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 1)
3705 multi_id_mode = BT656_1120_MULTI_ID_MODE_2;
3706 for (i = 0; i < 4; i++)
3707 multi_id |= DVP_SW_MULTI_ID(i, i, bt1120_info.id_en_bits);
3708 rkcif_write_register_or(dev, CIF_REG_DVP_MULTI_ID, multi_id);
3709 }
3710 }
3711
3712 mbus_flags = mbus->flags;
3713 if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
3714 bt1120_edge_mode = (dev->chip_id < CHIP_RK3588_CIF ?
3715 BT1120_CLOCK_DOUBLE_EDGES : BT1120_CLOCK_DOUBLE_EDGES_RK3588);
3716 rkcif_enable_dvp_clk_dual_edge(dev, true);
3717 } else {
3718 bt1120_edge_mode = dev->chip_id < CHIP_RK3588_CIF ?
3719 BT1120_CLOCK_SINGLE_EDGES : BT1120_CLOCK_SINGLE_EDGES_RK3588;
3720 rkcif_enable_dvp_clk_dual_edge(dev, false);
3721 }
3722
3723 if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3724 rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
3725 else
3726 rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
3727
3728 href_pol = (mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) ?
3729 HSY_HIGH_ACTIVE : HSY_LOW_ACTIVE;
3730 vsync_pol = (mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) ?
3731 VSY_HIGH_ACTIVE : VSY_LOW_ACTIVE;
3732
3733 if (dev->chip_id < CHIP_RK3588_CIF)
3734 inputmode = rkcif_determine_input_mode(stream);
3735 else
3736 inputmode = rkcif_determine_input_mode_rk3588(stream);
3737 if (dev->chip_id <= CHIP_RK1808_CIF) {
3738 if (inputmode == INPUT_MODE_BT1120) {
3739 if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
3740 xfer_mode = BT1120_TRANSMIT_PROGRESS;
3741 else
3742 xfer_mode = BT1120_TRANSMIT_INTERFACE;
3743 if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
3744 yc_swap = BT1120_YC_SWAP;
3745 }
3746 } else if (dev->chip_id < CHIP_RK3588_CIF) {
3747 if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
3748 if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
3749 xfer_mode = BT1120_TRANSMIT_PROGRESS;
3750 else
3751 xfer_mode = BT1120_TRANSMIT_INTERFACE;
3752 }
3753
3754 if (inputmode == INPUT_MODE_BT1120) {
3755 if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
3756 yc_swap = BT1120_YC_SWAP;
3757 }
3758 } else {
3759 if ((inputmode & INPUT_BT1120_YUV422) == INPUT_BT1120_YUV422)
3760 if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
3761 yc_swap = BT1120_YC_SWAP_RK3588;
3762 }
3763
3764 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
3765 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
3766 inputmode = INPUT_MODE_MIPI;
3767
3768 /* if cif is linked with mipi,
3769 * href pol must be set as high active,
3770 * vsyn pol must be set as low active.
3771 */
3772 href_pol = HSY_HIGH_ACTIVE;
3773 vsync_pol = VSY_LOW_ACTIVE;
3774
3775 if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_YUV)
3776 mipimode = MIPI_MODE_YUV;
3777 else if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW)
3778 mipimode = MIPI_MODE_RGB;
3779 else
3780 mipimode = MIPI_MODE_32BITS_BYPASS;
3781 }
3782
3783 if (dev->chip_id < CHIP_RK3588_CIF) {
3784 val = vsync_pol | href_pol | inputmode | mipimode
3785 | stream->cif_fmt_out->fmt_val
3786 | stream->cif_fmt_in->dvp_fmt_val
3787 | xfer_mode | yc_swap | multi_id_en
3788 | multi_id_sel | multi_id_mode | bt1120_edge_mode;
3789 if (stream->is_high_align)
3790 val |= CIF_HIGH_ALIGN;
3791 else
3792 val &= ~CIF_HIGH_ALIGN;
3793 } else {
3794 out_fmt_mask = rkcif_dvp_get_output_type_mask(stream);
3795 in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order(stream);
3796 val = vsync_pol | href_pol | inputmode
3797 | yc_swap
3798 | out_fmt_mask
3799 | in_fmt_yuv_order
3800 | multi_id_en
3801 | sav_detect
3802 | multi_id_sel | multi_id_mode | bt1120_edge_mode;
3803 if (stream->is_high_align)
3804 val |= CIF_HIGH_ALIGN_RK3588;
3805 else
3806 val &= ~CIF_HIGH_ALIGN_RK3588;
3807 }
3808 rkcif_write_register(dev, CIF_REG_DVP_FOR, val);
3809
3810 if (dev->chip_id >= CHIP_RK3588_CIF) {
3811 val = stream->pixm.plane_fmt[0].bytesperline;
3812 } else {
3813 fmt = find_output_fmt(stream, stream->pixm.pixelformat);
3814 if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
3815 fmt->csi_fmt_val == CSI_WRDDR_TYPE_RAW8)
3816 val = ALIGN(stream->pixm.width * fmt->raw_bpp / 8, 256);
3817 else
3818 val = stream->pixm.width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
3819 }
3820
3821 if (stream->crop_enable) {
3822 dev->channels[stream->id].crop_en = 1;
3823 dev->channels[stream->id].crop_st_x = stream->crop[CROP_SRC_ACT].left;
3824 dev->channels[stream->id].crop_st_y = stream->crop[CROP_SRC_ACT].top;
3825 dev->channels[stream->id].width = stream->crop[CROP_SRC_ACT].width;
3826 dev->channels[stream->id].height = stream->crop[CROP_SRC_ACT].height;
3827 } else {
3828 dev->channels[stream->id].crop_st_y = 0;
3829 dev->channels[stream->id].crop_st_x = 0;
3830 dev->channels[stream->id].width = stream->pixm.width;
3831 dev->channels[stream->id].height = stream->pixm.height;
3832 dev->channels[stream->id].crop_en = 0;
3833 }
3834
3835 rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
3836 rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
3837 dev->channels[stream->id].width |
3838 (dev->channels[stream->id].height << 16));
3839 rkcif_write_register(dev, CIF_REG_DVP_CROP,
3840 dev->channels[stream->id].crop_st_y << CIF_CROP_Y_SHIFT |
3841 dev->channels[stream->id].crop_st_x);
3842
3843 if (atomic_read(&dev->pipe.stream_cnt) <= 1)
3844 rkcif_write_register(dev, CIF_REG_DVP_FRAME_STATUS, FRAME_STAT_CLS);
3845
3846 if (dev->chip_id < CHIP_RK3588_CIF) {
3847 rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
3848 rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
3849 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
3850 DVP_DMA_END_INTSTAT(stream->id) |
3851 INTSTAT_ERR | PST_INF_FRAME_END);
3852 /* enable line int for sof */
3853 rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
3854 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
3855 } else {
3856 rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, 0x3c3ffff);
3857 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
3858 }
3859
3860 if (dma_en) {
3861 if (dev->chip_id < CHIP_RK1808_CIF)
3862 rkcif_assign_new_buffer_oneframe(stream,
3863 RKCIF_YUV_ADDR_STATE_INIT);
3864 else
3865 rkcif_assign_new_buffer_pingpong(stream,
3866 RKCIF_YUV_ADDR_STATE_INIT,
3867 stream->id);
3868 }
3869 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
3870 DVP_DMA_END_INTSTAT(stream->id) |
3871 INTSTAT_ERR | PST_INF_FRAME_END);
3872
3873 /* enable line int for sof */
3874 rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
3875 rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
3876
3877 if (dev->workmode == RKCIF_WORKMODE_ONEFRAME)
3878 workmode = MODE_ONEFRAME;
3879 else if (dev->workmode == RKCIF_WORKMODE_PINGPONG)
3880 workmode = MODE_PINGPONG;
3881 else
3882 workmode = MODE_LINELOOP;
3883
3884 if ((inputmode & INPUT_MODE_BT1120) == INPUT_MODE_BT1120) {
3885 workmode = MODE_PINGPONG;
3886 dev->workmode = RKCIF_WORKMODE_PINGPONG;
3887 }
3888
3889 if (dev->chip_id < CHIP_RK3588_CIF)
3890 rkcif_write_register(dev, CIF_REG_DVP_CTRL,
3891 AXI_BURST_16 | workmode | ENABLE_CAPTURE);
3892 else
3893 rkcif_write_register(dev, CIF_REG_DVP_CTRL,
3894 DVP_SW_WATER_LINE_25
3895 | dma_en
3896 | DVP_PRESS_EN
3897 | DVP_HURRY_EN
3898 | DVP_SW_WATER_LINE_25
3899 | DVP_SW_PRESS_VALUE(3)
3900 | DVP_SW_HURRY_VALUE(3)
3901 | ENABLE_CAPTURE);
3902
3903 atomic_set(&sof_sd->frm_sync_seq, 0);
3904 stream->state = RKCIF_STATE_STREAMING;
3905 stream->cifdev->dvp_sof_in_oneframe = 0;
3906
3907 return 0;
3908 }
3909
rkcif_attach_sync_mode(struct rkcif_hw * hw)3910 static void rkcif_attach_sync_mode(struct rkcif_hw *hw)
3911 {
3912 struct rkcif_device *dev;
3913 int i = 0;
3914 int ret = 0;
3915 int sync_type = 0;
3916 int count = 0;
3917
3918 if (hw->sync_config.is_attach)
3919 return;
3920
3921 memset(&hw->sync_config, 0, sizeof(struct rkcif_multi_sync_config));
3922 for (i = 0; i < hw->dev_num; i++) {
3923 dev = hw->cif_dev[i];
3924 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
3925 core, ioctl,
3926 RKMODULE_GET_SYNC_MODE,
3927 &sync_type);
3928 if (!ret) {
3929 if (sync_type == EXTERNAL_MASTER_MODE) {
3930 count = hw->sync_config.ext_master.count;
3931 hw->sync_config.ext_master.cif_dev[count] = dev;
3932 hw->sync_config.ext_master.count++;
3933 hw->sync_config.dev_cnt++;
3934 dev->sync_type = EXTERNAL_MASTER_MODE;
3935 } else if (sync_type == INTERNAL_MASTER_MODE) {
3936 count = hw->sync_config.int_master.count;
3937 hw->sync_config.int_master.cif_dev[count] = dev;
3938 hw->sync_config.int_master.count++;
3939 hw->sync_config.dev_cnt++;
3940 dev->sync_type = INTERNAL_MASTER_MODE;
3941 } else if (sync_type == SLAVE_MODE) {
3942 count = hw->sync_config.slave.count;
3943 hw->sync_config.slave.cif_dev[count] = dev;
3944 hw->sync_config.slave.count++;
3945 hw->sync_config.dev_cnt++;
3946 dev->sync_type = SLAVE_MODE;
3947 }
3948 }
3949 }
3950 if (hw->sync_config.int_master.count == 1) {
3951 if (hw->sync_config.ext_master.count) {
3952 hw->sync_config.mode = RKCIF_MASTER_MASTER;
3953 hw->sync_config.is_attach = true;
3954 } else if (hw->sync_config.slave.count) {
3955 hw->sync_config.mode = RKCIF_MASTER_SLAVE;
3956 hw->sync_config.is_attach = true;
3957 } else {
3958 dev_info(hw->dev,
3959 "Missing slave device, do not use sync mode\n");
3960 }
3961 if (hw->sync_config.ext_master.count &&
3962 hw->sync_config.slave.count)
3963 dev_info(hw->dev,
3964 "There are two types of slave devices, it may cause problems\n");
3965 } else {
3966 dev_info(hw->dev,
3967 "Only support one master device, master device count %d\n",
3968 hw->sync_config.int_master.count);
3969 }
3970 }
3971
rkcif_do_start_stream(struct rkcif_stream * stream,unsigned int mode)3972 int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
3973 {
3974 struct rkcif_vdev_node *node = &stream->vnode;
3975 struct rkcif_device *dev = stream->cifdev;
3976 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3977 struct rkcif_sensor_info *sensor_info = dev->active_sensor;
3978 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
3979 struct rkmodule_hdr_cfg hdr_cfg;
3980 int rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
3981 int ret;
3982
3983 v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
3984
3985 mutex_lock(&dev->stream_lock);
3986 rkcif_attach_sync_mode(dev->hw_dev);
3987 if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
3988 ret = -EBUSY;
3989 v4l2_err(v4l2_dev, "stream in busy state\n");
3990 goto destroy_buf;
3991 }
3992 if (stream->dma_en == 0)
3993 stream->fs_cnt_in_single_frame = 0;
3994 if (stream->is_line_wake_up)
3995 stream->is_line_inten = true;
3996 else
3997 stream->is_line_inten = false;
3998
3999 if (dev->active_sensor) {
4000 ret = rkcif_update_sensor_info(stream);
4001 if (ret < 0) {
4002 v4l2_err(v4l2_dev,
4003 "update sensor info failed %d\n",
4004 ret);
4005 goto out;
4006 }
4007 }
4008
4009 if (terminal_sensor->sd) {
4010 ret = v4l2_subdev_call(terminal_sensor->sd,
4011 core, ioctl,
4012 RKMODULE_GET_HDR_CFG,
4013 &hdr_cfg);
4014 if (!ret)
4015 dev->hdr = hdr_cfg;
4016 else
4017 dev->hdr.hdr_mode = NO_HDR;
4018
4019 ret = v4l2_subdev_call(terminal_sensor->sd,
4020 video, g_frame_interval, &terminal_sensor->fi);
4021 if (ret)
4022 terminal_sensor->fi.interval = (struct v4l2_fract) {1, 30};
4023
4024 ret = v4l2_subdev_call(terminal_sensor->sd,
4025 core, ioctl,
4026 RKMODULE_GET_START_STREAM_SEQ,
4027 &rkmodule_stream_seq);
4028 if (ret)
4029 rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
4030
4031 rkcif_sync_crop_info(stream);
4032 }
4033
4034 ret = rkcif_sanity_check_fmt(stream, NULL);
4035 if (ret < 0)
4036 goto destroy_buf;
4037
4038 if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) ||
4039 dev->is_use_dummybuf) &&
4040 (!dev->dummy_buf.vaddr)) {
4041 ret = rkcif_create_dummy_buf(stream);
4042 if (ret < 0) {
4043 v4l2_err(v4l2_dev, "Failed to create dummy_buf, %d\n", ret);
4044 goto destroy_buf;
4045 }
4046 }
4047
4048 if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
4049 /* enable clocks/power-domains */
4050 ret = pm_runtime_resume_and_get(dev->dev);
4051 if (ret < 0) {
4052 v4l2_err(v4l2_dev, "Failed to get runtime pm, %d\n",
4053 ret);
4054 goto destroy_buf;
4055 }
4056 ret = v4l2_pipeline_pm_get(&node->vdev.entity);
4057 if (ret < 0) {
4058 v4l2_err(v4l2_dev, "cif pipeline_pm_get fail %d\n",
4059 ret);
4060 goto destroy_buf;
4061 }
4062 ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
4063 if (ret < 0) {
4064 v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
4065 ret);
4066 goto destroy_buf;
4067 }
4068
4069 /*
4070 * start sub-devices
4071 * When use bt601, the sampling edge of cif is random,
4072 * can be rising or fallling after powering on cif.
4073 * To keep the coherence of edge, open sensor in advance.
4074 */
4075 if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL ||
4076 rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
4077 ret = dev->pipe.set_stream(&dev->pipe, true);
4078 if (ret < 0)
4079 goto runtime_put;
4080 }
4081 }
4082 if (dev->chip_id >= CHIP_RK1808_CIF) {
4083 if (dev->active_sensor &&
4084 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
4085 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
4086 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
4087 ret = rkcif_csi_stream_start(stream, mode);
4088 else
4089 ret = rkcif_stream_start(stream, mode);
4090 } else {
4091 ret = rkcif_stream_start(stream, mode);
4092 }
4093
4094 if (ret < 0)
4095 goto runtime_put;
4096
4097 if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
4098 ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
4099 if (ret < 0) {
4100 v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
4101 ret);
4102 goto pipe_stream_off;
4103 }
4104
4105 if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
4106 rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
4107 ret = dev->pipe.set_stream(&dev->pipe, true);
4108 if (ret < 0)
4109 goto stop_stream;
4110 }
4111 }
4112 if (dev->chip_id == CHIP_RV1126_CIF ||
4113 dev->chip_id == CHIP_RV1126_CIF_LITE ||
4114 dev->chip_id == CHIP_RK3568_CIF) {
4115 if (dev->hdr.hdr_mode == NO_HDR) {
4116 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING)
4117 rkcif_start_luma(&dev->luma_vdev,
4118 dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
4119 } else if (dev->hdr.hdr_mode == HDR_X2) {
4120 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
4121 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING)
4122 rkcif_start_luma(&dev->luma_vdev,
4123 dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
4124 } else if (dev->hdr.hdr_mode == HDR_X3) {
4125 if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
4126 dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
4127 dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING)
4128 rkcif_start_luma(&dev->luma_vdev,
4129 dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
4130 }
4131 }
4132 dev->reset_work_cancel = false;
4133 stream->cur_stream_mode |= mode;
4134 goto out;
4135
4136 stop_stream:
4137 rkcif_stream_stop(stream);
4138 pipe_stream_off:
4139 dev->pipe.set_stream(&dev->pipe, false);
4140 runtime_put:
4141 pm_runtime_put_sync(dev->dev);
4142 destroy_buf:
4143 if (stream->next_buf)
4144 vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
4145 VB2_BUF_STATE_QUEUED);
4146 if (stream->curr_buf)
4147 vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
4148 VB2_BUF_STATE_QUEUED);
4149 while (!list_empty(&stream->buf_head)) {
4150 struct rkcif_buffer *buf;
4151
4152 buf = list_first_entry(&stream->buf_head,
4153 struct rkcif_buffer, queue);
4154 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
4155 list_del(&buf->queue);
4156 }
4157
4158 out:
4159 mutex_unlock(&dev->stream_lock);
4160 return ret;
4161 }
4162
rkcif_start_streaming(struct vb2_queue * queue,unsigned int count)4163 static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
4164 {
4165 struct rkcif_stream *stream = queue->drv_priv;
4166 int ret = 0;
4167
4168 ret = rkcif_do_start_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
4169 return ret;
4170 }
4171
4172 static struct vb2_ops rkcif_vb2_ops = {
4173 .queue_setup = rkcif_queue_setup,
4174 .buf_queue = rkcif_buf_queue,
4175 .wait_prepare = vb2_ops_wait_prepare,
4176 .wait_finish = vb2_ops_wait_finish,
4177 .stop_streaming = rkcif_stop_streaming,
4178 .start_streaming = rkcif_start_streaming,
4179 };
4180
rkcif_init_vb2_queue(struct vb2_queue * q,struct rkcif_stream * stream,enum v4l2_buf_type buf_type)4181 static int rkcif_init_vb2_queue(struct vb2_queue *q,
4182 struct rkcif_stream *stream,
4183 enum v4l2_buf_type buf_type)
4184 {
4185 struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
4186
4187 q->type = buf_type;
4188 q->io_modes = VB2_MMAP | VB2_DMABUF;
4189 q->drv_priv = stream;
4190 q->ops = &rkcif_vb2_ops;
4191 if (hw_dev->iommu_en)
4192 q->mem_ops = &vb2_dma_sg_memops;
4193 else
4194 q->mem_ops = &vb2_dma_contig_memops;
4195 q->buf_struct_size = sizeof(struct rkcif_buffer);
4196 if (stream->cifdev->is_use_dummybuf)
4197 q->min_buffers_needed = 1;
4198 else
4199 q->min_buffers_needed = CIF_REQ_BUFS_MIN;
4200 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
4201 q->lock = &stream->vnode.vlock;
4202 q->dev = hw_dev->dev;
4203 q->allow_cache_hints = 1;
4204 q->bidirectional = 1;
4205 q->gfp_flags = GFP_DMA32;
4206 return vb2_queue_init(q);
4207 }
4208
rkcif_set_fmt(struct rkcif_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)4209 int rkcif_set_fmt(struct rkcif_stream *stream,
4210 struct v4l2_pix_format_mplane *pixm,
4211 bool try)
4212 {
4213 struct rkcif_device *dev = stream->cifdev;
4214 const struct cif_output_fmt *fmt;
4215 const struct cif_input_fmt *cif_fmt_in = NULL;
4216 struct v4l2_rect input_rect;
4217 unsigned int imagesize = 0, ex_imagesize = 0, planes;
4218 u32 xsubs = 1, ysubs = 1, i;
4219 struct rkmodule_hdr_cfg hdr_cfg;
4220 struct rkcif_extend_info *extend_line = &stream->extend_line;
4221 int ret;
4222
4223 for (i = 0; i < RKCIF_MAX_PLANE; i++)
4224 memset(&pixm->plane_fmt[i], 0, sizeof(struct v4l2_plane_pix_format));
4225
4226 fmt = find_output_fmt(stream, pixm->pixelformat);
4227 if (!fmt)
4228 fmt = &out_fmts[0];
4229
4230 input_rect.width = RKCIF_DEFAULT_WIDTH;
4231 input_rect.height = RKCIF_DEFAULT_HEIGHT;
4232
4233 if (dev->terminal_sensor.sd) {
4234 cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
4235 &input_rect, stream->id,
4236 &dev->channels[stream->id]);
4237 stream->cif_fmt_in = cif_fmt_in;
4238 } else {
4239 v4l2_err(&stream->cifdev->v4l2_dev,
4240 "terminal subdev does not exist\n");
4241 return -EINVAL;
4242 }
4243
4244 if (dev->terminal_sensor.sd) {
4245 ret = v4l2_subdev_call(dev->terminal_sensor.sd,
4246 core, ioctl,
4247 RKMODULE_GET_HDR_CFG,
4248 &hdr_cfg);
4249 if (!ret)
4250 dev->hdr = hdr_cfg;
4251 else
4252 dev->hdr.hdr_mode = NO_HDR;
4253
4254 dev->terminal_sensor.raw_rect = input_rect;
4255 }
4256
4257 /* CIF has not scale function,
4258 * the size should not be larger than input
4259 */
4260 pixm->width = clamp_t(u32, pixm->width,
4261 CIF_MIN_WIDTH, input_rect.width);
4262 pixm->height = clamp_t(u32, pixm->height,
4263 CIF_MIN_HEIGHT, input_rect.height);
4264 pixm->num_planes = fmt->mplanes;
4265 pixm->field = V4L2_FIELD_NONE;
4266 pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
4267
4268 rkcif_sync_crop_info(stream);
4269 /* calculate plane size and image size */
4270 fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
4271
4272 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
4273
4274 if (cif_fmt_in && (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 ||
4275 cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
4276 stream->crop_enable = false;
4277
4278 for (i = 0; i < planes; i++) {
4279 struct v4l2_plane_pix_format *plane_fmt;
4280 int width, height, bpl, size, bpp, ex_size;
4281
4282 if (i == 0) {
4283 if (stream->crop_enable) {
4284 width = stream->crop[CROP_SRC_ACT].width;
4285 height = stream->crop[CROP_SRC_ACT].height;
4286 } else {
4287 width = pixm->width;
4288 height = pixm->height;
4289 }
4290 } else {
4291 if (stream->crop_enable) {
4292 width = stream->crop[CROP_SRC_ACT].width / xsubs;
4293 height = stream->crop[CROP_SRC_ACT].height / ysubs;
4294 } else {
4295 width = pixm->width / xsubs;
4296 height = pixm->height / ysubs;
4297 }
4298 }
4299
4300 extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
4301
4302 /* compact mode need bytesperline 4bytes align,
4303 * align 8 to bring into correspondence with virtual width.
4304 * to optimize reading and writing of ddr, aliged with 256.
4305 */
4306 if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
4307 (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 ||
4308 stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
4309 stream->is_compact = false;
4310 }
4311
4312 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
4313 (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
4314 dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY ||
4315 dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
4316 bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
4317 } else {
4318 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
4319 dev->chip_id >= CHIP_RK3588_CIF) {
4320 bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
4321 } else {
4322 bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
4323 bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
4324 }
4325 }
4326 size = bpl * height;
4327 imagesize += size;
4328 ex_size = bpl * extend_line->pixm.height;
4329 ex_imagesize += ex_size;
4330
4331 if (fmt->mplanes > i) {
4332 /* Set bpl and size for each mplane */
4333 plane_fmt = pixm->plane_fmt + i;
4334 plane_fmt->bytesperline = bpl;
4335 plane_fmt->sizeimage = size;
4336
4337 plane_fmt = extend_line->pixm.plane_fmt + i;
4338 plane_fmt->bytesperline = bpl;
4339 plane_fmt->sizeimage = ex_size;
4340 }
4341 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
4342 "C-Plane %i size: %d, Total imagesize: %d\n",
4343 i, size, imagesize);
4344 }
4345
4346 /* convert to non-MPLANE format.
4347 * It's important since we want to unify non-MPLANE
4348 * and MPLANE.
4349 */
4350 if (fmt->mplanes == 1) {
4351 pixm->plane_fmt[0].sizeimage = imagesize;
4352 extend_line->pixm.plane_fmt[0].sizeimage = ex_imagesize;
4353 }
4354
4355 if (!try) {
4356 stream->cif_fmt_out = fmt;
4357 stream->pixm = *pixm;
4358
4359 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
4360 "%s: req(%d, %d) out(%d, %d)\n", __func__,
4361 pixm->width, pixm->height,
4362 stream->pixm.width, stream->pixm.height);
4363 }
4364 return 0;
4365 }
4366
rkcif_stream_init(struct rkcif_device * dev,u32 id)4367 void rkcif_stream_init(struct rkcif_device *dev, u32 id)
4368 {
4369 struct rkcif_stream *stream = &dev->stream[id];
4370 struct v4l2_pix_format_mplane pixm;
4371 int i;
4372
4373 memset(stream, 0, sizeof(*stream));
4374 memset(&pixm, 0, sizeof(pixm));
4375 stream->id = id;
4376 stream->cifdev = dev;
4377
4378 INIT_LIST_HEAD(&stream->buf_head);
4379 INIT_LIST_HEAD(&stream->rx_buf_head);
4380 spin_lock_init(&stream->vbq_lock);
4381 spin_lock_init(&stream->fps_lock);
4382 stream->state = RKCIF_STATE_READY;
4383 init_waitqueue_head(&stream->wq_stopped);
4384
4385 /* Set default format */
4386 pixm.pixelformat = V4L2_PIX_FMT_NV12;
4387 pixm.width = RKCIF_DEFAULT_WIDTH;
4388 pixm.height = RKCIF_DEFAULT_HEIGHT;
4389 rkcif_set_fmt(stream, &pixm, false);
4390
4391 for (i = 0; i < CROP_SRC_MAX; i++) {
4392 stream->crop[i].left = 0;
4393 stream->crop[i].top = 0;
4394 stream->crop[i].width = RKCIF_DEFAULT_WIDTH;
4395 stream->crop[i].height = RKCIF_DEFAULT_HEIGHT;
4396 }
4397
4398 stream->crop_enable = false;
4399 stream->crop_dyn_en = false;
4400 stream->crop_mask = 0x0;
4401
4402 if (dev->inf_id == RKCIF_DVP) {
4403 if (dev->chip_id <= CHIP_RK3568_CIF)
4404 stream->is_compact = false;
4405 else
4406 stream->is_compact = true;
4407 } else {
4408 if (dev->chip_id >= CHIP_RV1126_CIF)
4409 stream->is_compact = true;
4410 else
4411 stream->is_compact = false;
4412 }
4413
4414 stream->is_high_align = false;
4415
4416 if (dev->chip_id == CHIP_RV1126_CIF ||
4417 dev->chip_id == CHIP_RV1126_CIF_LITE)
4418 stream->extend_line.is_extended = true;
4419 else
4420 stream->extend_line.is_extended = false;
4421
4422 stream->is_dvp_yuv_addr_init = false;
4423 stream->is_fs_fe_not_paired = false;
4424 stream->fs_cnt_in_single_frame = 0;
4425 if (dev->wait_line) {
4426 dev->wait_line_cache = dev->wait_line;
4427 dev->wait_line_bak = dev->wait_line;
4428 stream->is_line_wake_up = true;
4429 } else {
4430 stream->is_line_wake_up = false;
4431 dev->wait_line_cache = 0;
4432 dev->wait_line_bak = 0;
4433 }
4434 stream->cur_stream_mode = 0;
4435 stream->dma_en = 0;
4436 stream->to_en_dma = 0;
4437 stream->to_stop_dma = 0;
4438 stream->to_en_scale = false;
4439
4440 }
4441
rkcif_fh_open(struct file * filp)4442 static int rkcif_fh_open(struct file *filp)
4443 {
4444 struct video_device *vdev = video_devdata(filp);
4445 struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
4446 struct rkcif_stream *stream = to_rkcif_stream(vnode);
4447 struct rkcif_device *cifdev = stream->cifdev;
4448 int ret;
4449
4450 ret = rkcif_attach_hw(cifdev);
4451 if (ret)
4452 return ret;
4453
4454 /* Make sure active sensor is valid before .set_fmt() */
4455 ret = rkcif_update_sensor_info(stream);
4456 if (ret < 0) {
4457 v4l2_err(vdev,
4458 "update sensor info failed %d\n",
4459 ret);
4460
4461 return ret;
4462 }
4463
4464 ret = pm_runtime_resume_and_get(cifdev->dev);
4465 if (ret < 0) {
4466 v4l2_err(vdev, "Failed to get runtime pm, %d\n",
4467 ret);
4468 return ret;
4469 }
4470 /*
4471 * Soft reset via CRU.
4472 * Because CRU would reset iommu too, so there's not chance
4473 * to reset cif once we hold buffers after buf queued
4474 */
4475 if (cifdev->chip_id == CHIP_RK1808_CIF ||
4476 cifdev->chip_id == CHIP_RV1126_CIF ||
4477 cifdev->chip_id == CHIP_RV1126_CIF_LITE ||
4478 cifdev->chip_id == CHIP_RK3568_CIF ||
4479 cifdev->chip_id == CHIP_RK3588_CIF) {
4480 mutex_lock(&cifdev->stream_lock);
4481 if (!atomic_read(&cifdev->fh_cnt))
4482 rkcif_soft_reset(cifdev, true);
4483 atomic_inc(&cifdev->fh_cnt);
4484 mutex_unlock(&cifdev->stream_lock);
4485 } else {
4486 rkcif_soft_reset(cifdev, true);
4487 }
4488
4489 ret = v4l2_fh_open(filp);
4490 if (!ret) {
4491 ret = v4l2_pipeline_pm_get(&vnode->vdev.entity);
4492 if (ret < 0)
4493 vb2_fop_release(filp);
4494 }
4495
4496 return ret;
4497 }
4498
rkcif_fh_release(struct file * filp)4499 static int rkcif_fh_release(struct file *filp)
4500 {
4501 struct video_device *vdev = video_devdata(filp);
4502 struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
4503 struct rkcif_stream *stream = to_rkcif_stream(vnode);
4504 struct rkcif_device *cifdev = stream->cifdev;
4505 int ret = 0;
4506
4507 ret = vb2_fop_release(filp);
4508 if (!ret)
4509 v4l2_pipeline_pm_put(&vnode->vdev.entity);
4510
4511 mutex_lock(&cifdev->stream_lock);
4512 if (!atomic_dec_return(&cifdev->fh_cnt))
4513 rkcif_soft_reset(cifdev, true);
4514 else if (atomic_read(&cifdev->fh_cnt) < 0)
4515 atomic_set(&cifdev->fh_cnt, 0);
4516 mutex_unlock(&cifdev->stream_lock);
4517
4518 pm_runtime_put_sync(cifdev->dev);
4519 return ret;
4520 }
4521
4522 static const struct v4l2_file_operations rkcif_fops = {
4523 .open = rkcif_fh_open,
4524 .release = rkcif_fh_release,
4525 .unlocked_ioctl = video_ioctl2,
4526 .poll = vb2_fop_poll,
4527 .mmap = vb2_fop_mmap,
4528 };
4529
rkcif_enum_input(struct file * file,void * priv,struct v4l2_input * input)4530 static int rkcif_enum_input(struct file *file, void *priv,
4531 struct v4l2_input *input)
4532 {
4533 if (input->index > 0)
4534 return -EINVAL;
4535
4536 input->type = V4L2_INPUT_TYPE_CAMERA;
4537 strlcpy(input->name, "Camera", sizeof(input->name));
4538
4539 return 0;
4540 }
4541
rkcif_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)4542 static int rkcif_try_fmt_vid_cap_mplane(struct file *file, void *fh,
4543 struct v4l2_format *f)
4544 {
4545 struct rkcif_stream *stream = video_drvdata(file);
4546 int ret = 0;
4547
4548 ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
4549
4550 return ret;
4551 }
4552
rkcif_enum_framesizes(struct file * file,void * prov,struct v4l2_frmsizeenum * fsize)4553 static int rkcif_enum_framesizes(struct file *file, void *prov,
4554 struct v4l2_frmsizeenum *fsize)
4555 {
4556 struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
4557 struct rkcif_stream *stream = video_drvdata(file);
4558 struct rkcif_device *dev = stream->cifdev;
4559 struct v4l2_rect input_rect;
4560 struct csi_channel_info csi_info;
4561
4562 if (fsize->index != 0)
4563 return -EINVAL;
4564
4565 if (!find_output_fmt(stream, fsize->pixel_format))
4566 return -EINVAL;
4567
4568 input_rect.width = RKCIF_DEFAULT_WIDTH;
4569 input_rect.height = RKCIF_DEFAULT_HEIGHT;
4570
4571 if (dev->terminal_sensor.sd)
4572 get_input_fmt(dev->terminal_sensor.sd,
4573 &input_rect, stream->id,
4574 &csi_info);
4575
4576 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
4577 s->min_width = CIF_MIN_WIDTH;
4578 s->min_height = CIF_MIN_HEIGHT;
4579 s->max_width = input_rect.width;
4580 s->max_height = input_rect.height;
4581 s->step_width = OUTPUT_STEP_WISE;
4582 s->step_height = OUTPUT_STEP_WISE;
4583
4584 return 0;
4585 }
4586
rkcif_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)4587 static int rkcif_enum_frameintervals(struct file *file, void *fh,
4588 struct v4l2_frmivalenum *fival)
4589 {
4590 struct rkcif_stream *stream = video_drvdata(file);
4591 struct rkcif_device *dev = stream->cifdev;
4592 struct rkcif_sensor_info *sensor = dev->active_sensor;
4593 struct v4l2_subdev_frame_interval fi;
4594 int ret;
4595
4596 if (fival->index != 0)
4597 return -EINVAL;
4598
4599 if (!sensor || !sensor->sd) {
4600 /* TODO: active_sensor is NULL if using DMARX path */
4601 v4l2_err(&dev->v4l2_dev, "%s Not active sensor\n", __func__);
4602 return -ENODEV;
4603 }
4604
4605 ret = v4l2_subdev_call(sensor->sd, video, g_frame_interval, &fi);
4606 if (ret && ret != -ENOIOCTLCMD) {
4607 return ret;
4608 } else if (ret == -ENOIOCTLCMD) {
4609 /* Set a default value for sensors not implements ioctl */
4610 fi.interval.numerator = 1;
4611 fi.interval.denominator = 30;
4612 }
4613
4614 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
4615 fival->stepwise.step.numerator = 1;
4616 fival->stepwise.step.denominator = 1;
4617 fival->stepwise.max.numerator = 1;
4618 fival->stepwise.max.denominator = 1;
4619 fival->stepwise.min.numerator = fi.interval.numerator;
4620 fival->stepwise.min.denominator = fi.interval.denominator;
4621
4622 return 0;
4623 }
4624
rkcif_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)4625 static int rkcif_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
4626 struct v4l2_fmtdesc *f)
4627 {
4628 const struct cif_output_fmt *fmt = NULL;
4629
4630 if (f->index >= ARRAY_SIZE(out_fmts))
4631 return -EINVAL;
4632
4633 fmt = &out_fmts[f->index];
4634 f->pixelformat = fmt->fourcc;
4635
4636 switch (f->pixelformat) {
4637 case V4l2_PIX_FMT_EBD8:
4638 strscpy(f->description,
4639 "Embedded data 8-bit",
4640 sizeof(f->description));
4641 break;
4642 case V4l2_PIX_FMT_SPD16:
4643 strscpy(f->description,
4644 "Shield pix data 16-bit",
4645 sizeof(f->description));
4646 break;
4647 default:
4648 break;
4649 }
4650 return 0;
4651 }
4652
rkcif_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)4653 static int rkcif_s_fmt_vid_cap_mplane(struct file *file,
4654 void *priv, struct v4l2_format *f)
4655 {
4656 struct rkcif_stream *stream = video_drvdata(file);
4657 struct rkcif_device *dev = stream->cifdev;
4658 int ret = 0;
4659
4660 if (vb2_is_busy(&stream->vnode.buf_queue)) {
4661 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
4662 return -EBUSY;
4663 }
4664
4665 ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
4666
4667 return ret;
4668 }
4669
rkcif_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)4670 static int rkcif_g_fmt_vid_cap_mplane(struct file *file, void *fh,
4671 struct v4l2_format *f)
4672 {
4673 struct rkcif_stream *stream = video_drvdata(file);
4674
4675 f->fmt.pix_mp = stream->pixm;
4676
4677 return 0;
4678 }
4679
rkcif_querycap(struct file * file,void * priv,struct v4l2_capability * cap)4680 static int rkcif_querycap(struct file *file, void *priv,
4681 struct v4l2_capability *cap)
4682 {
4683 struct rkcif_stream *stream = video_drvdata(file);
4684 struct device *dev = stream->cifdev->dev;
4685
4686 strlcpy(cap->driver, dev->driver->name, sizeof(cap->driver));
4687 strlcpy(cap->card, dev->driver->name, sizeof(cap->card));
4688 snprintf(cap->bus_info, sizeof(cap->bus_info),
4689 "platform:%s", dev_name(dev));
4690
4691 return 0;
4692 }
4693
rkcif_cropcap(struct file * file,void * fh,struct v4l2_cropcap * cap)4694 static __maybe_unused int rkcif_cropcap(struct file *file, void *fh,
4695 struct v4l2_cropcap *cap)
4696 {
4697 struct rkcif_stream *stream = video_drvdata(file);
4698 struct rkcif_device *dev = stream->cifdev;
4699 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
4700 int ret = 0;
4701
4702 if (stream->crop_mask & CROP_SRC_SENSOR) {
4703 cap->bounds.left = stream->crop[CROP_SRC_SENSOR].left;
4704 cap->bounds.top = stream->crop[CROP_SRC_SENSOR].top;
4705 cap->bounds.width = stream->crop[CROP_SRC_SENSOR].width;
4706 cap->bounds.height = stream->crop[CROP_SRC_SENSOR].height;
4707 } else {
4708 cap->bounds.left = raw_rect->left;
4709 cap->bounds.top = raw_rect->top;
4710 cap->bounds.width = raw_rect->width;
4711 cap->bounds.height = raw_rect->height;
4712 }
4713
4714 cap->defrect = cap->bounds;
4715 cap->pixelaspect.numerator = 1;
4716 cap->pixelaspect.denominator = 1;
4717
4718 return ret;
4719 }
4720
rkcif_s_crop(struct file * file,void * fh,const struct v4l2_crop * a)4721 static __maybe_unused int rkcif_s_crop(struct file *file, void *fh, const struct v4l2_crop *a)
4722 {
4723 struct rkcif_stream *stream = video_drvdata(file);
4724 struct rkcif_device *dev = stream->cifdev;
4725 const struct v4l2_rect *rect = &a->c;
4726 struct v4l2_rect sensor_crop;
4727 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
4728 int ret;
4729
4730 ret = rkcif_sanity_check_fmt(stream, rect);
4731 if (ret) {
4732 v4l2_err(&dev->v4l2_dev, "set crop failed\n");
4733 return ret;
4734 }
4735
4736 if (stream->crop_mask & CROP_SRC_SENSOR) {
4737 sensor_crop = stream->crop[CROP_SRC_SENSOR];
4738 if (rect->left + rect->width > sensor_crop.width ||
4739 rect->top + rect->height > sensor_crop.height) {
4740 v4l2_err(&dev->v4l2_dev,
4741 "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
4742 sensor_crop.left, sensor_crop.top, sensor_crop.width, sensor_crop.height);
4743 return -EINVAL;
4744 }
4745 } else {
4746 if (rect->left + rect->width > raw_rect->width ||
4747 rect->top + rect->height > raw_rect->height) {
4748 v4l2_err(&dev->v4l2_dev,
4749 "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
4750 raw_rect->left, raw_rect->top, raw_rect->width, raw_rect->height);
4751 return -EINVAL;
4752 }
4753 }
4754
4755 stream->crop[CROP_SRC_USR] = *rect;
4756 stream->crop_enable = true;
4757 stream->crop_mask |= CROP_SRC_USR_MASK;
4758 stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
4759 if (stream->crop_mask & CROP_SRC_SENSOR) {
4760 stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
4761 stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
4762 }
4763
4764 if (stream->state == RKCIF_STATE_STREAMING) {
4765 stream->crop_dyn_en = true;
4766
4767 v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_CROP(%ux%u@%u:%u) type: %d\n",
4768 rect->width, rect->height, rect->left, rect->top, a->type);
4769 } else {
4770 v4l2_info(&dev->v4l2_dev, "static crop, S_CROP(%ux%u@%u:%u) type: %d\n",
4771 rect->width, rect->height, rect->left, rect->top, a->type);
4772 }
4773
4774 return ret;
4775 }
4776
rkcif_g_crop(struct file * file,void * fh,struct v4l2_crop * a)4777 static __maybe_unused int rkcif_g_crop(struct file *file, void *fh, struct v4l2_crop *a)
4778 {
4779 struct rkcif_stream *stream = video_drvdata(file);
4780
4781 a->c = stream->crop[CROP_SRC_ACT];
4782
4783 return 0;
4784 }
4785
rkcif_s_selection(struct file * file,void * fh,struct v4l2_selection * s)4786 static int rkcif_s_selection(struct file *file, void *fh,
4787 struct v4l2_selection *s)
4788 {
4789 struct rkcif_stream *stream = video_drvdata(file);
4790 struct rkcif_device *dev = stream->cifdev;
4791 struct v4l2_subdev *sensor_sd;
4792 struct v4l2_subdev_selection sd_sel;
4793 u16 pad = 0;
4794 int ret = 0;
4795
4796 if (!s) {
4797 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "sel is null\n");
4798 goto err;
4799 }
4800
4801 sensor_sd = get_remote_sensor(stream, &pad);
4802
4803 sd_sel.r = s->r;
4804 sd_sel.pad = pad;
4805 sd_sel.target = s->target;
4806 sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
4807
4808 ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
4809 if (!ret) {
4810 s->r = sd_sel.r;
4811 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
4812 __func__, pad, sd_sel.which, sd_sel.target);
4813 }
4814
4815 return ret;
4816
4817 err:
4818 return -EINVAL;
4819 }
4820
rkcif_g_selection(struct file * file,void * fh,struct v4l2_selection * s)4821 static int rkcif_g_selection(struct file *file, void *fh,
4822 struct v4l2_selection *s)
4823 {
4824 struct rkcif_stream *stream = video_drvdata(file);
4825 struct rkcif_device *dev = stream->cifdev;
4826 struct v4l2_subdev *sensor_sd;
4827 struct v4l2_subdev_selection sd_sel;
4828 u16 pad = 0;
4829 int ret = 0;
4830
4831 if (!s) {
4832 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "sel is null\n");
4833 goto err;
4834 }
4835
4836 if (s->target == V4L2_SEL_TGT_CROP_BOUNDS) {
4837 sensor_sd = get_remote_sensor(stream, &pad);
4838
4839 sd_sel.pad = pad;
4840 sd_sel.target = s->target;
4841 sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
4842
4843 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s(line:%d): sd:%s pad:%d, which:%d, target:%d\n",
4844 __func__, __LINE__, sensor_sd->name, pad, sd_sel.which, sd_sel.target);
4845
4846 ret = v4l2_subdev_call(sensor_sd, pad, get_selection, NULL, &sd_sel);
4847 if (!ret) {
4848 s->r = sd_sel.r;
4849 } else {
4850 s->r.left = 0;
4851 s->r.top = 0;
4852 s->r.width = stream->pixm.width;
4853 s->r.height = stream->pixm.height;
4854 }
4855 }
4856
4857 if (s->target == V4L2_SEL_TGT_CROP) {
4858 if (stream->crop_mask & (CROP_SRC_USR_MASK | CROP_SRC_SENSOR_MASK)) {
4859 s->r = stream->crop[CROP_SRC_ACT];
4860 } else {
4861 s->r.left = 0;
4862 s->r.top = 0;
4863 s->r.width = stream->pixm.width;
4864 s->r.height = stream->pixm.height;
4865 }
4866 }
4867
4868 return ret;
4869 err:
4870 return -EINVAL;
4871 }
4872
rkcif_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)4873 static long rkcif_ioctl_default(struct file *file, void *fh,
4874 bool valid_prio, unsigned int cmd, void *arg)
4875 {
4876 struct rkcif_stream *stream = video_drvdata(file);
4877 struct rkcif_device *dev = stream->cifdev;
4878 const struct cif_input_fmt *in_fmt;
4879 struct v4l2_rect rect;
4880 struct csi_channel_info csi_info;
4881
4882 switch (cmd) {
4883 case RKCIF_CMD_GET_CSI_MEMORY_MODE:
4884 if (stream->is_compact) {
4885 *(int *)arg = CSI_LVDS_MEM_COMPACT;
4886 } else {
4887 if (stream->is_high_align)
4888 *(int *)arg = CSI_LVDS_MEM_WORD_HIGH_ALIGN;
4889 else
4890 *(int *)arg = CSI_LVDS_MEM_WORD_LOW_ALIGN;
4891 }
4892 break;
4893 case RKCIF_CMD_SET_CSI_MEMORY_MODE:
4894 if (dev->terminal_sensor.sd) {
4895 in_fmt = get_input_fmt(dev->terminal_sensor.sd,
4896 &rect, 0, &csi_info);
4897 if (in_fmt == NULL) {
4898 v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
4899 return -EINVAL;
4900 }
4901 } else {
4902 v4l2_err(&dev->v4l2_dev, "can't get sensor device\n");
4903 return -EINVAL;
4904 }
4905 if (*(int *)arg == CSI_LVDS_MEM_COMPACT) {
4906 if (((dev->inf_id == RKCIF_DVP && dev->chip_id <= CHIP_RK3568_CIF) ||
4907 (dev->inf_id == RKCIF_MIPI_LVDS && dev->chip_id < CHIP_RV1126_CIF)) &&
4908 in_fmt->csi_fmt_val != CSI_WRDDR_TYPE_RAW8) {
4909 v4l2_err(&dev->v4l2_dev, "device not support compact\n");
4910 return -EINVAL;
4911 }
4912 stream->is_compact = true;
4913 stream->is_high_align = false;
4914 } else if (*(int *)arg == CSI_LVDS_MEM_WORD_HIGH_ALIGN) {
4915 stream->is_compact = false;
4916 stream->is_high_align = true;
4917 } else {
4918 stream->is_compact = false;
4919 stream->is_high_align = false;
4920 }
4921 break;
4922 default:
4923 return -EINVAL;
4924 }
4925
4926 return 0;
4927 }
4928
4929 static const struct v4l2_ioctl_ops rkcif_v4l2_ioctl_ops = {
4930 .vidioc_reqbufs = vb2_ioctl_reqbufs,
4931 .vidioc_querybuf = vb2_ioctl_querybuf,
4932 .vidioc_create_bufs = vb2_ioctl_create_bufs,
4933 .vidioc_qbuf = vb2_ioctl_qbuf,
4934 .vidioc_expbuf = vb2_ioctl_expbuf,
4935 .vidioc_dqbuf = vb2_ioctl_dqbuf,
4936 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
4937 .vidioc_streamon = vb2_ioctl_streamon,
4938 .vidioc_streamoff = vb2_ioctl_streamoff,
4939 .vidioc_enum_input = rkcif_enum_input,
4940 .vidioc_try_fmt_vid_cap_mplane = rkcif_try_fmt_vid_cap_mplane,
4941 .vidioc_enum_fmt_vid_cap = rkcif_enum_fmt_vid_cap_mplane,
4942 .vidioc_s_fmt_vid_cap_mplane = rkcif_s_fmt_vid_cap_mplane,
4943 .vidioc_g_fmt_vid_cap_mplane = rkcif_g_fmt_vid_cap_mplane,
4944 .vidioc_querycap = rkcif_querycap,
4945 .vidioc_s_selection = rkcif_s_selection,
4946 .vidioc_g_selection = rkcif_g_selection,
4947 .vidioc_enum_frameintervals = rkcif_enum_frameintervals,
4948 .vidioc_enum_framesizes = rkcif_enum_framesizes,
4949 .vidioc_default = rkcif_ioctl_default,
4950 };
4951
rkcif_unregister_stream_vdev(struct rkcif_stream * stream)4952 static void rkcif_unregister_stream_vdev(struct rkcif_stream *stream)
4953 {
4954 media_entity_cleanup(&stream->vnode.vdev.entity);
4955 video_unregister_device(&stream->vnode.vdev);
4956 }
4957
rkcif_register_stream_vdev(struct rkcif_stream * stream,bool is_multi_input)4958 static int rkcif_register_stream_vdev(struct rkcif_stream *stream,
4959 bool is_multi_input)
4960 {
4961 struct rkcif_device *dev = stream->cifdev;
4962 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
4963 struct video_device *vdev = &stream->vnode.vdev;
4964 struct rkcif_vdev_node *node;
4965 int ret = 0;
4966 char *vdev_name;
4967
4968 if (dev->chip_id < CHIP_RV1126_CIF) {
4969 if (is_multi_input) {
4970 switch (stream->id) {
4971 case RKCIF_STREAM_MIPI_ID0:
4972 vdev_name = CIF_MIPI_ID0_VDEV_NAME;
4973 break;
4974 case RKCIF_STREAM_MIPI_ID1:
4975 vdev_name = CIF_MIPI_ID1_VDEV_NAME;
4976 break;
4977 case RKCIF_STREAM_MIPI_ID2:
4978 vdev_name = CIF_MIPI_ID2_VDEV_NAME;
4979 break;
4980 case RKCIF_STREAM_MIPI_ID3:
4981 vdev_name = CIF_MIPI_ID3_VDEV_NAME;
4982 break;
4983 case RKCIF_STREAM_DVP:
4984 vdev_name = CIF_DVP_VDEV_NAME;
4985 break;
4986 default:
4987 v4l2_err(v4l2_dev, "Invalid stream\n");
4988 goto unreg;
4989 }
4990 } else {
4991 vdev_name = CIF_VIDEODEVICE_NAME;
4992 }
4993 } else {
4994 if (dev->inf_id == RKCIF_MIPI_LVDS) {
4995 switch (stream->id) {
4996 case RKCIF_STREAM_MIPI_ID0:
4997 vdev_name = CIF_MIPI_ID0_VDEV_NAME;
4998 break;
4999 case RKCIF_STREAM_MIPI_ID1:
5000 vdev_name = CIF_MIPI_ID1_VDEV_NAME;
5001 break;
5002 case RKCIF_STREAM_MIPI_ID2:
5003 vdev_name = CIF_MIPI_ID2_VDEV_NAME;
5004 break;
5005 case RKCIF_STREAM_MIPI_ID3:
5006 vdev_name = CIF_MIPI_ID3_VDEV_NAME;
5007 break;
5008 default:
5009 v4l2_err(v4l2_dev, "Invalid stream\n");
5010 goto unreg;
5011 }
5012 } else {
5013 switch (stream->id) {
5014 case RKCIF_STREAM_MIPI_ID0:
5015 vdev_name = CIF_DVP_ID0_VDEV_NAME;
5016 break;
5017 case RKCIF_STREAM_MIPI_ID1:
5018 vdev_name = CIF_DVP_ID1_VDEV_NAME;
5019 break;
5020 case RKCIF_STREAM_MIPI_ID2:
5021 vdev_name = CIF_DVP_ID2_VDEV_NAME;
5022 break;
5023 case RKCIF_STREAM_MIPI_ID3:
5024 vdev_name = CIF_DVP_ID3_VDEV_NAME;
5025 break;
5026 default:
5027 v4l2_err(v4l2_dev, "Invalid stream\n");
5028 goto unreg;
5029 }
5030 }
5031 }
5032
5033 strlcpy(vdev->name, vdev_name, sizeof(vdev->name));
5034 node = vdev_to_node(vdev);
5035 mutex_init(&node->vlock);
5036
5037 vdev->ioctl_ops = &rkcif_v4l2_ioctl_ops;
5038 vdev->release = video_device_release_empty;
5039 vdev->fops = &rkcif_fops;
5040 vdev->minor = -1;
5041 vdev->v4l2_dev = v4l2_dev;
5042 vdev->lock = &node->vlock;
5043 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
5044 V4L2_CAP_STREAMING;
5045 video_set_drvdata(vdev, stream);
5046 vdev->vfl_dir = VFL_DIR_RX;
5047 node->pad.flags = MEDIA_PAD_FL_SINK;
5048
5049 rkcif_init_vb2_queue(&node->buf_queue, stream,
5050 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
5051 vdev->queue = &node->buf_queue;
5052
5053 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
5054 if (ret < 0) {
5055 v4l2_err(v4l2_dev,
5056 "video_register_device failed with error %d\n", ret);
5057 return ret;
5058 }
5059
5060 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
5061 if (ret < 0)
5062 goto unreg;
5063
5064 return 0;
5065 unreg:
5066 video_unregister_device(vdev);
5067 return ret;
5068 }
5069
rkcif_unregister_stream_vdevs(struct rkcif_device * dev,int stream_num)5070 void rkcif_unregister_stream_vdevs(struct rkcif_device *dev,
5071 int stream_num)
5072 {
5073 struct rkcif_stream *stream;
5074 int i;
5075
5076 for (i = 0; i < stream_num; i++) {
5077 stream = &dev->stream[i];
5078 rkcif_unregister_stream_vdev(stream);
5079 }
5080 }
5081
rkcif_register_stream_vdevs(struct rkcif_device * dev,int stream_num,bool is_multi_input)5082 int rkcif_register_stream_vdevs(struct rkcif_device *dev,
5083 int stream_num,
5084 bool is_multi_input)
5085 {
5086 struct rkcif_stream *stream;
5087 int i, j, ret;
5088
5089 for (i = 0; i < stream_num; i++) {
5090 stream = &dev->stream[i];
5091 stream->cifdev = dev;
5092 ret = rkcif_register_stream_vdev(stream, is_multi_input);
5093 if (ret < 0)
5094 goto err;
5095 }
5096
5097 return 0;
5098 err:
5099 for (j = 0; j < i; j++) {
5100 stream = &dev->stream[j];
5101 rkcif_unregister_stream_vdev(stream);
5102 }
5103
5104 return ret;
5105 }
5106
get_lvds_remote_sensor(struct v4l2_subdev * sd)5107 static struct v4l2_subdev *get_lvds_remote_sensor(struct v4l2_subdev *sd)
5108 {
5109 struct media_pad *local, *remote;
5110 struct media_entity *sensor_me;
5111
5112 local = &sd->entity.pads[RKCIF_LVDS_PAD_SINK];
5113 remote = media_entity_remote_pad(local);
5114 if (!remote) {
5115 v4l2_warn(sd, "No link between dphy and sensor with lvds\n");
5116 return NULL;
5117 }
5118
5119 sensor_me = media_entity_remote_pad(local)->entity;
5120 return media_entity_to_v4l2_subdev(sensor_me);
5121 }
5122
rkcif_lvds_subdev_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)5123 static int rkcif_lvds_subdev_link_setup(struct media_entity *entity,
5124 const struct media_pad *local,
5125 const struct media_pad *remote,
5126 u32 flags)
5127 {
5128 return 0;
5129 }
5130
rkcif_lvds_sd_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)5131 static int rkcif_lvds_sd_set_fmt(struct v4l2_subdev *sd,
5132 struct v4l2_subdev_pad_config *cfg,
5133 struct v4l2_subdev_format *fmt)
5134 {
5135 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
5136
5137 /*
5138 * Do not allow format changes and just relay whatever
5139 * set currently in the sensor.
5140 */
5141 return v4l2_subdev_call(sensor, pad, get_fmt, NULL, fmt);
5142 }
5143
rkcif_lvds_sd_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)5144 static int rkcif_lvds_sd_get_fmt(struct v4l2_subdev *sd,
5145 struct v4l2_subdev_pad_config *cfg,
5146 struct v4l2_subdev_format *fmt)
5147 {
5148 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
5149 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
5150 int ret;
5151
5152 /*
5153 * Do not allow format changes and just relay whatever
5154 * set currently in the sensor.
5155 */
5156 ret = v4l2_subdev_call(sensor, pad, get_fmt, NULL, fmt);
5157 if (!ret)
5158 subdev->in_fmt = fmt->format;
5159
5160 return ret;
5161 }
5162
rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev * subdev,struct v4l2_subdev_pad_config * cfg,enum v4l2_subdev_format_whence which)5163 static struct v4l2_rect *rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev *subdev,
5164 struct v4l2_subdev_pad_config *cfg,
5165 enum v4l2_subdev_format_whence which)
5166 {
5167 if (which == V4L2_SUBDEV_FORMAT_TRY)
5168 return v4l2_subdev_get_try_crop(&subdev->sd, cfg, RKCIF_LVDS_PAD_SINK);
5169 else
5170 return &subdev->crop;
5171 }
5172
rkcif_lvds_sd_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)5173 static int rkcif_lvds_sd_set_selection(struct v4l2_subdev *sd,
5174 struct v4l2_subdev_pad_config *cfg,
5175 struct v4l2_subdev_selection *sel)
5176 {
5177 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
5178 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
5179 int ret = 0;
5180
5181 ret = v4l2_subdev_call(sensor, pad, set_selection,
5182 cfg, sel);
5183 if (!ret)
5184 subdev->crop = sel->r;
5185
5186 return ret;
5187 }
5188
rkcif_lvds_sd_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)5189 static int rkcif_lvds_sd_get_selection(struct v4l2_subdev *sd,
5190 struct v4l2_subdev_pad_config *cfg,
5191 struct v4l2_subdev_selection *sel)
5192 {
5193 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
5194 struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
5195 struct v4l2_subdev_format fmt;
5196 int ret = 0;
5197
5198 if (!sel) {
5199 v4l2_dbg(1, rkcif_debug, sd, "sel is null\n");
5200 goto err;
5201 }
5202
5203 if (sel->pad > RKCIF_LVDS_PAD_SRC_ID3) {
5204 v4l2_dbg(1, rkcif_debug, sd, "pad[%d] isn't matched\n", sel->pad);
5205 goto err;
5206 }
5207
5208 switch (sel->target) {
5209 case V4L2_SEL_TGT_CROP_BOUNDS:
5210 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
5211 ret = v4l2_subdev_call(sensor, pad, get_selection,
5212 cfg, sel);
5213 if (ret) {
5214 fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
5215 ret = v4l2_subdev_call(sensor, pad, get_fmt, NULL, &fmt);
5216 if (!ret) {
5217 subdev->in_fmt = fmt.format;
5218 sel->r.top = 0;
5219 sel->r.left = 0;
5220 sel->r.width = subdev->in_fmt.width;
5221 sel->r.height = subdev->in_fmt.height;
5222 subdev->crop = sel->r;
5223 } else {
5224 sel->r = subdev->crop;
5225 }
5226 } else {
5227 subdev->crop = sel->r;
5228 }
5229 } else {
5230 sel->r = *v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
5231 }
5232 break;
5233
5234 case V4L2_SEL_TGT_CROP:
5235 sel->r = *rkcif_lvds_sd_get_crop(subdev, cfg, sel->which);
5236 break;
5237
5238 default:
5239 return -EINVAL;
5240 }
5241
5242 return 0;
5243 err:
5244 return -EINVAL;
5245 }
5246
rkcif_lvds_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * mbus)5247 static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
5248 struct v4l2_mbus_config *mbus)
5249 {
5250 struct v4l2_subdev *sensor_sd = get_lvds_remote_sensor(sd);
5251 int ret;
5252
5253 ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, mbus);
5254 if (ret)
5255 return ret;
5256
5257 return 0;
5258 }
5259
rkcif_lvds_sd_s_stream(struct v4l2_subdev * sd,int on)5260 static int rkcif_lvds_sd_s_stream(struct v4l2_subdev *sd, int on)
5261 {
5262 struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
5263
5264 if (on)
5265 atomic_set(&subdev->frm_sync_seq, 0);
5266
5267 return 0;
5268 }
5269
rkcif_lvds_sd_s_power(struct v4l2_subdev * sd,int on)5270 static int rkcif_lvds_sd_s_power(struct v4l2_subdev *sd, int on)
5271 {
5272 return 0;
5273 }
5274
rkcif_sof_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)5275 static int rkcif_sof_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
5276 struct v4l2_event_subscription *sub)
5277 {
5278 if (sub->type != V4L2_EVENT_FRAME_SYNC)
5279 return -EINVAL;
5280
5281 return v4l2_event_subscribe(fh, sub, 0, NULL);
5282 }
5283
5284 static const struct media_entity_operations rkcif_lvds_sd_media_ops = {
5285 .link_setup = rkcif_lvds_subdev_link_setup,
5286 .link_validate = v4l2_subdev_link_validate,
5287 };
5288
5289 static const struct v4l2_subdev_pad_ops rkcif_lvds_sd_pad_ops = {
5290 .set_fmt = rkcif_lvds_sd_set_fmt,
5291 .get_fmt = rkcif_lvds_sd_get_fmt,
5292 .set_selection = rkcif_lvds_sd_set_selection,
5293 .get_selection = rkcif_lvds_sd_get_selection,
5294 .get_mbus_config = rkcif_lvds_g_mbus_config,
5295 };
5296
5297 static const struct v4l2_subdev_video_ops rkcif_lvds_sd_video_ops = {
5298 .s_stream = rkcif_lvds_sd_s_stream,
5299 };
5300
5301 static const struct v4l2_subdev_core_ops rkcif_lvds_sd_core_ops = {
5302 .s_power = rkcif_lvds_sd_s_power,
5303 .subscribe_event = rkcif_sof_subscribe_event,
5304 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
5305 };
5306
5307 static struct v4l2_subdev_ops rkcif_lvds_sd_ops = {
5308 .core = &rkcif_lvds_sd_core_ops,
5309 .video = &rkcif_lvds_sd_video_ops,
5310 .pad = &rkcif_lvds_sd_pad_ops,
5311 };
5312
rkcif_lvds_event_inc_sof(struct rkcif_device * dev)5313 static void rkcif_lvds_event_inc_sof(struct rkcif_device *dev)
5314 {
5315 struct rkcif_lvds_subdev *subdev = &dev->lvds_subdev;
5316
5317 if (subdev) {
5318 struct v4l2_event event = {
5319 .type = V4L2_EVENT_FRAME_SYNC,
5320 .u.frame_sync.frame_sequence =
5321 atomic_inc_return(&subdev->frm_sync_seq) - 1,
5322 };
5323 v4l2_event_queue(subdev->sd.devnode, &event);
5324 }
5325 }
5326
rkcif_lvds_get_sof(struct rkcif_device * dev)5327 static u32 rkcif_lvds_get_sof(struct rkcif_device *dev)
5328 {
5329 if (dev)
5330 return atomic_read(&dev->lvds_subdev.frm_sync_seq) - 1;
5331
5332 return 0;
5333 }
5334
rkcif_lvds_set_sof(struct rkcif_device * dev,u32 seq)5335 static u32 rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
5336 {
5337 if (dev)
5338 atomic_set(&dev->lvds_subdev.frm_sync_seq, seq);
5339
5340 return 0;
5341 }
5342
rkcif_register_lvds_subdev(struct rkcif_device * dev)5343 int rkcif_register_lvds_subdev(struct rkcif_device *dev)
5344 {
5345 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
5346 struct rkcif_lvds_subdev *lvds_subdev = &dev->lvds_subdev;
5347 struct v4l2_subdev *sd;
5348 int ret;
5349
5350 memset(lvds_subdev, 0, sizeof(*lvds_subdev));
5351 lvds_subdev->cifdev = dev;
5352 sd = &lvds_subdev->sd;
5353 lvds_subdev->state = RKCIF_LVDS_STOP;
5354 v4l2_subdev_init(sd, &rkcif_lvds_sd_ops);
5355 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
5356 sd->entity.ops = &rkcif_lvds_sd_media_ops;
5357 if (dev->chip_id == CHIP_RV1126_CIF)
5358 snprintf(sd->name, sizeof(sd->name), "rkcif-lvds-subdev");
5359 else
5360 snprintf(sd->name, sizeof(sd->name), "rkcif-lite-lvds-subdev");
5361
5362 lvds_subdev->pads[RKCIF_LVDS_PAD_SINK].flags =
5363 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
5364 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID0].flags = MEDIA_PAD_FL_SOURCE;
5365 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID1].flags = MEDIA_PAD_FL_SOURCE;
5366 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID2].flags = MEDIA_PAD_FL_SOURCE;
5367 lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID3].flags = MEDIA_PAD_FL_SOURCE;
5368
5369 lvds_subdev->in_fmt.width = RKCIF_DEFAULT_WIDTH;
5370 lvds_subdev->in_fmt.height = RKCIF_DEFAULT_HEIGHT;
5371 lvds_subdev->crop.left = 0;
5372 lvds_subdev->crop.top = 0;
5373 lvds_subdev->crop.width = RKCIF_DEFAULT_WIDTH;
5374 lvds_subdev->crop.height = RKCIF_DEFAULT_HEIGHT;
5375
5376 ret = media_entity_pads_init(&sd->entity, RKCIF_LVDS_PAD_MAX,
5377 lvds_subdev->pads);
5378 if (ret < 0)
5379 return ret;
5380 sd->owner = THIS_MODULE;
5381 v4l2_set_subdevdata(sd, lvds_subdev);
5382 ret = v4l2_device_register_subdev(v4l2_dev, sd);
5383 if (ret < 0)
5384 goto free_media;
5385
5386 ret = v4l2_device_register_subdev_nodes(v4l2_dev);
5387 if (ret < 0)
5388 goto free_subdev;
5389 return ret;
5390 free_subdev:
5391 v4l2_device_unregister_subdev(sd);
5392 free_media:
5393 media_entity_cleanup(&sd->entity);
5394 v4l2_err(sd, "Failed to register subdev, ret:%d\n", ret);
5395 return ret;
5396 }
5397
rkcif_unregister_lvds_subdev(struct rkcif_device * dev)5398 void rkcif_unregister_lvds_subdev(struct rkcif_device *dev)
5399 {
5400 struct v4l2_subdev *sd = &dev->lvds_subdev.sd;
5401
5402 v4l2_device_unregister_subdev(sd);
5403 media_entity_cleanup(&sd->entity);
5404 }
5405
rkcif_dvp_event_inc_sof(struct rkcif_device * dev)5406 static void rkcif_dvp_event_inc_sof(struct rkcif_device *dev)
5407 {
5408 struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
5409
5410 if (subdev) {
5411 struct v4l2_event event = {
5412 .type = V4L2_EVENT_FRAME_SYNC,
5413 .u.frame_sync.frame_sequence =
5414 atomic_inc_return(&subdev->frm_sync_seq) - 1,
5415 };
5416 v4l2_event_queue(subdev->sd.devnode, &event);
5417 }
5418 }
5419
rkcif_dvp_get_sof(struct rkcif_device * dev)5420 static u32 rkcif_dvp_get_sof(struct rkcif_device *dev)
5421 {
5422 if (dev)
5423 return atomic_read(&dev->dvp_sof_subdev.frm_sync_seq) - 1;
5424
5425 return 0;
5426 }
5427
rkcif_dvp_set_sof(struct rkcif_device * dev,u32 seq)5428 static u32 rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
5429 {
5430 if (dev)
5431 atomic_set(&dev->dvp_sof_subdev.frm_sync_seq, seq);
5432
5433 return 0;
5434 }
5435
5436 static const struct v4l2_subdev_core_ops rkcif_dvp_sof_sd_core_ops = {
5437 .subscribe_event = rkcif_sof_subscribe_event,
5438 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
5439 };
5440
5441 static struct v4l2_subdev_ops rkcif_dvp_sof_sd_ops = {
5442 .core = &rkcif_dvp_sof_sd_core_ops,
5443 };
5444
rkcif_register_dvp_sof_subdev(struct rkcif_device * dev)5445 int rkcif_register_dvp_sof_subdev(struct rkcif_device *dev)
5446 {
5447 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
5448 struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
5449 struct v4l2_subdev *sd;
5450 int ret;
5451
5452 memset(subdev, 0, sizeof(*subdev));
5453 subdev->cifdev = dev;
5454 sd = &subdev->sd;
5455 v4l2_subdev_init(sd, &rkcif_dvp_sof_sd_ops);
5456 sd->owner = THIS_MODULE;
5457 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
5458 snprintf(sd->name, sizeof(sd->name), "rkcif-dvp-sof");
5459
5460 v4l2_set_subdevdata(sd, subdev);
5461 ret = v4l2_device_register_subdev(v4l2_dev, sd);
5462 if (ret < 0)
5463 goto end;
5464
5465 ret = v4l2_device_register_subdev_nodes(v4l2_dev);
5466 if (ret < 0)
5467 goto free_subdev;
5468
5469 return ret;
5470
5471 free_subdev:
5472 v4l2_device_unregister_subdev(sd);
5473
5474 end:
5475 v4l2_err(sd, "Failed to register subdev, ret:%d\n", ret);
5476 return ret;
5477 }
5478
rkcif_unregister_dvp_sof_subdev(struct rkcif_device * dev)5479 void rkcif_unregister_dvp_sof_subdev(struct rkcif_device *dev)
5480 {
5481 struct v4l2_subdev *sd = &dev->dvp_sof_subdev.sd;
5482
5483 v4l2_device_unregister_subdev(sd);
5484 }
5485
5486
rkcif_vb_done_oneframe(struct rkcif_stream * stream,struct vb2_v4l2_buffer * vb_done)5487 static void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
5488 struct vb2_v4l2_buffer *vb_done)
5489 {
5490 const struct cif_output_fmt *fmt = stream->cif_fmt_out;
5491 u32 i;
5492
5493 /* Dequeue a filled buffer */
5494 for (i = 0; i < fmt->mplanes; i++) {
5495 vb2_set_plane_payload(&vb_done->vb2_buf, i,
5496 stream->pixm.plane_fmt[i].sizeimage);
5497 }
5498
5499 if (stream->cifdev->hdr.hdr_mode == NO_HDR)
5500 vb_done->vb2_buf.timestamp = ktime_get_ns();
5501
5502 vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
5503 v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
5504 "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
5505 vb_done->vb2_buf.index, vb_done->sequence);
5506 }
5507
rkcif_irq_oneframe(struct rkcif_device * cif_dev)5508 void rkcif_irq_oneframe(struct rkcif_device *cif_dev)
5509 {
5510 /* TODO: xuhf-debug: add stream type */
5511 struct rkcif_stream *stream;
5512 u32 lastline, lastpix, ctl, cif_frmst, intstat, frmid;
5513 int ret = 0;
5514
5515 intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
5516 cif_frmst = rkcif_read_register(cif_dev, CIF_REG_DVP_FRAME_STATUS);
5517 lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_LINE);
5518 lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
5519 ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
5520 frmid = CIF_GET_FRAME_ID(cif_frmst);
5521
5522 /* There are two irqs enabled:
5523 * - PST_INF_FRAME_END: cif FIFO is ready, this is prior to FRAME_END
5524 * - FRAME_END: cif has saved frame to memory, a frame ready
5525 */
5526 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
5527
5528 if ((intstat & PST_INF_FRAME_END)) {
5529 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
5530 PST_INF_FRAME_END_CLR);
5531
5532 if (stream->stopping)
5533 /* To stop CIF ASAP, before FRAME_END irq */
5534 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL,
5535 ctl & (~ENABLE_CAPTURE));
5536 }
5537
5538 if ((intstat & FRAME_END)) {
5539 struct vb2_v4l2_buffer *vb_done = NULL;
5540
5541 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
5542 FRAME_END_CLR);
5543
5544 if (stream->stopping) {
5545 rkcif_stream_stop(stream);
5546 stream->stopping = false;
5547 wake_up(&stream->wq_stopped);
5548 return;
5549 }
5550
5551 if (lastline != stream->pixm.height ||
5552 !(cif_frmst & CIF_F0_READY)) {
5553 /* Clearing status must be complete before fe packet
5554 * arrives while cif is connected with mipi,
5555 * so it should be placed before printing log here,
5556 * otherwise it would be delayed.
5557 * At the same time, don't clear the frame id
5558 * for switching address.
5559 */
5560 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
5561 FRM0_STAT_CLS);
5562 v4l2_err(&cif_dev->v4l2_dev,
5563 "Bad frame, irq:0x%x frmst:0x%x size:%dx%d\n",
5564 intstat, cif_frmst, lastline, lastpix);
5565
5566 return;
5567 }
5568
5569 if (frmid % 2 != 0) {
5570 stream->frame_phase = CIF_CSI_FRAME0_READY;
5571 if (stream->curr_buf)
5572 vb_done = &stream->curr_buf->vb;
5573 } else {
5574 stream->frame_phase = CIF_CSI_FRAME1_READY;
5575 if (stream->next_buf)
5576 vb_done = &stream->next_buf->vb;
5577 }
5578
5579 /* In one-frame mode:
5580 * 1,must clear status manually by writing 0 to enable
5581 * the next frame end irq;
5582 * 2,do not clear the frame id for switching address.
5583 */
5584 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
5585 cif_frmst & FRM0_STAT_CLS);
5586 ret = rkcif_assign_new_buffer_oneframe(stream,
5587 RKCIF_YUV_ADDR_STATE_UPDATE);
5588
5589 if (vb_done && (!ret)) {
5590 vb_done->sequence = stream->frame_idx;
5591 rkcif_vb_done_oneframe(stream, vb_done);
5592 }
5593
5594 stream->frame_idx++;
5595 cif_dev->irq_stats.all_frm_end_cnt++;
5596 }
5597 }
5598
rkcif_csi_g_mipi_id(struct v4l2_device * v4l2_dev,unsigned int intstat)5599 static int rkcif_csi_g_mipi_id(struct v4l2_device *v4l2_dev,
5600 unsigned int intstat)
5601 {
5602 if (intstat & CSI_FRAME_END_ID0) {
5603 if ((intstat & CSI_FRAME_END_ID0) ==
5604 CSI_FRAME_END_ID0)
5605 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID0\n");
5606 return RKCIF_STREAM_MIPI_ID0;
5607 }
5608
5609 if (intstat & CSI_FRAME_END_ID1) {
5610 if ((intstat & CSI_FRAME_END_ID1) ==
5611 CSI_FRAME_END_ID1)
5612 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID1\n");
5613 return RKCIF_STREAM_MIPI_ID1;
5614 }
5615
5616 if (intstat & CSI_FRAME_END_ID2) {
5617 if ((intstat & CSI_FRAME_END_ID2) ==
5618 CSI_FRAME_END_ID2)
5619 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID2\n");
5620 return RKCIF_STREAM_MIPI_ID2;
5621 }
5622
5623 if (intstat & CSI_FRAME_END_ID3) {
5624 if ((intstat & CSI_FRAME_END_ID3) ==
5625 CSI_FRAME_END_ID3)
5626 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID3\n");
5627 return RKCIF_STREAM_MIPI_ID3;
5628 }
5629
5630 return -EINVAL;
5631 }
5632
rkcif_dvp_g_ch_id(struct v4l2_device * v4l2_dev,u32 * intstat,u32 frm_stat)5633 static int rkcif_dvp_g_ch_id(struct v4l2_device *v4l2_dev,
5634 u32 *intstat, u32 frm_stat)
5635 {
5636 if (*intstat & DVP_FRAME_END_ID0) {
5637 if ((frm_stat & DVP_CHANNEL0_FRM_READ) ==
5638 DVP_CHANNEL0_FRM_READ)
5639 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID0\n");
5640
5641 *intstat &= ~DVP_FRAME_END_ID0;
5642 return RKCIF_STREAM_MIPI_ID0;
5643 }
5644
5645 if (*intstat & DVP_FRAME_END_ID1) {
5646 if ((frm_stat & DVP_CHANNEL1_FRM_READ) ==
5647 DVP_CHANNEL1_FRM_READ)
5648 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID1\n");
5649
5650 *intstat &= ~DVP_FRAME_END_ID1;
5651 return RKCIF_STREAM_MIPI_ID1;
5652 }
5653
5654 if (*intstat & DVP_FRAME_END_ID2) {
5655 if ((frm_stat & DVP_CHANNEL2_FRM_READ) ==
5656 DVP_CHANNEL2_FRM_READ)
5657 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID2\n");
5658 *intstat &= ~DVP_FRAME_END_ID2;
5659 return RKCIF_STREAM_MIPI_ID2;
5660 }
5661
5662 if (*intstat & DVP_FRAME_END_ID3) {
5663 if ((frm_stat & DVP_CHANNEL3_FRM_READ) ==
5664 DVP_CHANNEL3_FRM_READ)
5665 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID3\n");
5666 *intstat &= ~DVP_FRAME_END_ID3;
5667 return RKCIF_STREAM_MIPI_ID3;
5668 }
5669
5670 return -EINVAL;
5671 }
5672
rkcif_dvp_g_ch_id_by_fe(struct v4l2_device * v4l2_dev,u32 intstat)5673 static int rkcif_dvp_g_ch_id_by_fe(struct v4l2_device *v4l2_dev,
5674 u32 intstat)
5675 {
5676 if (intstat & DVP_ALL_END_ID0) {
5677 if ((intstat & DVP_ALL_END_ID0) ==
5678 DVP_ALL_END_ID0)
5679 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID0\n");
5680 return RKCIF_STREAM_MIPI_ID0;
5681 }
5682
5683 if (intstat & DVP_ALL_END_ID1) {
5684 if ((intstat & DVP_ALL_END_ID1) ==
5685 DVP_ALL_END_ID1)
5686 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID1\n");
5687 return RKCIF_STREAM_MIPI_ID1;
5688 }
5689
5690 if (intstat & DVP_ALL_END_ID2) {
5691 if ((intstat & DVP_ALL_END_ID2) ==
5692 DVP_ALL_END_ID2)
5693 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID2\n");
5694 return RKCIF_STREAM_MIPI_ID2;
5695 }
5696
5697 if (intstat & DVP_ALL_END_ID3) {
5698 if ((intstat & DVP_ALL_END_ID3) ==
5699 DVP_ALL_END_ID3)
5700 v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID3\n");
5701 return RKCIF_STREAM_MIPI_ID3;
5702 }
5703
5704 return -EINVAL;
5705 }
5706
rkcif_is_csi2_err_trigger_reset(struct rkcif_timer * timer)5707 static bool rkcif_is_csi2_err_trigger_reset(struct rkcif_timer *timer)
5708 {
5709 struct rkcif_device *dev = container_of(timer,
5710 struct rkcif_device,
5711 reset_watchdog_timer);
5712 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
5713 bool is_triggered = false, is_assign_triggered = false, is_first_err = false;
5714 unsigned long flags;
5715 u64 cur_time, diff_time;
5716
5717 spin_lock_irqsave(&timer->csi2_err_lock, flags);
5718
5719 if (timer->csi2_err_cnt_even != 0 &&
5720 timer->csi2_err_cnt_odd != 0) {
5721 timer->csi2_err_cnt_odd = 0;
5722 timer->csi2_err_cnt_even = 0;
5723 timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5724 timer->csi2_err_triggered_cnt++;
5725 if (timer->csi2_err_triggered_cnt == 1) {
5726 is_first_err = true;
5727 timer->csi2_first_err_timestamp = ktime_get_ns();
5728 }
5729
5730 is_assign_triggered = true;
5731
5732 v4l2_info(&dev->v4l2_dev,
5733 "find csi2 err cnt is:%d\n",
5734 timer->csi2_err_triggered_cnt);
5735 }
5736
5737 if (!is_first_err) {
5738 if (timer->csi2_err_triggered_cnt >= 1) {
5739 cur_time = ktime_get_ns();
5740 diff_time = cur_time - timer->csi2_first_err_timestamp;
5741 diff_time = div_u64(diff_time, 1000000);
5742 if (diff_time >= timer->err_time_interval) {
5743 is_triggered = true;
5744 v4l2_info(&dev->v4l2_dev, "trigger reset for time out of csi err\n");
5745 goto end_judge;
5746 }
5747
5748 if (!is_assign_triggered &&
5749 (timer->csi2_err_cnt_odd == 0 ||
5750 timer->csi2_err_cnt_even == 0)) {
5751 is_triggered = true;
5752 v4l2_info(&dev->v4l2_dev, "trigger reset for csi err\n");
5753 goto end_judge;
5754 }
5755 }
5756 }
5757
5758 /*
5759 * when fs cnt is beyond 2, it indicates that frame end is not coming,
5760 * or fs and fe had been not paired.
5761 */
5762 if (stream->is_fs_fe_not_paired ||
5763 stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM) {
5764 is_triggered = true;
5765 v4l2_info(&dev->v4l2_dev, "reset for fs & fe not paired\n");
5766 }
5767 end_judge:
5768 spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
5769
5770 return is_triggered;
5771 }
5772
rkcif_is_triggered_monitoring(struct rkcif_device * dev)5773 static bool rkcif_is_triggered_monitoring(struct rkcif_device *dev)
5774 {
5775 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5776 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
5777 bool ret = false;
5778
5779 if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
5780 ret = false;
5781
5782 if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE ||
5783 timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
5784 if (stream->frame_idx >= timer->triggered_frame_num)
5785 ret = true;
5786 }
5787
5788 if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
5789 timer->is_csi2_err_occurred = rkcif_is_csi2_err_trigger_reset(timer);
5790 ret = timer->is_csi2_err_occurred;
5791 }
5792
5793 return ret;
5794 }
5795
rkcif_get_sensor_vblank(struct rkcif_device * dev)5796 static s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
5797 {
5798 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
5799 struct v4l2_subdev *sd = terminal_sensor->sd;
5800 struct v4l2_ctrl_handler *hdl = sd->ctrl_handler;
5801 struct v4l2_ctrl *ctrl = NULL;
5802
5803 if (!list_empty(&hdl->ctrls)) {
5804 list_for_each_entry(ctrl, &hdl->ctrls, node) {
5805 if (ctrl->id == V4L2_CID_VBLANK)
5806 return ctrl->val;
5807 }
5808 }
5809
5810 return 0;
5811 }
5812
rkcif_cal_csi_crop_width_vwidth(struct rkcif_stream * stream,u32 raw_width,u32 * crop_width,u32 * crop_vwidth)5813 static void rkcif_cal_csi_crop_width_vwidth(struct rkcif_stream *stream,
5814 u32 raw_width, u32 *crop_width,
5815 u32 *crop_vwidth)
5816 {
5817 struct rkcif_device *dev = stream->cifdev;
5818 struct csi_channel_info *channel = &dev->channels[stream->id];
5819 const struct cif_output_fmt *fmt;
5820 u32 fourcc;
5821
5822 fmt = find_output_fmt(stream, stream->pixm.pixelformat);
5823 if (!fmt) {
5824 v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
5825 stream->pixm.pixelformat);
5826 return;
5827 }
5828
5829 *crop_width = raw_width;
5830
5831 /*
5832 * for mipi or lvds, when enable compact, the virtual width of raw10/raw12
5833 * needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
5834 * needs aligned with :ALIGN(bits_per_pixel * width * 2, 8), to optimize reading and
5835 * writing of ddr, aliged with 256
5836 */
5837 if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact) {
5838 *crop_vwidth = ALIGN(raw_width * fmt->raw_bpp / 8, 256);
5839 } else {
5840 if (fmt->fmt_type == CIF_FMT_TYPE_RAW)
5841 *crop_vwidth = ALIGN(raw_width * 2, 8);
5842 else
5843 *crop_vwidth = ALIGN(raw_width * fmt->bpp[0] / 8, 8);
5844 }
5845
5846 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
5847 *crop_width = raw_width * fmt->bpp[0] / 8;
5848 /*
5849 * rk cif don't support output yuyv fmt data
5850 * if user request yuyv fmt, the input mode must be RAW8
5851 * and the width is double Because the real input fmt is
5852 * yuyv
5853 */
5854 fourcc = stream->cif_fmt_out->fourcc;
5855 if (fourcc == V4L2_PIX_FMT_YUYV || fourcc == V4L2_PIX_FMT_YVYU ||
5856 fourcc == V4L2_PIX_FMT_UYVY || fourcc == V4L2_PIX_FMT_VYUY) {
5857 *crop_width = 2 * raw_width;
5858 *crop_vwidth *= 2;
5859 }
5860 }
5861
rkcif_dynamic_crop(struct rkcif_stream * stream)5862 static void rkcif_dynamic_crop(struct rkcif_stream *stream)
5863 {
5864 struct rkcif_device *cif_dev = stream->cifdev;
5865 struct v4l2_mbus_config *mbus;
5866 const struct cif_output_fmt *fmt;
5867 u32 raw_width, crop_width = 64, crop_vwidth = 64,
5868 crop_height = 64, crop_x = 0, crop_y = 0;
5869
5870 if (!cif_dev->active_sensor)
5871 return;
5872
5873 mbus = &cif_dev->active_sensor->mbus;
5874 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
5875 mbus->type == V4L2_MBUS_CSI2_CPHY ||
5876 mbus->type == V4L2_MBUS_CCP2) {
5877 struct csi_channel_info *channel = &cif_dev->channels[stream->id];
5878
5879 if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
5880 crop_x = 3 * stream->crop[CROP_SRC_ACT].left;
5881 else
5882 crop_x = stream->crop[CROP_SRC_ACT].left;
5883
5884 crop_y = stream->crop[CROP_SRC_ACT].top;
5885 raw_width = stream->crop[CROP_SRC_ACT].width;
5886 crop_height = stream->crop[CROP_SRC_ACT].height;
5887
5888 rkcif_cal_csi_crop_width_vwidth(stream,
5889 raw_width,
5890 &crop_width, &crop_vwidth);
5891 rkcif_write_register(cif_dev,
5892 get_reg_index_of_id_crop_start(channel->id),
5893 crop_y << 16 | crop_x);
5894 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl1(channel->id),
5895 crop_height << 16 | crop_width);
5896
5897 rkcif_write_register(cif_dev,
5898 get_reg_index_of_frm0_y_vlw(channel->id),
5899 crop_vwidth);
5900 rkcif_write_register(cif_dev,
5901 get_reg_index_of_frm1_y_vlw(channel->id),
5902 crop_vwidth);
5903 rkcif_write_register(cif_dev,
5904 get_reg_index_of_frm0_uv_vlw(channel->id),
5905 crop_vwidth);
5906 rkcif_write_register(cif_dev,
5907 get_reg_index_of_frm1_uv_vlw(channel->id),
5908 crop_vwidth);
5909 } else {
5910
5911 raw_width = stream->crop[CROP_SRC_ACT].width;
5912 crop_width = raw_width;
5913 crop_vwidth = raw_width;
5914 crop_height = stream->crop[CROP_SRC_ACT].height;
5915 crop_x = stream->crop[CROP_SRC_ACT].left;
5916 crop_y = stream->crop[CROP_SRC_ACT].top;
5917
5918 rkcif_write_register(cif_dev, CIF_REG_DVP_CROP,
5919 crop_y << CIF_CROP_Y_SHIFT | crop_x);
5920
5921 if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
5922 fmt = find_output_fmt(stream, stream->pixm.pixelformat);
5923 crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
5924 }
5925 rkcif_write_register(cif_dev, CIF_REG_DVP_VIR_LINE_WIDTH, crop_vwidth);
5926
5927 rkcif_write_register(cif_dev, CIF_REG_DVP_SET_SIZE,
5928 crop_height << 16 | crop_width);
5929 }
5930
5931 stream->crop_dyn_en = false;
5932 }
5933
rkcif_monitor_reset_event(struct rkcif_device * dev)5934 static void rkcif_monitor_reset_event(struct rkcif_device *dev)
5935 {
5936 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
5937 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5938 unsigned int cycle = 0;
5939 u64 fps, timestamp0, timestamp1;
5940 unsigned long flags, fps_flags;
5941
5942 if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
5943 return;
5944
5945 if (stream->state != RKCIF_STATE_STREAMING)
5946 return;
5947
5948 if (timer->is_running)
5949 return;
5950
5951 timer->is_triggered = rkcif_is_triggered_monitoring(dev);
5952
5953 if (timer->is_triggered) {
5954
5955 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
5956 enum rkcif_monitor_mode mode;
5957 s32 vblank = 0;
5958 u32 vts = 0;
5959
5960 spin_lock_irqsave(&stream->fps_lock, fps_flags);
5961 timestamp0 = stream->fps_stats.frm0_timestamp;
5962 timestamp1 = stream->fps_stats.frm1_timestamp;
5963 spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
5964
5965 spin_lock_irqsave(&timer->timer_lock, flags);
5966
5967 fps = timestamp0 > timestamp1 ?
5968 timestamp0 - timestamp1 : timestamp1 - timestamp0;
5969 fps = div_u64(fps, 1000);
5970 timer->frame_end_cycle_us = fps;
5971
5972 vblank = rkcif_get_sensor_vblank(dev);
5973 timer->raw_height = raw_rect->height;
5974 vts = timer->raw_height + vblank;
5975 timer->vts = vts;
5976
5977 timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
5978 fps = div_u64(timer->frame_end_cycle_us, 1000);
5979 cycle = fps * timer->frm_num_of_monitor_cycle;
5980 timer->cycle = msecs_to_jiffies(cycle);
5981
5982 timer->run_cnt = 0;
5983 timer->is_running = true;
5984 timer->is_buf_stop_update = false;
5985 timer->last_buf_wakeup_cnt = dev->buf_wake_up_cnt;
5986 /* in trigger mode, monitoring count is fps */
5987 mode = timer->monitor_mode;
5988 if (mode == RKCIF_MONITOR_MODE_CONTINUE ||
5989 mode == RKCIF_MONITOR_MODE_HOTPLUG)
5990 timer->max_run_cnt = 0xffffffff - CIF_TIMEOUT_FRAME_NUM;
5991 else
5992 timer->max_run_cnt = div_u64(1000, fps) * 1;
5993
5994 timer->timer.expires = jiffies + timer->cycle;
5995 mod_timer(&timer->timer, timer->timer.expires);
5996
5997 spin_unlock_irqrestore(&timer->timer_lock, flags);
5998
5999 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
6000 "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n",
6001 __func__, timer->monitor_mode, raw_rect->height,
6002 vblank, timer->cycle, div_u64(1000, fps));
6003 }
6004 }
6005
rkcif_rdbk_frame_end(struct rkcif_stream * stream)6006 static void rkcif_rdbk_frame_end(struct rkcif_stream *stream)
6007 {
6008 struct rkcif_device *dev = stream->cifdev;
6009 struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
6010 u32 denominator, numerator;
6011 u64 l_ts, m_ts, s_ts, time = 30000000LL;
6012 int ret, fps = -1;
6013
6014 if (dev->hdr.hdr_mode == HDR_X2) {
6015 if (stream->id != RKCIF_STREAM_MIPI_ID1 ||
6016 dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING ||
6017 dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING)
6018 return;
6019 } else if (dev->hdr.hdr_mode == HDR_X3) {
6020 if (stream->id != RKCIF_STREAM_MIPI_ID2 ||
6021 dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING ||
6022 dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING ||
6023 dev->stream[RKCIF_STREAM_MIPI_ID2].state != RKCIF_STATE_STREAMING)
6024 return;
6025 }
6026
6027 numerator = sensor->fi.interval.numerator;
6028 denominator = sensor->fi.interval.denominator;
6029 if (denominator && numerator)
6030 time = numerator * 1000 / denominator * 1000 * 1000;
6031
6032 if (dev->hdr.hdr_mode == HDR_X3) {
6033 if (dev->rdbk_buf[RDBK_L] &&
6034 dev->rdbk_buf[RDBK_M] &&
6035 dev->rdbk_buf[RDBK_S]) {
6036 l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
6037 m_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
6038 s_ts = dev->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
6039
6040 if (m_ts < l_ts || s_ts < m_ts) {
6041 v4l2_err(&dev->v4l2_dev,
6042 "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
6043 s_ts, m_ts, l_ts);
6044 goto RDBK_FRM_UNMATCH;
6045 }
6046
6047 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
6048 ret = v4l2_subdev_call(sensor->sd,
6049 video,
6050 g_frame_interval,
6051 &sensor->fi);
6052 if (!ret) {
6053 denominator = sensor->fi.interval.denominator;
6054 numerator = sensor->fi.interval.numerator;
6055 if (denominator && numerator) {
6056 time = numerator * 1000 / denominator * 1000 * 1000;
6057 fps = denominator / numerator;
6058 }
6059 }
6060
6061 if ((m_ts - l_ts) > time || (s_ts - m_ts) > time) {
6062 v4l2_err(&dev->v4l2_dev,
6063 "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
6064 s_ts, m_ts, l_ts, fps);
6065 goto RDBK_FRM_UNMATCH;
6066 }
6067 }
6068 dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
6069 dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
6070 rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
6071 &dev->rdbk_buf[RDBK_L]->vb);
6072 rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
6073 &dev->rdbk_buf[RDBK_M]->vb);
6074 rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID2],
6075 &dev->rdbk_buf[RDBK_S]->vb);
6076 } else {
6077 if (!dev->rdbk_buf[RDBK_L])
6078 v4l2_err(&dev->v4l2_dev, "lost long frames\n");
6079 if (!dev->rdbk_buf[RDBK_M])
6080 v4l2_err(&dev->v4l2_dev, "lost medium frames\n");
6081 if (!dev->rdbk_buf[RDBK_S])
6082 v4l2_err(&dev->v4l2_dev, "lost short frames\n");
6083 goto RDBK_FRM_UNMATCH;
6084 }
6085 } else if (dev->hdr.hdr_mode == HDR_X2) {
6086 if (dev->rdbk_buf[RDBK_L] && dev->rdbk_buf[RDBK_M]) {
6087 l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
6088 s_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
6089
6090 if (s_ts < l_ts) {
6091 v4l2_err(&dev->v4l2_dev,
6092 "s/l frame err, timestamp s:%lld l:%lld\n",
6093 s_ts, l_ts);
6094 goto RDBK_FRM_UNMATCH;
6095 }
6096
6097 if ((s_ts - l_ts) > time) {
6098 ret = v4l2_subdev_call(sensor->sd,
6099 video,
6100 g_frame_interval,
6101 &sensor->fi);
6102 if (!ret) {
6103 denominator = sensor->fi.interval.denominator;
6104 numerator = sensor->fi.interval.numerator;
6105 if (denominator && numerator) {
6106 time = numerator * 1000 / denominator * 1000 * 1000;
6107 fps = denominator / numerator;
6108 }
6109 }
6110 if ((s_ts - l_ts) > time) {
6111 v4l2_err(&dev->v4l2_dev,
6112 "timestamp no match, s:%lld l:%lld, fps:%d\n",
6113 s_ts, l_ts, fps);
6114 goto RDBK_FRM_UNMATCH;
6115 }
6116 }
6117 dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_M]->vb.sequence;
6118 rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
6119 &dev->rdbk_buf[RDBK_L]->vb);
6120 rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
6121 &dev->rdbk_buf[RDBK_M]->vb);
6122 } else {
6123 if (!dev->rdbk_buf[RDBK_L])
6124 v4l2_err(&dev->v4l2_dev, "lost long frames\n");
6125 if (!dev->rdbk_buf[RDBK_M])
6126 v4l2_err(&dev->v4l2_dev, "lost short frames\n");
6127 goto RDBK_FRM_UNMATCH;
6128 }
6129 } else {
6130 rkcif_vb_done_oneframe(stream, &dev->rdbk_buf[RDBK_S]->vb);
6131 }
6132
6133 dev->rdbk_buf[RDBK_L] = NULL;
6134 dev->rdbk_buf[RDBK_M] = NULL;
6135 dev->rdbk_buf[RDBK_S] = NULL;
6136 return;
6137
6138 RDBK_FRM_UNMATCH:
6139 if (dev->rdbk_buf[RDBK_L]) {
6140 dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6141 rkcif_buf_queue(&dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
6142 }
6143 if (dev->rdbk_buf[RDBK_M]) {
6144 dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6145 rkcif_buf_queue(&dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
6146 }
6147 if (dev->rdbk_buf[RDBK_S]) {
6148 dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6149 rkcif_buf_queue(&dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
6150 }
6151
6152 dev->rdbk_buf[RDBK_L] = NULL;
6153 dev->rdbk_buf[RDBK_M] = NULL;
6154 dev->rdbk_buf[RDBK_S] = NULL;
6155 }
6156
rkcif_buf_done_prepare(struct rkcif_stream * stream,struct rkcif_buffer * active_buf,int mipi_id,u32 mode)6157 static void rkcif_buf_done_prepare(struct rkcif_stream *stream,
6158 struct rkcif_buffer *active_buf,
6159 int mipi_id,
6160 u32 mode)
6161 {
6162 unsigned long flags;
6163 struct vb2_v4l2_buffer *vb_done = NULL;
6164 struct rkcif_device *cif_dev = stream->cifdev;
6165
6166 if (active_buf) {
6167 vb_done = &active_buf->vb;
6168 vb_done->vb2_buf.timestamp = ktime_get_ns();
6169 vb_done->sequence = stream->frame_idx;
6170 if (stream->is_line_wake_up) {
6171 spin_lock_irqsave(&stream->fps_lock, flags);
6172 if (mode)
6173 stream->fps_stats.frm0_timestamp = vb_done->vb2_buf.timestamp;
6174 else
6175 stream->fps_stats.frm1_timestamp = vb_done->vb2_buf.timestamp;
6176 stream->readout.wk_timestamp = vb_done->vb2_buf.timestamp;
6177 spin_unlock_irqrestore(&stream->fps_lock, flags);
6178 }
6179 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED)
6180 vb_done->sequence /= 2;
6181 }
6182
6183 if (cif_dev->hdr.hdr_mode == NO_HDR) {
6184 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
6185 if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf)
6186 rkcif_vb_done_oneframe(stream, vb_done);
6187 } else {
6188 if (active_buf)
6189 rkcif_vb_done_oneframe(stream, vb_done);
6190 }
6191 } else {
6192 if (cif_dev->is_start_hdr) {
6193 spin_lock_irqsave(&cif_dev->hdr_lock, flags);
6194 if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
6195 if (cif_dev->rdbk_buf[RDBK_L]) {
6196 v4l2_err(&cif_dev->v4l2_dev,
6197 "multiple long data in %s frame,frm_idx:%d,state:0x%x\n",
6198 cif_dev->hdr.hdr_mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
6199 stream->frame_idx,
6200 cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state);
6201 cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6202 rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
6203 }
6204 if (active_buf)
6205 cif_dev->rdbk_buf[RDBK_L] = active_buf;
6206 } else if (mipi_id == RKCIF_STREAM_MIPI_ID1) {
6207 if (cif_dev->rdbk_buf[RDBK_M]) {
6208 v4l2_err(&cif_dev->v4l2_dev,
6209 "multiple %s frame,frm_idx:%d,state:0x%x\n",
6210 cif_dev->hdr.hdr_mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
6211 stream->frame_idx,
6212 cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state);
6213 cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6214 rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
6215 }
6216 if (active_buf)
6217 cif_dev->rdbk_buf[RDBK_M] = active_buf;
6218 if (cif_dev->hdr.hdr_mode == HDR_X2)
6219 rkcif_rdbk_frame_end(stream);
6220 } else if (mipi_id == RKCIF_STREAM_MIPI_ID2) {
6221 if (cif_dev->rdbk_buf[RDBK_S]) {
6222 v4l2_err(&cif_dev->v4l2_dev,
6223 "multiple %s frame, frm_idx:%d,state:0x%x\n",
6224 cif_dev->hdr.hdr_mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
6225 stream->frame_idx,
6226 cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state);
6227 cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6228 rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
6229 }
6230 if (active_buf)
6231 cif_dev->rdbk_buf[RDBK_S] = active_buf;
6232 if (cif_dev->hdr.hdr_mode == HDR_X3)
6233 rkcif_rdbk_frame_end(stream);
6234 }
6235 spin_unlock_irqrestore(&cif_dev->hdr_lock, flags);
6236 } else {
6237 if (active_buf) {
6238 vb_done->vb2_buf.state = VB2_BUF_STATE_ACTIVE;
6239 rkcif_buf_queue(&vb_done->vb2_buf);
6240 }
6241
6242 v4l2_info(&cif_dev->v4l2_dev,
6243 "warning:hdr runs stream[%d], stream[0]:%s stream[1]:%s stream[2]:%s stream[3]:%s\n",
6244 stream->id,
6245 cif_dev->stream[0].state != RKCIF_STATE_STREAMING ? "stopped" : "running",
6246 cif_dev->stream[1].state != RKCIF_STATE_STREAMING ? "stopped" : "running",
6247 cif_dev->stream[2].state != RKCIF_STATE_STREAMING ? "stopped" : "running",
6248 cif_dev->stream[3].state != RKCIF_STATE_STREAMING ? "stopped" : "running");
6249 }
6250 }
6251
6252 }
6253
rkcif_line_wake_up(struct rkcif_stream * stream,int mipi_id)6254 static void rkcif_line_wake_up(struct rkcif_stream *stream, int mipi_id)
6255 {
6256 u32 mode;
6257 struct rkcif_buffer *active_buf = NULL;
6258 struct rkcif_device *cif_dev = stream->cifdev;
6259 int ret = 0;
6260
6261 mode = stream->line_int_cnt % 2;
6262 if (mode) {
6263 if (stream->curr_buf)
6264 active_buf = stream->curr_buf;
6265 } else {
6266 if (stream->next_buf)
6267 active_buf = stream->next_buf;
6268 }
6269
6270 if (stream->stopping) {
6271 stream->is_can_stop = true;
6272 return;
6273 }
6274 ret = rkcif_get_new_buffer_wake_up_mode(stream);
6275 if (ret)
6276 goto end_wake_up;
6277
6278 rkcif_buf_done_prepare(stream, active_buf, mipi_id, mode);
6279 end_wake_up:
6280 if (mipi_id == RKCIF_STREAM_MIPI_ID0)
6281 cif_dev->buf_wake_up_cnt += 1;
6282 stream->frame_idx++;
6283
6284 }
6285
rkcif_deal_readout_time(struct rkcif_stream * stream)6286 static void rkcif_deal_readout_time(struct rkcif_stream *stream)
6287 {
6288 struct rkcif_device *cif_dev = stream->cifdev;
6289 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
6290 unsigned long flags;
6291
6292 spin_lock_irqsave(&stream->fps_lock, flags);
6293 stream->readout.fe_timestamp = ktime_get_ns();
6294 if (stream->id == RKCIF_STREAM_MIPI_ID0)
6295 detect_stream->readout.readout_time = stream->readout.fe_timestamp - stream->readout.fs_timestamp;
6296
6297 if ((cif_dev->hdr.hdr_mode == NO_HDR) && (stream->id == RKCIF_STREAM_MIPI_ID0)) {
6298 detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
6299
6300 } else if ((cif_dev->hdr.hdr_mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
6301 detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
6302 detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
6303 detect_stream->readout.total_time += detect_stream->readout.readout_time;
6304 } else if ((cif_dev->hdr.hdr_mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
6305 detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
6306 detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
6307 detect_stream->readout.total_time += detect_stream->readout.readout_time;
6308 }
6309 if (!stream->is_line_wake_up)
6310 detect_stream->readout.early_time = 0;
6311 spin_unlock_irqrestore(&stream->fps_lock, flags);
6312 }
6313
rkcif_update_stream(struct rkcif_device * cif_dev,struct rkcif_stream * stream,int mipi_id)6314 static void rkcif_update_stream(struct rkcif_device *cif_dev,
6315 struct rkcif_stream *stream,
6316 int mipi_id)
6317 {
6318 struct rkcif_buffer *active_buf = NULL;
6319 unsigned long flags;
6320 int ret = 0;
6321
6322 if (stream->frame_phase == (CIF_CSI_FRAME0_READY | CIF_CSI_FRAME1_READY)) {
6323
6324 v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
6325 stream->id, stream->frame_idx);
6326
6327 stream->frame_idx++;
6328 return;
6329 }
6330 if (!stream->is_line_wake_up) {
6331
6332 spin_lock_irqsave(&stream->fps_lock, flags);
6333 if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
6334 if (stream->curr_buf)
6335 active_buf = stream->curr_buf;
6336 stream->fps_stats.frm0_timestamp = ktime_get_ns();
6337 } else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
6338 if (stream->next_buf)
6339 active_buf = stream->next_buf;
6340 stream->fps_stats.frm1_timestamp = ktime_get_ns();
6341 }
6342 spin_unlock_irqrestore(&stream->fps_lock, flags);
6343 if (mipi_id == RKCIF_STREAM_MIPI_ID0)
6344 cif_dev->buf_wake_up_cnt += 1;
6345 }
6346
6347 if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
6348 rkcif_deal_readout_time(stream);
6349
6350 if (cif_dev->chip_id == CHIP_RV1126_CIF ||
6351 cif_dev->chip_id == CHIP_RV1126_CIF_LITE ||
6352 cif_dev->chip_id == CHIP_RK3568_CIF)
6353 rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, stream->frame_idx);
6354
6355 if (!stream->is_line_wake_up) {
6356 ret = rkcif_assign_new_buffer_pingpong(stream,
6357 RKCIF_YUV_ADDR_STATE_UPDATE,
6358 mipi_id);
6359 if (ret)
6360 goto end;
6361 } else {
6362 ret = rkcif_update_new_buffer_wake_up_mode(stream);
6363 if (ret)
6364 return;
6365 }
6366 if (!stream->is_line_wake_up)
6367 rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
6368
6369 end:
6370 if (!stream->is_line_wake_up)
6371 stream->frame_idx++;
6372 }
6373
rkcif_update_stream_toisp(struct rkcif_device * cif_dev,struct rkcif_stream * stream,int mipi_id)6374 static void rkcif_update_stream_toisp(struct rkcif_device *cif_dev,
6375 struct rkcif_stream *stream,
6376 int mipi_id)
6377 {
6378 if (stream->frame_phase == (CIF_CSI_FRAME0_READY | CIF_CSI_FRAME1_READY)) {
6379
6380 v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
6381 stream->id, stream->frame_idx);
6382
6383 stream->frame_idx++;
6384 return;
6385 }
6386
6387 spin_lock(&stream->fps_lock);
6388 if (stream->frame_phase & CIF_CSI_FRAME0_READY)
6389 stream->fps_stats.frm0_timestamp = ktime_get_ns();
6390 else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
6391 stream->fps_stats.frm1_timestamp = ktime_get_ns();
6392 spin_unlock(&stream->fps_lock);
6393
6394 rkcif_assign_new_buffer_pingpong_toisp(stream,
6395 RKCIF_YUV_ADDR_STATE_UPDATE,
6396 mipi_id);
6397 stream->frame_idx++;
6398 }
6399
rkcif_get_sof(struct rkcif_device * cif_dev)6400 static u32 rkcif_get_sof(struct rkcif_device *cif_dev)
6401 {
6402 u32 val = 0x0;
6403 struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
6404 struct csi2_dev *csi;
6405
6406 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
6407 sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
6408 csi = container_of(sensor->sd, struct csi2_dev, sd);
6409 val = rkcif_csi2_get_sof(csi);
6410 } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
6411 val = rkcif_lvds_get_sof(cif_dev);
6412 } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL ||
6413 sensor->mbus.type == V4L2_MBUS_BT656) {
6414 val = rkcif_dvp_get_sof(cif_dev);
6415 }
6416 return val;
6417 }
6418
rkcif_set_sof(struct rkcif_device * cif_dev,u32 seq)6419 static void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
6420 {
6421 struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
6422 struct csi2_dev *csi;
6423
6424 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
6425 sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
6426 csi = container_of(sensor->sd, struct csi2_dev, sd);
6427 rkcif_csi2_set_sof(csi, seq);
6428 } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
6429 rkcif_lvds_set_sof(cif_dev, seq);
6430 } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL ||
6431 sensor->mbus.type == V4L2_MBUS_BT656) {
6432 rkcif_dvp_set_sof(cif_dev, seq);
6433 }
6434 }
6435
rkcif_do_reset_work(struct rkcif_device * cif_dev,enum rkmodule_reset_src reset_src)6436 static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
6437 enum rkmodule_reset_src reset_src)
6438 {
6439 struct rkcif_pipeline *p = &cif_dev->pipe;
6440 struct rkcif_stream *stream = NULL;
6441 struct rkcif_stream *resume_stream[RKCIF_MAX_STREAM_MIPI] = { NULL };
6442 struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
6443 struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
6444 struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
6445 int i, j, ret = 0;
6446 u32 on, sof_cnt;
6447 u64 fps;
6448
6449 mutex_lock(&cif_dev->stream_lock);
6450
6451 if (cif_dev->reset_work_cancel)
6452 goto unlock_stream;
6453
6454 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
6455
6456 fps = div_u64(timer->frame_end_cycle_us, 1000);
6457 for (i = 0, j = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6458 stream = &cif_dev->stream[i];
6459
6460 if (stream->state == RKCIF_STATE_STREAMING) {
6461
6462 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
6463 "stream[%d] stopping\n", stream->id);
6464
6465 stream->stopping = true;
6466
6467 ret = wait_event_timeout(stream->wq_stopped,
6468 stream->state != RKCIF_STATE_STREAMING,
6469 msecs_to_jiffies(fps));
6470 if (!ret) {
6471 rkcif_stream_stop(stream);
6472 stream->stopping = false;
6473 }
6474
6475 if (stream->id == RKCIF_STREAM_MIPI_ID0) {
6476 sof_cnt = rkcif_get_sof(cif_dev);
6477 v4l2_err(&cif_dev->v4l2_dev,
6478 "%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
6479 __func__,
6480 stream->id,
6481 stream->frame_idx,
6482 sof_cnt);
6483
6484 resume_info->frm_sync_seq = sof_cnt;
6485 if (stream->frame_idx != sof_cnt)
6486 stream->frame_idx = sof_cnt;
6487 }
6488
6489 stream->state = RKCIF_STATE_RESET_IN_STREAMING;
6490 stream->is_fs_fe_not_paired = false;
6491 stream->fs_cnt_in_single_frame = 0;
6492 resume_stream[j] = stream;
6493 j += 1;
6494
6495 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
6496 "%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
6497 __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
6498
6499 }
6500 }
6501
6502 on = 0;
6503 for (i = 0; i < p->num_subdevs; i++) {
6504
6505 if (p->subdevs[i] == terminal_sensor->sd) {
6506
6507 if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 ||
6508 reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG ||
6509 reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
6510
6511 ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
6512 RKMODULE_SET_QUICK_STREAM, &on);
6513 if (ret)
6514 v4l2_err(&cif_dev->v4l2_dev, "quick stream off subdev:%s failed\n",
6515 p->subdevs[i]->name);
6516 }
6517 } else {
6518 ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
6519 }
6520
6521 if (ret)
6522 v4l2_err(&cif_dev->v4l2_dev, "%s:stream %s subdev:%s failed\n",
6523 __func__, on ? "on" : "off", p->subdevs[i]->name);
6524
6525 }
6526
6527 rockchip_clear_system_status(SYS_STATUS_CIF0);
6528
6529 rkcif_do_cru_reset(cif_dev);
6530
6531 rkcif_disable_sys_clk(cif_dev->hw_dev);
6532
6533 udelay(5);
6534
6535 ret = rkcif_enable_sys_clk(cif_dev->hw_dev);
6536 if (ret < 0) {
6537 v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
6538 goto unlock_stream;
6539 }
6540
6541 for (i = 0; i < j; i++) {
6542 stream = resume_stream[i];
6543 stream->fs_cnt_in_single_frame = 0;
6544 if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
6545 if (stream->curr_buf == stream->next_buf) {
6546 if (stream->curr_buf)
6547 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
6548 } else {
6549 if (stream->curr_buf)
6550 list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
6551 if (stream->next_buf)
6552 list_add_tail(&stream->next_buf->queue, &stream->buf_head);
6553 }
6554 stream->curr_buf = NULL;
6555 stream->next_buf = NULL;
6556 }
6557 ret = rkcif_csi_stream_start(stream, RKCIF_STREAM_MODE_CAPTURE);
6558 if (ret) {
6559 v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
6560 __func__, stream->id);
6561 goto unlock_stream;
6562 }
6563
6564 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
6565 "resume stream[%d], frm_idx:%d, csi_sof:%d\n",
6566 stream->id, stream->frame_idx,
6567 rkcif_get_sof(cif_dev));
6568 }
6569
6570 rockchip_set_system_status(SYS_STATUS_CIF0);
6571
6572 on = 1;
6573 for (i = 0; i < p->num_subdevs; i++) {
6574
6575 if (p->subdevs[i] == terminal_sensor->sd) {
6576
6577 rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
6578
6579 if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 ||
6580 reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG ||
6581 reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
6582 ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
6583 RKMODULE_SET_QUICK_STREAM, &on);
6584 if (ret)
6585 v4l2_err(&cif_dev->v4l2_dev,
6586 "quick stream on subdev:%s failed\n",
6587 p->subdevs[i]->name);
6588 }
6589 } else {
6590 if (p->subdevs[i] == terminal_sensor->sd)
6591 rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
6592
6593 ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
6594 }
6595
6596 if (ret)
6597 v4l2_err(&cif_dev->v4l2_dev, "reset subdev:%s failed\n",
6598 p->subdevs[i]->name);
6599 }
6600
6601 rkcif_start_luma(&cif_dev->luma_vdev,
6602 cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
6603
6604 timer->csi2_err_triggered_cnt = 0;
6605 rkcif_monitor_reset_event(cif_dev);
6606
6607 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
6608
6609 mutex_unlock(&cif_dev->stream_lock);
6610 return 0;
6611
6612 unlock_stream:
6613 mutex_unlock(&cif_dev->stream_lock);
6614 return ret;
6615 }
6616
rkcif_reset_work(struct work_struct * work)6617 void rkcif_reset_work(struct work_struct *work)
6618 {
6619 struct rkcif_work_struct *reset_work = container_of(work,
6620 struct rkcif_work_struct,
6621 work);
6622 struct rkcif_device *dev = container_of(reset_work,
6623 struct rkcif_device,
6624 reset_work);
6625 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
6626 int ret;
6627
6628 ret = rkcif_do_reset_work(dev, reset_work->reset_src);
6629 if (ret)
6630 v4l2_info(&dev->v4l2_dev, "do reset work failed!\n");
6631 timer->is_running = false;
6632 timer->has_been_init = false;
6633 }
6634
rkcif_is_reduced_frame_rate(struct rkcif_device * dev)6635 static bool rkcif_is_reduced_frame_rate(struct rkcif_device *dev)
6636 {
6637 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
6638 struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
6639 struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
6640 u64 fps, timestamp0, timestamp1, diff_time;
6641 unsigned long fps_flags;
6642 unsigned int deviation = 1;
6643 bool is_reduced = false;
6644
6645 spin_lock_irqsave(&stream->fps_lock, fps_flags);
6646 timestamp0 = stream->fps_stats.frm0_timestamp;
6647 timestamp1 = stream->fps_stats.frm1_timestamp;
6648 spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
6649
6650 fps = timestamp0 > timestamp1 ?
6651 timestamp0 - timestamp1 : timestamp1 - timestamp0;
6652 fps = div_u64(fps, 1000);
6653 diff_time = fps > timer->frame_end_cycle_us ?
6654 fps - timer->frame_end_cycle_us : 0;
6655 deviation = DIV_ROUND_UP(timer->vts, 100);
6656
6657 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "diff_time:%lld,devi_t:%ld,devi_h:%d\n",
6658 diff_time, timer->line_end_cycle * deviation, deviation);
6659
6660 if (diff_time > timer->line_end_cycle * deviation) {
6661 s32 vblank = 0;
6662 unsigned int vts;
6663
6664 is_reduced = true;
6665 vblank = rkcif_get_sensor_vblank(dev);
6666 vts = vblank + timer->raw_height;
6667
6668 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "old vts:%d,new vts:%d\n", timer->vts, vts);
6669
6670 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
6671 "reduce frame rate,vblank:%d, height(raw output):%d, fps:%lld, frm_end_t:%ld, line_t:%ld, diff:%lld\n",
6672 rkcif_get_sensor_vblank(dev),
6673 raw_rect->height,
6674 fps,
6675 timer->frame_end_cycle_us,
6676 timer->line_end_cycle,
6677 diff_time);
6678
6679 timer->vts = vts;
6680 timer->frame_end_cycle_us = fps;
6681 timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
6682 } else {
6683 is_reduced = false;
6684 }
6685
6686 timer->frame_end_cycle_us = fps;
6687
6688 fps = div_u64(fps, 1000);
6689 fps = fps * timer->frm_num_of_monitor_cycle;
6690 timer->cycle = msecs_to_jiffies(fps);
6691 timer->timer.expires = jiffies + timer->cycle;
6692
6693 return is_reduced;
6694
6695 }
6696
rkcif_init_reset_work(struct rkcif_timer * timer)6697 static void rkcif_init_reset_work(struct rkcif_timer *timer)
6698 {
6699 struct rkcif_device *dev = container_of(timer,
6700 struct rkcif_device,
6701 reset_watchdog_timer);
6702 unsigned long flags;
6703
6704 if (timer->has_been_init)
6705 return;
6706
6707 v4l2_info(&dev->v4l2_dev,
6708 "do reset work schedule, run_cnt:%d, reset source:%d\n",
6709 timer->run_cnt, timer->reset_src);
6710
6711 spin_lock_irqsave(&timer->timer_lock, flags);
6712 timer->is_running = true;
6713 timer->is_triggered = false;
6714 timer->csi2_err_cnt_odd = 0;
6715 timer->csi2_err_cnt_even = 0;
6716 timer->csi2_err_fs_fe_cnt = 0;
6717 timer->notifer_called_cnt = 0;
6718 timer->last_buf_wakeup_cnt = dev->buf_wake_up_cnt;
6719 spin_unlock_irqrestore(&timer->timer_lock, flags);
6720
6721 dev->reset_work.reset_src = timer->reset_src;
6722 if (schedule_work(&dev->reset_work.work)) {
6723 timer->has_been_init = true;
6724 v4l2_info(&dev->v4l2_dev,
6725 "schedule reset work successfully\n");
6726 } else {
6727 v4l2_info(&dev->v4l2_dev,
6728 "schedule reset work failed\n");
6729 }
6730 }
6731
rkcif_reset_watchdog_timer_handler(struct timer_list * t)6732 void rkcif_reset_watchdog_timer_handler(struct timer_list *t)
6733 {
6734 struct rkcif_timer *timer = container_of(t, struct rkcif_timer, timer);
6735 struct rkcif_device *dev = container_of(timer,
6736 struct rkcif_device,
6737 reset_watchdog_timer);
6738 struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
6739
6740 unsigned long flags;
6741 unsigned int i, stream_num = 1;
6742 int ret, is_reset = 0;
6743 struct rkmodule_vicap_reset_info rst_info;
6744
6745 if (dev->hdr.hdr_mode == NO_HDR) {
6746 i = 0;
6747 if (dev->stream[i].state != RKCIF_STATE_STREAMING)
6748 goto end_detect;
6749 } else {
6750 if (dev->hdr.hdr_mode == HDR_X3)
6751 stream_num = 3;
6752 else if (dev->hdr.hdr_mode == HDR_X2)
6753 stream_num = 2;
6754
6755 for (i = 0; i < stream_num; i++) {
6756 if (dev->stream[i].state != RKCIF_STATE_STREAMING)
6757 goto end_detect;
6758 }
6759 }
6760
6761 timer->run_cnt += 1;
6762
6763 if (timer->last_buf_wakeup_cnt < dev->buf_wake_up_cnt) {
6764
6765 v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
6766 "info: frame end still update(%d, %d) in detecting cnt:%d, mode:%d\n",
6767 timer->last_buf_wakeup_cnt, dev->buf_wake_up_cnt,
6768 timer->run_cnt, timer->monitor_mode);
6769
6770 timer->last_buf_wakeup_cnt = dev->buf_wake_up_cnt;
6771
6772 rkcif_is_reduced_frame_rate(dev);
6773
6774 if (timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
6775 ret = v4l2_subdev_call(terminal_sensor->sd,
6776 core, ioctl,
6777 RKMODULE_GET_VICAP_RST_INFO,
6778 &rst_info);
6779 if (ret)
6780 is_reset = 0;
6781 else
6782 is_reset = rst_info.is_reset;
6783 rst_info.is_reset = 0;
6784 timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
6785 v4l2_subdev_call(terminal_sensor->sd, core, ioctl,
6786 RKMODULE_SET_VICAP_RST_INFO, &rst_info);
6787 if (!is_reset)
6788 is_reset = rkcif_is_csi2_err_trigger_reset(timer);
6789 } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
6790 is_reset = rkcif_is_csi2_err_trigger_reset(timer);
6791 } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
6792 is_reset = timer->is_csi2_err_occurred;
6793 if (is_reset)
6794 timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
6795 timer->is_csi2_err_occurred = false;
6796 }
6797
6798 if (is_reset) {
6799 rkcif_init_reset_work(timer);
6800 return;
6801 }
6802
6803 if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE ||
6804 timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
6805 if (timer->run_cnt == timer->max_run_cnt)
6806 timer->run_cnt = 0x0;
6807 mod_timer(&timer->timer, jiffies + timer->cycle);
6808 } else {
6809 if (timer->run_cnt <= timer->max_run_cnt) {
6810 mod_timer(&timer->timer, jiffies + timer->cycle);
6811 } else {
6812 spin_lock_irqsave(&timer->timer_lock, flags);
6813 timer->is_triggered = false;
6814 timer->is_running = false;
6815 spin_unlock_irqrestore(&timer->timer_lock, flags);
6816 v4l2_info(&dev->v4l2_dev, "stop reset detecting!\n");
6817 }
6818 }
6819 } else if (timer->last_buf_wakeup_cnt == dev->buf_wake_up_cnt) {
6820
6821 bool is_reduced = rkcif_is_reduced_frame_rate(dev);
6822
6823 if (is_reduced) {
6824 mod_timer(&timer->timer, jiffies + timer->cycle);
6825 v4l2_info(&dev->v4l2_dev, "%s fps is reduced\n", __func__);
6826 } else {
6827
6828 v4l2_info(&dev->v4l2_dev,
6829 "do reset work due to frame end is stopped, run_cnt:%d\n",
6830 timer->run_cnt);
6831
6832 timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
6833 rkcif_init_reset_work(timer);
6834 }
6835 }
6836
6837 return;
6838 end_detect:
6839
6840 spin_lock_irqsave(&timer->timer_lock, flags);
6841 timer->is_triggered = false;
6842 timer->is_running = false;
6843 spin_unlock_irqrestore(&timer->timer_lock, flags);
6844
6845 v4l2_info(&dev->v4l2_dev,
6846 "stream[%d] is stopped, stop reset detect!\n",
6847 dev->stream[i].id);
6848 }
6849
rkcif_reset_notifier(struct notifier_block * nb,unsigned long action,void * data)6850 int rkcif_reset_notifier(struct notifier_block *nb,
6851 unsigned long action, void *data)
6852 {
6853 struct rkcif_device *dev = container_of(nb, struct rkcif_device, reset_notifier);
6854 struct rkcif_timer *timer = &dev->reset_watchdog_timer;
6855 unsigned long flags, val;
6856
6857 if (timer->is_running) {
6858 val = action & CSI2_ERR_COUNT_ALL_MASK;
6859 spin_lock_irqsave(&timer->csi2_err_lock, flags);
6860 if ((val % timer->csi2_err_ref_cnt) == 0) {
6861 timer->notifer_called_cnt++;
6862 if ((timer->notifer_called_cnt % 2) == 0)
6863 timer->csi2_err_cnt_even = val;
6864 else
6865 timer->csi2_err_cnt_odd = val;
6866 }
6867
6868 timer->csi2_err_fs_fe_cnt = (action & CSI2_ERR_FSFE_MASK) >> 8;
6869 spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
6870 }
6871
6872 return 0;
6873 }
6874
rkcif_modify_line_int(struct rkcif_stream * stream,bool en)6875 static void rkcif_modify_line_int(struct rkcif_stream *stream, bool en)
6876 {
6877 struct rkcif_device *cif_dev = stream->cifdev;
6878
6879 if (en) {
6880 if (cif_dev->wait_line_bak != cif_dev->wait_line) {
6881 cif_dev->wait_line_bak = cif_dev->wait_line;
6882 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
6883 cif_dev->wait_line << 16 | cif_dev->wait_line);
6884 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
6885 cif_dev->wait_line << 16 | cif_dev->wait_line);
6886 }
6887 rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
6888 CSI_LINE_INTEN(stream->id));
6889 } else {
6890 rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
6891 ~(CSI_LINE_INTEN(stream->id)));
6892 }
6893 }
6894
rkcif_detect_wake_up_mode_change(struct rkcif_stream * stream)6895 static void rkcif_detect_wake_up_mode_change(struct rkcif_stream *stream)
6896 {
6897 struct rkcif_device *cif_dev = stream->cifdev;
6898 struct sditf_priv *priv = cif_dev->sditf;
6899
6900 if (!priv || priv->toisp_inf.link_mode != TOISP_NONE)
6901 return;
6902
6903 if (cif_dev->wait_line && (!stream->is_line_wake_up)) {
6904 stream->is_line_wake_up = true;
6905 if (stream->frame_phase == CIF_CSI_FRAME0_READY)
6906 stream->line_int_cnt = 1;
6907 else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
6908 stream->line_int_cnt = 0;
6909 } else if ((cif_dev->wait_line == 0) && stream->is_line_wake_up) {
6910 stream->is_line_wake_up = false;
6911 }
6912 if (stream->is_line_wake_up) {
6913 rkcif_modify_line_int(stream, true);
6914 stream->is_line_inten = true;
6915 }
6916
6917 if (cif_dev->hdr.hdr_mode == NO_HDR && stream->id == RKCIF_STREAM_MIPI_ID0) {
6918 if (cif_dev->wait_line != cif_dev->wait_line_cache)
6919 cif_dev->wait_line = cif_dev->wait_line_cache;
6920 } else if (cif_dev->hdr.hdr_mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
6921 if (cif_dev->wait_line != cif_dev->wait_line_cache)
6922 cif_dev->wait_line = cif_dev->wait_line_cache;
6923 } else if (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
6924 if (cif_dev->wait_line != cif_dev->wait_line_cache)
6925 cif_dev->wait_line = cif_dev->wait_line_cache;
6926 }
6927 }
6928
rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)6929 u32 rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)
6930 {
6931 u32 pixelformat;
6932
6933 switch (pixelcode) {
6934 case MEDIA_BUS_FMT_Y8_1X8:
6935 pixelformat = V4L2_PIX_FMT_GREY;
6936 break;
6937 case MEDIA_BUS_FMT_SBGGR8_1X8:
6938 pixelformat = V4L2_PIX_FMT_SBGGR8;
6939 break;
6940 case MEDIA_BUS_FMT_SGBRG8_1X8:
6941 pixelformat = V4L2_PIX_FMT_SGBRG8;
6942 break;
6943 case MEDIA_BUS_FMT_SGRBG8_1X8:
6944 pixelformat = V4L2_PIX_FMT_SGRBG8;
6945 break;
6946 case MEDIA_BUS_FMT_SRGGB8_1X8:
6947 pixelformat = V4L2_PIX_FMT_SRGGB8;
6948 break;
6949 case MEDIA_BUS_FMT_Y10_1X10:
6950 pixelformat = V4L2_PIX_FMT_Y10;
6951 break;
6952 case MEDIA_BUS_FMT_SBGGR10_1X10:
6953 pixelformat = V4L2_PIX_FMT_SBGGR10;
6954 break;
6955 case MEDIA_BUS_FMT_SGBRG10_1X10:
6956 pixelformat = V4L2_PIX_FMT_SGBRG10;
6957 break;
6958 case MEDIA_BUS_FMT_SGRBG10_1X10:
6959 pixelformat = V4L2_PIX_FMT_SGRBG10;
6960 break;
6961 case MEDIA_BUS_FMT_SRGGB10_1X10:
6962 pixelformat = V4L2_PIX_FMT_SRGGB10;
6963 break;
6964 case MEDIA_BUS_FMT_Y12_1X12:
6965 pixelformat = V4L2_PIX_FMT_Y12;
6966 break;
6967 case MEDIA_BUS_FMT_SBGGR12_1X12:
6968 pixelformat = V4L2_PIX_FMT_SBGGR12;
6969 break;
6970 case MEDIA_BUS_FMT_SGBRG12_1X12:
6971 pixelformat = V4L2_PIX_FMT_SGBRG12;
6972 break;
6973 case MEDIA_BUS_FMT_SGRBG12_1X12:
6974 pixelformat = V4L2_PIX_FMT_SGRBG12;
6975 break;
6976 case MEDIA_BUS_FMT_SRGGB12_1X12:
6977 pixelformat = V4L2_PIX_FMT_SRGGB12;
6978 break;
6979 case MEDIA_BUS_FMT_SPD_2X8:
6980 pixelformat = V4l2_PIX_FMT_SPD16;
6981 break;
6982 case MEDIA_BUS_FMT_EBD_1X8:
6983 pixelformat = V4l2_PIX_FMT_EBD8;
6984 break;
6985 default:
6986 pixelformat = V4L2_PIX_FMT_SRGGB10;
6987 }
6988
6989 return pixelformat;
6990 }
6991
rkcif_set_default_fmt(struct rkcif_device * cif_dev)6992 void rkcif_set_default_fmt(struct rkcif_device *cif_dev)
6993 {
6994 struct v4l2_subdev_selection input_sel;
6995 struct v4l2_pix_format_mplane pixm;
6996 struct v4l2_subdev_format fmt;
6997 int stream_num = 0;
6998 int ret, i;
6999
7000 if (cif_dev->chip_id < CHIP_RV1126_CIF)
7001 return;
7002
7003 stream_num = RKCIF_MAX_STREAM_MIPI;
7004
7005 if (!cif_dev->terminal_sensor.sd)
7006 rkcif_update_sensor_info(&cif_dev->stream[0]);
7007
7008 if (cif_dev->terminal_sensor.sd) {
7009 for (i = 0; i < stream_num; i++) {
7010 if (i == RKCIF_STREAM_MIPI_ID3)
7011 cif_dev->stream[i].is_compact = false;
7012 memset(&fmt, 0, sizeof(fmt));
7013 fmt.pad = i;
7014 fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
7015 v4l2_subdev_call(cif_dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt);
7016
7017 memset(&pixm, 0, sizeof(pixm));
7018 pixm.pixelformat = rkcif_mbus_pixelcode_to_v4l2(fmt.format.code);
7019 pixm.width = fmt.format.width;
7020 pixm.height = fmt.format.height;
7021
7022 memset(&input_sel, 0, sizeof(input_sel));
7023 input_sel.pad = i;
7024 input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
7025 input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
7026 ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
7027 pad, get_selection, NULL,
7028 &input_sel);
7029 if (!ret) {
7030 pixm.width = input_sel.r.width;
7031 pixm.height = input_sel.r.height;
7032 }
7033 rkcif_set_fmt(&cif_dev->stream[i], &pixm, false);
7034 }
7035 }
7036 }
7037
rkcif_enable_dma_capture(struct rkcif_stream * stream)7038 void rkcif_enable_dma_capture(struct rkcif_stream *stream)
7039 {
7040 struct rkcif_device *cif_dev = stream->cifdev;
7041 struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
7042 struct csi_channel_info *channel = &cif_dev->channels[stream->id];
7043 u32 val = 0;
7044
7045 if (stream->dma_en) {
7046 stream->dma_en |= stream->to_en_dma;
7047 stream->to_en_dma = 0;
7048 return;
7049 }
7050
7051 stream->dma_en |= stream->to_en_dma;
7052 val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
7053 if (stream->to_en_dma == RKCIF_DMAEN_BY_VICAP) {
7054 rkcif_assign_new_buffer_pingpong(stream,
7055 RKCIF_YUV_ADDR_STATE_INIT,
7056 stream->id);
7057 rkcif_write_register(cif_dev, get_reg_index_of_frm0_y_vlw(stream->id),
7058 channel->virtual_width);
7059 if (stream->is_compact)
7060 val |= LVDS_COMPACT;
7061 else
7062 val &= ~LVDS_COMPACT;
7063 } else if (stream->to_en_dma == RKCIF_DMAEN_BY_ISP) {
7064 rkcif_assign_new_buffer_pingpong_toisp(stream,
7065 RKCIF_YUV_ADDR_STATE_INIT,
7066 stream->id);
7067 }
7068 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
7069 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
7070 mbus_cfg->type == V4L2_MBUS_CCP2) {
7071 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
7072 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
7073 val |= CSI_DMA_ENABLE;
7074 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
7075 }
7076
7077 stream->to_en_dma = 0;
7078 }
7079
rkcif_stop_dma_capture(struct rkcif_stream * stream)7080 static void rkcif_stop_dma_capture(struct rkcif_stream *stream)
7081 {
7082 struct rkcif_device *cif_dev = stream->cifdev;
7083 struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
7084 u32 val = 0;
7085
7086 stream->dma_en &= ~stream->to_stop_dma;
7087 if (stream->dma_en != 0) {
7088 stream->to_stop_dma = 0;
7089 return;
7090 }
7091
7092 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
7093 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY ||
7094 mbus_cfg->type == V4L2_MBUS_CCP2) {
7095 val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
7096 if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY ||
7097 mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
7098 val &= ~CSI_DMA_ENABLE;
7099
7100 rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
7101 }
7102 stream->to_stop_dma = 0;
7103 }
7104
rkcif_g_toisp_ch(unsigned int intstat_glb,int index)7105 static int rkcif_g_toisp_ch(unsigned int intstat_glb, int index)
7106 {
7107 if (intstat_glb & TOISP_END_CH0(index))
7108 return RKCIF_TOISP_CH0;
7109 if (intstat_glb & TOISP_END_CH1(index))
7110 return RKCIF_TOISP_CH1;
7111 if (intstat_glb & TOISP_END_CH2(index))
7112 return RKCIF_TOISP_CH2;
7113
7114 return -EINVAL;
7115 }
7116
rkcif_toisp_check_stop_status(struct sditf_priv * priv,unsigned int intstat_glb,int index)7117 static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
7118 unsigned int intstat_glb,
7119 int index)
7120 {
7121 int ch = 0;
7122 struct rkcif_stream *stream;
7123 int src_id = 0;
7124 int i = 0;
7125 u32 val = 0;
7126
7127 for (i = 0; i < TOISP_CH_MAX; i++) {
7128 ch = rkcif_g_toisp_ch(intstat_glb, index);
7129 if (ch < 0)
7130 continue;
7131 src_id = priv->toisp_inf.ch_info[ch].id;
7132 if (src_id == 24)
7133 stream = &priv->cif_dev->stream[0];
7134 else
7135 stream = &priv->cif_dev->stream[src_id % 4];
7136 if (stream->stopping) {
7137 v4l2_dbg(3, rkcif_debug, &priv->cif_dev->v4l2_dev,
7138 "stream[%d] stop\n",
7139 stream->id);
7140 rkcif_stream_stop(stream);
7141 stream->stopping = false;
7142 wake_up(&stream->wq_stopped);
7143 }
7144 if (stream->to_en_dma)
7145 rkcif_enable_dma_capture(stream);
7146 if (stream->to_en_scale) {
7147 stream->to_en_scale = false;
7148 rkcif_scale_start(stream->scale_vdev);
7149 }
7150 switch (ch) {
7151 case RKCIF_TOISP_CH0:
7152 val = TOISP_END_CH0(index);
7153 intstat_glb = intstat_glb & (~val);
7154 break;
7155 case RKCIF_TOISP_CH1:
7156 val = TOISP_END_CH1(index);
7157 intstat_glb = intstat_glb & (~val);
7158 break;
7159 case RKCIF_TOISP_CH2:
7160 val = TOISP_END_CH2(index);
7161 intstat_glb = intstat_glb & (~val);
7162 break;
7163 default:
7164 break;
7165 }
7166 }
7167 }
7168
rkcif_irq_handle_toisp(struct rkcif_device * cif_dev,unsigned int intstat_glb)7169 void rkcif_irq_handle_toisp(struct rkcif_device *cif_dev, unsigned int intstat_glb)
7170 {
7171 int i = 0;
7172 bool to_check = false;
7173 struct sditf_priv *priv = cif_dev->sditf;
7174
7175 if (!priv || priv->toisp_inf.link_mode == TOISP_NONE)
7176 return;
7177
7178 for (i = 0; i < 2; i++) {
7179 if (priv->toisp_inf.link_mode == TOISP0 &&
7180 i == 0) {
7181 to_check = true;
7182 } else if (priv->toisp_inf.link_mode == TOISP1 &&
7183 i == 1) {
7184 to_check = true;
7185 } else if (priv->toisp_inf.link_mode == TOISP_UNITE &&
7186 i == 1) {
7187 to_check = true;
7188 }
7189 if (to_check)
7190 rkcif_toisp_check_stop_status(priv, intstat_glb, i);
7191 }
7192 }
7193
rkcif_deal_sof(struct rkcif_device * cif_dev)7194 static void rkcif_deal_sof(struct rkcif_device *cif_dev)
7195 {
7196 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
7197 struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
7198 struct csi2_dev *csi;
7199 unsigned long flags;
7200
7201 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
7202 mbus->type == V4L2_MBUS_CSI2_CPHY) {
7203 csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
7204 rkcif_csi2_event_inc_sof(csi);
7205 } else if (mbus->type == V4L2_MBUS_CCP2) {
7206 rkcif_lvds_event_inc_sof(cif_dev);
7207 } else {
7208 rkcif_dvp_event_inc_sof(cif_dev);
7209 }
7210
7211 detect_stream->fs_cnt_in_single_frame++;
7212 spin_lock_irqsave(&detect_stream->fps_lock, flags);
7213 detect_stream->readout.fs_timestamp = ktime_get_ns();
7214 spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
7215 }
7216
rkcif_irq_global(struct rkcif_device * cif_dev)7217 unsigned int rkcif_irq_global(struct rkcif_device *cif_dev)
7218 {
7219 unsigned int intstat_glb = 0;
7220
7221 intstat_glb = rkcif_read_register(cif_dev, CIF_REG_GLB_INTST);
7222 if (intstat_glb)
7223 rkcif_write_register(cif_dev, CIF_REG_GLB_INTST, intstat_glb);
7224
7225 if (intstat_glb & SCALE_TOISP_AXI0_ERR) {
7226 v4l2_err(&cif_dev->v4l2_dev,
7227 "ERROR: scale channel, AXI0 bus err intstat_glb:0x%x !!\n",
7228 intstat_glb);
7229 return 0;
7230 }
7231 if (intstat_glb & SCALE_TOISP_AXI1_ERR) {
7232 v4l2_err(&cif_dev->v4l2_dev,
7233 "ERROR: scale channel, AXI1 bus err intstat_glb:0x%x !!\n",
7234 intstat_glb);
7235 return 0;
7236 }
7237 rkcif_irq_handle_scale(cif_dev, intstat_glb);
7238 v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
7239 "intstat_glb 0x%x\n",
7240 intstat_glb);
7241 return intstat_glb;
7242 }
7243
7244 /* pingpong irq for rk3588 and next */
rkcif_irq_pingpong_v1(struct rkcif_device * cif_dev)7245 void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
7246 {
7247 struct rkcif_stream *stream;
7248 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
7249 struct v4l2_mbus_config *mbus;
7250 unsigned int intstat, i = 0xff, bak_intstat = 0;
7251
7252 if (!cif_dev->active_sensor)
7253 return;
7254
7255 mbus = &cif_dev->active_sensor->mbus;
7256 if (mbus->type == V4L2_MBUS_CSI2_DPHY ||
7257 mbus->type == V4L2_MBUS_CSI2_CPHY ||
7258 mbus->type == V4L2_MBUS_CCP2) {
7259 int mipi_id;
7260 u32 lastline = 0;
7261
7262 intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
7263 lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
7264
7265 /* clear all interrupts that has been triggered */
7266 if (intstat) {
7267 bak_intstat = intstat;
7268 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
7269 v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
7270 "intstat 0x%x\n",
7271 intstat);
7272 } else {
7273 return;
7274 }
7275
7276 if (intstat & CSI_SIZE_ERR) {
7277 cif_dev->irq_stats.csi_size_err_cnt++;
7278 v4l2_err(&cif_dev->v4l2_dev,
7279 "ERROR: csi size err, intstat:0x%x, lastline:%d!!\n",
7280 intstat, lastline);
7281 return;
7282 }
7283
7284 if (intstat & CSI_FIFO_OVERFLOW_V1) {
7285 cif_dev->irq_stats.csi_overflow_cnt++;
7286 v4l2_err(&cif_dev->v4l2_dev,
7287 "ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
7288 intstat, lastline);
7289 return;
7290 }
7291
7292 if (intstat & CSI_BANDWIDTH_LACK_V1) {
7293 cif_dev->irq_stats.csi_bwidth_lack_cnt++;
7294 v4l2_err(&cif_dev->v4l2_dev,
7295 "ERROR: csi bandwidth lack, intstat:0x%x!!\n",
7296 intstat);
7297 return;
7298 }
7299
7300 if (intstat & CSI_ALL_ERROR_INTEN_V1) {
7301 cif_dev->irq_stats.all_err_cnt++;
7302 v4l2_err(&cif_dev->v4l2_dev,
7303 "ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
7304 return;
7305 }
7306
7307 if (intstat & CSI_FRAME0_START_ID0 || intstat & CSI_FRAME1_START_ID0)
7308 rkcif_deal_sof(cif_dev);
7309
7310 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
7311 if (intstat & CSI_LINE_INTSTAT(i)) {
7312 stream = &cif_dev->stream[i];
7313 if (stream->is_line_inten) {
7314 stream->line_int_cnt++;
7315 rkcif_line_wake_up(stream, stream->id);
7316 rkcif_modify_line_int(stream, false);
7317 stream->is_line_inten = false;
7318 }
7319 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
7320 "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
7321 }
7322 }
7323
7324 /* if do not reach frame dma end, return irq */
7325 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
7326 if (mipi_id < 0)
7327 return;
7328
7329 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
7330 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
7331 intstat);
7332 if (mipi_id < 0)
7333 continue;
7334
7335 stream = &cif_dev->stream[mipi_id];
7336
7337 if (stream->stopping &&
7338 !(stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP)) {
7339 rkcif_stream_stop(stream);
7340 stream->stopping = false;
7341 wake_up(&stream->wq_stopped);
7342 continue;
7343 }
7344
7345 if (stream->state != RKCIF_STATE_STREAMING)
7346 continue;
7347
7348 switch (mipi_id) {
7349 case RKCIF_STREAM_MIPI_ID0:
7350 stream->frame_phase = SW_FRM_END_ID0(intstat);
7351 intstat &= ~CSI_FRAME_END_ID0;
7352 break;
7353 case RKCIF_STREAM_MIPI_ID1:
7354 stream->frame_phase = SW_FRM_END_ID1(intstat);
7355 intstat &= ~CSI_FRAME_END_ID1;
7356 break;
7357 case RKCIF_STREAM_MIPI_ID2:
7358 stream->frame_phase = SW_FRM_END_ID2(intstat);
7359 intstat &= ~CSI_FRAME_END_ID2;
7360 break;
7361 case RKCIF_STREAM_MIPI_ID3:
7362 stream->frame_phase = SW_FRM_END_ID3(intstat);
7363 intstat &= ~CSI_FRAME_END_ID3;
7364 break;
7365 }
7366 if (stream->crop_dyn_en)
7367 rkcif_dynamic_crop(stream);
7368
7369 if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
7370 rkcif_update_stream(cif_dev, stream, mipi_id);
7371 else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
7372 rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
7373
7374 if (stream->to_en_dma)
7375 rkcif_enable_dma_capture(stream);
7376 if (stream->to_stop_dma) {
7377 rkcif_stop_dma_capture(stream);
7378 wake_up(&stream->wq_stopped);
7379 }
7380 if (stream->to_en_scale) {
7381 stream->to_en_scale = false;
7382 rkcif_scale_start(stream->scale_vdev);
7383 }
7384 rkcif_detect_wake_up_mode_change(stream);
7385 if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
7386 if ((intstat & (CSI_FRAME1_START_ID0 | CSI_FRAME0_START_ID0)) == 0 &&
7387 detect_stream->fs_cnt_in_single_frame > 1) {
7388 v4l2_err(&cif_dev->v4l2_dev,
7389 "%s ERR: multi fs in oneframe, bak_int:0x%x, fs_num:%u\n",
7390 __func__,
7391 bak_intstat,
7392 detect_stream->fs_cnt_in_single_frame);
7393 detect_stream->is_fs_fe_not_paired = true;
7394 detect_stream->fs_cnt_in_single_frame = 0;
7395 } else {
7396 detect_stream->fs_cnt_in_single_frame--;
7397 }
7398 }
7399 rkcif_monitor_reset_event(cif_dev);
7400 }
7401 cif_dev->irq_stats.all_frm_end_cnt++;
7402 } else {
7403 struct rkcif_stream *stream;
7404 int ch_id;
7405
7406 intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
7407
7408 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
7409
7410 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
7411
7412 if (intstat & DVP_FRAME0_START_ID0 || intstat & DVP_FRAME1_START_ID0)
7413 rkcif_deal_sof(cif_dev);
7414
7415 if (intstat & DVP_SIZE_ERR) {
7416 cif_dev->irq_stats.dvp_size_err_cnt++;
7417 v4l2_info(&cif_dev->v4l2_dev, "dvp size err intstat 0x%x\n", intstat);
7418 }
7419
7420 if (intstat & DVP_FIFO_OVERFLOW) {
7421 cif_dev->irq_stats.dvp_overflow_cnt++;
7422 v4l2_info(&cif_dev->v4l2_dev, "dvp overflow intstat 0x%x\n", intstat);
7423 }
7424
7425 if (intstat & DVP_BANDWIDTH_LACK) {
7426 cif_dev->irq_stats.dvp_bwidth_lack_cnt++;
7427 v4l2_info(&cif_dev->v4l2_dev,
7428 "dvp bandwidth lack err intstat 0x%x\n",
7429 intstat);
7430 }
7431
7432 if (intstat & INTSTAT_ERR_RK3588) {
7433 cif_dev->irq_stats.all_err_cnt++;
7434 v4l2_err(&cif_dev->v4l2_dev,
7435 "ERROR: DVP_ALL_ERROR_INTEN:0x%x!!\n", intstat);
7436 }
7437
7438 for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
7439 ch_id = rkcif_dvp_g_ch_id_by_fe(&cif_dev->v4l2_dev, intstat);
7440
7441 if (ch_id < 0)
7442 continue;
7443
7444 stream = &cif_dev->stream[ch_id];
7445
7446 if (stream->stopping) {
7447 rkcif_stream_stop(stream);
7448 stream->stopping = false;
7449 wake_up(&stream->wq_stopped);
7450 continue;
7451 }
7452
7453 if (stream->state != RKCIF_STATE_STREAMING)
7454 continue;
7455
7456 switch (ch_id) {
7457 case RKCIF_STREAM_MIPI_ID0:
7458 stream->frame_phase = SW_FRM_END_ID0(intstat);
7459 intstat &= ~DVP_ALL_END_ID0;
7460 break;
7461 case RKCIF_STREAM_MIPI_ID1:
7462 stream->frame_phase = SW_FRM_END_ID1(intstat);
7463 intstat &= ~DVP_ALL_END_ID1;
7464 break;
7465 case RKCIF_STREAM_MIPI_ID2:
7466 stream->frame_phase = SW_FRM_END_ID2(intstat);
7467 intstat &= ~DVP_ALL_END_ID2;
7468 break;
7469 case RKCIF_STREAM_MIPI_ID3:
7470 stream->frame_phase = SW_FRM_END_ID3(intstat);
7471 intstat &= ~DVP_ALL_END_ID3;
7472 break;
7473 }
7474 if (stream->dma_en)
7475 rkcif_update_stream(cif_dev, stream, ch_id);
7476 if (stream->to_en_dma)
7477 rkcif_enable_dma_capture(stream);
7478 if (stream->to_stop_dma) {
7479 rkcif_stop_dma_capture(stream);
7480 wake_up(&stream->wq_stopped);
7481 }
7482 cif_dev->irq_stats.all_frm_end_cnt++;
7483 }
7484
7485 if (stream->crop_dyn_en)
7486 rkcif_dynamic_crop(stream);
7487 }
7488 }
7489
rkcif_irq_pingpong(struct rkcif_device * cif_dev)7490 void rkcif_irq_pingpong(struct rkcif_device *cif_dev)
7491 {
7492 struct rkcif_stream *stream;
7493 struct rkcif_stream *detect_stream = &cif_dev->stream[0];
7494 struct v4l2_mbus_config *mbus;
7495 unsigned int intstat = 0x0, i = 0xff, bak_intstat = 0x0;
7496 unsigned long flags;
7497 int ret = 0;
7498
7499 if (!cif_dev->active_sensor)
7500 return;
7501
7502 mbus = &cif_dev->active_sensor->mbus;
7503 if ((mbus->type == V4L2_MBUS_CSI2_DPHY ||
7504 mbus->type == V4L2_MBUS_CSI2_CPHY ||
7505 mbus->type == V4L2_MBUS_CCP2) &&
7506 (cif_dev->chip_id == CHIP_RK1808_CIF ||
7507 cif_dev->chip_id == CHIP_RV1126_CIF ||
7508 cif_dev->chip_id == CHIP_RK3568_CIF)) {
7509 int mipi_id;
7510 u32 lastline = 0;
7511
7512 intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
7513 lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
7514
7515 /* clear all interrupts that has been triggered */
7516 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
7517
7518 if (intstat & CSI_FIFO_OVERFLOW) {
7519 cif_dev->irq_stats.csi_overflow_cnt++;
7520 v4l2_err(&cif_dev->v4l2_dev,
7521 "ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
7522 intstat, lastline);
7523 return;
7524 }
7525
7526 if (intstat & CSI_BANDWIDTH_LACK) {
7527 cif_dev->irq_stats.csi_bwidth_lack_cnt++;
7528 v4l2_err(&cif_dev->v4l2_dev,
7529 "ERROR: csi bandwidth lack, intstat:0x%x!!\n",
7530 intstat);
7531 return;
7532 }
7533
7534 if (intstat & CSI_ALL_ERROR_INTEN) {
7535 cif_dev->irq_stats.all_err_cnt++;
7536 v4l2_err(&cif_dev->v4l2_dev,
7537 "ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
7538 return;
7539 }
7540
7541 if ((intstat & (CSI_FRAME0_START_ID0 | CSI_FRAME1_START_ID0)) ==
7542 (CSI_FRAME0_START_ID0 | CSI_FRAME1_START_ID0)) {
7543 v4l2_err(&cif_dev->v4l2_dev, "%s:ERR: double fs in one fs int\n",
7544 __func__);
7545 }
7546
7547 if (intstat & CSI_FRAME0_START_ID0 || intstat & CSI_FRAME1_START_ID0)
7548 rkcif_deal_sof(cif_dev);
7549
7550 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
7551 if (intstat & CSI_LINE_INTSTAT(i)) {
7552 stream = &cif_dev->stream[i];
7553 if (stream->is_line_inten) {
7554 stream->line_int_cnt++;
7555 rkcif_line_wake_up(stream, stream->id);
7556 rkcif_modify_line_int(stream, false);
7557 stream->is_line_inten = false;
7558 }
7559 v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
7560 "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
7561 }
7562 }
7563
7564 /* if do not reach frame dma end, return irq */
7565 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
7566 if (mipi_id < 0)
7567 return;
7568
7569 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
7570 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
7571 intstat);
7572 if (mipi_id < 0)
7573 continue;
7574
7575 stream = &cif_dev->stream[mipi_id];
7576 if (stream->stopping && stream->is_can_stop) {
7577 rkcif_stream_stop(stream);
7578 stream->stopping = false;
7579 wake_up(&stream->wq_stopped);
7580 continue;
7581 }
7582
7583 if (stream->state != RKCIF_STATE_STREAMING)
7584 continue;
7585
7586 switch (mipi_id) {
7587 case RKCIF_STREAM_MIPI_ID0:
7588 stream->frame_phase = SW_FRM_END_ID0(intstat);
7589 intstat &= ~CSI_FRAME_END_ID0;
7590 break;
7591 case RKCIF_STREAM_MIPI_ID1:
7592 stream->frame_phase = SW_FRM_END_ID1(intstat);
7593 intstat &= ~CSI_FRAME_END_ID1;
7594 break;
7595 case RKCIF_STREAM_MIPI_ID2:
7596 stream->frame_phase = SW_FRM_END_ID2(intstat);
7597 intstat &= ~CSI_FRAME_END_ID2;
7598 break;
7599 case RKCIF_STREAM_MIPI_ID3:
7600 stream->frame_phase = SW_FRM_END_ID3(intstat);
7601 intstat &= ~CSI_FRAME_END_ID3;
7602 break;
7603 }
7604
7605 if (stream->crop_dyn_en)
7606 rkcif_dynamic_crop(stream);
7607
7608 rkcif_update_stream(cif_dev, stream, mipi_id);
7609 rkcif_detect_wake_up_mode_change(stream);
7610 rkcif_monitor_reset_event(cif_dev);
7611 if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
7612 if ((intstat & (CSI_FRAME1_START_ID0 | CSI_FRAME0_START_ID0)) == 0 &&
7613 detect_stream->fs_cnt_in_single_frame > 1) {
7614 v4l2_err(&cif_dev->v4l2_dev,
7615 "%s ERR: multi fs in oneframe, bak_int:0x%x, fs_num:%u\n",
7616 __func__,
7617 bak_intstat,
7618 detect_stream->fs_cnt_in_single_frame);
7619 detect_stream->is_fs_fe_not_paired = true;
7620 detect_stream->fs_cnt_in_single_frame = 0;
7621 } else {
7622 detect_stream->fs_cnt_in_single_frame--;
7623 }
7624 }
7625 }
7626 cif_dev->irq_stats.all_frm_end_cnt++;
7627 } else {
7628 u32 lastline, lastpix, ctl;
7629 u32 cif_frmst, frmid, int_en;
7630 struct rkcif_stream *stream;
7631 int ch_id;
7632
7633 intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
7634 cif_frmst = rkcif_read_register(cif_dev, CIF_REG_DVP_FRAME_STATUS);
7635 lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_LINE);
7636 lastline = CIF_FETCH_Y_LAST_LINE(lastline);
7637 lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
7638 lastpix = CIF_FETCH_Y_LAST_LINE(lastpix);
7639 ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
7640
7641 rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
7642
7643 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
7644
7645 if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
7646 (cif_dev->dvp_sof_in_oneframe == 0)) {
7647 if ((intstat & (PRE_INF_FRAME_END | PST_INF_FRAME_END)) == 0x0) {
7648 if ((intstat & INTSTAT_ERR) == 0x0) {
7649 rkcif_deal_sof(cif_dev);
7650 int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
7651 int_en &= ~LINE_INT_EN;
7652 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
7653 cif_dev->dvp_sof_in_oneframe = 1;
7654 }
7655 }
7656 }
7657
7658 if (intstat & BUS_ERR) {
7659 cif_dev->irq_stats.dvp_bus_err_cnt++;
7660 v4l2_info(&cif_dev->v4l2_dev, "dvp bus err\n");
7661 }
7662
7663 if (intstat & DVP_ALL_OVERFLOW) {
7664 cif_dev->irq_stats.dvp_overflow_cnt++;
7665 v4l2_info(&cif_dev->v4l2_dev, "dvp overflow err\n");
7666 }
7667
7668 if (intstat & LINE_ERR) {
7669 cif_dev->irq_stats.dvp_line_err_cnt++;
7670 v4l2_info(&cif_dev->v4l2_dev, "dvp line err\n");
7671 }
7672
7673 if (intstat & PIX_ERR) {
7674 cif_dev->irq_stats.dvp_pix_err_cnt++;
7675 v4l2_info(&cif_dev->v4l2_dev, "dvp pix err\n");
7676 }
7677
7678 if (intstat & INTSTAT_ERR) {
7679 cif_dev->irq_stats.all_err_cnt++;
7680 v4l2_err(&cif_dev->v4l2_dev,
7681 "ERROR: DVP_ALL_ERROR_INTEN:0x%x!!\n", intstat);
7682 }
7683
7684 /* There are two irqs enabled:
7685 * - PST_INF_FRAME_END: cif FIFO is ready,
7686 * this is prior to FRAME_END
7687 * - FRAME_END: cif has saved frame to memory,
7688 * a frame ready
7689 */
7690 if ((intstat & PST_INF_FRAME_END)) {
7691 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
7692 if (stream->stopping)
7693 /* To stop CIF ASAP, before FRAME_END irq */
7694 rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL,
7695 ctl & (~ENABLE_CAPTURE));
7696 }
7697
7698 if (cif_dev->chip_id <= CHIP_RK1808_CIF) {
7699
7700 stream = &cif_dev->stream[RKCIF_STREAM_CIF];
7701
7702 if ((intstat & FRAME_END)) {
7703 struct vb2_v4l2_buffer *vb_done = NULL;
7704
7705 int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
7706 int_en |= LINE_INT_EN;
7707 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
7708 cif_dev->dvp_sof_in_oneframe = 0;
7709
7710 if (stream->stopping) {
7711 rkcif_stream_stop(stream);
7712 stream->stopping = false;
7713 rkcif_assign_dummy_buffer(stream);
7714 wake_up(&stream->wq_stopped);
7715 return;
7716 }
7717
7718 frmid = CIF_GET_FRAME_ID(cif_frmst);
7719 if ((cif_frmst == 0xfffd0002) || (cif_frmst == 0xfffe0002)) {
7720 v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
7721 frmid, cif_frmst);
7722 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
7723 FRAME_STAT_CLS);
7724 }
7725
7726 if (lastline != stream->pixm.height ||
7727 (!(cif_frmst & CIF_F0_READY) &&
7728 !(cif_frmst & CIF_F1_READY))) {
7729
7730 cif_dev->dvp_sof_in_oneframe = 1;
7731 v4l2_err(&cif_dev->v4l2_dev,
7732 "Bad frame, pp irq:0x%x frmst:0x%x size:%dx%d\n",
7733 intstat, cif_frmst, lastpix, lastline);
7734 return;
7735 }
7736
7737 if (cif_frmst & CIF_F0_READY) {
7738 if (stream->curr_buf)
7739 vb_done = &stream->curr_buf->vb;
7740 stream->frame_phase = CIF_CSI_FRAME0_READY;
7741 } else if (cif_frmst & CIF_F1_READY) {
7742 if (stream->next_buf)
7743 vb_done = &stream->next_buf->vb;
7744 stream->frame_phase = CIF_CSI_FRAME1_READY;
7745 }
7746
7747 spin_lock_irqsave(&stream->fps_lock, flags);
7748 if (stream->frame_phase & CIF_CSI_FRAME0_READY)
7749 stream->fps_stats.frm0_timestamp = ktime_get_ns();
7750 else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
7751 stream->fps_stats.frm1_timestamp = ktime_get_ns();
7752 spin_unlock_irqrestore(&stream->fps_lock, flags);
7753
7754 ret = rkcif_assign_new_buffer_oneframe(stream,
7755 RKCIF_YUV_ADDR_STATE_UPDATE);
7756
7757 if (vb_done && (!ret)) {
7758 vb_done->sequence = stream->frame_idx;
7759 rkcif_vb_done_oneframe(stream, vb_done);
7760 }
7761 stream->frame_idx++;
7762 cif_dev->irq_stats.all_frm_end_cnt++;
7763 }
7764 } else {
7765 for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
7766 ch_id = rkcif_dvp_g_ch_id(&cif_dev->v4l2_dev, &intstat, cif_frmst);
7767
7768 if (ch_id < 0)
7769 continue;
7770
7771 if (ch_id == RKCIF_STREAM_MIPI_ID0) {
7772 int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
7773 int_en |= LINE_INT_EN;
7774 rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
7775 cif_dev->dvp_sof_in_oneframe = 0;
7776 }
7777
7778 stream = &cif_dev->stream[ch_id];
7779
7780 if (stream->stopping) {
7781 rkcif_stream_stop(stream);
7782 stream->stopping = false;
7783 wake_up(&stream->wq_stopped);
7784 continue;
7785 }
7786
7787 if (stream->state != RKCIF_STATE_STREAMING)
7788 continue;
7789
7790 switch (ch_id) {
7791 case RKCIF_STREAM_MIPI_ID0:
7792 stream->frame_phase = DVP_FRM_STS_ID0(cif_frmst);
7793 break;
7794 case RKCIF_STREAM_MIPI_ID1:
7795 stream->frame_phase = DVP_FRM_STS_ID1(cif_frmst);
7796 break;
7797 case RKCIF_STREAM_MIPI_ID2:
7798 stream->frame_phase = DVP_FRM_STS_ID2(cif_frmst);
7799 break;
7800 case RKCIF_STREAM_MIPI_ID3:
7801 stream->frame_phase = DVP_FRM_STS_ID3(cif_frmst);
7802 break;
7803 }
7804
7805
7806 frmid = CIF_GET_FRAME_ID(cif_frmst);
7807 if ((frmid == 0xfffd) || (frmid == 0xfffe)) {
7808 v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
7809 frmid, cif_frmst);
7810 rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
7811 FRAME_STAT_CLS);
7812 }
7813 rkcif_update_stream(cif_dev, stream, ch_id);
7814 cif_dev->irq_stats.all_frm_end_cnt++;
7815 }
7816 }
7817
7818 if (stream->crop_dyn_en)
7819 rkcif_dynamic_crop(stream);
7820 }
7821 }
7822
rkcif_irq_lite_lvds(struct rkcif_device * cif_dev)7823 void rkcif_irq_lite_lvds(struct rkcif_device *cif_dev)
7824 {
7825 struct rkcif_stream *stream;
7826 struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
7827 unsigned int intstat, i = 0xff;
7828
7829 if (mbus->type == V4L2_MBUS_CCP2 &&
7830 cif_dev->chip_id == CHIP_RV1126_CIF_LITE) {
7831 int mipi_id;
7832 u32 lastline = 0;
7833
7834 intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
7835 lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1);
7836
7837 /* clear all interrupts that has been triggered */
7838 rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
7839
7840 if (intstat & CSI_FIFO_OVERFLOW) {
7841 v4l2_err(&cif_dev->v4l2_dev,
7842 "ERROR: cif lite lvds fifo overflow, intstat:0x%x, lastline:%d!!\n",
7843 intstat, lastline);
7844 return;
7845 }
7846
7847 if (intstat & CSI_BANDWIDTH_LACK) {
7848 v4l2_err(&cif_dev->v4l2_dev,
7849 "ERROR: cif lite lvds bandwidth lack, intstat:0x%x!!\n",
7850 intstat);
7851 return;
7852 }
7853
7854 if (intstat & CSI_ALL_ERROR_INTEN) {
7855 v4l2_err(&cif_dev->v4l2_dev,
7856 "ERROR: cif lite lvds all err:0x%x!!\n", intstat);
7857 return;
7858 }
7859
7860 if (intstat & CSI_FRAME0_START_ID0)
7861 rkcif_lvds_event_inc_sof(cif_dev);
7862
7863
7864 if (intstat & CSI_FRAME1_START_ID0)
7865 rkcif_lvds_event_inc_sof(cif_dev);
7866
7867 /* if do not reach frame dma end, return irq */
7868 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
7869 if (mipi_id < 0)
7870 return;
7871
7872 for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
7873 mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
7874 intstat);
7875 if (mipi_id < 0)
7876 continue;
7877
7878 stream = &cif_dev->stream[mipi_id];
7879
7880 if (stream->stopping) {
7881 rkcif_stream_stop(stream);
7882 stream->stopping = false;
7883 wake_up(&stream->wq_stopped);
7884 continue;
7885 }
7886
7887 if (stream->state != RKCIF_STATE_STREAMING)
7888 continue;
7889
7890 switch (mipi_id) {
7891 case RKCIF_STREAM_MIPI_ID0:
7892 stream->frame_phase = SW_FRM_END_ID0(intstat);
7893 intstat &= ~CSI_FRAME_END_ID0;
7894 break;
7895 case RKCIF_STREAM_MIPI_ID1:
7896 stream->frame_phase = SW_FRM_END_ID1(intstat);
7897 intstat &= ~CSI_FRAME_END_ID1;
7898 break;
7899 case RKCIF_STREAM_MIPI_ID2:
7900 stream->frame_phase = SW_FRM_END_ID2(intstat);
7901 intstat &= ~CSI_FRAME_END_ID2;
7902 break;
7903 case RKCIF_STREAM_MIPI_ID3:
7904 stream->frame_phase = SW_FRM_END_ID3(intstat);
7905 intstat &= ~CSI_FRAME_END_ID3;
7906 break;
7907 }
7908
7909 rkcif_update_stream(cif_dev, stream, mipi_id);
7910 rkcif_monitor_reset_event(cif_dev);
7911 }
7912 cif_dev->irq_stats.all_frm_end_cnt++;
7913 }
7914 }
7915