1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip CIF Driver 4 * 5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _RKCIF_REGS_H 9 #define _RKCIF_REGS_H 10 11 struct cif_reg { 12 u32 offset; 13 }; 14 15 #define CIF_REG(_offset) { .offset = (_offset), } 16 17 enum cif_reg_index { 18 /* dvp registers index */ 19 CIF_REG_DVP_CTRL = 0x0, 20 CIF_REG_DVP_INTEN, 21 CIF_REG_DVP_INTSTAT, 22 CIF_REG_DVP_FOR, 23 CIF_REG_DVP_LINE_NUM_ADDR, 24 CIF_REG_DVP_DMA_IDLE_REQ, 25 CIF_REG_DVP_MULTI_ID, 26 CIF_REG_DVP_FRM0_ADDR_Y, 27 CIF_REG_DVP_FRM0_ADDR_UV, 28 CIF_REG_DVP_FRM1_ADDR_Y, 29 CIF_REG_DVP_FRM1_ADDR_UV, 30 CIF_REG_DVP_VIR_LINE_WIDTH, 31 CIF_REG_DVP_SET_SIZE, 32 CIF_REG_DVP_SCM_ADDR_Y, 33 CIF_REG_DVP_SCM_ADDR_U, 34 CIF_REG_DVP_SCM_ADDR_V, 35 CIF_REG_DVP_WB_UP_FILTER, 36 CIF_REG_DVP_WB_LOW_FILTER, 37 CIF_REG_DVP_WBC_CNT, 38 CIF_REG_DVP_LINE_INT_NUM, 39 CIF_REG_DVP_LINE_CNT, 40 CIF_REG_DVP_CROP, 41 CIF_REG_DVP_SCL_CTRL, 42 CIF_REG_DVP_SCL_DST, 43 CIF_REG_DVP_SCL_FCT, 44 CIF_REG_DVP_SCL_VALID_NUM, 45 CIF_REG_DVP_LINE_LOOP_CTRL, 46 CIF_REG_DVP_PATH_SEL, 47 CIF_REG_DVP_FIFO_ENTRY, 48 CIF_REG_DVP_FRAME_STATUS, 49 CIF_REG_DVP_CUR_DST, 50 CIF_REG_DVP_LAST_LINE, 51 CIF_REG_DVP_LAST_PIX, 52 CIF_REG_DVP_FRM0_ADDR_Y_ID1, 53 CIF_REG_DVP_FRM0_ADDR_UV_ID1, 54 CIF_REG_DVP_FRM1_ADDR_Y_ID1, 55 CIF_REG_DVP_FRM1_ADDR_UV_ID1, 56 CIF_REG_DVP_FRM0_ADDR_Y_ID2, 57 CIF_REG_DVP_FRM0_ADDR_UV_ID2, 58 CIF_REG_DVP_FRM1_ADDR_Y_ID2, 59 CIF_REG_DVP_FRM1_ADDR_UV_ID2, 60 CIF_REG_DVP_FRM0_ADDR_Y_ID3, 61 CIF_REG_DVP_FRM0_ADDR_UV_ID3, 62 CIF_REG_DVP_FRM1_ADDR_Y_ID3, 63 CIF_REG_DVP_FRM1_ADDR_UV_ID3, 64 CIF_REG_DVP_SAV_EAV, 65 CIF_REG_DVP_LINE_CNT1, 66 CIF_REG_DVP_LINE_INT_NUM1, 67 /* mipi & lvds registers index */ 68 CIF_REG_MIPI_LVDS_ID0_CTRL0, 69 CIF_REG_MIPI_LVDS_ID0_CTRL1, 70 CIF_REG_MIPI_LVDS_ID1_CTRL0, 71 CIF_REG_MIPI_LVDS_ID1_CTRL1, 72 CIF_REG_MIPI_LVDS_ID2_CTRL0, 73 CIF_REG_MIPI_LVDS_ID2_CTRL1, 74 CIF_REG_MIPI_LVDS_ID3_CTRL0, 75 CIF_REG_MIPI_LVDS_ID3_CTRL1, 76 CIF_REG_MIPI_WATER_LINE, 77 CIF_REG_MIPI_LVDS_CTRL, 78 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID0, 79 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID0, 80 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID0, 81 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID0, 82 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID0, 83 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID0, 84 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID0, 85 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID0, 86 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID1, 87 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID1, 88 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID1, 89 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID1, 90 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID1, 91 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID1, 92 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID1, 93 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID1, 94 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID2, 95 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID2, 96 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID2, 97 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID2, 98 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID2, 99 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID2, 100 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID2, 101 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID2, 102 CIF_REG_MIPI_LVDS_FRAME0_ADDR_Y_ID3, 103 CIF_REG_MIPI_LVDS_FRAME1_ADDR_Y_ID3, 104 CIF_REG_MIPI_LVDS_FRAME0_ADDR_UV_ID3, 105 CIF_REG_MIPI_LVDS_FRAME1_ADDR_UV_ID3, 106 CIF_REG_MIPI_LVDS_FRAME0_VLW_Y_ID3, 107 CIF_REG_MIPI_LVDS_FRAME1_VLW_Y_ID3, 108 CIF_REG_MIPI_LVDS_FRAME0_VLW_UV_ID3, 109 CIF_REG_MIPI_LVDS_FRAME1_VLW_UV_ID3, 110 CIF_REG_MIPI_LVDS_INTEN, 111 CIF_REG_MIPI_LVDS_INTSTAT, 112 CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1, 113 CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3, 114 CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1, 115 CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID2_3, 116 CIF_REG_MIPI_LVDS_ID0_CROP_START, 117 CIF_REG_MIPI_LVDS_ID1_CROP_START, 118 CIF_REG_MIPI_LVDS_ID2_CROP_START, 119 CIF_REG_MIPI_LVDS_ID3_CROP_START, 120 CIF_REG_MIPI_FRAME_NUM_VC0, 121 CIF_REG_MIPI_FRAME_NUM_VC1, 122 CIF_REG_MIPI_FRAME_NUM_VC2, 123 CIF_REG_MIPI_FRAME_NUM_VC3, 124 CIF_REG_LVDS_SAV_EAV_ACT0_ID0, 125 CIF_REG_LVDS_SAV_EAV_BLK0_ID0, 126 CIF_REG_LVDS_SAV_EAV_ACT1_ID0, 127 CIF_REG_LVDS_SAV_EAV_BLK1_ID0, 128 CIF_REG_LVDS_SAV_EAV_ACT0_ID1, 129 CIF_REG_LVDS_SAV_EAV_BLK0_ID1, 130 CIF_REG_LVDS_SAV_EAV_ACT1_ID1, 131 CIF_REG_LVDS_SAV_EAV_BLK1_ID1, 132 CIF_REG_LVDS_SAV_EAV_ACT0_ID2, 133 CIF_REG_LVDS_SAV_EAV_BLK0_ID2, 134 CIF_REG_LVDS_SAV_EAV_ACT1_ID2, 135 CIF_REG_LVDS_SAV_EAV_BLK1_ID2, 136 CIF_REG_LVDS_SAV_EAV_ACT0_ID3, 137 CIF_REG_LVDS_SAV_EAV_BLK0_ID3, 138 CIF_REG_LVDS_SAV_EAV_ACT1_ID3, 139 CIF_REG_LVDS_SAV_EAV_BLK1_ID3, 140 CIF_REG_MIPI_EFFECT_CODE_ID0, 141 CIF_REG_MIPI_EFFECT_CODE_ID1, 142 CIF_REG_MIPI_EFFECT_CODE_ID2, 143 CIF_REG_MIPI_EFFECT_CODE_ID3, 144 CIF_REG_MIPI_ON_PAD, 145 146 CIF_REG_Y_STAT_CONTROL, 147 CIF_REG_Y_STAT_VALUE, 148 CIF_REG_MMU_DTE_ADDR, 149 CIF_REG_MMU_STATUS, 150 CIF_REG_MMU_COMMAND, 151 CIF_REG_MMU_PAGE_FAULT_ADDR, 152 CIF_REG_MMU_ZAP_ONE_LINE, 153 CIF_REG_MMU_INT_RAWSTAT, 154 CIF_REG_MMU_INT_CLEAR, 155 CIF_REG_MMU_INT_MASK, 156 CIF_REG_MMU_INT_STATUS, 157 CIF_REG_MMU_AUTO_GATING, 158 /* reg belowed is in grf */ 159 CIF_REG_GRF_CIFIO_CON, 160 CIF_REG_GRF_CIFIO_CON1, 161 /* reg global control */ 162 CIF_REG_GLB_CTRL, 163 CIF_REG_GLB_INTEN, 164 CIF_REG_GLB_INTST, 165 CIF_REG_SCL_CH_CTRL, 166 CIF_REG_SCL_CTRL, 167 CIF_REG_SCL_FRM0_ADDR_CH0, 168 CIF_REG_SCL_FRM1_ADDR_CH0, 169 CIF_REG_SCL_VLW_CH0, 170 CIF_REG_SCL_FRM0_ADDR_CH1, 171 CIF_REG_SCL_FRM1_ADDR_CH1, 172 CIF_REG_SCL_VLW_CH1, 173 CIF_REG_SCL_FRM0_ADDR_CH2, 174 CIF_REG_SCL_FRM1_ADDR_CH2, 175 CIF_REG_SCL_VLW_CH2, 176 CIF_REG_SCL_FRM0_ADDR_CH3, 177 CIF_REG_SCL_FRM1_ADDR_CH3, 178 CIF_REG_SCL_VLW_CH3, 179 CIF_REG_SCL_BLC_CH0, 180 CIF_REG_SCL_BLC_CH1, 181 CIF_REG_SCL_BLC_CH2, 182 CIF_REG_SCL_BLC_CH3, 183 CIF_REG_TOISP0_CTRL, 184 CIF_REG_TOISP0_SIZE, 185 CIF_REG_TOISP0_CROP, 186 CIF_REG_TOISP1_CTRL, 187 CIF_REG_TOISP1_SIZE, 188 CIF_REG_TOISP1_CROP, 189 CIF_REG_INDEX_MAX 190 }; 191 192 /* CIF Reg Offset */ 193 #define CIF_CTRL 0x00 194 #define CIF_INTEN 0x04 195 #define CIF_INTSTAT 0x08 196 #define CIF_FOR 0x0c 197 #define CIF_LINE_NUM_ADDR 0x10 198 #define CIF_DMA_IDLE_REQ 0x10 199 #define CIF_FRM0_ADDR_Y 0x14 200 #define CIF_FRM0_ADDR_UV 0x18 201 #define CIF_FRM1_ADDR_Y 0x1c 202 #define CIF_FRM1_ADDR_UV 0x20 203 #define CIF_VIR_LINE_WIDTH 0x24 204 #define CIF_SET_SIZE 0x28 205 #define CIF_SCM_ADDR_Y 0x2c 206 #define CIF_LINE_INT_NUM 0x2c 207 #define CIF_SCM_ADDR_U 0x30 208 #define CIF_LINE_CNT 0x30 209 #define CIF_SCM_ADDR_V 0x34 210 #define CIF_WB_UP_FILTER 0x38 211 #define CIF_WB_LOW_FILTER 0x3c 212 #define CIF_WBC_CNT 0x40 213 #define CIF_CROP 0x44 214 #define RV1126_CIF_CROP 0x34 215 #define RK3568_CIF_FIFO_ENTRY 0x38 216 #define CIF_SCL_CTRL 0x48 217 #define CIF_PATH_SEL 0x48 218 #define CIF_SCL_DST 0x4c 219 #define CIF_SCL_FCT 0x50 220 #define CIF_SCL_VALID_NUM 0x54 221 #define CIF_FIFO_ENTRY 0x54 222 #define CIF_LINE_LOOP_CTR 0x58 223 #define CIF_FRAME_STATUS 0x60 224 #define RV1126_CIF_FRAME_STATUS 0x3c 225 #define CIF_CUR_DST 0x64 226 #define RV1126_CIF_CUR_DST 0x40 227 #define CIF_LAST_LINE 0x68 228 #define RV1126_CIF_LAST_LINE 0x44 229 #define CIF_LAST_PIX 0x6c 230 #define RV1126_CIF_LAST_PIX 0x48 231 #define CIF_MULTI_ID 0x10 232 #define CIF_FRM0_ADDR_Y_ID1 0x50 233 #define CIF_FRM0_ADDR_UV_ID1 0x54 234 #define CIF_FRM1_ADDR_Y_ID1 0x58 235 #define CIF_FRM1_ADDR_UV_ID1 0x5c 236 #define CIF_FRM0_ADDR_Y_ID2 0x60 237 #define CIF_FRM0_ADDR_UV_ID2 0x64 238 #define CIF_FRM1_ADDR_Y_ID2 0x68 239 #define CIF_FRM1_ADDR_UV_ID2 0x6c 240 #define CIF_FRM0_ADDR_Y_ID3 0x70 241 #define CIF_FRM0_ADDR_UV_ID3 0x74 242 #define CIF_FRM1_ADDR_Y_ID3 0x78 243 #define CIF_FRM1_ADDR_UV_ID3 0x7c 244 245 #define CIF_FETCH_Y_LAST_LINE(val) ((val) & 0x1fff) 246 /* Check if swap y and c in bt1120 mode */ 247 #define CIF_FETCH_IS_Y_FIRST(val) ((val >> 5) & 0x3) 248 #define CIF_RAW_STORED_BIT_WIDTH (16U) 249 #define CIF_RAW_STORED_BIT_WIDTH_RV1126 (8U) 250 #define CIF_YUV_STORED_BIT_WIDTH (8U) 251 252 /* RK1808 & RV1126 CIF CSI & LVDS Registers Offset */ 253 #define CIF_CSI_ID0_CTRL0 0x80 254 #define CIF_CSI_ID0_CTRL1 0x84 255 #define CIF_CSI_ID1_CTRL0 0x88 256 #define CIF_CSI_ID1_CTRL1 0x8c 257 #define CIF_CSI_ID2_CTRL0 0x90 258 #define CIF_CSI_ID2_CTRL1 0x94 259 #define CIF_CSI_ID3_CTRL0 0x98 260 #define CIF_CSI_ID3_CTRL1 0x9c 261 #define CIF_CSI_WATER_LINE 0xa0 262 #define CIF_CSI_MIPI_LVDS_CTRL 0xa0 263 #define CIF_CSI_FRM0_ADDR_Y_ID0 0xa4 264 #define CIF_CSI_FRM1_ADDR_Y_ID0 0xa8 265 #define CIF_CSI_FRM0_ADDR_UV_ID0 0xac 266 #define CIF_CSI_FRM1_ADDR_UV_ID0 0xb0 267 #define CIF_CSI_FRM0_VLW_Y_ID0 0xb4 268 #define CIF_CSI_FRM1_VLW_Y_ID0 0xb8 269 #define CIF_CSI_FRM0_VLW_UV_ID0 0xbc 270 #define CIF_CSI_FRM1_VLW_UV_ID0 0xc0 271 #define CIF_CSI_FRM0_ADDR_Y_ID1 0xc4 272 #define CIF_CSI_FRM1_ADDR_Y_ID1 0xc8 273 #define CIF_CSI_FRM0_ADDR_UV_ID1 0xcc 274 #define CIF_CSI_FRM1_ADDR_UV_ID1 0xd0 275 #define CIF_CSI_FRM0_VLW_Y_ID1 0xd4 276 #define CIF_CSI_FRM1_VLW_Y_ID1 0xd8 277 #define CIF_CSI_FRM0_VLW_UV_ID1 0xdc 278 #define CIF_CSI_FRM1_VLW_UV_ID1 0xe0 279 #define CIF_CSI_FRM0_ADDR_Y_ID2 0xe4 280 #define CIF_CSI_FRM1_ADDR_Y_ID2 0xe8 281 #define CIF_CSI_FRM0_ADDR_UV_ID2 0xec 282 #define CIF_CSI_FRM1_ADDR_UV_ID2 0xf0 283 #define CIF_CSI_FRM0_VLW_Y_ID2 0xf4 284 #define CIF_CSI_FRM1_VLW_Y_ID2 0xf8 285 #define CIF_CSI_FRM0_VLW_UV_ID2 0xfc 286 #define CIF_CSI_FRM1_VLW_UV_ID2 0x100 287 #define CIF_CSI_FRM0_ADDR_Y_ID3 0x104 288 #define CIF_CSI_FRM1_ADDR_Y_ID3 0x108 289 #define CIF_CSI_FRM0_ADDR_UV_ID3 0x10c 290 #define CIF_CSI_FRM1_ADDR_UV_ID3 0x110 291 #define CIF_CSI_FRM0_VLW_Y_ID3 0x114 292 #define CIF_CSI_FRM1_VLW_Y_ID3 0x118 293 #define CIF_CSI_FRM0_VLW_UV_ID3 0x11c 294 #define CIF_CSI_FRM1_VLW_UV_ID3 0x120 295 #define CIF_CSI_INTEN 0x124 296 #define CIF_CSI_INTSTAT 0x128 297 #define CIF_CSI_LINE_INT_NUM_ID0_1 0x12c 298 #define CIF_CSI_LINE_INT_NUM_ID2_3 0x130 299 #define CIF_CSI_LINE_CNT_ID0_1 0x134 300 #define CIF_CSI_LINE_CNT_ID2_3 0x138 301 #define CIF_CSI_ID0_CROP_START 0x13c 302 #define CIF_CSI_ID1_CROP_START 0x140 303 #define CIF_CSI_ID2_CROP_START 0x144 304 #define CIF_CSI_ID3_CROP_START 0x148 305 #define CIF_CSI_FRAME_NUM_VC0 0x14c 306 #define CIF_CSI_FRAME_NUM_VC1 0x150 307 #define CIF_CSI_FRAME_NUM_VC2 0x154 308 #define CIF_CSI_FRAME_NUM_VC3 0x158 309 #define CIF_LVDS_SAV_EAV_ACT0_ID0 0x150 310 #define CIF_LVDS_SAV_EAV_BLK0_ID0 0x154 311 #define CIF_LVDS_SAV_EAV_ACT1_ID0 0x158 312 #define CIF_LVDS_SAV_EAV_BLK1_ID0 0x15c 313 #define CIF_LVDS_SAV_EAV_ACT0_ID1 0x160 314 #define CIF_LVDS_SAV_EAV_BLK0_ID1 0x164 315 #define CIF_LVDS_SAV_EAV_ACT1_ID1 0x168 316 #define CIF_LVDS_SAV_EAV_BLK1_ID1 0x16c 317 #define CIF_LVDS_SAV_EAV_ACT0_ID2 0x170 318 #define CIF_LVDS_SAV_EAV_BLK0_ID2 0x174 319 #define CIF_LVDS_SAV_EAV_ACT1_ID2 0x178 320 #define CIF_LVDS_SAV_EAV_BLK1_ID2 0x17c 321 #define CIF_LVDS_SAV_EAV_ACT0_ID3 0x180 322 #define CIF_LVDS_SAV_EAV_BLK0_ID3 0x184 323 #define CIF_LVDS_SAV_EAV_ACT1_ID3 0x188 324 #define CIF_LVDS_SAV_EAV_BLK1_ID3 0x18c 325 #define CIF_Y_STAT_CONTROL 0x190 326 #define CIF_Y_STAT_VALUE 0x194 327 #define CIF_MMU_DTE_ADDR 0x800 328 #define CIF_MMU_STATUS 0x804 329 #define CIF_MMU_COMMAND 0x808 330 #define CIF_MMU_PAGE_FAULT_ADDR 0x80c 331 #define CIF_MMU_ZAP_ONE_LINE 0x810 332 #define CIF_MMU_INT_RAWSTAT 0x814 333 #define CIF_MMU_INT_CLEAR 0x818 334 #define CIF_MMU_INT_MASK 0x81c 335 #define CIF_MMU_INT_STATUS 0x820 336 #define CIF_MMU_AUTO_GATING 0x824 337 338 /* RK3588 DVP Registers Offset */ 339 #define DVP_CTRL 0x10 340 #define DVP_INTEN 0x14 341 #define DVP_INTSTAT 0x18 342 #define DVP_FOR 0x1C 343 #define DVP_MULTI_ID 0x20 344 #define DVP_SAV_EAV 0x24 345 #define DVP_CROP_SIZE 0x28 346 #define DVP_CROP 0x2C 347 #define DVP_FRM0_ADDR_Y_ID0 0x30 348 #define DVP_FRM0_ADDR_UV_ID0 0x34 349 #define DVP_FRM1_ADDR_Y_ID0 0x38 350 #define DVP_FRM1_ADDR_UV_ID0 0x3C 351 #define DVP_FRM0_ADDR_Y_ID1 0x40 352 #define DVP_FRM0_ADDR_UV_ID1 0x44 353 #define DVP_FRM1_ADDR_Y_ID1 0x48 354 #define DVP_FRM1_ADDR_UV_ID1 0x4C 355 #define DVP_FRM0_ADDR_Y_ID2 0x50 356 #define DVP_FRM0_ADDR_UV_ID2 0x54 357 #define DVP_FRM1_ADDR_Y_ID2 0x58 358 #define DVP_FRM1_ADDR_UV_ID2 0x5C 359 #define DVP_FRM0_ADDR_Y_ID3 0x60 360 #define DVP_FRM0_ADDR_UV_ID3 0x64 361 #define DVP_FRM1_ADDR_Y_ID3 0x68 362 #define DVP_FRM1_ADDR_UV_ID3 0x6C 363 #define DVP_VIR_LINE_WIDTH 0x70 364 #define DVP_LINE_INT_NUM_01 0x74 365 #define DVP_LINE_INT_NUM_23 0x78 366 #define DVP_LINE_CNT_01 0x7C 367 #define DVP_LINE_CNT_23 0x80 368 369 /* RK3588 CSI Registers Offset */ 370 #define CSI_MIPI0_ID0_CTRL0 0x100 371 #define CSI_MIPI0_ID0_CTRL1 0x104 372 #define CSI_MIPI0_ID1_CTRL0 0x108 373 #define CSI_MIPI0_ID1_CTRL1 0x10C 374 #define CSI_MIPI0_ID2_CTRL0 0x110 375 #define CSI_MIPI0_ID2_CTRL1 0x114 376 #define CSI_MIPI0_ID3_CTRL0 0x118 377 #define CSI_MIPI0_ID3_CTRL1 0x11C 378 #define CSI_MIPI0_CTRL 0x120 379 #define CSI_MIPI0_FRM0_ADDR_Y_ID0 0x124 380 #define CSI_MIPI0_FRM1_ADDR_Y_ID0 0x128 381 #define CSI_MIPI0_FRM0_ADDR_UV_ID0 0x12C 382 #define CSI_MIPI0_FRM1_ADDR_UV_ID0 0x130 383 #define CSI_MIPI0_VLW_ID0 0x134 384 #define CSI_MIPI0_FRM0_ADDR_Y_ID1 0x138 385 #define CSI_MIPI0_FRM1_ADDR_Y_ID1 0x13C 386 #define CSI_MIPI0_FRM0_ADDR_UV_ID1 0x140 387 #define CSI_MIPI0_FRM1_ADDR_UV_ID1 0x144 388 #define CSI_MIPI0_VLW_ID1 0x148 389 #define CSI_MIPI0_FRM0_ADDR_Y_ID2 0x14C 390 #define CSI_MIPI0_FRM1_ADDR_Y_ID2 0x150 391 #define CSI_MIPI0_FRM0_ADDR_UV_ID2 0x154 392 #define CSI_MIPI0_FRM1_ADDR_UV_ID2 0x158 393 #define CSI_MIPI0_VLW_ID2 0x15C 394 #define CSI_MIPI0_FRM0_ADDR_Y_ID3 0x160 395 #define CSI_MIPI0_FRM1_ADDR_Y_ID3 0x164 396 #define CSI_MIPI0_FRM0_ADDR_UV_ID3 0x168 397 #define CSI_MIPI0_FRM1_ADDR_UV_ID3 0x16C 398 #define CSI_MIPI0_VLW_ID3 0x170 399 #define CSI_MIPI0_INTEN 0x174 400 #define CSI_MIPI0_INTSTAT 0x178 401 #define CSI_MIPI0_LINE_INT_NUM_ID0_1 0x17C 402 #define CSI_MIPI0_LINE_INT_NUM_ID2_3 0x180 403 #define CSI_MIPI0_LINE_CNT_ID0_1 0x184 404 #define CSI_MIPI0_LINE_CNT_ID2_3 0x188 405 #define CSI_MIPI0_ID0_CROP_START 0x18C 406 #define CSI_MIPI0_ID1_CROP_START 0x190 407 #define CSI_MIPI0_ID2_CROP_START 0x194 408 #define CSI_MIPI0_ID3_CROP_START 0x198 409 #define CSI_MIPI0_FRAME_NUM_VC0 0x19C 410 #define CSI_MIPI0_FRAME_NUM_VC1 0x1A0 411 #define CSI_MIPI0_FRAME_NUM_VC2 0x1A4 412 #define CSI_MIPI0_FRAME_NUM_VC3 0x1A8 413 #define CSI_MIPI0_EFFECT_CODE_ID0 0x1AC 414 #define CSI_MIPI0_EFFECT_CODE_ID1 0x1B0 415 #define CSI_MIPI0_EFFECT_CODE_ID2 0x1B4 416 #define CSI_MIPI0_EFFECT_CODE_ID3 0x1B8 417 #define CSI_MIPI0_ON_PAD 0x1BC 418 419 /* RK3588 CONTROL Registers Offset */ 420 #define GLB_CTRL 0X000 421 #define GLB_INTEN 0X004 422 #define GLB_INTST 0X008 423 #define SCL_CH_CTRL 0x700 424 #define SCL_CTRL 0x704 425 #define SCL_FRM0_ADDR_CH0 0x708 426 #define SCL_FRM1_ADDR_CH0 0x70C 427 #define SCL_VLW_CH0 0x710 428 #define SCL_FRM0_ADDR_CH1 0x714 429 #define SCL_FRM1_ADDR_CH1 0x718 430 #define SCL_VLW_CH1 0x71C 431 #define SCL_FRM0_ADDR_CH2 0x720 432 #define SCL_FRM1_ADDR_CH2 0x724 433 #define SCL_VLW_CH2 0x728 434 #define SCL_FRM0_ADDR_CH3 0x72C 435 #define SCL_FRM1_ADDR_CH3 0x730 436 #define SCL_VLW_CH3 0x734 437 #define SCL_BLC_CH0 0x738 438 #define SCL_BLC_CH1 0x73C 439 #define SCL_BLC_CH2 0x740 440 #define SCL_BLC_CH3 0x744 441 #define TOISP0_CH_CTRL 0x780 442 #define TOISP0_CROP_SIZE 0x784 443 #define TOISP0_CROP 0x788 444 #define TOISP1_CH_CTRL 0x78C 445 #define TOISP1_CROP_SIZE 0x790 446 #define TOISP1_CROP 0x794 447 448 /* The key register bit description */ 449 450 /* CIF_CTRL Reg */ 451 #define DISABLE_CAPTURE (0x0 << 0) 452 #define ENABLE_CAPTURE (0x1 << 0) 453 #define MODE_ONEFRAME (0x0 << 1) 454 #define MODE_PINGPONG (0x1 << 1) 455 #define MODE_LINELOOP (0x2 << 1) 456 #define AXI_BURST_16 (0xF << 12) 457 #define DVP_PRESS_EN (0x1 << 12) 458 #define DVP_HURRY_EN (0x1 << 8) 459 #define DVP_DMA_EN (0x1 << 1) 460 #define DVP_SW_WATER_LINE_75 (0x0 << 5) 461 #define DVP_SW_WATER_LINE_50 (0x1 << 5) 462 #define DVP_SW_WATER_LINE_25 (0x2 << 5) 463 #define DVP_SW_WATER_LINE_00 (0x3 << 5) 464 465 /* CIF_INTEN */ 466 #define INTEN_DISABLE (0x0 << 0) 467 #define FRAME_END_EN (0x1 << 0) 468 #define BUS_ERR_EN (0x1 << 6) 469 #define SCL_ERR_EN (0x1 << 7) 470 #define PRE_INF_FRAME_END_EN (0x1 << 8) 471 #define PST_INF_FRAME_END_EN (0x1 << 9) 472 #define LINE_INT_EN (0x1 << 10) 473 #define DVP_CHANNEL1_FRM_END_EN (0x1 << 11) 474 #define DVP_CHANNEL2_FRM_END_EN (0x1 << 12) 475 #define DVP_CHANNEL3_FRM_END_EN (0x1 << 13) 476 477 /* CIF INTSTAT */ 478 #define INTSTAT_CLS (0x3FF) 479 #define FRAME_END (0x01 << 0) 480 #define LINE_ERR (0x01 << 2) 481 #define PIX_ERR (0x01 << 3) 482 #define IFIFO_OVERFLOW (0x01 << 4) 483 #define DFIFO_OVERFLOW (0x01 << 5) 484 #define BUS_ERR (0x01 << 6) 485 #define PRE_INF_FRAME_END (0x01 << 8) 486 #define PST_INF_FRAME_END (0x01 << 9) 487 #define LINE_INT_END (0x01 << 10) 488 #define FRAME_END_CLR (0x01 << 0) 489 #define PRE_INF_FRAME_END_CLR (0x01 << 8) 490 #define PST_INF_FRAME_END_CLR (0x01 << 9) 491 #define INTSTAT_ERR (0xFC) 492 #define INTSTAT_ERR_RK3588 (DVP_SIZE_ERR |\ 493 DVP_FIFO_OVERFLOW |\ 494 DVP_BANDWIDTH_LACK) 495 496 #define DVP_ALL_OVERFLOW (IFIFO_OVERFLOW | DFIFO_OVERFLOW) 497 498 #define DVP_FIFO_OVERFLOW (0x01 << 16) 499 #define DVP_BANDWIDTH_LACK (0x01 << 17) 500 501 #define DVP_SIZE_ERR_ID0 (0x1 << 22) 502 #define DVP_SIZE_ERR_ID1 (0x1 << 23) 503 #define DVP_SIZE_ERR_ID2 (0x1 << 24) 504 #define DVP_SIZE_ERR_ID3 (0x1 << 25) 505 506 #define DVP_SIZE_ERR (DVP_SIZE_ERR_ID0 |\ 507 DVP_SIZE_ERR_ID1 |\ 508 DVP_SIZE_ERR_ID2 |\ 509 DVP_SIZE_ERR_ID3) 510 511 #define DVP_SW_PRESS_VALUE(val) (((val) & 0x7) << 13) 512 #define DVP_SW_HURRY_VALUE(val) (((val) & 0x7) << 9) 513 514 #define DVP_DMA_END_INTEN(id) \ 515 ({ \ 516 unsigned int mask; \ 517 switch (id) { \ 518 case 0: \ 519 mask = 0x1 << 0; \ 520 break; \ 521 default: \ 522 mask = 0x1 << (id + 10); \ 523 break; \ 524 } \ 525 mask; \ 526 }) 527 528 #define DVP_LINE_INTEN (0x01 << 10) 529 530 #define DVP_DMA_END_INTSTAT(id) \ 531 ({ \ 532 unsigned int mask; \ 533 switch (id) { \ 534 case 0: \ 535 mask = 0x1 << 0; \ 536 break; \ 537 default: \ 538 mask = 0x1 << (id + 10); \ 539 break; \ 540 } \ 541 mask; \ 542 }) 543 544 #define DVP_PST_INTSTAT PST_INF_FRAME_END 545 #define DVP_LINE_INTSTAT (0x01 << 10) 546 547 /* FRAME STATUS */ 548 #define FRAME_STAT_CLS 0x00 549 /* write 0 to clear frame 0 */ 550 #define FRM0_STAT_CLS 0xfffffffe 551 #define FRAME_NUM_SHIFT (16U) 552 #define FRAME_NUM_MASK (0xffff << FRAME_NUM_SHIFT) 553 #define CIF_GET_FRAME_ID(val) (((val) & FRAME_NUM_MASK) >> FRAME_NUM_SHIFT) 554 555 /* CIF FORMAT */ 556 #define VSY_HIGH_ACTIVE (0x01 << 0) 557 #define VSY_LOW_ACTIVE (0x00 << 0) 558 #define HSY_LOW_ACTIVE (0x01 << 1) 559 #define HSY_HIGH_ACTIVE (0x00 << 1) 560 #define INPUT_MODE_YUV (0x00 << 2) 561 #define INPUT_MODE_PAL (0x02 << 2) 562 #define INPUT_MODE_BT656_YUV422 (0x02 << 2) 563 #define INPUT_MODE_NTSC (0x03 << 2) 564 #define INPUT_MODE_BT1120 (0x07 << 2) 565 #define INPUT_MODE_RAW (0x04 << 2) 566 #define INPUT_MODE_JPEG (0x05 << 2) 567 #define INPUT_MODE_SONY_RAW (0x05 << 2) 568 #define INPUT_MODE_MIPI (0x06 << 2) 569 #define YUV_INPUT_ORDER_UYVY (0x00 << 5) 570 #define YUV_INPUT_ORDER_YVYU (0x01 << 5) 571 #define YUV_INPUT_ORDER_VYUY (0x10 << 5) 572 #define YUV_INPUT_ORDER_YUYV (0x03 << 5) 573 #define YUV_INPUT_422 (0x00 << 7) 574 #define YUV_INPUT_420 (0x01 << 7) 575 #define INPUT_420_ORDER_EVEN (0x00 << 8) 576 #define INPUT_420_ORDER_ODD (0x01 << 8) 577 #define CCIR_INPUT_ORDER_ODD (0x00 << 9) 578 #define CCIR_INPUT_ORDER_EVEN (0x01 << 9) 579 #define RAW_DATA_WIDTH_8 (0x00 << 11) 580 #define RAW_DATA_WIDTH_10 (0x01 << 11) 581 #define RAW_DATA_WIDTH_12 (0x02 << 11) 582 #define MIPI_MODE_32BITS_BYPASS (0x00 << 13) 583 #define MIPI_MODE_RGB (0x01 << 13) 584 #define MIPI_MODE_YUV (0x02 << 13) 585 #define YUV_OUTPUT_422 (0x00 << 16) 586 #define YUV_OUTPUT_420 (0x01 << 16) 587 #define OUTPUT_420_ORDER_EVEN (0x00 << 17) 588 #define OUTPUT_420_ORDER_ODD (0x01 << 17) 589 #define RAWD_DATA_LITTLE_ENDIAN (0x00 << 18) 590 #define RAWD_DATA_BIG_ENDIAN (0x01 << 18) 591 #define UV_STORAGE_ORDER_UVUV (0x00 << 19) 592 #define UV_STORAGE_ORDER_VUVU (0x01 << 19) 593 #define BT1120_CLOCK_SINGLE_EDGES (0x00 << 24) 594 #define BT1120_CLOCK_DOUBLE_EDGES (0x01 << 24) 595 #define BT1120_TRANSMIT_INTERFACE (0x00 << 25) 596 #define BT1120_TRANSMIT_PROGRESS (0x01 << 25) 597 #define BT1120_YC_SWAP (0x01 << 26) 598 #define BT656_1120_MULTI_ID_DISABLE (0x00 << 28) 599 #define BT656_1120_MULTI_ID_ENABLE (0x01 << 28) 600 #define BT656_1120_MULTI_ID_SEL_MSB (0x00 << 29) 601 #define BT656_1120_MULTI_ID_SEL_LSB (0x01 << 29) 602 #define BT656_1120_MULTI_ID_MODE_1 (0x00 << 30) 603 #define BT656_1120_MULTI_ID_MODE_2 (0x01 << 30) 604 #define BT656_1120_MULTI_ID_MODE_4 (0x02 << 30) 605 #define BT656_1120_MULTI_ID_0_MASK ~(0x03 << 4) 606 #define BT656_1120_MULTI_ID_1_MASK ~(0x03 << 12) 607 #define BT656_1120_MULTI_ID_2_MASK ~(0x03 << 20) 608 #define BT656_1120_MULTI_ID_3_MASK ~(0x03 << 28) 609 #define CIF_HIGH_ALIGN (0x01 << 18) 610 #define CIF_HIGH_ALIGN_RK3588 (0x01 << 21) 611 #define BT656_DETECT_SAV (0X01 << 13) 612 #define BT656_DETECT_SAV_EAV (0X00 << 13) 613 614 #define BT1120_CLOCK_SINGLE_EDGES_RK3588 (0x00 << 11) 615 #define BT1120_CLOCK_DOUBLE_EDGES_RK3588 (0x01 << 11) 616 #define TRANSMIT_INTERFACE_RK3588 (0x01 << 9) 617 #define TRANSMIT_PROGRESS_RK3588 (0x00 << 9) 618 #define BT1120_YC_SWAP_RK3588 (0x01 << 12) 619 #define INPUT_BT601_YUV422 (0x00 << 2) 620 #define INPUT_BT601_RAW (0x01 << 2) 621 #define INPUT_BT656_YUV422 (0x02 << 2) 622 #define INPUT_BT1120_YUV422 (0x03 << 2) 623 #define INPUT_SONY_RAW (0x04 << 2) 624 625 /* CIF_SCL_CTRL */ 626 #define ENABLE_SCL_DOWN (0x01 << 0) 627 #define DISABLE_SCL_DOWN (0x00 << 0) 628 #define ENABLE_SCL_UP (0x01 << 1) 629 #define DISABLE_SCL_UP (0x00 << 1) 630 #define ENABLE_YUV_16BIT_BYPASS (0x01 << 4) 631 #define DISABLE_YUV_16BIT_BYPASS (0x00 << 4) 632 #define ENABLE_RAW_16BIT_BYPASS (0x01 << 5) 633 #define DISABLE_RAW_16BIT_BYPASS (0x00 << 5) 634 #define ENABLE_32BIT_BYPASS (0x01 << 6) 635 #define DISABLE_32BIT_BYPASS (0x00 << 6) 636 637 /* CIF_FRAME_INTSTAT */ 638 #define CIF_F0_READY (0x01 << 0) 639 #define CIF_F1_READY (0x01 << 1) 640 #define DVP_CHANNEL0_FRM_READ (CIF_F0_READY | CIF_F1_READY) 641 #define DVP_CHANNEL1_F0_READY (0x01 << 4) 642 #define DVP_CHANNEL1_F1_READY (0x01 << 5) 643 #define DVP_CHANNEL1_FRM_READ (DVP_CHANNEL1_F0_READY | DVP_CHANNEL1_F1_READY) 644 #define DVP_CHANNEL2_F0_READY (0x01 << 8) 645 #define DVP_CHANNEL2_F1_READY (0x01 << 9) 646 #define DVP_CHANNEL2_FRM_READ (DVP_CHANNEL2_F0_READY | DVP_CHANNEL2_F1_READY) 647 #define DVP_CHANNEL3_F0_READY (0x01 << 12) 648 #define DVP_CHANNEL3_F1_READY (0x01 << 13) 649 #define DVP_CHANNEL3_FRM_READ (DVP_CHANNEL3_F0_READY | DVP_CHANNEL3_F1_READY) 650 651 #define DVP_FRAME0_START_ID0 (0x1 << 0) 652 #define DVP_FRAME1_START_ID0 (0x1 << 1) 653 654 #define DVP_FRAME_END_ID0 (0x1 << 0) 655 #define DVP_FRAME_END_ID1 (0x1 << 11) 656 #define DVP_FRAME_END_ID2 (0x1 << 12) 657 #define DVP_FRAME_END_ID3 (0x1 << 13) 658 659 #define DVP_FRAME0_END_ID0 (0x1 << 8) 660 #define DVP_FRAME1_END_ID0 (0x1 << 9) 661 #define DVP_ALL_END_ID0 (DVP_FRAME0_END_ID0 | DVP_FRAME1_END_ID0) 662 663 #define DVP_FRAME0_END_ID1 (0x1 << 10) 664 #define DVP_FRAME1_END_ID1 (0x1 << 11) 665 #define DVP_ALL_END_ID1 (DVP_FRAME0_END_ID1 | DVP_FRAME1_END_ID1) 666 667 #define DVP_FRAME0_END_ID2 (0x1 << 12) 668 #define DVP_FRAME1_END_ID2 (0x1 << 13) 669 #define DVP_ALL_END_ID2 (DVP_FRAME0_END_ID2 | DVP_FRAME1_END_ID2) 670 671 #define DVP_FRAME0_END_ID3 (0x1 << 14) 672 #define DVP_FRAME1_END_ID3 (0x1 << 15) 673 #define DVP_ALL_END_ID3 (DVP_FRAME0_END_ID3 | DVP_FRAME1_END_ID3) 674 675 #define DVP_ALIGN_MSB (0x01 << 21) 676 #define DVP_ALIGN_LSB (0x00 << 21) 677 678 #define DVP_FRM_STS_ID0(x) (((x) & (0x3 << 0)) >> 0) 679 #define DVP_FRM_STS_ID1(x) (((x) & (0x3 << 4)) >> 4) 680 #define DVP_FRM_STS_ID2(x) (((x) & (0x3 << 8)) >> 8) 681 #define DVP_FRM_STS_ID3(x) (((x) & (0x3 << 12)) >> 12) 682 683 #define DVP_SW_MULTI_ID(channel, id, bits) \ 684 ({ \ 685 unsigned int mask; \ 686 switch (channel) { \ 687 case 0: \ 688 mask = ((bits) << 4) | ((id) << 0); \ 689 break; \ 690 case 1: \ 691 mask = ((bits) << 12) | ((id) << 8); \ 692 break; \ 693 case 2: \ 694 mask = ((bits) << 20) | ((id) << 16); \ 695 break; \ 696 case 3: \ 697 mask = ((bits) << 28) | ((id) << 24); \ 698 break; \ 699 default: \ 700 mask = ((bits) << 4) | ((id) << 0); \ 701 break; \ 702 } \ 703 mask; \ 704 }) 705 706 /* CIF CROP */ 707 #define CIF_CROP_Y_SHIFT 16 708 #define CIF_CROP_X_SHIFT 0 709 710 /* CIF SCALE*/ 711 #define SCALE_END_INTSTAT(ch) (0x3 << ((ch + 1) * 2)) 712 #define SCALE_FIFO_OVERFLOW(ch) (1 << (10 + ch)) 713 #define SCALE_TOISP_AXI0_ERR (1 << 0) 714 #define SCALE_TOISP_AXI1_ERR (1 << 1) 715 #define CIF_SCALE_SW_PRESS_VALUE(val) (((val) & 0x7) << 13) 716 #define CIF_SCALE_SW_PRESS_ENABLE (0x1 << 12) 717 #define CIF_SCALE_SW_HURRY_VALUE(val) (((val) & 0x7) << 5) 718 #define CIF_SCALE_SW_HURRY_ENABLE (0x1 << 4) 719 #define CIF_SCALE_SW_WATER_LINE(val) (val << 1) 720 #define CIF_SCALE_SW_SRC_CH(val, ch) ((val & 0x1f) << (3 + ch * 8)) 721 #define CIF_SCALE_SW_MODE(val, ch) ((val & 0x3) << (1 + ch * 8)) 722 #define CIF_SCALE_EN(ch) (1 << (ch * 8)) 723 #define SW_SCALE_END(intstat, ch) ((intstat >> ((ch + 1) * 2)) & 0x3) 724 #define SCALE_SOFT_RESET(ch) (0x1 << (ch + 16)) 725 726 /* CIF_CSI_ID_CTRL0 */ 727 #define CSI_DISABLE_CAPTURE (0x0 << 0) 728 #define CSI_ENABLE_CAPTURE (0x1 << 0) 729 #define CSI_WRDDR_TYPE_RAW8 (0x0 << 1) 730 #define CSI_WRDDR_TYPE_RAW10 (0x1 << 1) 731 #define CSI_WRDDR_TYPE_RAW12 (0x2 << 1) 732 #define CSI_WRDDR_TYPE_RGB888 (0x3 << 1) 733 #define CSI_WRDDR_TYPE_YUV422 (0x4 << 1) 734 #define CSI_WRDDR_TYPE_YUV420SP (0x5 << 1) 735 #define CSI_WRDDR_TYPE_YUV400 (0x6 << 1) 736 #define CSI_DISABLE_COMMAND_MODE (0x0 << 4) 737 #define CSI_ENABLE_COMMAND_MODE (0x1 << 4) 738 #define CSI_DISABLE_CROP (0x0 << 5) 739 #define CSI_ENABLE_CROP (0x1 << 5) 740 #define CSI_DISABLE_CROP_V1 (0x0 << 4) 741 #define CSI_ENABLE_CROP_V1 (0x1 << 4) 742 #define CSI_ENABLE_MIPI_COMPACT (0x1 << 6) 743 #define CSI_YUV_INPUT_ORDER_UYVY (0x0 << 16) 744 #define CSI_YUV_INPUT_ORDER_VYUY (0x1 << 16) 745 #define CSI_YUV_INPUT_ORDER_YUYV (0x2 << 16) 746 #define CSI_YUV_INPUT_ORDER_YVYU (0x3 << 16) 747 #define CSI_HIGH_ALIGN (0x1 << 31) 748 #define CSI_HIGH_ALIGN_RK3588 (0x1 << 27) 749 750 #define CSI_YUV_OUTPUT_ORDER_UYVY (0x0 << 18) 751 #define CSI_YUV_OUTPUT_ORDER_VYUY (0x1 << 18) 752 #define CSI_YUV_OUTPUT_ORDER_YUYV (0x2 << 18) 753 #define CSI_YUV_OUTPUT_ORDER_YVYU (0x3 << 18) 754 #define CSI_WRDDR_TYPE_RAW_COMPACT (0x0 << 5) 755 #define CSI_WRDDR_TYPE_RAW_UNCOMPACT (0x1 << 5) 756 #define CSI_WRDDR_TYPE_YUV_PACKET (0x2 << 5) 757 #define CSI_WRDDR_TYPE_YUV400_RK3588 (0x3 << 5) 758 #define CSI_WRDDR_TYPE_YUV422SP_RK3588 (0x4 << 5) 759 #define CSI_WRDDR_TYPE_YUV420SP_RK3588 (0x5 << 5) 760 #define CSI_ALIGN_MSB (0x01 << 27) 761 #define CSI_ALIGN_LSB (0x0 << 27) 762 #define CSI_DMA_ENABLE (0x1 << 28) 763 764 #define CSI_NO_HDR (0X0 << 22) 765 #define CSI_HDR2 (0X1 << 22) 766 #define CSI_HDR3 (0X2 << 22) 767 768 #define CSI_HDR_MODE_VC (0x0 << 20) 769 #define CSI_HDR_MODE_LINE_CNT (0x1 << 20) 770 #define CSI_HDR_MODE_LINE_INFO (0x2 << 20) 771 #define CSI_HDR_VC_MODE_PROTECT (0x1 << 29) 772 773 #define LVDS_ENABLE_CAPTURE (0x1 << 16) 774 #define LVDS_MODE(mode) (((mode) & 0x7) << 17) 775 #define LVDS_LANES_ENABLED(lanes) \ 776 ({ \ 777 unsigned int mask; \ 778 switch (lanes) { \ 779 case 1: \ 780 mask = 0x1 << 20; \ 781 break; \ 782 case 2: \ 783 mask = 0x3 << 20; \ 784 break; \ 785 case 3: \ 786 mask = 0x7 << 20; \ 787 break; \ 788 case 4: \ 789 mask = 0xf << 20; \ 790 break; \ 791 default: \ 792 mask = 0x1 << 20; \ 793 break; \ 794 } \ 795 mask; \ 796 }) 797 798 #define LVDS_MAIN_LANE(index) (((index) & 0x3) << 24) 799 #define LVDS_FID(id) (((id) & 0x3) << 26) 800 #define LVDS_HDR_FRAME_X2 (0x0 << 28) 801 #define LVDS_HDR_FRAME_X3 (0x1 << 28) 802 #define LVDS_COMPACT (0x1 << 29) 803 804 /* CIF_CSI_INTEN */ 805 #define CSI_FRAME1_START_INTEN(id) (0x1 << ((id) * 2 + 1)) 806 #define CSI_FRAME0_END_INTEN(id) (0x1 << ((id) * 2 + 8)) 807 #define CSI_FRAME1_END_INTEN(id) (0x1 << ((id) * 2 + 9)) 808 #define CSI_DMA_Y_FIFO_OVERFLOW_INTEN (0x1 << 16) 809 #define CSI_DMA_UV_FIFO_OVERFLOW_INTEN (0x1 << 17) 810 #define CSI_CONFIG_FIFO_OVERFLOW_INTEN (0x1 << 18) 811 #define CSI_BANDWIDTH_LACK_INTEN (0x1 << 19) 812 #define CSI_RX_FIFO_OVERFLOW_INTEN (0x1 << 20) 813 #define CSI_ALL_FRAME_START_INTEN (0xff << 0) 814 #define CSI_ALL_FRAME_END_INTEN (0xff << 8) 815 #define CSI_ALL_ERROR_INTEN (0x1f << 16) 816 #define CSI_ALL_ERROR_INTEN_V1 (0xf0f << 16) 817 818 #define CSI_START_INTEN(id) (0x3 << ((id) * 2)) 819 #define CSI_DMA_END_INTEN(id) (0x3 << ((id) * 2 + 8)) 820 #define CSI_LINE_INTEN(id) (0x1 << ((id) + 21)) 821 #define CSI_LINE_INTEN_RK3588(id) (0x1 << ((id) + 20)) 822 823 #define CSI_START_INTSTAT(id) (0x3 << ((id) * 2)) 824 #define CSI_DMA_END_INTSTAT(id) (0x3 << ((id) * 2 + 8)) 825 #define CSI_LINE_INTSTAT(id) (0x1 << ((id) + 21)) 826 #define CSI_LINE_INTSTAT_V1(id) (0x1 << ((id) + 20)) 827 828 /* CIF_CSI_INTSTAT */ 829 #define CSI_FRAME0_START_ID0 (0x1 << 0) 830 #define CSI_FRAME1_START_ID0 (0x1 << 1) 831 #define CSI_FRAME0_START_ID1 (0x1 << 2) 832 #define CSI_FRAME1_START_ID1 (0x1 << 3) 833 #define CSI_FRAME0_START_ID2 (0x1 << 4) 834 #define CSI_FRAME1_START_ID2 (0x1 << 5) 835 #define CSI_FRAME0_START_ID3 (0x1 << 6) 836 #define CSI_FRAME1_START_ID3 (0x1 << 7) 837 #define CSI_FRAME0_END_ID0 (0x1 << 8) 838 #define CSI_FRAME1_END_ID0 (0x1 << 9) 839 #define CSI_FRAME0_END_ID1 (0x1 << 10) 840 #define CSI_FRAME1_END_ID1 (0x1 << 11) 841 #define CSI_FRAME0_END_ID2 (0x1 << 12) 842 #define CSI_FRAME1_END_ID2 (0x1 << 13) 843 #define CSI_FRAME0_END_ID3 (0x1 << 14) 844 #define CSI_FRAME1_END_ID3 (0x1 << 15) 845 #define CSI_DMA_Y_FIFO_OVERFLOW (0x1 << 16) 846 #define CSI_DMA_UV_FIFO_OVERFLOW (0x1 << 17) 847 #define CSI_CONFIG_FIFO_OVERFLOW (0x1 << 18) 848 #define CSI_BANDWIDTH_LACK (0x1 << 19) 849 #define CSI_RX_FIFO_OVERFLOW (0x1 << 20) 850 #define CSI_LINE_ID0_INTST (0x1 << 21) 851 #define CSI_LINE_ID1_INTST (0x1 << 22) 852 #define CSI_LINE_ID2_INTST (0x1 << 23) 853 #define CSI_LINE_ID3_INTST (0x1 << 24) 854 #define CSI_DMA_LVDS_ID2_FIFO_OVERFLOW (0x1 << 25) 855 #define CSI_DMA_LVDS_ID3_FIFO_OVERFLOW (0x1 << 26) 856 #define CSI_SIZE_ERR_ID0 (0x1 << 24) 857 #define CSI_SIZE_ERR_ID1 (0x1 << 25) 858 #define CSI_SIZE_ERR_ID2 (0x1 << 26) 859 #define CSI_SIZE_ERR_ID3 (0x1 << 27) 860 861 #define CSI_FRAME_START_ID0 (CSI_FRAME0_START_ID0 |\ 862 CSI_FRAME1_START_ID0) 863 #define CSI_FRAME_START_ID1 (CSI_FRAME0_START_ID1 |\ 864 CSI_FRAME1_START_ID1) 865 #define CSI_FRAME_START_ID2 (CSI_FRAME0_START_ID2 |\ 866 CSI_FRAME1_START_ID2) 867 #define CSI_FRAME_START_ID3 (CSI_FRAME0_START_ID3 |\ 868 CSI_FRAME1_START_ID3) 869 #define CSI_FRAME_END_ID0 (CSI_FRAME0_END_ID0 |\ 870 CSI_FRAME1_END_ID0) 871 #define CSI_FRAME_END_ID1 (CSI_FRAME0_END_ID1 |\ 872 CSI_FRAME1_END_ID1) 873 #define CSI_FRAME_END_ID2 (CSI_FRAME0_END_ID2 |\ 874 CSI_FRAME1_END_ID2) 875 #define CSI_FRAME_END_ID3 (CSI_FRAME0_END_ID3 |\ 876 CSI_FRAME1_END_ID3) 877 #define CSI_FIFO_OVERFLOW (CSI_DMA_Y_FIFO_OVERFLOW |\ 878 CSI_DMA_UV_FIFO_OVERFLOW |\ 879 CSI_CONFIG_FIFO_OVERFLOW |\ 880 CSI_RX_FIFO_OVERFLOW |\ 881 CSI_DMA_LVDS_ID2_FIFO_OVERFLOW |\ 882 CSI_DMA_LVDS_ID3_FIFO_OVERFLOW) 883 884 /*mask for rk3588*/ 885 #define CSI_RX_FIFO_OVERFLOW_V1 (0x1 << 19) 886 #define CSI_BANDWIDTH_LACK_V1 (0x1 << 18) 887 #define CSI_ALL_ERROR_INTEN_V1 (0xf0f << 16) 888 889 890 #define CSI_FIFO_OVERFLOW_V1 (CSI_DMA_Y_FIFO_OVERFLOW |\ 891 CSI_DMA_UV_FIFO_OVERFLOW |\ 892 CSI_RX_FIFO_OVERFLOW_V1) 893 #define CSI_SIZE_ERR (CSI_SIZE_ERR_ID0 |\ 894 CSI_SIZE_ERR_ID1 |\ 895 CSI_SIZE_ERR_ID2 |\ 896 CSI_SIZE_ERR_ID3) 897 898 /* CIF_MIPI_LVDS_CTRL */ 899 #define CIF_MIPI_LVDS_SW_DMA_IDLE (0x1 << 16) 900 #define CIF_MIPI_LVDS_SW_PRESS_VALUE(val) (((val) & 0x3) << 13) 901 #define CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(val) (((val) & 0x7) << 13) 902 #define CIF_MIPI_LVDS_SW_PRESS_ENABLE (0x1 << 12) 903 #define CIF_MIPI_LVDS_SW_LVDS_WIDTH_8BITS (0x0 << 9) 904 #define CIF_MIPI_LVDS_SW_LVDS_WIDTH_10BITS (0x1 << 9) 905 #define CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS (0x2 << 9) 906 #define CIF_MIPI_LVDS_SW_SEL_LVDS (0x1 << 8) 907 #define CIF_MIPI_LVDS_SW_HURRY_VALUE(val) (((val) & 0x3) << 5) 908 #define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(val) (((val) & 0x7) << 5) 909 #define CIF_MIPI_LVDS_SW_HURRY_ENABLE (0x1 << 4) 910 #define CIF_MIPI_LVDS_SW_WATER_LINE_75 (0x0 << 1) 911 #define CIF_MIPI_LVDS_SW_WATER_LINE_50 (0x1 << 1) 912 #define CIF_MIPI_LVDS_SW_WATER_LINE_25 (0x2 << 1) 913 #define CIF_MIPI_LVDS_SW_WATER_LINE_00 (0x3 << 1) 914 #define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE (0x1 << 0) 915 #define CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808 (0x1 << 24) 916 #define CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(val) (((val) & 0x3) << 17) 917 #define CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808 (0x1 << 16) 918 #define CIF_MIPI_LVDS_SW_WATER_LINE_75_RK1808 (0x0 << 0) 919 #define CIF_MIPI_LVDS_SW_WATER_LINE_50_RK1808 (0x1 << 0) 920 #define CIF_MIPI_LVDS_SW_WATER_LINE_25_RK1808 (0x2 << 0) 921 #define CIF_MIPI_LVDS_SW_WATER_LINE_00_RK1808 (0x3 << 0) 922 #define CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE_RK1808 (0x1 << 4) 923 924 /* CSI Host Registers Define */ 925 #define CSIHOST_N_LANES 0x04 926 #define CSIHOST_PHY_RSTZ 0x0c 927 #define CSIHOST_RESETN 0x10 928 #define CSIHOST_ERR1 0x20 929 #define CSIHOST_ERR2 0x24 930 #define CSIHOST_MSK1 0x28 931 #define CSIHOST_MSK2 0x2c 932 #define CSIHOST_CONTROL 0x40 933 934 #define SW_CPHY_EN(x) ((x) << 0) 935 #define SW_DSI_EN(x) ((x) << 4) 936 #define SW_DATATYPE_FS(x) ((x) << 8) 937 #define SW_DATATYPE_FE(x) ((x) << 14) 938 #define SW_DATATYPE_LS(x) ((x) << 20) 939 #define SW_DATATYPE_LE(x) ((x) << 26) 940 941 #define SW_FRM_END_ID0(x) (((x) & CSI_FRAME_END_ID0) >> 8) 942 #define SW_FRM_END_ID1(x) (((x) & CSI_FRAME_END_ID1) >> 10) 943 #define SW_FRM_END_ID2(x) (((x) & CSI_FRAME_END_ID2) >> 12) 944 #define SW_FRM_END_ID3(x) (((x) & CSI_FRAME_END_ID3) >> 14) 945 946 /* CIF LVDS SAV EAV Define */ 947 #define SW_LVDS_EAV_ACT(code) (((code) & 0xfff) << 16) 948 #define SW_LVDS_SAV_ACT(code) (((code) & 0xfff) << 0) 949 #define SW_LVDS_EAV_BLK(code) (((code) & 0xfff) << 16) 950 #define SW_LVDS_SAV_BLK(code) (((code) & 0xfff) << 0) 951 952 /* GRF related with CIF */ 953 #define CIF_GRF_CIFIO_CON (0x10250) 954 #define CIF_PCLK_SAMPLING_EDGE_RISING (0x04000400) 955 #define CIF_PCLK_SAMPLING_EDGE_FALLING (0x04000000) 956 #define CIF_PCLK_DELAY_ENABLE (0x02000200) 957 #define CIF_PCLK_DELAY_DISABLE (0x02000000) 958 #define CIF_SAMPLING_EDGE_DOUBLE (0x01000100) 959 #define CIF_SAMPLING_EDGE_SINGLE (0x01000000) 960 #define CIF_PCLK_DELAY_NUM(num) (0x00ff0000 | ((num) & 0xff)) 961 #define CIF_GRF_VI_CON0 (0x340) 962 #define CIF_GRF_VI_CON1 (0x344) 963 #define RK3568_CIF_PCLK_SAMPLING_EDGE_RISING (0x10000000) 964 #define RK3568_CIF_PCLK_SAMPLING_EDGE_FALLING (0x10001000) 965 #define RK3568_CIF_PCLK_SINGLE_EDGE (0x02000000) 966 #define RK3568_CIF_PCLK_DUAL_EDGE (0x02000200) 967 #define CIF_GRF_SOC_CON2 (0x308) 968 #define RK3588_CIF_PCLK_SAMPLING_EDGE_RISING (0x00100000) 969 #define RK3588_CIF_PCLK_SAMPLING_EDGE_FALLING (0x00100010) 970 #define RK3588_CIF_PCLK_SINGLE_EDGE (0x00200000) 971 #define RK3588_CIF_PCLK_DUAL_EDGE (0x00200020) 972 973 974 /*toisp*/ 975 #define TOISP_END_CH0(index) (0x1 << (20 + index * 3)) 976 #define TOISP_END_CH1(index) (0x1 << (21 + index * 3)) 977 #define TOISP_END_CH2(index) (0x1 << (22 + index * 3)) 978 979 #endif 980