1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * gc8034 driver
4 *
5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 add poweron function.
8 * V0.0X01.0X02 fix mclk issue when probe multiple camera.
9 * V0.0X01.0X03 add enum_frame_interval function.
10 * V0.0X01.0X04 add quick stream on/off
11 * V0.0X01.0X05 add function g_mbus_config
12 * V0.0X01.0X06
13 * 1. add 2lane support.
14 * 2. add some debug info.
15 * 3. adjust gc8034_g_mbus_config function.
16 * V0.0X01.0X06 support get channel info
17 */
18
19 #include <linux/clk.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/i2c.h>
24 #include <linux/module.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/of.h>
27 #include <linux/of_graph.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/sysfs.h>
30 #include <linux/version.h>
31 #include <linux/rk-camera-module.h>
32 #include <media/media-entity.h>
33 #include <media/v4l2-async.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-fwnode.h>
38 #include <media/v4l2-image-sizes.h>
39 #include <media/v4l2-mediabus.h>
40 #include <media/v4l2-subdev.h>
41 #include <linux/pinctrl/consumer.h>
42 #include <linux/slab.h>
43
44 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
45
46 #ifndef V4L2_CID_DIGITAL_GAIN
47 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
48 #endif
49
50 #define GC8034_LANES 4
51 #define GC8034_BITS_PER_SAMPLE 10
52 #define GC8034_MIPI_FREQ_336MHZ 336000000U
53
54 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
55 #define GC8034_PIXEL_RATE 288000000
56 #define GC8034_XVCLK_FREQ 24000000
57
58 #define CHIP_ID 0x8044
59 #define GC8034_REG_CHIP_ID_H 0xf0
60 #define GC8034_REG_CHIP_ID_L 0xf1
61
62 #define GC8034_REG_SET_PAGE 0xfe
63 #define GC8034_SET_PAGE_ZERO 0x00
64
65 #define GC8034_REG_CTRL_MODE 0x3f
66 #define GC8034_MODE_SW_STANDBY 0x00
67 #define GC8034_MODE_STREAMING 0xd0
68
69 #define GC8034_REG_EXPOSURE_H 0x03
70 #define GC8034_REG_EXPOSURE_L 0x04
71 #define GC8034_FETCH_HIGH_BYTE_EXP(VAL) (((VAL) >> 8) & 0x7F) /* 4 Bits */
72 #define GC8034_FETCH_LOW_BYTE_EXP(VAL) ((VAL) & 0xFF) /* 8 Bits */
73 #define GC8034_EXPOSURE_MIN 4
74 #define GC8034_EXPOSURE_STEP 1
75 #define GC8034_VTS_MAX 0x1fff
76
77 #define GC8034_REG_AGAIN 0xb6
78 #define GC8034_REG_DGAIN_INT 0xb1
79 #define GC8034_REG_DGAIN_FRAC 0xb2
80 #define GC8034_GAIN_MIN 64
81 #define GC8034_GAIN_MAX 1092
82 #define GC8034_GAIN_STEP 1
83 #define GC8034_GAIN_DEFAULT 64
84
85 #define GC8034_REG_VTS_H 0x07
86 #define GC8034_REG_VTS_L 0x08
87
88 #define REG_NULL 0xFF
89
90 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
91 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
92
93 #define GC8034_NAME "gc8034"
94 #define GC8034_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
95
96 static const char * const gc8034_supply_names[] = {
97 "avdd", /* Analog power */
98 "dovdd", /* Digital I/O power */
99 "dvdd", /* Digital core power */
100 };
101
102 static const struct regval *gc8034_global_regs;
103 #define GC8034_NUM_SUPPLIES ARRAY_SIZE(gc8034_supply_names)
104
105 struct gc8034_dd {
106 u16 x;
107 u16 y;
108 u16 t;
109 };
110
111 struct gc8034_otp_info {
112 int flag; //bit[7]: info bit[6]:wb bit[5]:vcm bit[4]:lenc
113 //bit[3] dd bit[2] chip version
114 u32 module_id;
115 u32 lens_id;
116 u32 year;
117 u32 month;
118 u32 day;
119 u32 rg_ratio;
120 u32 bg_ratio;
121 u32 golden_rg;
122 u32 golden_bg;
123 u8 lsc[396];
124 u32 vcm_start;
125 u32 vcm_end;
126 u32 vcm_dir;
127 u32 dd_cnt;
128 struct gc8034_dd dd_param[160];
129 u16 reg_page[5];
130 u16 reg_addr[5];
131 u16 reg_value[5];
132 u16 reg_num;
133 };
134
135 struct gc8034_id_name {
136 u32 id;
137 char name[RKMODULE_NAME_LEN];
138 };
139
140 static const struct gc8034_id_name gc8034_module_info[] = {
141 {0x0d, "CameraKing"},
142 {0x00, "Unknown"}
143 };
144
145 static const struct gc8034_id_name gc8034_lens_info[] = {
146 {0xd0, "CK8401"},
147 {0x00, "Unknown"}
148 };
149
150 struct regval {
151 u8 addr;
152 u8 val;
153 };
154
155 struct gc8034_mode {
156 u32 width;
157 u32 height;
158 struct v4l2_fract max_fps;
159 u32 hts_def;
160 u32 vts_def;
161 u32 exp_def;
162 const struct regval *reg_list;
163 u32 vc[PAD_MAX];
164 };
165
166 struct gc8034 {
167 struct i2c_client *client;
168 struct clk *xvclk;
169 struct gpio_desc *power_gpio;
170 struct gpio_desc *reset_gpio;
171 struct gpio_desc *pwdn_gpio;
172 struct regulator_bulk_data supplies[GC8034_NUM_SUPPLIES];
173 struct pinctrl *pinctrl;
174 struct pinctrl_state *pins_default;
175 struct pinctrl_state *pins_sleep;
176 struct v4l2_subdev subdev;
177 struct media_pad pad;
178 struct v4l2_ctrl_handler ctrl_handler;
179 struct v4l2_ctrl *exposure;
180 struct v4l2_ctrl *anal_gain;
181 struct v4l2_ctrl *digi_gain;
182 struct v4l2_ctrl *hblank;
183 struct v4l2_ctrl *vblank;
184 struct v4l2_ctrl *link_freq;
185 struct mutex mutex;
186 bool streaming;
187 unsigned int lane_num;
188 unsigned int cfg_num;
189 unsigned int pixel_rate;
190 bool power_on;
191 const struct gc8034_mode *cur_mode;
192 u32 module_index;
193 const char *module_facing;
194 const char *module_name;
195 const char *len_name;
196 u32 Dgain_ratio;
197 struct gc8034_otp_info *otp;
198 struct rkmodule_inf module_inf;
199 struct rkmodule_awb_cfg awb_cfg;
200 };
201
202 #define to_gc8034(sd) container_of(sd, struct gc8034, subdev)
203
204 #undef GC8034_MIRROR_NORMAL
205 #undef GC8034_MIRROR_H
206 #undef GC8034_MIRROR_V
207 #undef GC8034_MIRROR_HV
208 /* If you use the otp function, keep the otp_drv ->
209 * gc8034_common_otp_drv.h consistent.
210 */
211 #define GC8034_MIRROR_NORMAL
212
213 #if defined(GC8034_MIRROR_NORMAL)
214 #define GC8034_MIRROR 0xc0
215 #define BINNING_STARTY 0x04
216 #define BINNING_STARTX 0x05
217 #define FULL_STARTY 0x08
218 #define FULL_STARTX 0x09
219 #elif defined(GC8034_MIRROR_H)
220 #define GC8034_MIRROR 0xc1
221 #define BINNING_STARTY 0x04
222 #define BINNING_STARTX 0x04
223 #define FULL_STARTY 0x08
224 #define FULL_STARTX 0x08
225 #elif defined(GC8034_MIRROR_V)
226 #define GC8034_MIRROR 0xc2
227 #define BINNING_STARTY 0x05
228 #define BINNING_STARTX 0x05
229 #define FULL_STARTY 0x09
230 #define FULL_STARTX 0x09
231 #elif defined(GC8034_MIRROR_HV)
232 #define GC8034_MIRROR 0xc3
233 #define BINNING_STARTY 0x05
234 #define BINNING_STARTX 0x04
235 #define FULL_STARTY 0x09
236 #define FULL_STARTX 0x08
237 #else
238 #define GC8034_MIRROR 0xc0
239 #define BINNING_STARTY 0x04
240 #define BINNING_STARTX 0x05
241 #define FULL_STARTY 0x08
242 #define FULL_STARTX 0x09
243 #endif
244
245 /*
246 * Xclk 24Mhz
247 */
248 static const struct regval gc8034_global_regs_2lane[] = {
249 /*SYS*/
250 {0xf2, 0x00},
251 {0xf4, 0x80},
252 {0xf5, 0x19},
253 {0xf6, 0x44},
254 {0xf7, 0x95}, //pll enable
255 {0xf8, 0x63}, //pll mode
256 {0xf9, 0x00},
257 {0xfa, 0x45},
258 {0xfc, 0xfe},
259
260 /*Cisctl&Analog*/
261 {0xfe, 0x00},
262 {0x03, 0x08},
263 {0x04, 0xc6},
264 {0x05, 0x02},
265 {0x06, 0x16},
266 {0x07, 0x00},
267 {0x08, 0x10},
268 {0x0a, 0x3a}, //row start
269 {0x0b, 0x00},
270 {0x0c, 0x04}, //col start
271 {0x0d, 0x09},
272 {0x0e, 0xa0}, //win_height 2464
273 {0x0f, 0x0c},
274 {0x10, 0xd4}, //win_width 3284
275 {0x17, GC8034_MIRROR},
276 {0x18, 0x02},
277 {0x19, 0x17},
278 {0x1e, 0x50},
279 {0x1f, 0x80},
280 {0x21, 0x4c},
281 {0x25, 0x00},
282 {0x28, 0x4a},
283 {0x2d, 0x89},
284 {0xca, 0x02},
285 {0xcb, 0x00},
286 {0xcc, 0x39},
287 {0xce, 0xd0},
288 {0xcf, 0x93},
289 {0xd0, 0x1b},
290 {0xd1, 0xaa},
291 {0xd2, 0xcb},
292 {0xd8, 0x40},
293 {0xd9, 0xff},
294 {0xda, 0x0e},
295 {0xdb, 0xb0},
296 {0xdc, 0x0e},
297 {0xde, 0x08},
298 {0xe4, 0xc6},
299 {0xe5, 0x08},
300 {0xe6, 0x10},
301 {0xed, 0x2a},
302 {0xfe, 0x02},
303 {0x59, 0x02},
304 {0x5a, 0x04},
305 {0x5b, 0x08},
306 {0x5c, 0x20},
307 {0xfe, 0x00},
308 {0x1a, 0x09},
309 {0x1d, 0x13},
310 {0xfe, 0x10},
311 {0xfe, 0x00},
312 {0xfe, 0x10},
313 {0xfe, 0x00},
314
315 /* Gamma */
316 {0xfe, 0x00},
317 {0x20, 0x54},
318 {0x33, 0x82},
319 {0xfe, 0x01},
320 {0xdf, 0x06},
321 {0xe7, 0x18},
322 {0xe8, 0x20},
323 {0xe9, 0x16},
324 {0xea, 0x17},
325 {0xeb, 0x50},
326 {0xec, 0x6c},
327 {0xed, 0x9b},
328 {0xee, 0xd8},
329
330 /*ISP*/
331 {0xfe, 0x00},
332 {0x80, 0x13},
333 {0x84, 0x01},
334 {0x89, 0x03},
335 {0x8d, 0x03},
336 {0x8f, 0x14},
337 {0xad, 0x00},
338
339 /*Crop window*/
340 {0x90, 0x01},
341 {0x92, FULL_STARTY},
342 {0x94, FULL_STARTX},
343 {0x95, 0x09},
344 {0x96, 0x90},
345 {0x97, 0x0c},
346 {0x98, 0xc0},
347
348 /*Gain*/
349 {0xb0, 0x90},
350 {0xb1, 0x01},
351 {0xb2, 0x00},
352 {0xb6, 0x00},
353
354 /*BLK*/
355 {0xfe, 0x00},
356 {0x40, 0x22},
357 {0x43, 0x03}, //add_offset
358 {0x4e, 0x00}, //row_bits[15:8]
359 {0x4f, 0x3c}, //row_bits[7:0]
360 {0x58, 0x80}, //dark current ratio
361 {0x59, 0x80},
362 {0x5a, 0x80},
363 {0x5b, 0x80},
364 {0x5c, 0x00},
365 {0x5d, 0x00},
366 {0x5e, 0x00},
367 {0x5f, 0x00},
368
369 /*WB offset*/
370 {0xfe, 0x01},
371 {0xbf, 0x40},
372
373 /*Dark Sun*/
374 {0xfe, 0x01},
375 {0x68, 0x77},
376
377 /*DPC*/
378 {0xfe, 0x01},
379 {0x60, 0x15},
380 {0x61, 0x10},
381 {0x62, 0x60},
382 {0x63, 0x48},
383 {0x64, 0x02},
384
385 /*LSC*/
386 {0xfe, 0x01},
387 {0xa0, 0x10}, //[6]segment_width[8], 0x[5:4]segment_height[9:8]
388 {0xa8, 0x60}, //segment_height[7:0]
389 {0xa2, 0xd1}, //height_ratio[7:0]
390 {0xc8, 0x5b}, //[7:4]height_ratio[11:8]
391 {0xa1, 0xb8}, //segment_width[7:0]
392 {0xa3, 0x91}, //width_ratio[7:0]
393 {0xc0, 0x50}, //[7:4]width_ratio[11:8]
394 {0xd0, 0x05}, //segment_width_end[11:8]
395 {0xd1, 0xb2}, //segment_width_end[7:0]
396 {0xd2, 0x1f}, //col_segment
397 {0xd3, 0x00}, //row_num_start[7:0]
398 {0xd4, 0x00}, //[5:4]row_num_start[9:8] [3:0]col_seg_start
399 {0xd5, 0x00}, //[7:2]col_num_start[7:2]
400 {0xd6, 0x00}, //[2:0]col_num_start[10:8]
401 {0xd7, 0x00}, //row_seg_start
402 {0xd8, 0x00}, //col_cal_start[7:0]
403 {0xd9, 0x00}, //[2:0]col_cal_start[10:8]
404
405 /*ABB*/
406 {0xfe, 0x01},
407 {0x20, 0x02},
408 {0x21, 0x02},
409 {0x23, 0x43},
410
411 /*MIPI*/
412 {0xfe, 0x03},
413 {0x01, 0x07},
414 {0x02, 0x07},
415 {0x03, 0x92},
416 {0x04, 0x80},
417 {0x11, 0x2b},
418 {0x12, 0xf0}, //lwc 3264*5/4
419 {0x13, 0x0f},
420 {0x15, 0x10}, //LP
421 {0x16, 0x29},
422 {0x17, 0xff},
423 {0x18, 0x01},
424 {0x19, 0xaa},
425 {0x1a, 0x02},
426 {0x21, 0x05},
427 {0x22, 0x05},
428 {0x23, 0x16},
429 {0x24, 0x00},
430 {0x25, 0x12},
431 {0x26, 0x07},
432 {0x29, 0x07},
433 {0x2a, 0x08},
434 {0x2b, 0x07},
435 {0xfe, 0x00},
436 //{0x3f, 0x91},
437 {0x3f, 0x00},
438
439 {REG_NULL, 0x00},
440 };
441
442 /*
443 * Xclk 24Mhz
444 * max_framerate 30fps
445 * mipi_datarate per lane 672Mbps
446 */
447 static const struct regval gc8034_1632x1224_regs_2lane[] = {
448 /*SYS*/
449 {0xf2, 0x00},
450 {0xf4, 0x80},
451 {0xf5, 0x19},
452 {0xf6, 0x44},
453 {0xf8, 0x63},
454 {0xfa, 0x45},
455 {0xf9, 0x00},
456 {0xf7, 0x95},
457 {0xfc, 0x00},
458 {0xfc, 0x00},
459 {0xfc, 0xea},
460 {0xfe, 0x03},
461 {0x03, 0x9a},
462 {0xfc, 0xee},
463 {0xfe, 0x10},
464 {0xfe, 0x00},
465 {0xfe, 0x10},
466 {0xfe, 0x00},
467
468 /*ISP*/
469 {0xfe, 0x00},
470 {0x80, 0x10},
471 {0xad, 0x30},
472 {0x66, 0x2c},
473 {0xbc, 0x49},
474
475 /*Crop window*/
476 {0x90, 0x01},
477 {0x92, BINNING_STARTY}, //crop y
478 {0x94, BINNING_STARTX}, //crop x
479 {0x95, 0x04},
480 {0x96, 0xc8},
481 {0x97, 0x06},
482 {0x98, 0x60},
483
484 /*MIPI*/
485 {0xfe, 0x03},
486 {0x01, 0x07},
487 {0x02, 0x03},
488 {0x04, 0x80},
489 {0x11, 0x2b},
490 {0x12, 0xf8},
491 {0x13, 0x07},
492 {0x15, 0x10}, //LP mode
493 {0x16, 0x29},
494 {0x17, 0xff},
495 {0x18, 0x01},
496 {0x19, 0xaa},
497 {0x1a, 0x02},
498 {0x21, 0x05},
499 {0x22, 0x06},
500 {0x23, 0x16},
501 {0x24, 0x00},
502 {0x25, 0x12},
503 {0x26, 0x07},
504 {0x29, 0x07},
505 {0x2a, 0x08},
506 {0x2b, 0x07},
507 {0xfe, 0x00},
508 {0x3f, 0x00},
509
510 {REG_NULL, 0x00},
511 };
512
513 /*
514 * Xclk 24Mhz
515 * max_framerate 15fps
516 * mipi_datarate per lane 672Mbps
517 */
518 static const struct regval gc8034_3264x2448_regs_2lane[] = {
519 /*SYS*/
520 {0xf2, 0x00},
521 {0xf4, 0x80},
522 {0xf5, 0x19},
523 {0xf6, 0x44},
524 {0xf7, 0x95}, //pll enable
525 {0xf8, 0x63}, //pll mode
526 {0xf9, 0x00},
527 {0xfa, 0x45},
528 {0xfc, 0x00},
529 {0xfc, 0x00},
530 {0xfc, 0xfe},
531
532 /* ISP */
533 {0xfe, 0x00},
534 {0x80, 0x13},
535 {0xad, 0x00},
536 {0x66, 0x0c},
537 {0xbc, 0x09},
538
539 /* Crop window */
540 {0x90, 0x01},
541 {0x92, FULL_STARTY},
542 {0x94, FULL_STARTX},
543 {0x95, 0x09},
544 {0x96, 0x90},
545 {0x97, 0x0c},
546 {0x98, 0xc0},
547
548 /* MIPI */
549 {0xfe, 0x03},
550 {0x01, 0x07},
551 {0x02, 0x03},
552 {0x03, 0x92},
553 {0x04, 0x80},
554 {0x11, 0x2b},
555 {0x12, 0xf0}, //lwc 3264*5/4
556 {0x13, 0x0f},
557 {0x15, 0x10}, //LP
558 {0x16, 0x29},
559 {0x17, 0xff},
560 {0x18, 0x01},
561 {0x19, 0xaa},
562 {0x1a, 0x02},
563 {0x21, 0x05},
564 {0x22, 0x05},
565 {0x23, 0x16},
566 {0x24, 0x00},
567 {0x25, 0x12},
568 {0x26, 0x07},
569 {0x29, 0x07},
570 {0x2a, 0x08},
571 {0x2b, 0x07},
572 {0xfe, 0x00},
573 //{0x3f, 0x91},
574 {0x3f, 0x00},
575 {REG_NULL, 0x00},
576 };
577
578 /*
579 * Xclk 24Mhz
580 */
581 static const struct regval gc8034_global_regs_4lane[] = {
582 /*SYS*/
583 {0xf2, 0x00},
584 {0xf4, 0x80},
585 {0xf5, 0x19},
586 {0xf6, 0x44},
587 {0xf8, 0x63},
588 {0xfa, 0x45},
589 {0xf9, 0x00},
590 {0xf7, 0x9d},
591 {0xfc, 0x00},
592 {0xfc, 0x00},
593 {0xfc, 0xea},
594 {0xfe, 0x03},
595 {0x03, 0x9a},
596 {0x18, 0x07},
597 {0x01, 0x07},
598 {0xfc, 0xee},
599 /*Cisctl&Analog*/
600 {0xfe, 0x00},
601 {0x03, 0x08},
602 {0x04, 0xc6},
603 {0x05, 0x02},
604 {0x06, 0x16},
605 {0x07, 0x00},
606 {0x08, 0x10},
607 {0x0a, 0x3a},
608 {0x0b, 0x00},
609 {0x0c, 0x04},
610 {0x0d, 0x09},
611 {0x0e, 0xa0},
612 {0x0f, 0x0c},
613 {0x10, 0xd4},
614 {0x17, 0xc0},
615 {0x18, 0x02},
616 {0x19, 0x17},
617 {0x1e, 0x50},
618 {0x1f, 0x80},
619 {0x21, 0x4c},
620 {0x25, 0x00},
621 {0x28, 0x4a},
622 {0x2d, 0x89},
623 {0xca, 0x02},
624 {0xcb, 0x00},
625 {0xcc, 0x39},
626 {0xce, 0xd0},
627 {0xcf, 0x93},
628 {0xd0, 0x19},
629 {0xd1, 0xaa},
630 {0xd2, 0xcb},
631 {0xd8, 0x40},
632 {0xd9, 0xff},
633 {0xda, 0x0e},
634 {0xdb, 0xb0},
635 {0xdc, 0x0e},
636 {0xde, 0x08},
637 {0xe4, 0xc6},
638 {0xe5, 0x08},
639 {0xe6, 0x10},
640 {0xed, 0x2a},
641 {0xfe, 0x02},
642 {0x59, 0x02},
643 {0x5a, 0x04},
644 {0x5b, 0x08},
645 {0x5c, 0x20},
646 {0xfe, 0x00},
647 {0x1a, 0x09},
648 {0x1d, 0x13},
649 {0xfe, 0x10},
650 {0xfe, 0x00},
651 {0xfe, 0x10},
652 {0xfe, 0x00},
653 /*Gamma*/
654 {0xfe, 0x00},
655 {0x20, 0x55},
656 {0x33, 0x83},
657 {0xfe, 0x01},
658 {0xdf, 0x06},
659 {0xe7, 0x18},
660 {0xe8, 0x20},
661 {0xe9, 0x16},
662 {0xea, 0x17},
663 {0xeb, 0x50},
664 {0xec, 0x6c},
665 {0xed, 0x9b},
666 {0xee, 0xd8},
667 /*ISP*/
668 {0xfe, 0x00},
669 {0x80, 0x10},
670 {0x84, 0x01},
671 {0x88, 0x03},
672 {0x89, 0x03},
673 {0x8d, 0x03},
674 {0x8f, 0x14},
675 {0xad, 0x30},
676 {0x66, 0x2c},
677 {0xbc, 0x49},
678 {0xc2, 0x7f},
679 {0xc3, 0xff},
680 /*Crop window*/
681 {0x90, 0x01},
682 {0x92, 0x08},
683 {0x94, 0x09},
684 {0x95, 0x04},
685 {0x96, 0xc8},
686 {0x97, 0x06},
687 {0x98, 0x60},
688 /*Gain*/
689 {0xb0, 0x90},
690 {0xb1, 0x01},
691 {0xb2, 0x00},
692 {0xb6, 0x00},
693 /*BLK*/
694 {0xfe, 0x00},
695 {0x40, 0x22},
696 {0x41, 0x20},
697 {0x42, 0x02},
698 {0x43, 0x08},
699 {0x4e, 0x0f},
700 {0x4f, 0xf0},
701 {0x58, 0x80},
702 {0x59, 0x80},
703 {0x5a, 0x80},
704 {0x5b, 0x80},
705 {0x5c, 0x00},
706 {0x5d, 0x00},
707 {0x5e, 0x00},
708 {0x5f, 0x00},
709 {0x6b, 0x01},
710 {0x6c, 0x00},
711 {0x6d, 0x0c},
712 /*WB offset*/
713 {0xfe, 0x01},
714 {0xbf, 0x40},
715 /*Dark Sun*/
716 {0xfe, 0x01},
717 {0x68, 0x77},
718 /*DPC*/
719 {0xfe, 0x01},
720 {0x60, 0x00},
721 {0x61, 0x10},
722 {0x62, 0x28},
723 {0x63, 0x10},
724 {0x64, 0x02},
725 /*LSC*/
726 {0xfe, 0x01},
727 {0xa8, 0x60},
728 {0xa2, 0xd1},
729 {0xc8, 0x57},
730 {0xa1, 0xb8},
731 {0xa3, 0x91},
732 {0xc0, 0x50},
733 {0xd0, 0x05},
734 {0xd1, 0xb2},
735 {0xd2, 0x1f},
736 {0xd3, 0x00},
737 {0xd4, 0x00},
738 {0xd5, 0x00},
739 {0xd6, 0x00},
740 {0xd7, 0x00},
741 {0xd8, 0x00},
742 {0xd9, 0x00},
743 {0xa4, 0x10},
744 {0xa5, 0x20},
745 {0xa6, 0x60},
746 {0xa7, 0x80},
747 {0xab, 0x18},
748 {0xc7, 0xc0},
749 /*ABB*/
750 {0xfe, 0x01},
751 {0x20, 0x02},
752 {0x21, 0x02},
753 {0x23, 0x42},
754 /*MIPI*/
755 {0xfe, 0x03},
756 {0x02, 0x03},
757 {0x04, 0x80},
758 {0x11, 0x2b},
759 {0x12, 0xf8},
760 {0x13, 0x07},
761 {0x15, 0x10},
762 {0x16, 0x29},
763 {0x17, 0xff},
764 {0x19, 0xaa},
765 {0x1a, 0x02},
766 {0x21, 0x02},
767 {0x22, 0x03},
768 {0x23, 0x0a},
769 {0x24, 0x00},
770 {0x25, 0x12},
771 {0x26, 0x04},
772 {0x29, 0x04},
773 {0x2a, 0x02},
774 {0x2b, 0x04},
775 {0xfe, 0x00},
776 {0x3f, 0x00},
777
778 /*SYS*/
779 {0xf2, 0x00},
780 {0xf4, 0x80},
781 {0xf5, 0x19},
782 {0xf6, 0x44},
783 {0xf8, 0x63},
784 {0xfa, 0x45},
785 {0xf9, 0x00},
786 {0xf7, 0x95},
787 {0xfc, 0x00},
788 {0xfc, 0x00},
789 {0xfc, 0xea},
790 {0xfe, 0x03},
791 {0x03, 0x9a},
792 {0x18, 0x07},
793 {0x01, 0x07},
794 {0xfc, 0xee},
795 /*ISP*/
796 {0xfe, 0x00},
797 {0x80, 0x13},
798 {0xad, 0x00},
799 /*Crop window*/
800 {0x90, 0x01},
801 {0x92, 0x08},
802 {0x94, 0x09},
803 {0x95, 0x09},
804 {0x96, 0x90},
805 {0x97, 0x0c},
806 {0x98, 0xc0},
807 /*DPC*/
808 {0xfe, 0x01},
809 {0x62, 0x60},
810 {0x63, 0x48},
811 /*MIPI*/
812 {0xfe, 0x03},
813 {0x02, 0x03},
814 {0x04, 0x80},
815 {0x11, 0x2b},
816 {0x12, 0xf0},
817 {0x13, 0x0f},
818 {0x15, 0x10},
819 {0x16, 0x29},
820 {0x17, 0xff},
821 {0x19, 0xaa},
822 {0x1a, 0x02},
823 {0x21, 0x05},
824 {0x22, 0x06},
825 {0x23, 0x2b},
826 {0x24, 0x00},
827 {0x25, 0x12},
828 {0x26, 0x07},
829 {0x29, 0x07},
830 {0x2a, 0x12},
831 {0x2b, 0x07},
832 {0xfe, 0x00},
833 {0x3f, 0x00},
834
835 {REG_NULL, 0x00},
836 };
837
838 /*
839 * Xclk 24Mhz
840 * max_framerate 30fps
841 * mipi_datarate per lane 656Mbps
842 */
843 static const struct regval gc8034_3264x2448_regs_4lane[] = {
844 {REG_NULL, 0x00},
845 };
846
847 static const struct gc8034_mode supported_modes_2lane[] = {
848 {
849 .width = 3264,
850 .height = 2448,
851 .max_fps = {
852 .numerator = 10000,
853 .denominator = 150000,
854 },
855 .exp_def = 0x09a0,
856 .hts_def = 0x0858 * 2,
857 .vts_def = 0x09c4,
858 .reg_list = gc8034_3264x2448_regs_2lane,
859 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
860 },
861 {
862 .width = 1632,
863 .height = 1224,
864 .max_fps = {
865 .numerator = 10000,
866 .denominator = 300000,
867 },
868 .exp_def = 0x09a0,
869 .hts_def = 0x0858 * 2,
870 .vts_def = 0x09c4,
871 .reg_list = gc8034_1632x1224_regs_2lane,
872 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
873 },
874 };
875
876 static const struct gc8034_mode supported_modes_4lane[] = {
877 {
878 .width = 3264,
879 .height = 2448,
880 .max_fps = {
881 .numerator = 10000,
882 .denominator = 300000,
883 },
884 .exp_def = 0x08c6,
885 .hts_def = 0x10b0,
886 .vts_def = 0x09c0,
887 .reg_list = gc8034_3264x2448_regs_4lane,
888 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
889 },
890 };
891
892 static const struct gc8034_mode *supported_modes;
893
894 static const s64 link_freq_menu_items[] = {
895 GC8034_MIPI_FREQ_336MHZ,
896 };
897
898 /* Write registers up to 4 at a time */
gc8034_write_reg(struct i2c_client * client,u8 reg,u8 val)899 static int gc8034_write_reg(struct i2c_client *client, u8 reg, u8 val)
900 {
901 struct i2c_msg msg;
902 u8 buf[2];
903 int ret;
904
905 buf[0] = reg & 0xFF;
906 buf[1] = val;
907
908 msg.addr = client->addr;
909 msg.flags = client->flags;
910 msg.buf = buf;
911 msg.len = sizeof(buf);
912
913 ret = i2c_transfer(client->adapter, &msg, 1);
914 if (ret >= 0)
915 return 0;
916
917 dev_err(&client->dev,
918 "gc8034 write reg(0x%x val:0x%x) failed !\n", reg, val);
919
920 return ret;
921 }
922
gc8034_write_array(struct i2c_client * client,const struct regval * regs)923 static int gc8034_write_array(struct i2c_client *client,
924 const struct regval *regs)
925 {
926 u32 i = 0;
927 int ret = 0;
928
929 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
930 ret = gc8034_write_reg(client, regs[i].addr, regs[i].val);
931
932 return ret;
933 }
934
935 /* Read registers up to 4 at a time */
gc8034_read_reg(struct i2c_client * client,u8 reg,u8 * val)936 static int gc8034_read_reg(struct i2c_client *client, u8 reg, u8 *val)
937 {
938 struct i2c_msg msg[2];
939 u8 buf[1];
940 int ret;
941
942 buf[0] = reg & 0xFF;
943
944 msg[0].addr = client->addr;
945 msg[0].flags = client->flags;
946 msg[0].buf = buf;
947 msg[0].len = sizeof(buf);
948
949 msg[1].addr = client->addr;
950 msg[1].flags = client->flags | I2C_M_RD;
951 msg[1].buf = buf;
952 msg[1].len = 1;
953
954 ret = i2c_transfer(client->adapter, msg, 2);
955 if (ret >= 0) {
956 *val = buf[0];
957 return 0;
958 }
959
960 dev_err(&client->dev,
961 "gc8034 read reg:0x%x failed !\n", reg);
962
963 return ret;
964 }
965
gc8034_get_reso_dist(const struct gc8034_mode * mode,struct v4l2_mbus_framefmt * framefmt)966 static int gc8034_get_reso_dist(const struct gc8034_mode *mode,
967 struct v4l2_mbus_framefmt *framefmt)
968 {
969 return abs(mode->width - framefmt->width) +
970 abs(mode->height - framefmt->height);
971 }
972
973 static const struct gc8034_mode *
gc8034_find_best_fit(struct gc8034 * gc8034,struct v4l2_subdev_format * fmt)974 gc8034_find_best_fit(struct gc8034 *gc8034,
975 struct v4l2_subdev_format *fmt)
976 {
977 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
978 int dist;
979 int cur_best_fit = 0;
980 int cur_best_fit_dist = -1;
981 unsigned int i;
982
983 for (i = 0; i < gc8034->cfg_num; i++) {
984 dist = gc8034_get_reso_dist(&supported_modes[i], framefmt);
985 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
986 cur_best_fit_dist = dist;
987 cur_best_fit = i;
988 }
989 }
990
991 return &supported_modes[cur_best_fit];
992 }
993
gc8034_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)994 static int gc8034_set_fmt(struct v4l2_subdev *sd,
995 struct v4l2_subdev_pad_config *cfg,
996 struct v4l2_subdev_format *fmt)
997 {
998 struct gc8034 *gc8034 = to_gc8034(sd);
999 const struct gc8034_mode *mode;
1000 s64 h_blank, vblank_def;
1001
1002 mutex_lock(&gc8034->mutex);
1003
1004 mode = gc8034_find_best_fit(gc8034, fmt);
1005 fmt->format.code = GC8034_MEDIA_BUS_FMT;
1006 fmt->format.width = mode->width;
1007 fmt->format.height = mode->height;
1008 fmt->format.field = V4L2_FIELD_NONE;
1009 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1010 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1011 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1012 #else
1013 mutex_unlock(&gc8034->mutex);
1014 return -ENOTTY;
1015 #endif
1016 } else {
1017 gc8034->cur_mode = mode;
1018 h_blank = mode->hts_def - mode->width;
1019 __v4l2_ctrl_modify_range(gc8034->hblank, h_blank,
1020 h_blank, 1, h_blank);
1021 vblank_def = mode->vts_def - mode->height;
1022 __v4l2_ctrl_modify_range(gc8034->vblank, vblank_def,
1023 GC8034_VTS_MAX - mode->height,
1024 1, vblank_def);
1025 __v4l2_ctrl_s_ctrl(gc8034->link_freq,
1026 link_freq_menu_items[0]);
1027 }
1028
1029 mutex_unlock(&gc8034->mutex);
1030
1031 return 0;
1032 }
1033
gc8034_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1034 static int gc8034_get_fmt(struct v4l2_subdev *sd,
1035 struct v4l2_subdev_pad_config *cfg,
1036 struct v4l2_subdev_format *fmt)
1037 {
1038 struct gc8034 *gc8034 = to_gc8034(sd);
1039 const struct gc8034_mode *mode = gc8034->cur_mode;
1040
1041 mutex_lock(&gc8034->mutex);
1042 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1043 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1044 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
1045 #else
1046 mutex_unlock(&gc8034->mutex);
1047 return -ENOTTY;
1048 #endif
1049 } else {
1050 fmt->format.width = mode->width;
1051 fmt->format.height = mode->height;
1052 fmt->format.code = GC8034_MEDIA_BUS_FMT;
1053 fmt->format.field = V4L2_FIELD_NONE;
1054 }
1055 mutex_unlock(&gc8034->mutex);
1056
1057 return 0;
1058 }
1059
gc8034_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1060 static int gc8034_enum_mbus_code(struct v4l2_subdev *sd,
1061 struct v4l2_subdev_pad_config *cfg,
1062 struct v4l2_subdev_mbus_code_enum *code)
1063 {
1064 if (code->index != 0)
1065 return -EINVAL;
1066 code->code = GC8034_MEDIA_BUS_FMT;
1067
1068 return 0;
1069 }
1070
gc8034_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1071 static int gc8034_enum_frame_sizes(struct v4l2_subdev *sd,
1072 struct v4l2_subdev_pad_config *cfg,
1073 struct v4l2_subdev_frame_size_enum *fse)
1074 {
1075 struct gc8034 *gc8034 = to_gc8034(sd);
1076
1077 if (fse->index >= gc8034->cfg_num)
1078 return -EINVAL;
1079
1080 if (fse->code != GC8034_MEDIA_BUS_FMT)
1081 return -EINVAL;
1082
1083 fse->min_width = supported_modes[fse->index].width;
1084 fse->max_width = supported_modes[fse->index].width;
1085 fse->max_height = supported_modes[fse->index].height;
1086 fse->min_height = supported_modes[fse->index].height;
1087
1088 return 0;
1089 }
1090
gc8034_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1091 static int gc8034_g_frame_interval(struct v4l2_subdev *sd,
1092 struct v4l2_subdev_frame_interval *fi)
1093 {
1094 struct gc8034 *gc8034 = to_gc8034(sd);
1095 const struct gc8034_mode *mode = gc8034->cur_mode;
1096
1097 mutex_lock(&gc8034->mutex);
1098 fi->interval = mode->max_fps;
1099 mutex_unlock(&gc8034->mutex);
1100
1101 return 0;
1102 }
1103
1104 #define DD_WIDTH 3284
1105 #define DD_HEIGHT 2464
1106
1107 #define DD_PARAM_QTY 350
1108 #define WINDOW_WIDTH 0x0cd4//3284 max effective pixels
1109 #define WINDOW_HEIGHT 0x09a0//2462
1110 #define REG_ROM_START 0x4e
1111 #define INFO_ROM_START 0x70
1112 #define INFO_WIDTH 0x08
1113 #define WB_ROM_START 0x5f
1114 #define WB_WIDTH 0x04
1115 #define GOLDEN_ROM_START 0x67//golden R/G ratio
1116 #define GOLDEN_WIDTH 0x04
1117 #define LSC_NUM 99//0x63 //(7+2)*(9+2)
1118 #define VCM_START 0x3B
1119 #define VCM_WIDTH 0x04
1120
gc8034_otp_read_reg(struct i2c_client * client,int page,int address)1121 static int gc8034_otp_read_reg(struct i2c_client *client,
1122 int page, int address)
1123 {
1124 int ret = 0;
1125 u8 val = 0;
1126
1127 ret = gc8034_write_reg(client, 0xfe, 0x00);
1128 ret |= gc8034_write_reg(client, 0xD4,
1129 ((page << 2) & 0x3c) + ((address >> 5) & 0x03));
1130 ret |= gc8034_write_reg(client, 0xD5,
1131 (address << 3) & 0xff);
1132 ret |= gc8034_write_reg(client, 0xF3,
1133 0x20);
1134 ret |= gc8034_read_reg(client, 0xD7, &val);
1135 if (ret != 0)
1136 return ret;
1137 return val;
1138 }
1139
gc8034_otp_read_group(struct i2c_client * client,int page,int address,u8 * buf,int size)1140 static int gc8034_otp_read_group(struct i2c_client *client,
1141 int page, int address, u8 *buf, int size)
1142 {
1143 int i = 0;
1144 int val = 0;
1145
1146 for (i = 0; i < size; i++) {
1147 if ((address % 0x80) == 0) {
1148 page += 1;
1149 address = 0;
1150 }
1151 val = gc8034_otp_read_reg(client, page, address);
1152 if (val >= 0)
1153 buf[i] = val;
1154 else
1155 return val;
1156 address += 1;
1157 }
1158 return 0;
1159 }
1160
gc8034_otp_enable(struct gc8034 * gc8034)1161 static int gc8034_otp_enable(struct gc8034 *gc8034)
1162 {
1163 struct i2c_client *client = gc8034->client;
1164 u8 otp_clk = 0;
1165 u8 otp_en = 0;
1166 int ret = 0;
1167
1168 ret = gc8034_write_reg(client, 0xf2, 0x00);
1169 ret |= gc8034_write_reg(client, 0xf4, 0x80);
1170 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1171 ret |= gc8034_write_reg(client, 0xf7, 0x97);
1172 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1173 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1174 ret |= gc8034_write_reg(client, 0xfc, 0xee);
1175 ret |= gc8034_read_reg(client, 0xF2, &otp_clk);
1176 ret |= gc8034_read_reg(client, 0xF4, &otp_en);
1177 otp_clk |= 0x01;
1178 otp_en |= 0x08;
1179 ret |= gc8034_write_reg(client, 0xF2, otp_clk);
1180 ret |= gc8034_write_reg(client, 0xF4, otp_en);
1181 usleep_range(100, 200);
1182 return ret;
1183 }
1184
gc8034_otp_disable(struct gc8034 * gc8034)1185 static int gc8034_otp_disable(struct gc8034 *gc8034)
1186 {
1187 struct i2c_client *client = gc8034->client;
1188 u8 otp_clk = 0;
1189 u8 otp_en = 0;
1190 int ret = 0;
1191
1192 ret = gc8034_read_reg(client, 0xF2, &otp_clk);
1193 ret |= gc8034_read_reg(client, 0xF4, &otp_en);
1194 otp_clk &= 0xFE;
1195 otp_en &= 0xF7;
1196 ret |= gc8034_write_reg(client, 0xF2, otp_clk);
1197 ret |= gc8034_write_reg(client, 0xF4, otp_en);
1198 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1199 ret |= gc8034_write_reg(client, 0xf7, 0x95);
1200 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1201 ret |= gc8034_write_reg(client, 0xfc, 0x00);
1202 ret |= gc8034_write_reg(client, 0xfc, 0xee);
1203 return ret;
1204 }
1205
gc8034_check_prsel(struct gc8034 * gc8034)1206 static void gc8034_check_prsel(struct gc8034 *gc8034)
1207 {
1208 struct i2c_client *client = gc8034->client;
1209 u8 product_level = 0;
1210
1211 gc8034_write_reg(client, 0xfe, 0x02);
1212 gc8034_read_reg(client, 0x68, &product_level);
1213 product_level &= 0x07;
1214
1215 if (product_level == 0x00 || product_level == 0x01) {
1216 gc8034_write_reg(client, 0xfe, 0x00);
1217 gc8034_write_reg(client, 0xd2, 0xcb);
1218 } else {
1219 gc8034_write_reg(client, 0xfe, 0x00);
1220 gc8034_write_reg(client, 0xd2, 0xc3);
1221 }
1222 }
1223
gc8034_otp_read(struct gc8034 * gc8034)1224 static int gc8034_otp_read(struct gc8034 *gc8034)
1225 {
1226 int otp_flag, i, j, index, temp;
1227 struct gc8034_otp_info *otp_ptr;
1228 struct device *dev = &gc8034->client->dev;
1229 struct i2c_client *client = gc8034->client;
1230 int ret = 0;
1231 int cnt = 0;
1232 int checksum = 0;
1233 u8 info[8] = {0};
1234 u8 wb[4] = {0};
1235 u8 vcm[4] = {0};
1236 u8 golden[4] = {0};
1237 int total_number = 0;
1238 u8 ddtempbuff[4 * 80] = { 0 };
1239
1240 otp_ptr = devm_kzalloc(dev, sizeof(*otp_ptr), GFP_KERNEL);
1241 if (!otp_ptr)
1242 return -ENOMEM;
1243
1244 /* OTP base information*/
1245 otp_flag = gc8034_otp_read_reg(client, 9, 0x6f);
1246 for (index = 0; index < 2; index++) {
1247 switch ((otp_flag << (2 * index)) & 0x0c) {
1248 case 0x00:
1249 dev_err(dev, "%s GC8034_OTP_INFO group %d is Empty!\n",
1250 __func__, index + 1);
1251 break;
1252 case 0x04:
1253 dev_err(dev, "%s GC8034_OTP_INFO group %d is Valid!\n",
1254 __func__, index + 1);
1255 checksum = 0;
1256 ret |= gc8034_otp_read_group(client, 9,
1257 (INFO_ROM_START + index * INFO_WIDTH),
1258 &info[0], INFO_WIDTH);
1259 if (ret < 0) {
1260 dev_err(dev, "%s read otp error!\n", __func__);
1261 return ret;
1262 }
1263 for (i = 0; i < INFO_WIDTH - 1; i++)
1264 checksum += info[i];
1265 if ((checksum % 255 + 1) == info[INFO_WIDTH - 1]) {
1266 otp_ptr->flag = 0x80;
1267 otp_ptr->module_id = info[0];
1268 otp_ptr->lens_id = info[1];
1269 otp_ptr->year = info[4];
1270 otp_ptr->month = info[5];
1271 otp_ptr->day = info[6];
1272 dev_err(dev, "fac info: module(0x%x) lens(0x%x) time(%d_%d_%d)!\n",
1273 otp_ptr->module_id,
1274 otp_ptr->lens_id,
1275 otp_ptr->year,
1276 otp_ptr->month,
1277 otp_ptr->day);
1278 } else {
1279 dev_err(dev, "%s GC8034_OTP_INFO Check sum %d Error!\n",
1280 __func__, index + 1);
1281 }
1282 break;
1283 case 0x08:
1284 case 0x0c:
1285 dev_err(dev, "%s GC8034_OTP_INFO group %d is Invalid !!\n",
1286 __func__, index + 1);
1287 break;
1288 default:
1289 break;
1290 }
1291 }
1292
1293 /* OTP WB calibration data */
1294 otp_flag = gc8034_otp_read_reg(client, 9, 0x5e);
1295 for (index = 0; index < 2; index++) {
1296 switch ((otp_flag << (2 * index)) & 0x0c) {
1297 case 0x00:
1298 dev_err(dev, "%s GC8034_OTP_WB group %d is Empty !\n",
1299 __func__, index + 1);
1300 break;
1301 case 0x04:
1302 dev_err(dev, "%s GC8034_OTP_WB group %d is Valid !!\n",
1303 __func__, index + 1);
1304 checksum = 0;
1305 ret |= gc8034_otp_read_group(client,
1306 9,
1307 (WB_ROM_START + index * WB_WIDTH),
1308 &wb[0],
1309 WB_WIDTH);
1310 if (ret < 0) {
1311 dev_err(dev, "%s read otp error!\n", __func__);
1312 return ret;
1313 }
1314 for (i = 0; i < WB_WIDTH - 1; i++)
1315 checksum += wb[i];
1316 if ((checksum % 255 + 1) == wb[WB_WIDTH - 1]) {
1317 otp_ptr->flag |= 0x40; /* valid AWB in OTP */
1318 otp_ptr->rg_ratio =
1319 ((wb[1] & 0xf0) << 4) | wb[0];
1320 otp_ptr->bg_ratio =
1321 ((wb[1] & 0x0f) << 8) | wb[2];
1322 dev_err(dev, "otp:(rg_ratio 0x%x, bg_ratio 0x%x)\n",
1323 otp_ptr->rg_ratio, otp_ptr->bg_ratio);
1324 } else {
1325 dev_err(dev, "%s GC8034_OTP_WB Check sum %d Error !!\n",
1326 __func__, index + 1);
1327 }
1328 break;
1329 case 0x08:
1330 case 0x0c:
1331 dev_err(dev, "%s GC8034_OTP_WB group %d is Invalid !!\n",
1332 __func__, index + 1);
1333 break;
1334 default:
1335 break;
1336 }
1337 switch ((otp_flag << (2 * index)) & 0xc0) {
1338 case 0x00:
1339 dev_err(dev, "%s GC8034_OTP_GOLDEN group %d is Empty!\n",
1340 __func__, index + 1);
1341 break;
1342 case 0x40:
1343 dev_err(dev, "%s GC8034_OTP_GOLDEN group %d is Valid !!\n",
1344 __func__, index + 1);
1345 checksum = 0;
1346 ret = gc8034_otp_read_group(client, 9,
1347 (GOLDEN_ROM_START + index * GOLDEN_WIDTH),
1348 &golden[0], GOLDEN_WIDTH);
1349 if (ret < 0) {
1350 dev_err(dev, "%s read otp error!\n", __func__);
1351 return ret;
1352 }
1353 for (i = 0; i < GOLDEN_WIDTH - 1; i++)
1354 checksum += golden[i];
1355 if ((checksum % 255 + 1) == golden[GOLDEN_WIDTH - 1]) {
1356 otp_ptr->golden_rg =
1357 golden[0] | ((golden[1] & 0xf0) << 4);
1358 otp_ptr->golden_bg =
1359 ((golden[1] & 0x0f) << 8) | golden[2];
1360 dev_err(dev, "otp:(golden_rg 0x%x, golden_bg 0x%x)\n",
1361 otp_ptr->golden_rg, otp_ptr->golden_bg);
1362 } else {
1363 dev_err(dev, "%s GC8034_OTP_GOLDEN Check sum %d Error !!\n",
1364 __func__, index + 1);
1365 }
1366 break;
1367 case 0x80:
1368 case 0xc0:
1369 dev_err(dev, "%s GC8034_OTP_GOLDEN group %d is Invalid !!\n",
1370 __func__, index + 1);
1371 break;
1372 default:
1373 break;
1374 }
1375 }
1376
1377 /* OTP VCM calibration data */
1378 otp_flag = gc8034_otp_read_reg(client, 3, 0x3A);
1379 for (index = 0; index < 2; index++) {
1380 switch ((otp_flag << (2 * index)) & 0x0c) {
1381 case 0x00:
1382 dev_err(dev, "%s GC8034_OTP_VCM group %d is Empty !\n",
1383 __func__, index + 1);
1384 break;
1385 case 0x04:
1386 dev_err(dev, "%s GC8034_OTP_VCM group %d is Valid !\n",
1387 __func__, index + 1);
1388 ret |= gc8034_otp_read_group(client,
1389 3,
1390 (VCM_START + index * VCM_WIDTH),
1391 &vcm[0],
1392 VCM_WIDTH);
1393 if (ret < 0) {
1394 dev_err(dev, "%s read otp error!\n", __func__);
1395 return ret;
1396 }
1397 checksum = 0;
1398 for (i = 0; i < 3; i++)
1399 checksum += vcm[i];
1400 if ((checksum % 255 + 1) == vcm[3]) {
1401 otp_ptr->flag |= 0x20; /* valid LSC in OTP */
1402 otp_ptr->vcm_dir = 0;//not dir register
1403 otp_ptr->vcm_start =
1404 ((vcm[0] & 0x0f) << 8) + vcm[2];
1405 otp_ptr->vcm_end =
1406 ((vcm[0] & 0xf0) << 4) + vcm[1];
1407 dev_err(dev, "%s GC8034_OTP_VCM check sum success\n",
1408 __func__);
1409 dev_err(dev, "vcm_info: 0x%x, 0x%x, 0x%x!\n",
1410 otp_ptr->vcm_start,
1411 otp_ptr->vcm_end,
1412 otp_ptr->vcm_dir);
1413 } else {
1414 dev_err(dev, "VCM check sum read: 0x%x, calculate:0x%x\n",
1415 vcm[3], checksum % 255 + 1);
1416 }
1417 break;
1418 case 0x08:
1419 case 0x0c:
1420 dev_err(dev, "%s GC8034_OTP_VCM group %d is Invalid !\n",
1421 __func__, index + 1);
1422 break;
1423 default:
1424 break;
1425 }
1426 }
1427
1428 /* OTP LSC calibration data */
1429 otp_flag = gc8034_otp_read_reg(client, 3, 0x43);
1430 for (index = 0; index < 2; index++) {
1431 switch ((otp_flag << (2 * index)) & 0x0c) {
1432 case 0x00:
1433 dev_err(dev, "%s GC8034_OTP_LSC group %d is Empty !\n",
1434 __func__, index + 1);
1435 break;
1436 case 0x04:
1437 dev_err(dev, "%s GC8034_OTP_LSC group %d is Valid !\n",
1438 __func__, index + 1);
1439 if (index == 0) {
1440 ret |= gc8034_otp_read_group(client,
1441 3, 0x44, otp_ptr->lsc, 396);
1442 temp = gc8034_otp_read_reg(client, 6, 0x50);
1443 } else {
1444 ret |= gc8034_otp_read_group(client,
1445 6, 0x51, otp_ptr->lsc, 396);
1446 temp = gc8034_otp_read_reg(client, 9, 0x5d);
1447 }
1448 checksum = 0;
1449 for (i = 0; i < 396; i++) {
1450 checksum += otp_ptr->lsc[i];
1451 usleep_range(100, 200);
1452 dev_err(dev, "otp lsc[%d] = %d\n",
1453 i, otp_ptr->lsc[i]);
1454 }
1455 if ((checksum % 255 + 1) == temp) {
1456 otp_ptr->flag |= 0x10; /* valid LSC in OTP */
1457 dev_err(dev, "%s GC8034_OTP_LSC check sum success\n",
1458 __func__);
1459 } else {
1460 dev_err(dev, "LSC check sum read: 0x%x, calculate:0x%x\n",
1461 temp, checksum % 255 + 1);
1462 }
1463 break;
1464 case 0x08:
1465 case 0x0c:
1466 dev_err(dev, "%s GC8034_OTP_LSC group %d is Invalid !\n",
1467 __func__, index + 1);
1468 break;
1469 default:
1470 break;
1471 }
1472 }
1473 /* OTP DD calibration data */
1474 otp_flag = gc8034_otp_read_reg(client, 0, 0x0b);
1475 for (index = 0; index < 2; index++) {
1476 switch (otp_flag & 0x03) {
1477 case 0x00:
1478 dev_err(dev, "%s GC8034 OTP:flag_dd is EMPTY!\n",
1479 __func__);
1480 break;
1481 case 0x04:
1482 dev_err(dev, "%s GC8034_OTP_DD group %d is valid!\n",
1483 __func__, index + 1);
1484 total_number = gc8034_otp_read_reg(client, 0, 0x0c) +
1485 gc8034_otp_read_reg(client, 0, 0x0d);
1486 ret |= gc8034_otp_read_group(client, 0, 0x0e,
1487 &ddtempbuff[0], 4 * total_number);
1488 for (i = 0; i < total_number; i++) {
1489 if ((ddtempbuff[4 * i + 3] & 0x80) == 0x80) {
1490 if ((ddtempbuff[4 * i + 3] & 0x03) == 0x03) {
1491 otp_ptr->dd_param[cnt].x =
1492 (((u16)ddtempbuff[4 * i + 1] & 0x0f) << 8) +
1493 ddtempbuff[4 * i];
1494 otp_ptr->dd_param[cnt].y =
1495 ((u16)ddtempbuff[4 * i + 2] << 4) +
1496 ((ddtempbuff[4 * i + 1] & 0xf0) >> 4);
1497 otp_ptr->dd_param[cnt++].t = 2;
1498 otp_ptr->dd_param[cnt].x =
1499 (((u16)ddtempbuff[4 * i + 1] & 0x0f) << 8) +
1500 ddtempbuff[4 * i];
1501 otp_ptr->dd_param[cnt].y =
1502 ((u16)ddtempbuff[4 * i + 2] << 4) +
1503 ((ddtempbuff[4 * i + 1] & 0xf0) >> 4) + 1;
1504 otp_ptr->dd_param[cnt++].t = 2;
1505 } else {
1506 otp_ptr->dd_param[cnt].x =
1507 (((u16)ddtempbuff[4 * i + 1] & 0x0f) << 8) +
1508 ddtempbuff[4 * i];
1509 otp_ptr->dd_param[cnt].y =
1510 ((u16)ddtempbuff[4 * i + 2] << 4) +
1511 ((ddtempbuff[4 * i + 1] & 0xf0) >> 4);
1512 otp_ptr->dd_param[cnt++].t =
1513 ddtempbuff[4 * i + 3] & 0x03;
1514 }
1515 }
1516 }
1517 otp_ptr->dd_cnt = total_number;
1518 otp_ptr->flag |= 0x08;
1519 dev_err(dev, "%s GC8034 OTP:total_number = %d!\n",
1520 __func__, total_number);
1521 break;
1522 case 0x08:
1523 case 0x0c:
1524 dev_err(dev, "%s GC8034_OTP_DD group %d is Invalid!\n",
1525 __func__, index + 1);
1526 break;
1527 default:
1528 break;
1529 }
1530 }
1531 /* OTP Chip Register*/
1532 otp_flag = gc8034_otp_read_reg(client, 2, 0x4e);
1533 if (otp_flag == 1) {
1534 for (i = 0; i < 5; i++) {
1535 dev_err(dev, "%s GC8034 reg is valid!\n", __func__);
1536 temp = gc8034_otp_read_reg(client, 2, (0x4f + 5 * i));
1537 for (j = 0; j < 2; j++) {
1538 if (((temp >> (4 * j + 3)) & 0x01) == 0x01) {
1539 otp_ptr->reg_page[otp_ptr->reg_num] =
1540 (temp >> (4 * j)) & 0x03;
1541 otp_ptr->reg_addr[otp_ptr->reg_num] =
1542 gc8034_otp_read_reg(client,
1543 2,
1544 0x50 + 5 * i + 2 * j);
1545 otp_ptr->reg_value[otp_ptr->reg_num] =
1546 gc8034_otp_read_reg(client,
1547 2,
1548 0x50 + 5 * i + 2 * j + 1);
1549 otp_ptr->reg_num++;
1550 }
1551 }
1552 }
1553 otp_ptr->flag |= 0x04;
1554 }
1555
1556 if (otp_ptr->flag) {
1557 gc8034->otp = otp_ptr;
1558 } else {
1559 gc8034->otp = NULL;
1560 devm_kfree(dev, otp_ptr);
1561 }
1562
1563 return 0;
1564 }
1565
gc8034_get_otp(struct gc8034_otp_info * otp,struct rkmodule_inf * inf)1566 static void gc8034_get_otp(struct gc8034_otp_info *otp,
1567 struct rkmodule_inf *inf)
1568 {
1569 u32 i;
1570
1571 /* fac */
1572 if (otp->flag & 0x80) {
1573 inf->fac.flag = 1;
1574 inf->fac.year = otp->year;
1575 inf->fac.month = otp->month;
1576 inf->fac.day = otp->day;
1577 for (i = 0; i < ARRAY_SIZE(gc8034_module_info) - 1; i++) {
1578 if (gc8034_module_info[i].id == otp->module_id)
1579 break;
1580 }
1581 strlcpy(inf->fac.module, gc8034_module_info[i].name,
1582 sizeof(inf->fac.module));
1583
1584 for (i = 0; i < ARRAY_SIZE(gc8034_lens_info) - 1; i++) {
1585 if (gc8034_lens_info[i].id == otp->lens_id)
1586 break;
1587 }
1588 strlcpy(inf->fac.lens, gc8034_lens_info[i].name,
1589 sizeof(inf->fac.lens));
1590 }
1591 /* awb */
1592 if (otp->flag & 0x40) {
1593 inf->awb.flag = 1;
1594 inf->awb.r_value = otp->rg_ratio;
1595 inf->awb.b_value = otp->bg_ratio;
1596 inf->awb.gr_value = 0;
1597 inf->awb.gb_value = 0;
1598
1599 inf->awb.golden_r_value = 0;
1600 inf->awb.golden_b_value = 0;
1601 inf->awb.golden_gr_value = 0;
1602 inf->awb.golden_gb_value = 0;
1603 }
1604 /* af */
1605 if (otp->flag & 0x20) {
1606 inf->af.flag = 1;
1607 inf->af.dir_cnt = 1;
1608 inf->af.af_otp[0].vcm_start = otp->vcm_start;
1609 inf->af.af_otp[0].vcm_end = otp->vcm_end;
1610 inf->af.af_otp[0].vcm_dir = otp->vcm_dir;
1611 }
1612 }
1613
gc8034_get_module_inf(struct gc8034 * gc8034,struct rkmodule_inf * inf)1614 static void gc8034_get_module_inf(struct gc8034 *gc8034,
1615 struct rkmodule_inf *inf)
1616 {
1617 struct gc8034_otp_info *otp = gc8034->otp;
1618
1619 strlcpy(inf->base.sensor,
1620 GC8034_NAME,
1621 sizeof(inf->base.sensor));
1622 strlcpy(inf->base.module,
1623 gc8034->module_name,
1624 sizeof(inf->base.module));
1625 strlcpy(inf->base.lens,
1626 gc8034->len_name,
1627 sizeof(inf->base.lens));
1628 if (otp)
1629 gc8034_get_otp(otp, inf);
1630 }
1631
gc8034_set_module_inf(struct gc8034 * gc8034,struct rkmodule_awb_cfg * cfg)1632 static void gc8034_set_module_inf(struct gc8034 *gc8034,
1633 struct rkmodule_awb_cfg *cfg)
1634 {
1635 mutex_lock(&gc8034->mutex);
1636 memcpy(&gc8034->awb_cfg, cfg, sizeof(*cfg));
1637 mutex_unlock(&gc8034->mutex);
1638 }
1639
gc8034_get_channel_info(struct gc8034 * gc8034,struct rkmodule_channel_info * ch_info)1640 static int gc8034_get_channel_info(struct gc8034 *gc8034, struct rkmodule_channel_info *ch_info)
1641 {
1642 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
1643 return -EINVAL;
1644 ch_info->vc = gc8034->cur_mode->vc[ch_info->index];
1645 ch_info->width = gc8034->cur_mode->width;
1646 ch_info->height = gc8034->cur_mode->height;
1647 ch_info->bus_fmt = GC8034_MEDIA_BUS_FMT;
1648 return 0;
1649 }
1650
gc8034_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1651 static long gc8034_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1652 {
1653 struct gc8034 *gc8034 = to_gc8034(sd);
1654 long ret = 0;
1655 u32 stream = 0;
1656 struct rkmodule_channel_info *ch_info;
1657
1658 switch (cmd) {
1659 case RKMODULE_GET_MODULE_INFO:
1660 gc8034_get_module_inf(gc8034, (struct rkmodule_inf *)arg);
1661 break;
1662 case RKMODULE_AWB_CFG:
1663 gc8034_set_module_inf(gc8034, (struct rkmodule_awb_cfg *)arg);
1664 break;
1665 case RKMODULE_SET_QUICK_STREAM:
1666
1667 stream = *((u32 *)arg);
1668
1669 if (stream) {
1670 ret = gc8034_write_reg(gc8034->client,
1671 GC8034_REG_SET_PAGE,
1672 GC8034_SET_PAGE_ZERO);
1673 if (2 == gc8034->lane_num) {
1674 ret |= gc8034_write_reg(gc8034->client,
1675 GC8034_REG_CTRL_MODE,
1676 0x91);
1677 } else {
1678 ret |= gc8034_write_reg(gc8034->client,
1679 GC8034_REG_CTRL_MODE,
1680 GC8034_MODE_STREAMING);
1681 }
1682 } else {
1683 ret = gc8034_write_reg(gc8034->client,
1684 GC8034_REG_SET_PAGE,
1685 GC8034_SET_PAGE_ZERO);
1686 ret |= gc8034_write_reg(gc8034->client,
1687 GC8034_REG_CTRL_MODE,
1688 GC8034_MODE_SW_STANDBY);
1689 }
1690 break;
1691 case RKMODULE_GET_CHANNEL_INFO:
1692 ch_info = (struct rkmodule_channel_info *)arg;
1693 ret = gc8034_get_channel_info(gc8034, ch_info);
1694 break;
1695 default:
1696 ret = -ENOTTY;
1697 break;
1698 }
1699
1700 return ret;
1701 }
1702
1703 #ifdef CONFIG_COMPAT
gc8034_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1704 static long gc8034_compat_ioctl32(struct v4l2_subdev *sd,
1705 unsigned int cmd, unsigned long arg)
1706 {
1707 void __user *up = compat_ptr(arg);
1708 struct rkmodule_inf *inf;
1709 struct rkmodule_awb_cfg *cfg;
1710 long ret = 0;
1711 u32 stream = 0;
1712 struct rkmodule_channel_info *ch_info;
1713
1714 switch (cmd) {
1715 case RKMODULE_GET_MODULE_INFO:
1716 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1717 if (!inf) {
1718 ret = -ENOMEM;
1719 return ret;
1720 }
1721
1722 ret = gc8034_ioctl(sd, cmd, inf);
1723 if (!ret) {
1724 ret = copy_to_user(up, inf, sizeof(*inf));
1725 if (ret)
1726 ret = -EFAULT;
1727 }
1728 kfree(inf);
1729 break;
1730 case RKMODULE_AWB_CFG:
1731 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1732 if (!cfg) {
1733 ret = -ENOMEM;
1734 return ret;
1735 }
1736
1737 ret = copy_from_user(cfg, up, sizeof(*cfg));
1738 if (!ret)
1739 ret = gc8034_ioctl(sd, cmd, cfg);
1740 else
1741 ret = -EFAULT;
1742 kfree(cfg);
1743 break;
1744 case RKMODULE_SET_QUICK_STREAM:
1745 ret = copy_from_user(&stream, up, sizeof(u32));
1746 if (!ret)
1747 ret = gc8034_ioctl(sd, cmd, &stream);
1748 else
1749 ret = -EFAULT;
1750 break;
1751 case RKMODULE_GET_CHANNEL_INFO:
1752 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1753 if (!ch_info) {
1754 ret = -ENOMEM;
1755 return ret;
1756 }
1757
1758 ret = gc8034_ioctl(sd, cmd, ch_info);
1759 if (!ret) {
1760 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1761 if (ret)
1762 ret = -EFAULT;
1763 }
1764 kfree(ch_info);
1765 break;
1766 default:
1767 ret = -ENOTTY;
1768 break;
1769 }
1770
1771 return ret;
1772 }
1773 #endif
1774
1775 /*--------------------------------------------------------------------------*/
gc8034_apply_otp(struct gc8034 * gc8034)1776 static int gc8034_apply_otp(struct gc8034 *gc8034)
1777 {
1778 int R_gain, G_gain, B_gain, base_gain;
1779 struct i2c_client *client = gc8034->client;
1780 struct gc8034_otp_info *otp_ptr = gc8034->otp;
1781 struct rkmodule_awb_cfg *awb_cfg = &gc8034->awb_cfg;
1782 u32 golden_bg_ratio;
1783 u32 golden_rg_ratio;
1784 u32 golden_g_value;
1785 u32 i, j;
1786 u16 base = 0;
1787 u32 dd_cnt = 0;
1788 u8 temp_val0 = 0;
1789 u8 temp_val1 = 0;
1790 u8 temp_val2 = 0;
1791 struct gc8034_dd dd_temp = {0, 0, 0};
1792
1793 if (!gc8034->awb_cfg.enable)
1794 return 0;
1795
1796 golden_g_value = (awb_cfg->golden_gb_value +
1797 awb_cfg->golden_gr_value) / 2;
1798 golden_bg_ratio = awb_cfg->golden_b_value * 0x400 / golden_g_value;
1799 golden_rg_ratio = awb_cfg->golden_r_value * 0x400 / golden_g_value;
1800 /* apply OTP WB Calibration */
1801 if ((otp_ptr->flag & 0x40) && golden_bg_ratio && golden_rg_ratio) {
1802 /* calculate G gain */
1803 R_gain = golden_rg_ratio * 1000 / otp_ptr->rg_ratio;
1804 B_gain = golden_bg_ratio * 1000 / otp_ptr->bg_ratio;
1805 G_gain = 1000;
1806 base_gain = (R_gain < B_gain) ? R_gain : B_gain;
1807 base_gain = (base_gain < G_gain) ? base_gain : G_gain;
1808
1809 R_gain = 0x400 * R_gain / (base_gain);
1810 B_gain = 0x400 * B_gain / (base_gain);
1811 G_gain = 0x400 * G_gain / (base_gain);
1812
1813 /* update sensor WB gain */
1814 gc8034_write_reg(client, 0xfe, 0x01);
1815
1816 gc8034_write_reg(client, 0x84, G_gain >> 3);
1817 gc8034_write_reg(client, 0x85, R_gain >> 3);
1818 gc8034_write_reg(client, 0x86, B_gain >> 3);
1819 gc8034_write_reg(client, 0x87, G_gain >> 3);
1820 gc8034_write_reg(client, 0x88,
1821 ((G_gain & 0X07) << 4) + (R_gain & 0x07));
1822 gc8034_write_reg(client, 0x89,
1823 ((B_gain & 0X07) << 4) + (G_gain & 0x07));
1824
1825 gc8034_write_reg(client, 0xfe, 0x00);
1826
1827 dev_dbg(&client->dev, "apply awb gain: 0x%x, 0x%x, 0x%x\n",
1828 R_gain, G_gain, B_gain);
1829 }
1830 /* apply OTP Lenc Calibration */
1831 if (otp_ptr->flag & 0x10) {
1832 gc8034_write_reg(client, 0xfe, 0x01);
1833 gc8034_write_reg(client, 0xcf, 0x00);
1834 gc8034_write_reg(client, 0xc9, 0x01);
1835 for (i = 0; i < 9; i++) {
1836 gc8034_write_reg(client, 0xca, i * 0x0c);
1837 for (j = 0; j < 11; j++) {
1838 #if defined(GC8034_MIRROR_NORMAL)
1839 base = 4 * (11 * i + j);
1840 #elif defined(GC8034_MIRROR_H)
1841 base = 4 * (11 * i + 10 - j);
1842 #elif defined(GC8034_MIRROR_V)
1843 base = 4 * (11 * (8 - i) + j);
1844 #elif defined(GC8034_MIRROR_HV)
1845 base = 4 * (11 * (8 - i) + 10 - j);
1846 #endif
1847 gc8034_write_reg(client, 0xcc,
1848 otp_ptr->lsc[base + 0]);
1849 gc8034_write_reg(client, 0xcc,
1850 otp_ptr->lsc[base + 1]);
1851 gc8034_write_reg(client, 0xcc,
1852 otp_ptr->lsc[base + 2]);
1853 gc8034_write_reg(client, 0xcc,
1854 otp_ptr->lsc[base + 3]);
1855 dev_dbg(&client->dev,
1856 "apply lsc otp_ptr->lsc[%d]=%d\n",
1857 base + 0,
1858 otp_ptr->lsc[base + 0]);
1859 dev_dbg(&client->dev,
1860 "apply lsc otp_ptr->lsc[%d]=%d\n",
1861 base + 1,
1862 otp_ptr->lsc[base + 1]);
1863 dev_dbg(&client->dev,
1864 "apply lsc otp_ptr->lsc[%d]=%d\n",
1865 base + 2,
1866 otp_ptr->lsc[base + 2]);
1867 dev_dbg(&client->dev,
1868 "apply lsc otp_ptr->lsc[%d]=%d\n",
1869 base + 3,
1870 otp_ptr->lsc[base + 3]);
1871 }
1872 }
1873 gc8034_write_reg(client, 0xcf, 0x01);
1874 gc8034_write_reg(client, 0xa0, 0x13);
1875 gc8034_write_reg(client, 0xfe, 0x00);
1876 dev_err(&client->dev, "apply lsc\n");
1877 }
1878 /* apply OTP DD Calibration */
1879 if (otp_ptr->flag & 0x08) {
1880 dd_cnt = otp_ptr->dd_cnt;
1881 for (i = 0; i < dd_cnt; i++) {
1882 #if defined(GC8034_MIRROR_H) || defined(GC8034_MIRROR_HV)
1883 switch (otp_ptr->dd_param[i].t) {
1884 case 0:
1885 otp_ptr->dd_param[i].x =
1886 DD_WIDTH - otp_ptr->dd_param[i].x + 1;
1887 break;
1888 case 1:
1889 otp_ptr->dd_param[i].x =
1890 DD_WIDTH - otp_ptr->dd_param[i].x - 1;
1891 break;
1892 default:
1893 otp_ptr->dd_param[i].x =
1894 DD_WIDTH - otp_ptr->dd_param[i].x;
1895 break;
1896 }
1897 #endif
1898 #if defined(GC8034_MIRROR_V) || defined(GC8034_MIRROR_HV)
1899 otp_ptr->dd_param[i].y =
1900 DD_HEIGHT - otp_ptr->dd_param[i].y + 1;
1901 #endif
1902 }
1903 for (i = 0; i < dd_cnt - 1; i++) {
1904 for (j = i + 1; j < dd_cnt; j++) {
1905 if (otp_ptr->dd_param[i].y *
1906 DD_WIDTH + otp_ptr->dd_param[i].x >
1907 otp_ptr->dd_param[j].y * DD_WIDTH +
1908 otp_ptr->dd_param[j].x) {
1909 dd_temp.x = otp_ptr->dd_param[i].x;
1910 dd_temp.y = otp_ptr->dd_param[i].y;
1911 dd_temp.t = otp_ptr->dd_param[i].t;
1912 otp_ptr->dd_param[i].x =
1913 otp_ptr->dd_param[j].x;
1914 otp_ptr->dd_param[i].y =
1915 otp_ptr->dd_param[j].y;
1916 otp_ptr->dd_param[i].t =
1917 otp_ptr->dd_param[j].t;
1918 otp_ptr->dd_param[j].x = dd_temp.x;
1919 otp_ptr->dd_param[j].y = dd_temp.y;
1920 otp_ptr->dd_param[j].t = dd_temp.t;
1921 }
1922 }
1923 }
1924 gc8034_write_reg(client, 0xfe, 0x01);
1925 gc8034_write_reg(client, 0xbe, 0x00);
1926 gc8034_write_reg(client, 0xa9, 0x01);
1927 for (i = 0; i < dd_cnt; i++) {
1928 temp_val0 = otp_ptr->dd_param[i].x & 0x00ff;
1929 temp_val1 = ((otp_ptr->dd_param[i].y & 0x000f) << 4) +
1930 ((otp_ptr->dd_param[i].x & 0x0f00) >> 8);
1931 temp_val2 = (otp_ptr->dd_param[i].y & 0x0ff0) >> 4;
1932 gc8034_write_reg(client, 0xaa, i);
1933 gc8034_write_reg(client, 0xac, temp_val0);
1934 gc8034_write_reg(client, 0xac, temp_val1);
1935 gc8034_write_reg(client, 0xac, temp_val2);
1936 gc8034_write_reg(client, 0xac, otp_ptr->dd_param[i].t);
1937 }
1938 gc8034_write_reg(client, 0xbe, 0x01);
1939 gc8034_write_reg(client, 0xfe, 0x00);
1940 dev_err(&client->dev, "apply dd\n");
1941 }
1942
1943 if (otp_ptr->flag & 0x04) {
1944 gc8034_write_reg(client, 0xfe, 0x00);
1945 for (i = 0; i < otp_ptr->reg_num; i++) {
1946 gc8034_write_reg(client, 0xfe, otp_ptr->reg_page[i]);
1947 gc8034_write_reg(client,
1948 otp_ptr->reg_addr[i],
1949 otp_ptr->reg_value[i]);
1950 }
1951 dev_err(&client->dev, "apply chip reg\n");
1952 }
1953 return 0;
1954 }
1955
__gc8034_start_stream(struct gc8034 * gc8034)1956 static int __gc8034_start_stream(struct gc8034 *gc8034)
1957 {
1958 int ret;
1959
1960 if (gc8034->otp) {
1961 ret = gc8034_otp_enable(gc8034);
1962 gc8034_check_prsel(gc8034);
1963 ret |= gc8034_apply_otp(gc8034);
1964 usleep_range(1000, 2000);
1965 ret |= gc8034_otp_disable(gc8034);
1966 if (ret)
1967 return ret;
1968 }
1969 ret = gc8034_write_array(gc8034->client, gc8034->cur_mode->reg_list);
1970 if (ret)
1971 return ret;
1972
1973 /* In case these controls are set before streaming */
1974 mutex_unlock(&gc8034->mutex);
1975 ret = v4l2_ctrl_handler_setup(&gc8034->ctrl_handler);
1976 mutex_lock(&gc8034->mutex);
1977 ret |= gc8034_write_reg(gc8034->client,
1978 GC8034_REG_SET_PAGE,
1979 GC8034_SET_PAGE_ZERO);
1980 if (2 == gc8034->lane_num) {
1981 ret |= gc8034_write_reg(gc8034->client,
1982 GC8034_REG_CTRL_MODE,
1983 0x91);
1984 } else {
1985 ret |= gc8034_write_reg(gc8034->client,
1986 GC8034_REG_CTRL_MODE,
1987 GC8034_MODE_STREAMING);
1988 }
1989 return ret;
1990 }
1991
__gc8034_stop_stream(struct gc8034 * gc8034)1992 static int __gc8034_stop_stream(struct gc8034 *gc8034)
1993 {
1994 int ret;
1995
1996 ret = gc8034_write_reg(gc8034->client,
1997 GC8034_REG_SET_PAGE,
1998 GC8034_SET_PAGE_ZERO);
1999 ret |= gc8034_write_reg(gc8034->client,
2000 GC8034_REG_CTRL_MODE,
2001 GC8034_MODE_SW_STANDBY);
2002
2003 return ret;
2004 }
2005
gc8034_s_stream(struct v4l2_subdev * sd,int on)2006 static int gc8034_s_stream(struct v4l2_subdev *sd, int on)
2007 {
2008 struct gc8034 *gc8034 = to_gc8034(sd);
2009 struct i2c_client *client = gc8034->client;
2010 int ret = 0;
2011
2012 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
2013 gc8034->cur_mode->width,
2014 gc8034->cur_mode->height,
2015 DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
2016 gc8034->cur_mode->max_fps.numerator));
2017
2018 mutex_lock(&gc8034->mutex);
2019 on = !!on;
2020 if (on == gc8034->streaming)
2021 goto unlock_and_return;
2022
2023 if (on) {
2024 ret = pm_runtime_get_sync(&client->dev);
2025 if (ret < 0) {
2026 pm_runtime_put_noidle(&client->dev);
2027 goto unlock_and_return;
2028 }
2029
2030 ret = __gc8034_start_stream(gc8034);
2031 if (ret) {
2032 v4l2_err(sd, "start stream failed while write regs\n");
2033 pm_runtime_put(&client->dev);
2034 goto unlock_and_return;
2035 }
2036 } else {
2037 __gc8034_stop_stream(gc8034);
2038 pm_runtime_put(&client->dev);
2039 }
2040
2041 gc8034->streaming = on;
2042
2043 unlock_and_return:
2044 mutex_unlock(&gc8034->mutex);
2045
2046 return ret;
2047 }
2048
gc8034_s_power(struct v4l2_subdev * sd,int on)2049 static int gc8034_s_power(struct v4l2_subdev *sd, int on)
2050 {
2051 struct gc8034 *gc8034 = to_gc8034(sd);
2052 struct i2c_client *client = gc8034->client;
2053 int ret = 0;
2054 int retry = 0;
2055
2056 dev_info(&client->dev, "%s(%d) on(%d)\n", __func__, __LINE__, on);
2057 mutex_lock(&gc8034->mutex);
2058
2059 /* If the power state is not modified - no work to do. */
2060 if (gc8034->power_on == !!on)
2061 goto unlock_and_return;
2062
2063 if (on) {
2064 ret = pm_runtime_get_sync(&client->dev);
2065 if (ret < 0) {
2066 pm_runtime_put_noidle(&client->dev);
2067 goto unlock_and_return;
2068 }
2069
2070 while (retry++ < 10) {
2071 ret = gc8034_write_array(gc8034->client, gc8034_global_regs);
2072 if (!ret)
2073 break;
2074 mdelay(100);
2075 dev_info(&client->dev, "gc8034_s_power retry = %d\n", retry);
2076 }
2077 if (retry == 0) {
2078 v4l2_err(sd, "could not set init registers\n");
2079 pm_runtime_put_noidle(&client->dev);
2080 goto unlock_and_return;
2081 }
2082
2083 gc8034->power_on = true;
2084 } else {
2085 pm_runtime_put(&client->dev);
2086 gc8034->power_on = false;
2087 }
2088
2089 unlock_and_return:
2090 mutex_unlock(&gc8034->mutex);
2091
2092 return ret;
2093 }
2094
2095 /* Calculate the delay in us by clock rate and clock cycles */
gc8034_cal_delay(u32 cycles)2096 static inline u32 gc8034_cal_delay(u32 cycles)
2097 {
2098 return DIV_ROUND_UP(cycles, GC8034_XVCLK_FREQ / 1000 / 1000);
2099 }
2100
__gc8034_power_on(struct gc8034 * gc8034)2101 static int __gc8034_power_on(struct gc8034 *gc8034)
2102 {
2103 int ret;
2104 u32 delay_us;
2105 struct device *dev = &gc8034->client->dev;
2106
2107 if (!IS_ERR(gc8034->power_gpio))
2108 gpiod_set_value_cansleep(gc8034->power_gpio, 1);
2109
2110 usleep_range(1000, 2000);
2111
2112 if (!IS_ERR_OR_NULL(gc8034->pins_default)) {
2113 ret = pinctrl_select_state(gc8034->pinctrl,
2114 gc8034->pins_default);
2115 if (ret < 0)
2116 dev_err(dev, "could not set pins\n");
2117 }
2118 ret = clk_set_rate(gc8034->xvclk, GC8034_XVCLK_FREQ);
2119 if (ret < 0)
2120 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
2121 if (clk_get_rate(gc8034->xvclk) != GC8034_XVCLK_FREQ)
2122 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
2123 ret = clk_prepare_enable(gc8034->xvclk);
2124 if (ret < 0) {
2125 dev_err(dev, "Failed to enable xvclk\n");
2126 return ret;
2127 }
2128 if (!IS_ERR(gc8034->reset_gpio))
2129 gpiod_set_value_cansleep(gc8034->reset_gpio, 1);
2130
2131 ret = regulator_bulk_enable(GC8034_NUM_SUPPLIES, gc8034->supplies);
2132 if (ret < 0) {
2133 dev_err(dev, "Failed to enable regulators\n");
2134 goto disable_clk;
2135 }
2136
2137 usleep_range(1000, 1100);
2138 if (!IS_ERR(gc8034->reset_gpio))
2139 gpiod_set_value_cansleep(gc8034->reset_gpio, 0);
2140
2141 usleep_range(500, 1000);
2142 if (!IS_ERR(gc8034->pwdn_gpio))
2143 gpiod_set_value_cansleep(gc8034->pwdn_gpio, 0);
2144
2145 /* 8192 cycles prior to first SCCB transaction */
2146 delay_us = gc8034_cal_delay(8192);
2147 usleep_range(delay_us, delay_us * 2);
2148
2149 mdelay(500);
2150 return 0;
2151
2152 disable_clk:
2153 clk_disable_unprepare(gc8034->xvclk);
2154
2155 return ret;
2156 }
2157
__gc8034_power_off(struct gc8034 * gc8034)2158 static void __gc8034_power_off(struct gc8034 *gc8034)
2159 {
2160 int ret;
2161
2162 if (!IS_ERR(gc8034->pwdn_gpio))
2163 gpiod_set_value_cansleep(gc8034->pwdn_gpio, 1);
2164 clk_disable_unprepare(gc8034->xvclk);
2165 if (!IS_ERR(gc8034->reset_gpio))
2166 gpiod_set_value_cansleep(gc8034->reset_gpio, 1);
2167 if (!IS_ERR_OR_NULL(gc8034->pins_sleep)) {
2168 ret = pinctrl_select_state(gc8034->pinctrl,
2169 gc8034->pins_sleep);
2170 if (ret < 0)
2171 dev_dbg(&gc8034->client->dev, "could not set pins\n");
2172 }
2173 if (!IS_ERR(gc8034->power_gpio))
2174 gpiod_set_value_cansleep(gc8034->power_gpio, 0);
2175
2176 regulator_bulk_disable(GC8034_NUM_SUPPLIES, gc8034->supplies);
2177 }
2178
gc8034_runtime_resume(struct device * dev)2179 static int gc8034_runtime_resume(struct device *dev)
2180 {
2181 struct i2c_client *client = to_i2c_client(dev);
2182 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2183 struct gc8034 *gc8034 = to_gc8034(sd);
2184
2185 return __gc8034_power_on(gc8034);
2186 }
2187
gc8034_runtime_suspend(struct device * dev)2188 static int gc8034_runtime_suspend(struct device *dev)
2189 {
2190 struct i2c_client *client = to_i2c_client(dev);
2191 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2192 struct gc8034 *gc8034 = to_gc8034(sd);
2193
2194 __gc8034_power_off(gc8034);
2195
2196 return 0;
2197 }
2198
2199 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
gc8034_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)2200 static int gc8034_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
2201 {
2202 struct gc8034 *gc8034 = to_gc8034(sd);
2203 struct v4l2_mbus_framefmt *try_fmt =
2204 v4l2_subdev_get_try_format(sd, fh->pad, 0);
2205 const struct gc8034_mode *def_mode = &supported_modes[0];
2206
2207 mutex_lock(&gc8034->mutex);
2208 /* Initialize try_fmt */
2209 try_fmt->width = def_mode->width;
2210 try_fmt->height = def_mode->height;
2211 try_fmt->code = GC8034_MEDIA_BUS_FMT;
2212 try_fmt->field = V4L2_FIELD_NONE;
2213
2214 mutex_unlock(&gc8034->mutex);
2215 /* No crop or compose */
2216
2217 return 0;
2218 }
2219 #endif
2220
gc8034_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)2221 static int gc8034_enum_frame_interval(struct v4l2_subdev *sd,
2222 struct v4l2_subdev_pad_config *cfg,
2223 struct v4l2_subdev_frame_interval_enum *fie)
2224 {
2225 struct gc8034 *gc8034 = to_gc8034(sd);
2226
2227 if (fie->index >= gc8034->cfg_num)
2228 return -EINVAL;
2229
2230 if (fie->code != GC8034_MEDIA_BUS_FMT)
2231 return -EINVAL;
2232
2233 fie->width = supported_modes[fie->index].width;
2234 fie->height = supported_modes[fie->index].height;
2235 fie->interval = supported_modes[fie->index].max_fps;
2236 return 0;
2237 }
2238
gc8034_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)2239 static int gc8034_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
2240 struct v4l2_mbus_config *config)
2241 {
2242 struct gc8034 *sensor = to_gc8034(sd);
2243 struct device *dev = &sensor->client->dev;
2244
2245 dev_info(dev, "%s(%d) enter!\n", __func__, __LINE__);
2246
2247 if (2 == sensor->lane_num) {
2248 config->type = V4L2_MBUS_CSI2_DPHY;
2249 config->flags = V4L2_MBUS_CSI2_2_LANE |
2250 V4L2_MBUS_CSI2_CHANNEL_0 |
2251 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2252 } else if (4 == sensor->lane_num) {
2253 config->type = V4L2_MBUS_CSI2_DPHY;
2254 config->flags = V4L2_MBUS_CSI2_4_LANE |
2255 V4L2_MBUS_CSI2_CHANNEL_0 |
2256 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2257 } else {
2258 dev_err(&sensor->client->dev,
2259 "unsupported lane_num(%d)\n", sensor->lane_num);
2260 }
2261 return 0;
2262 }
2263
2264 static const struct dev_pm_ops gc8034_pm_ops = {
2265 SET_RUNTIME_PM_OPS(gc8034_runtime_suspend,
2266 gc8034_runtime_resume, NULL)
2267 };
2268
2269 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2270 static const struct v4l2_subdev_internal_ops gc8034_internal_ops = {
2271 .open = gc8034_open,
2272 };
2273 #endif
2274
2275 static const struct v4l2_subdev_core_ops gc8034_core_ops = {
2276 .s_power = gc8034_s_power,
2277 .ioctl = gc8034_ioctl,
2278 #ifdef CONFIG_COMPAT
2279 .compat_ioctl32 = gc8034_compat_ioctl32,
2280 #endif
2281 };
2282
2283 static const struct v4l2_subdev_video_ops gc8034_video_ops = {
2284 .s_stream = gc8034_s_stream,
2285 .g_frame_interval = gc8034_g_frame_interval,
2286 };
2287
2288 static const struct v4l2_subdev_pad_ops gc8034_pad_ops = {
2289 .enum_mbus_code = gc8034_enum_mbus_code,
2290 .enum_frame_size = gc8034_enum_frame_sizes,
2291 .enum_frame_interval = gc8034_enum_frame_interval,
2292 .get_fmt = gc8034_get_fmt,
2293 .set_fmt = gc8034_set_fmt,
2294 .get_mbus_config = gc8034_g_mbus_config,
2295 };
2296
2297 static const struct v4l2_subdev_ops gc8034_subdev_ops = {
2298 .core = &gc8034_core_ops,
2299 .video = &gc8034_video_ops,
2300 .pad = &gc8034_pad_ops,
2301 };
2302
gc8034_set_exposure_reg(struct gc8034 * gc8034,u32 exposure)2303 static int gc8034_set_exposure_reg(struct gc8034 *gc8034, u32 exposure)
2304 {
2305 int ret = 0;
2306 u32 cal_shutter = 0;
2307
2308 cal_shutter = exposure >> 1;
2309 cal_shutter = cal_shutter << 1;
2310
2311 gc8034->Dgain_ratio = 256 * exposure / cal_shutter;
2312 ret = gc8034_write_reg(gc8034->client,
2313 GC8034_REG_SET_PAGE, GC8034_SET_PAGE_ZERO);
2314 ret |= gc8034_write_reg(gc8034->client,
2315 GC8034_REG_EXPOSURE_H,
2316 GC8034_FETCH_HIGH_BYTE_EXP(cal_shutter));
2317 ret |= gc8034_write_reg(gc8034->client,
2318 GC8034_REG_EXPOSURE_L,
2319 GC8034_FETCH_LOW_BYTE_EXP(cal_shutter));
2320 return ret;
2321 }
2322
2323 #define MAX_AG_INDEX 9
2324 #define AGC_REG_NUM 14
2325 #define MEAG_INDEX 7
2326
2327 u16 gain_level[MAX_AG_INDEX] = {
2328 0x0040, /* 1.000*/
2329 0x0058, /* 1.375*/
2330 0x007d, /* 1.950*/
2331 0x00ad, /* 2.700*/
2332 0x00f3, /* 3.800*/
2333 0x0159, /* 5.400*/
2334 0x01ea, /* 7.660*/
2335 0x02ac, /*10.688*/
2336 0x03c2, /*15.030*/
2337 };
2338
2339 u8 agc_register[MAX_AG_INDEX][AGC_REG_NUM] = {
2340 /* fullsize */
2341 { 0x00, 0x55, 0x83, 0x01, 0x06, 0x18, 0x20,
2342 0x16, 0x17, 0x50, 0x6c, 0x9b, 0xd8, 0x00 },
2343 { 0x00, 0x55, 0x83, 0x01, 0x06, 0x18, 0x20,
2344 0x16, 0x17, 0x50, 0x6c, 0x9b, 0xd8, 0x00 },
2345 { 0x00, 0x4e, 0x84, 0x01, 0x0c, 0x2e, 0x2d,
2346 0x15, 0x19, 0x47, 0x70, 0x9f, 0xd8, 0x00 },
2347 { 0x00, 0x51, 0x80, 0x01, 0x07, 0x28, 0x32,
2348 0x22, 0x20, 0x49, 0x70, 0x91, 0xd9, 0x00 },
2349 { 0x00, 0x4d, 0x83, 0x01, 0x0f, 0x3b, 0x3b,
2350 0x1c, 0x1f, 0x47, 0x6f, 0x9b, 0xd3, 0x00 },
2351 { 0x00, 0x50, 0x83, 0x01, 0x08, 0x35, 0x46,
2352 0x1e, 0x22, 0x4c, 0x70, 0x9a, 0xd2, 0x00 },
2353 { 0x00, 0x52, 0x80, 0x01, 0x0c, 0x35, 0x3a,
2354 0x2b, 0x2d, 0x4c, 0x67, 0x8d, 0xc0, 0x00 },
2355 { 0x00, 0x52, 0x80, 0x01, 0x0c, 0x35, 0x3a,
2356 0x2b, 0x2d, 0x4c, 0x67, 0x8d, 0xc0, 0x00 },
2357 { 0x00, 0x52, 0x80, 0x01, 0x0c, 0x35, 0x3a,
2358 0x2b, 0x2d, 0x4c, 0x67, 0x8d, 0xc0, 0x00 }
2359 };
2360
gc8034_set_gain_reg(struct gc8034 * gc8034,u32 a_gain)2361 static int gc8034_set_gain_reg(struct gc8034 *gc8034, u32 a_gain)
2362 {
2363 int ret = 0;
2364 u32 temp_gain = 0;
2365 int gain_index = 0;
2366 u32 Dgain_ratio = 0;
2367
2368 Dgain_ratio = gc8034->Dgain_ratio;
2369 for (gain_index = MEAG_INDEX - 1; gain_index >= 0; gain_index--) {
2370 if (a_gain >= gain_level[gain_index]) {
2371 ret = gc8034_write_reg(gc8034->client,
2372 GC8034_REG_SET_PAGE, GC8034_SET_PAGE_ZERO);
2373 ret |= gc8034_write_reg(gc8034->client,
2374 0xb6, gain_index);
2375 temp_gain = 256 * a_gain / gain_level[gain_index];
2376 temp_gain = temp_gain * Dgain_ratio / 256;
2377 ret |= gc8034_write_reg(gc8034->client,
2378 0xb1, temp_gain >> 8);
2379 ret |= gc8034_write_reg(gc8034->client,
2380 0xb2, temp_gain & 0xff);
2381
2382 ret |= gc8034_write_reg(gc8034->client, 0xfe,
2383 agc_register[gain_index][0]);
2384 ret |= gc8034_write_reg(gc8034->client, 0x20,
2385 agc_register[gain_index][1]);
2386 ret |= gc8034_write_reg(gc8034->client, 0x33,
2387 agc_register[gain_index][2]);
2388 ret |= gc8034_write_reg(gc8034->client, 0xfe,
2389 agc_register[gain_index][3]);
2390 ret |= gc8034_write_reg(gc8034->client, 0xdf,
2391 agc_register[gain_index][4]);
2392 ret |= gc8034_write_reg(gc8034->client, 0xe7,
2393 agc_register[gain_index][5]);
2394 ret |= gc8034_write_reg(gc8034->client, 0xe8,
2395 agc_register[gain_index][6]);
2396 ret |= gc8034_write_reg(gc8034->client, 0xe9,
2397 agc_register[gain_index][7]);
2398 ret |= gc8034_write_reg(gc8034->client, 0xea,
2399 agc_register[gain_index][8]);
2400 ret |= gc8034_write_reg(gc8034->client, 0xeb,
2401 agc_register[gain_index][9]);
2402 ret |= gc8034_write_reg(gc8034->client, 0xec,
2403 agc_register[gain_index][10]);
2404 ret |= gc8034_write_reg(gc8034->client, 0xed,
2405 agc_register[gain_index][11]);
2406 ret |= gc8034_write_reg(gc8034->client, 0xee,
2407 agc_register[gain_index][12]);
2408 ret |= gc8034_write_reg(gc8034->client, 0xfe,
2409 agc_register[gain_index][13]);
2410 break;
2411 }
2412 }
2413 return ret;
2414 }
2415
gc8034_set_ctrl(struct v4l2_ctrl * ctrl)2416 static int gc8034_set_ctrl(struct v4l2_ctrl *ctrl)
2417 {
2418 struct gc8034 *gc8034 = container_of(ctrl->handler,
2419 struct gc8034, ctrl_handler);
2420 struct i2c_client *client = gc8034->client;
2421 s64 max;
2422 int ret = 0;
2423 s32 temp;
2424
2425 /* Propagate change of current control to all related controls */
2426 switch (ctrl->id) {
2427 case V4L2_CID_VBLANK:
2428 /* Update max exposure while meeting expected vblanking */
2429 max = gc8034->cur_mode->height + ctrl->val - 4;
2430 __v4l2_ctrl_modify_range(gc8034->exposure,
2431 gc8034->exposure->minimum, max,
2432 gc8034->exposure->step,
2433 gc8034->exposure->default_value);
2434 break;
2435 }
2436
2437 if (!pm_runtime_get_if_in_use(&client->dev))
2438 return 0;
2439
2440 switch (ctrl->id) {
2441 case V4L2_CID_EXPOSURE:
2442 /* 4 least significant bits of expsoure are fractional part */
2443 dev_info(&client->dev, "set exposure value 0x%x\n", ctrl->val);
2444 ret = gc8034_set_exposure_reg(gc8034, ctrl->val);
2445 break;
2446 case V4L2_CID_ANALOGUE_GAIN:
2447 dev_info(&client->dev, "set analog gain value 0x%x\n", ctrl->val);
2448 ret = gc8034_set_gain_reg(gc8034, ctrl->val);
2449 break;
2450 case V4L2_CID_VBLANK:
2451 dev_info(&client->dev, "set vb value 0x%x\n", ctrl->val);
2452 /* VB = VTS - 2448 -36, according android8.1 driver */
2453 temp = ctrl->val + gc8034->cur_mode->height - 2448 - 36;
2454 ret = gc8034_write_reg(gc8034->client,
2455 GC8034_REG_SET_PAGE,
2456 GC8034_SET_PAGE_ZERO);
2457 ret |= gc8034_write_reg(gc8034->client,
2458 GC8034_REG_VTS_H,
2459 (temp >> 8) & 0xff);
2460 ret |= gc8034_write_reg(gc8034->client,
2461 GC8034_REG_VTS_L,
2462 temp & 0xff);
2463 break;
2464 default:
2465 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
2466 __func__, ctrl->id, ctrl->val);
2467 break;
2468 }
2469
2470 pm_runtime_put(&client->dev);
2471
2472 return ret;
2473 }
2474
2475 static const struct v4l2_ctrl_ops gc8034_ctrl_ops = {
2476 .s_ctrl = gc8034_set_ctrl,
2477 };
2478
gc8034_initialize_controls(struct gc8034 * gc8034)2479 static int gc8034_initialize_controls(struct gc8034 *gc8034)
2480 {
2481 const struct gc8034_mode *mode;
2482 struct v4l2_ctrl_handler *handler;
2483 s64 exposure_max, vblank_def;
2484 u32 h_blank;
2485 int ret;
2486
2487 handler = &gc8034->ctrl_handler;
2488 mode = gc8034->cur_mode;
2489 ret = v4l2_ctrl_handler_init(handler, 8);
2490 if (ret)
2491 return ret;
2492 handler->lock = &gc8034->mutex;
2493
2494 gc8034->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
2495 V4L2_CID_LINK_FREQ, 0, 0,
2496 link_freq_menu_items);
2497
2498 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
2499 0, gc8034->pixel_rate, 1, gc8034->pixel_rate);
2500
2501 h_blank = mode->hts_def - mode->width;
2502 gc8034->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
2503 h_blank, h_blank, 1, h_blank);
2504 if (gc8034->hblank)
2505 gc8034->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2506
2507 vblank_def = mode->vts_def - mode->height;
2508 gc8034->vblank = v4l2_ctrl_new_std(handler, &gc8034_ctrl_ops,
2509 V4L2_CID_VBLANK, vblank_def,
2510 GC8034_VTS_MAX - mode->height,
2511 1, vblank_def);
2512
2513 exposure_max = mode->vts_def - 4;
2514 gc8034->exposure = v4l2_ctrl_new_std(handler, &gc8034_ctrl_ops,
2515 V4L2_CID_EXPOSURE, GC8034_EXPOSURE_MIN,
2516 exposure_max, GC8034_EXPOSURE_STEP,
2517 mode->exp_def);
2518
2519 gc8034->anal_gain = v4l2_ctrl_new_std(handler, &gc8034_ctrl_ops,
2520 V4L2_CID_ANALOGUE_GAIN, GC8034_GAIN_MIN,
2521 GC8034_GAIN_MAX, GC8034_GAIN_STEP,
2522 GC8034_GAIN_DEFAULT);
2523 if (handler->error) {
2524 ret = handler->error;
2525 dev_err(&gc8034->client->dev,
2526 "Failed to init controls(%d)\n", ret);
2527 goto err_free_handler;
2528 }
2529
2530 gc8034->subdev.ctrl_handler = handler;
2531
2532 return 0;
2533
2534 err_free_handler:
2535 v4l2_ctrl_handler_free(handler);
2536
2537 return ret;
2538 }
2539
gc8034_check_sensor_id(struct gc8034 * gc8034,struct i2c_client * client)2540 static int gc8034_check_sensor_id(struct gc8034 *gc8034,
2541 struct i2c_client *client)
2542 {
2543 struct device *dev = &gc8034->client->dev;
2544 u16 id = 0;
2545 u8 reg_H = 0;
2546 u8 reg_L = 0;
2547 int ret;
2548
2549 ret = gc8034_read_reg(client, GC8034_REG_CHIP_ID_H, ®_H);
2550 ret |= gc8034_read_reg(client, GC8034_REG_CHIP_ID_L, ®_L);
2551 id = ((reg_H << 8) & 0xff00) | (reg_L & 0xff);
2552 if (id != CHIP_ID) {
2553 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
2554 return -ENODEV;
2555 }
2556 dev_info(dev, "detected gc%04x sensor\n", id);
2557 return ret;
2558 }
2559
gc8034_configure_regulators(struct gc8034 * gc8034)2560 static int gc8034_configure_regulators(struct gc8034 *gc8034)
2561 {
2562 unsigned int i;
2563
2564 for (i = 0; i < GC8034_NUM_SUPPLIES; i++)
2565 gc8034->supplies[i].supply = gc8034_supply_names[i];
2566
2567 return devm_regulator_bulk_get(&gc8034->client->dev,
2568 GC8034_NUM_SUPPLIES,
2569 gc8034->supplies);
2570 }
2571
gc8034_parse_of(struct gc8034 * gc8034)2572 static int gc8034_parse_of(struct gc8034 *gc8034)
2573 {
2574 struct device *dev = &gc8034->client->dev;
2575 struct device_node *endpoint;
2576 struct fwnode_handle *fwnode;
2577 int rval;
2578 unsigned int fps;
2579
2580 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
2581 if (!endpoint) {
2582 dev_err(dev, "Failed to get endpoint\n");
2583 return -EINVAL;
2584 }
2585 fwnode = of_fwnode_handle(endpoint);
2586 rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
2587 if (rval <= 0) {
2588 dev_warn(dev, " Get mipi lane num failed!\n");
2589 return -1;
2590 }
2591
2592 gc8034->lane_num = rval;
2593 if (4 == gc8034->lane_num) {
2594 gc8034->cur_mode = &supported_modes_4lane[0];
2595 supported_modes = supported_modes_4lane;
2596 gc8034->cfg_num = ARRAY_SIZE(supported_modes_4lane);
2597 gc8034_global_regs = gc8034_global_regs_4lane;
2598 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2599 fps = DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
2600 gc8034->cur_mode->max_fps.numerator);
2601 gc8034->pixel_rate = gc8034->cur_mode->vts_def *
2602 gc8034->cur_mode->hts_def * fps;
2603
2604 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
2605 gc8034->lane_num, gc8034->pixel_rate);
2606 } else if (2 == gc8034->lane_num) {
2607 gc8034->cur_mode = &supported_modes_2lane[0];
2608 supported_modes = supported_modes_2lane;
2609 gc8034->cfg_num = ARRAY_SIZE(supported_modes_2lane);
2610 gc8034_global_regs = gc8034_global_regs_2lane;
2611 /*pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
2612 fps = DIV_ROUND_CLOSEST(gc8034->cur_mode->max_fps.denominator,
2613 gc8034->cur_mode->max_fps.numerator);
2614 gc8034->pixel_rate = gc8034->cur_mode->vts_def *
2615 gc8034->cur_mode->hts_def * fps;
2616 dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
2617 gc8034->lane_num, gc8034->pixel_rate);
2618 } else {
2619 dev_err(dev, "unsupported lane_num(%d)\n", gc8034->lane_num);
2620 return -1;
2621 }
2622
2623 return 0;
2624 }
2625
gc8034_probe(struct i2c_client * client,const struct i2c_device_id * id)2626 static int gc8034_probe(struct i2c_client *client,
2627 const struct i2c_device_id *id)
2628 {
2629 struct device *dev = &client->dev;
2630 struct device_node *node = dev->of_node;
2631 struct gc8034 *gc8034;
2632 struct v4l2_subdev *sd;
2633 char facing[2];
2634 int ret;
2635
2636 dev_info(dev, "driver version: %02x.%02x.%02x",
2637 DRIVER_VERSION >> 16,
2638 (DRIVER_VERSION & 0xff00) >> 8,
2639 DRIVER_VERSION & 0x00ff);
2640
2641 gc8034 = devm_kzalloc(dev, sizeof(*gc8034), GFP_KERNEL);
2642 if (!gc8034)
2643 return -ENOMEM;
2644
2645 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2646 &gc8034->module_index);
2647 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2648 &gc8034->module_facing);
2649 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2650 &gc8034->module_name);
2651 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2652 &gc8034->len_name);
2653 if (ret) {
2654 dev_err(dev, "could not get module information!\n");
2655 return -EINVAL;
2656 }
2657 gc8034->client = client;
2658
2659 gc8034->xvclk = devm_clk_get(dev, "xvclk");
2660 if (IS_ERR(gc8034->xvclk)) {
2661 dev_err(dev, "Failed to get xvclk\n");
2662 return -EINVAL;
2663 }
2664
2665 gc8034->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
2666 if (IS_ERR(gc8034->power_gpio))
2667 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
2668 gc8034->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
2669 if (IS_ERR(gc8034->reset_gpio))
2670 dev_warn(dev, "Failed to get reset-gpios\n");
2671
2672 gc8034->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
2673 if (IS_ERR(gc8034->pwdn_gpio))
2674 dev_warn(dev, "Failed to get pwdn-gpios\n");
2675
2676 ret = gc8034_configure_regulators(gc8034);
2677 if (ret) {
2678 dev_err(dev, "Failed to get power regulators\n");
2679 return ret;
2680 }
2681
2682 ret = gc8034_parse_of(gc8034);
2683 if (ret != 0)
2684 return -EINVAL;
2685
2686 gc8034->pinctrl = devm_pinctrl_get(dev);
2687 if (!IS_ERR(gc8034->pinctrl)) {
2688 gc8034->pins_default =
2689 pinctrl_lookup_state(gc8034->pinctrl,
2690 OF_CAMERA_PINCTRL_STATE_DEFAULT);
2691 if (IS_ERR(gc8034->pins_default))
2692 dev_err(dev, "could not get default pinstate\n");
2693
2694 gc8034->pins_sleep =
2695 pinctrl_lookup_state(gc8034->pinctrl,
2696 OF_CAMERA_PINCTRL_STATE_SLEEP);
2697 if (IS_ERR(gc8034->pins_sleep))
2698 dev_err(dev, "could not get sleep pinstate\n");
2699 }
2700
2701 mutex_init(&gc8034->mutex);
2702
2703 sd = &gc8034->subdev;
2704 v4l2_i2c_subdev_init(sd, client, &gc8034_subdev_ops);
2705 ret = gc8034_initialize_controls(gc8034);
2706 if (ret)
2707 goto err_destroy_mutex;
2708
2709 ret = __gc8034_power_on(gc8034);
2710 if (ret)
2711 goto err_free_handler;
2712
2713 ret = gc8034_check_sensor_id(gc8034, client);
2714 if (ret)
2715 goto err_power_off;
2716
2717 gc8034_otp_enable(gc8034);
2718 gc8034_otp_read(gc8034);
2719 gc8034_otp_disable(gc8034);
2720
2721 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
2722 sd->internal_ops = &gc8034_internal_ops;
2723 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
2724 V4L2_SUBDEV_FL_HAS_EVENTS;
2725 #endif
2726 #if defined(CONFIG_MEDIA_CONTROLLER)
2727 gc8034->pad.flags = MEDIA_PAD_FL_SOURCE;
2728 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2729 ret = media_entity_pads_init(&sd->entity, 1, &gc8034->pad);
2730 if (ret < 0)
2731 goto err_power_off;
2732 #endif
2733
2734 memset(facing, 0, sizeof(facing));
2735 if (strcmp(gc8034->module_facing, "back") == 0)
2736 facing[0] = 'b';
2737 else
2738 facing[0] = 'f';
2739
2740 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2741 gc8034->module_index, facing,
2742 GC8034_NAME, dev_name(sd->dev));
2743 ret = v4l2_async_register_subdev_sensor_common(sd);
2744 if (ret) {
2745 dev_err(dev, "v4l2 async register subdev failed\n");
2746 goto err_clean_entity;
2747 }
2748
2749 pm_runtime_set_active(dev);
2750 pm_runtime_enable(dev);
2751 pm_runtime_idle(dev);
2752
2753 return 0;
2754
2755 err_clean_entity:
2756 #if defined(CONFIG_MEDIA_CONTROLLER)
2757 media_entity_cleanup(&sd->entity);
2758 #endif
2759 err_power_off:
2760 __gc8034_power_off(gc8034);
2761 err_free_handler:
2762 v4l2_ctrl_handler_free(&gc8034->ctrl_handler);
2763 err_destroy_mutex:
2764 mutex_destroy(&gc8034->mutex);
2765
2766 return ret;
2767 }
2768
gc8034_remove(struct i2c_client * client)2769 static int gc8034_remove(struct i2c_client *client)
2770 {
2771 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2772 struct gc8034 *gc8034 = to_gc8034(sd);
2773
2774 v4l2_async_unregister_subdev(sd);
2775 #if defined(CONFIG_MEDIA_CONTROLLER)
2776 media_entity_cleanup(&sd->entity);
2777 #endif
2778 v4l2_ctrl_handler_free(&gc8034->ctrl_handler);
2779 mutex_destroy(&gc8034->mutex);
2780
2781 pm_runtime_disable(&client->dev);
2782 if (!pm_runtime_status_suspended(&client->dev))
2783 __gc8034_power_off(gc8034);
2784 pm_runtime_set_suspended(&client->dev);
2785
2786 return 0;
2787 }
2788
2789 #if IS_ENABLED(CONFIG_OF)
2790 static const struct of_device_id gc8034_of_match[] = {
2791 { .compatible = "galaxycore,gc8034" },
2792 {},
2793 };
2794 MODULE_DEVICE_TABLE(of, gc8034_of_match);
2795 #endif
2796
2797 static const struct i2c_device_id gc8034_match_id[] = {
2798 { "galaxycore,gc8034", 0},
2799 { },
2800 };
2801
2802 static struct i2c_driver gc8034_i2c_driver = {
2803 .driver = {
2804 .name = GC8034_NAME,
2805 .pm = &gc8034_pm_ops,
2806 .of_match_table = of_match_ptr(gc8034_of_match),
2807 },
2808 .probe = &gc8034_probe,
2809 .remove = &gc8034_remove,
2810 .id_table = gc8034_match_id,
2811 };
2812
sensor_mod_init(void)2813 static int __init sensor_mod_init(void)
2814 {
2815 return i2c_add_driver(&gc8034_i2c_driver);
2816 }
2817
sensor_mod_exit(void)2818 static void __exit sensor_mod_exit(void)
2819 {
2820 i2c_del_driver(&gc8034_i2c_driver);
2821 }
2822
2823 device_initcall_sync(sensor_mod_init);
2824 module_exit(sensor_mod_exit);
2825
2826 MODULE_DESCRIPTION("GalaxyCore gc8034 sensor driver");
2827 MODULE_LICENSE("GPL v2");
2828