1 /*
2 * Rockchip isp1 driver
3 *
4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/clk.h>
36 #include <linux/compat.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/regmap.h>
40 #include <linux/rk-camera-module.h>
41 #include <linux/videodev2.h>
42 #include <linux/vmalloc.h>
43 #include <linux/kfifo.h>
44 #include <linux/interrupt.h>
45 #include <linux/rk-preisp.h>
46 #include <linux/rkisp21-config.h>
47 #include <linux/iommu.h>
48 #include <media/v4l2-event.h>
49 #include <media/media-entity.h>
50
51 #include "common.h"
52 #include "isp_external.h"
53 #include "regs.h"
54 #include "rkisp_tb_helper.h"
55
56 #define ISP_SUBDEV_NAME DRIVER_NAME "-isp-subdev"
57 /*
58 * NOTE: MIPI controller and input MUX are also configured in this file,
59 * because ISP Subdev is not only describe ISP submodule(input size,format, output size, format),
60 * but also a virtual route device.
61 */
62
63 /*
64 * There are many variables named with format/frame in below code,
65 * please see here for their meaning.
66 *
67 * Cropping regions of ISP
68 *
69 * +---------------------------------------------------------+
70 * | Sensor image/ISP in_frm |
71 * | +---------------------------------------------------+ |
72 * | | ISP_ACQ (for black level) | |
73 * | | in_crop | |
74 * | | +--------------------------------------------+ | |
75 * | | | ISP_IS | | |
76 * | | | rkisp_isp_subdev: out_crop | | |
77 * | | | | | |
78 * | | | | | |
79 * | | | | | |
80 * | | | | | |
81 * | | +--------------------------------------------+ | |
82 * | +---------------------------------------------------+ |
83 * +---------------------------------------------------------+
84 */
85
86 static void rkisp_config_cmsk(struct rkisp_device *dev);
87
88 struct backup_reg {
89 const u32 base;
90 const u32 shd;
91 u32 val;
92 };
93
sd_to_isp_dev(struct v4l2_subdev * sd)94 static inline struct rkisp_device *sd_to_isp_dev(struct v4l2_subdev *sd)
95 {
96 return container_of(sd->v4l2_dev, struct rkisp_device, v4l2_dev);
97 }
98
mbus_pixelcode_to_mipi_dt(u32 pixelcode)99 static int mbus_pixelcode_to_mipi_dt(u32 pixelcode)
100 {
101 int mipi_dt;
102
103 switch (pixelcode) {
104 case MEDIA_BUS_FMT_Y8_1X8:
105 case MEDIA_BUS_FMT_SRGGB8_1X8:
106 case MEDIA_BUS_FMT_SBGGR8_1X8:
107 case MEDIA_BUS_FMT_SGBRG8_1X8:
108 case MEDIA_BUS_FMT_SGRBG8_1X8:
109 mipi_dt = CIF_CSI2_DT_RAW8;
110 break;
111 case MEDIA_BUS_FMT_Y10_1X10:
112 case MEDIA_BUS_FMT_SBGGR10_1X10:
113 case MEDIA_BUS_FMT_SRGGB10_1X10:
114 case MEDIA_BUS_FMT_SGBRG10_1X10:
115 case MEDIA_BUS_FMT_SGRBG10_1X10:
116 mipi_dt = CIF_CSI2_DT_RAW10;
117 break;
118 case MEDIA_BUS_FMT_Y12_1X12:
119 case MEDIA_BUS_FMT_SRGGB12_1X12:
120 case MEDIA_BUS_FMT_SBGGR12_1X12:
121 case MEDIA_BUS_FMT_SGBRG12_1X12:
122 case MEDIA_BUS_FMT_SGRBG12_1X12:
123 mipi_dt = CIF_CSI2_DT_RAW12;
124 break;
125 case MEDIA_BUS_FMT_YUYV8_2X8:
126 case MEDIA_BUS_FMT_YVYU8_2X8:
127 case MEDIA_BUS_FMT_UYVY8_2X8:
128 case MEDIA_BUS_FMT_VYUY8_2X8:
129 mipi_dt = CIF_CSI2_DT_YUV422_8b;
130 break;
131 case MEDIA_BUS_FMT_EBD_1X8:
132 mipi_dt = CIF_CSI2_DT_EBD;
133 break;
134 case MEDIA_BUS_FMT_SPD_2X8:
135 mipi_dt = CIF_CSI2_DT_SPD;
136 break;
137 default:
138 mipi_dt = -EINVAL;
139 }
140 return mipi_dt;
141 }
142
143 /* Get sensor by enabled media link */
get_remote_sensor(struct v4l2_subdev * sd)144 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
145 {
146 struct media_pad *local, *remote;
147 struct media_entity *sensor_me;
148 struct v4l2_subdev *remote_sd = NULL;
149
150 local = &sd->entity.pads[0];
151 if (!local)
152 goto end;
153 remote = rkisp_media_entity_remote_pad(local);
154 if (!remote)
155 goto end;
156
157 //skip csi subdev
158 if (!strcmp(remote->entity->name, CSI_DEV_NAME)) {
159 local = &remote->entity->pads[CSI_SINK];
160 if (!local)
161 goto end;
162 remote = media_entity_remote_pad(local);
163 if (!remote)
164 goto end;
165 }
166
167 sensor_me = remote->entity;
168 remote_sd = media_entity_to_v4l2_subdev(sensor_me);
169 end:
170 return remote_sd;
171 }
172
sd_to_sensor(struct rkisp_device * dev,struct v4l2_subdev * sd)173 static struct rkisp_sensor_info *sd_to_sensor(struct rkisp_device *dev,
174 struct v4l2_subdev *sd)
175 {
176 int i;
177
178 for (i = 0; i < dev->num_sensors; ++i)
179 if (dev->sensors[i].sd == sd)
180 return &dev->sensors[i];
181
182 return NULL;
183 }
184
rkisp_align_sensor_resolution(struct rkisp_device * dev,struct v4l2_rect * crop,bool user)185 int rkisp_align_sensor_resolution(struct rkisp_device *dev,
186 struct v4l2_rect *crop, bool user)
187 {
188 struct v4l2_subdev *sensor = NULL;
189 struct v4l2_subdev_selection sel;
190 u32 code = dev->isp_sdev.in_frm.code;
191 u32 src_w = dev->isp_sdev.in_frm.width;
192 u32 src_h = dev->isp_sdev.in_frm.height;
193 u32 dest_w, dest_h, w, h;
194 int ret = 0;
195
196 if (!crop)
197 return -EINVAL;
198
199 switch (dev->isp_ver) {
200 case ISP_V12:
201 w = clamp_t(u32, src_w,
202 CIF_ISP_INPUT_W_MIN,
203 CIF_ISP_INPUT_W_MAX_V12);
204 h = clamp_t(u32, src_h,
205 CIF_ISP_INPUT_H_MIN,
206 CIF_ISP_INPUT_H_MAX_V12);
207 break;
208 case ISP_V13:
209 w = clamp_t(u32, src_w,
210 CIF_ISP_INPUT_W_MIN,
211 CIF_ISP_INPUT_W_MAX_V13);
212 h = clamp_t(u32, src_h,
213 CIF_ISP_INPUT_H_MIN,
214 CIF_ISP_INPUT_H_MAX_V13);
215 break;
216 case ISP_V21:
217 w = clamp_t(u32, src_w,
218 CIF_ISP_INPUT_W_MIN,
219 CIF_ISP_INPUT_W_MAX_V21);
220 h = clamp_t(u32, src_h,
221 CIF_ISP_INPUT_H_MIN,
222 CIF_ISP_INPUT_H_MAX_V21);
223 break;
224 case ISP_V30:
225 w = dev->hw_dev->is_unite ?
226 CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
227 w = clamp_t(u32, src_w, CIF_ISP_INPUT_W_MIN, w);
228 h = dev->hw_dev->is_unite ?
229 CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
230 h = clamp_t(u32, src_h, CIF_ISP_INPUT_H_MIN, h);
231 break;
232 default:
233 w = clamp_t(u32, src_w,
234 CIF_ISP_INPUT_W_MIN,
235 CIF_ISP_INPUT_W_MAX);
236 h = clamp_t(u32, src_h,
237 CIF_ISP_INPUT_H_MIN,
238 CIF_ISP_INPUT_H_MAX);
239 }
240
241 if (dev->active_sensor)
242 sensor = dev->active_sensor->sd;
243 if (sensor) {
244 /* crop info from sensor */
245 sel.pad = 0;
246 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
247 sel.target = V4L2_SEL_TGT_CROP;
248 /* crop by sensor, isp don't input crop */
249 ret = v4l2_subdev_call(sensor, pad, get_selection, NULL, &sel);
250 if (!ret && !user) {
251 crop->left = 0;
252 crop->top = 0;
253 crop->width = clamp_t(u32, sel.r.width,
254 CIF_ISP_INPUT_W_MIN, w);
255 crop->height = clamp_t(u32, sel.r.height,
256 CIF_ISP_INPUT_H_MIN, h);
257 return 0;
258 }
259
260 if (ret) {
261 sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
262 /* only crop bounds, want to isp to do input crop */
263 ret = v4l2_subdev_call(sensor, pad, get_selection, NULL, &sel);
264 if (!ret) {
265 crop->left = ALIGN(sel.r.left, 2);
266 crop->width = ALIGN(sel.r.width, 2);
267
268 crop->left = clamp_t(u32, crop->left, 0, w);
269 crop->top = clamp_t(u32, sel.r.top, 0, h);
270 crop->width = clamp_t(u32, crop->width,
271 CIF_ISP_INPUT_W_MIN, w - crop->left);
272 crop->height = clamp_t(u32, sel.r.height,
273 CIF_ISP_INPUT_H_MIN, h - crop->top);
274 return 0;
275 }
276 }
277 }
278
279 /* crop from user */
280 if (user) {
281 crop->left = clamp_t(u32, crop->left, 0, w);
282 crop->top = clamp_t(u32, crop->top, 0, h);
283 crop->width = clamp_t(u32, crop->width,
284 CIF_ISP_INPUT_W_MIN, w - crop->left);
285 crop->height = clamp_t(u32, crop->height,
286 CIF_ISP_INPUT_H_MIN, h - crop->top);
287 if ((code & RKISP_MEDIA_BUS_FMT_MASK) == RKISP_MEDIA_BUS_FMT_BAYER &&
288 (ALIGN_DOWN(crop->width, 16) != crop->width ||
289 ALIGN_DOWN(crop->height, 8) != crop->height))
290 v4l2_warn(&dev->v4l2_dev,
291 "Note: bayer raw need width 16 align, height 8 align!\n"
292 "suggest (%d,%d)/%dx%d, specical requirements, Ignore!\n",
293 ALIGN_DOWN(crop->left, 4), crop->top,
294 ALIGN_DOWN(crop->width, 16), ALIGN_DOWN(crop->height, 8));
295 return 0;
296 }
297
298 /* yuv format */
299 if ((code & RKISP_MEDIA_BUS_FMT_MASK) != RKISP_MEDIA_BUS_FMT_BAYER) {
300 crop->left = 0;
301 crop->top = 0;
302 crop->width = min_t(u32, src_w, CIF_ISP_INPUT_W_MAX);
303 crop->height = min_t(u32, src_h, CIF_ISP_INPUT_H_MAX);
304 return 0;
305 }
306
307 /* bayer raw processed by isp need:
308 * width 16 align
309 * height 8 align
310 * width and height no exceeding the max limit
311 */
312 dest_w = ALIGN_DOWN(w, 16);
313 dest_h = ALIGN_DOWN(h, 8);
314
315 /* try to center of crop
316 *4 align to no change bayer raw format
317 */
318 crop->left = ALIGN_DOWN((src_w - dest_w) >> 1, 4);
319 crop->top = (src_h - dest_h) >> 1;
320 crop->width = dest_w;
321 crop->height = dest_h;
322 return 0;
323 }
324
rkisp_media_entity_remote_pad(struct media_pad * pad)325 struct media_pad *rkisp_media_entity_remote_pad(struct media_pad *pad)
326 {
327 struct media_link *link;
328
329 list_for_each_entry(link, &pad->entity->links, list) {
330 if (!(link->flags & MEDIA_LNK_FL_ENABLED) ||
331 !strcmp(link->source->entity->name,
332 DMARX0_VDEV_NAME) ||
333 !strcmp(link->source->entity->name,
334 DMARX1_VDEV_NAME) ||
335 !strcmp(link->source->entity->name,
336 DMARX2_VDEV_NAME))
337 continue;
338 if (link->source == pad)
339 return link->sink;
340 if (link->sink == pad)
341 return link->source;
342 }
343
344 return NULL;
345 }
346
rkisp_update_sensor_info(struct rkisp_device * dev)347 int rkisp_update_sensor_info(struct rkisp_device *dev)
348 {
349 struct v4l2_subdev *sd = &dev->isp_sdev.sd;
350 struct rkisp_sensor_info *sensor;
351 struct v4l2_subdev *sensor_sd;
352 struct v4l2_subdev_format *fmt;
353 int i, ret = 0;
354
355 sensor_sd = get_remote_sensor(sd);
356 if (!sensor_sd)
357 return -ENODEV;
358
359 sensor = sd_to_sensor(dev, sensor_sd);
360 ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
361 0, &sensor->mbus);
362 if (ret && ret != -ENOIOCTLCMD)
363 return ret;
364
365 sensor->fmt[0].pad = 0;
366 sensor->fmt[0].which = V4L2_SUBDEV_FORMAT_ACTIVE;
367 ret = v4l2_subdev_call(sensor->sd, pad, get_fmt,
368 &sensor->cfg, &sensor->fmt[0]);
369 if (ret && ret != -ENOIOCTLCMD)
370 return ret;
371
372 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
373 u8 vc = 0;
374
375 memset(dev->csi_dev.mipi_di, 0,
376 sizeof(dev->csi_dev.mipi_di));
377 for (i = 0; i < dev->csi_dev.max_pad - 1; i++) {
378 struct rkmodule_channel_info ch = { 0 };
379
380 fmt = &sensor->fmt[i];
381 ch.index = i;
382 ret = v4l2_subdev_call(sensor->sd, core, ioctl,
383 RKMODULE_GET_CHANNEL_INFO, &ch);
384 if (ret) {
385 if (i)
386 *fmt = sensor->fmt[0];
387 } else {
388 fmt->format.width = ch.width;
389 fmt->format.height = ch.height;
390 fmt->format.code = ch.bus_fmt;
391 }
392 ret = mbus_pixelcode_to_mipi_dt(fmt->format.code);
393 if (ret < 0) {
394 v4l2_err(&dev->v4l2_dev,
395 "Invalid mipi data type\n");
396 return ret;
397 }
398
399 switch (ch.vc) {
400 case V4L2_MBUS_CSI2_CHANNEL_3:
401 vc = 3;
402 break;
403 case V4L2_MBUS_CSI2_CHANNEL_2:
404 vc = 2;
405 break;
406 case V4L2_MBUS_CSI2_CHANNEL_1:
407 vc = 1;
408 break;
409 case V4L2_MBUS_CSI2_CHANNEL_0:
410 default:
411 vc = 0;
412 }
413 dev->csi_dev.mipi_di[i] = CIF_MIPI_DATA_SEL_DT(ret) |
414 CIF_MIPI_DATA_SEL_VC(vc);
415 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
416 "CSI ch%d vc:%d dt:0x%x %dx%d\n",
417 i, vc, ret,
418 fmt->format.width,
419 fmt->format.height);
420 }
421 }
422
423 v4l2_subdev_call(sensor->sd, video, g_frame_interval, &sensor->fi);
424 dev->active_sensor = sensor;
425
426 return ret;
427 }
428
rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)429 u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)
430 {
431 u32 pixelformat;
432
433 switch (pixelcode) {
434 case MEDIA_BUS_FMT_Y8_1X8:
435 pixelformat = V4L2_PIX_FMT_GREY;
436 break;
437 case MEDIA_BUS_FMT_SBGGR8_1X8:
438 pixelformat = V4L2_PIX_FMT_SBGGR8;
439 break;
440 case MEDIA_BUS_FMT_SGBRG8_1X8:
441 pixelformat = V4L2_PIX_FMT_SGBRG8;
442 break;
443 case MEDIA_BUS_FMT_SGRBG8_1X8:
444 pixelformat = V4L2_PIX_FMT_SGRBG8;
445 break;
446 case MEDIA_BUS_FMT_SRGGB8_1X8:
447 pixelformat = V4L2_PIX_FMT_SRGGB8;
448 break;
449 case MEDIA_BUS_FMT_Y10_1X10:
450 pixelformat = V4L2_PIX_FMT_Y10;
451 break;
452 case MEDIA_BUS_FMT_SBGGR10_1X10:
453 pixelformat = V4L2_PIX_FMT_SBGGR10;
454 break;
455 case MEDIA_BUS_FMT_SGBRG10_1X10:
456 pixelformat = V4L2_PIX_FMT_SGBRG10;
457 break;
458 case MEDIA_BUS_FMT_SGRBG10_1X10:
459 pixelformat = V4L2_PIX_FMT_SGRBG10;
460 break;
461 case MEDIA_BUS_FMT_SRGGB10_1X10:
462 pixelformat = V4L2_PIX_FMT_SRGGB10;
463 break;
464 case MEDIA_BUS_FMT_Y12_1X12:
465 pixelformat = V4L2_PIX_FMT_Y12;
466 break;
467 case MEDIA_BUS_FMT_SBGGR12_1X12:
468 pixelformat = V4L2_PIX_FMT_SBGGR12;
469 break;
470 case MEDIA_BUS_FMT_SGBRG12_1X12:
471 pixelformat = V4L2_PIX_FMT_SGBRG12;
472 break;
473 case MEDIA_BUS_FMT_SGRBG12_1X12:
474 pixelformat = V4L2_PIX_FMT_SGRBG12;
475 break;
476 case MEDIA_BUS_FMT_SRGGB12_1X12:
477 pixelformat = V4L2_PIX_FMT_SRGGB12;
478 break;
479 case MEDIA_BUS_FMT_EBD_1X8:
480 pixelformat = V4l2_PIX_FMT_EBD8;
481 break;
482 case MEDIA_BUS_FMT_SPD_2X8:
483 pixelformat = V4l2_PIX_FMT_SPD16;
484 break;
485 default:
486 pixelformat = V4L2_PIX_FMT_SRGGB10;
487 }
488
489 return pixelformat;
490 }
491
492
493 /*
494 * for hdr read back mode, rawrd read back data
495 * this will update rawrd base addr to shadow.
496 */
rkisp_trigger_read_back(struct rkisp_device * dev,u8 dma2frm,u32 mode,bool is_try)497 void rkisp_trigger_read_back(struct rkisp_device *dev, u8 dma2frm, u32 mode, bool is_try)
498 {
499 struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
500 struct rkisp_hw_dev *hw = dev->hw_dev;
501 u32 val, cur_frame_id, tmp, rd_mode;
502 u64 iq_feature = hw->iq_feature;
503 bool is_feature_on = hw->is_feature_on;
504 bool is_upd = false, is_3dlut_upd = false;
505
506 hw->cur_dev_id = dev->dev_id;
507 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
508
509 val = 0;
510 if (mode & T_START_X1) {
511 rd_mode = HDR_RDBK_FRAME1;
512 } else if (mode & T_START_X2) {
513 rd_mode = HDR_RDBK_FRAME2;
514 val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
515 } else if (mode & T_START_X3) {
516 rd_mode = HDR_RDBK_FRAME3;
517 val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
518 } else {
519 rd_mode = dev->rd_mode;
520 val = rkisp_read(dev, ISP_HDRMGE_BASE, false) & 0xf;
521 }
522
523 if (is_feature_on) {
524 if ((ISP2X_MODULE_HDRMGE & ~iq_feature) && (val & SW_HDRMGE_EN)) {
525 v4l2_err(&dev->v4l2_dev, "hdrmge is not supported\n");
526 return;
527 }
528 }
529
530 if (rd_mode != dev->rd_mode) {
531 rkisp_unite_set_bits(dev, ISP_HDRMGE_BASE, ISP_HDRMGE_MODE_MASK,
532 val, false, hw->is_unite);
533 dev->skip_frame = 2;
534 is_upd = true;
535 }
536
537 if (dev->isp_ver == ISP_V20 && dev->dmarx_dev.trigger == T_MANUAL && !is_try) {
538 if (dev->rd_mode != rd_mode && dev->br_dev.en) {
539 tmp = dev->isp_sdev.in_crop.height;
540 val = rkisp_read(dev, CIF_DUAL_CROP_CTRL, false);
541 if (rd_mode == HDR_RDBK_FRAME1) {
542 val |= CIF_DUAL_CROP_MP_MODE_YUV;
543 tmp += RKMODULE_EXTEND_LINE;
544 } else {
545 val &= ~CIF_DUAL_CROP_MP_MODE_YUV;
546 }
547 rkisp_write(dev, CIF_DUAL_CROP_CTRL, val, false);
548 rkisp_write(dev, CIF_ISP_ACQ_V_SIZE, tmp, false);
549 rkisp_write(dev, CIF_ISP_OUT_V_SIZE, tmp, false);
550 }
551 dev->rd_mode = rd_mode;
552 rkisp_rawrd_set_pic_size(dev,
553 dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2].out_fmt.width,
554 dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2].out_fmt.height);
555 }
556 dev->rd_mode = rd_mode;
557
558 rkisp_params_first_cfg(&dev->params_vdev, &dev->isp_sdev.in_fmt,
559 dev->isp_sdev.quantization);
560 rkisp_params_cfg(params_vdev, cur_frame_id);
561 rkisp_config_cmsk(dev);
562 if (!hw->is_single && !is_try) {
563 rkisp_update_regs(dev, CTRL_VI_ISP_PATH, SUPER_IMP_COLOR_CR);
564 rkisp_update_regs(dev, DUAL_CROP_M_H_OFFS, DUAL_CROP_S_V_SIZE);
565 rkisp_update_regs(dev, ISP_ACQ_PROP, DUAL_CROP_CTRL);
566 rkisp_update_regs(dev, MAIN_RESIZE_SCALE_HY, MI_WR_CTRL);
567 rkisp_update_regs(dev, SELF_RESIZE_SCALE_HY, MAIN_RESIZE_CTRL);
568 rkisp_update_regs(dev, ISP_GAMMA_OUT_CTRL, SELF_RESIZE_CTRL);
569 rkisp_update_regs(dev, MI_RD_CTRL2, ISP_LSC_CTRL);
570 rkisp_update_regs(dev, MI_MP_WR_Y_BASE, MI_MP_WR_Y_LLENGTH);
571 rkisp_update_regs(dev, ISP_LSC_XGRAD_01, ISP_RAWAWB_RAM_DATA);
572 if (dev->isp_ver == ISP_V20 &&
573 (rkisp_read(dev, ISP_DHAZ_CTRL, false) & ISP_DHAZ_ENMUX ||
574 rkisp_read(dev, ISP_HDRTMO_CTRL, false) & ISP_HDRTMO_EN)) {
575 dma2frm += (dma2frm ? 0 : 1);
576 } else if (dev->isp_ver == ISP_V21) {
577 val = rkisp_read(dev, MI_WR_CTRL2, false);
578 rkisp_set_bits(dev, MI_WR_CTRL2, 0, val, true);
579 rkisp_write(dev, MI_WR_INIT, ISP21_SP_FORCE_UPD | ISP21_MP_FORCE_UPD, true);
580 /* sensor mode & index */
581 val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
582 val |= ISP21_SENSOR_MODE(hw->dev_num >= 3 ? 2 : hw->dev_num - 1) |
583 ISP21_SENSOR_INDEX(dev->dev_id);
584 writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
585 } else if (dev->isp_ver == ISP_V30) {
586 val = rkisp_read(dev, MI_WR_CTRL2, false);
587 val |= ISP3X_MPSELF_UPD | ISP3X_SPSELF_UPD | ISP3X_BPSELF_UPD |
588 ISP3X_BAY3D_RDSELF_UPD | ISP3X_DBR_RDSELF_UPD |
589 ISP3X_DBR_WRSELF_UPD | ISP3X_GAINSELF_UPD |
590 ISP3X_BAY3D_IIRSELF_UPD | ISP3X_BAY3D_CURSELF_UPD |
591 ISP3X_BAY3D_DSSELF_UPD;
592 writel(val, hw->base_addr + MI_WR_CTRL2);
593
594 val = rkisp_read(dev, ISP3X_MPFBC_CTRL, false);
595 val |= ISP3X_MPFBC_FORCE_UPD;
596 writel(val, hw->base_addr + ISP3X_MPFBC_CTRL);
597
598 /* sensor mode & index */
599 val = rkisp_read_reg_cache(dev, ISP_ACQ_H_OFFS);
600 val |= ISP21_SENSOR_MODE(hw->dev_num >= 3 ? 2 : hw->dev_num - 1) |
601 ISP21_SENSOR_INDEX(dev->dev_id);
602 writel(val, hw->base_addr + ISP_ACQ_H_OFFS);
603 }
604 is_upd = true;
605 }
606
607 if (dev->isp_ver == ISP_V21 || dev->isp_ver == ISP_V30)
608 dma2frm = 0;
609 if (dma2frm > 2)
610 dma2frm = 2;
611 if (dma2frm == 2)
612 dev->rdbk_cnt_x3++;
613 else if (dma2frm == 1)
614 dev->rdbk_cnt_x2++;
615 else
616 dev->rdbk_cnt_x1++;
617 dev->rdbk_cnt++;
618
619 rkisp_params_cfgsram(params_vdev);
620 params_vdev->rdbk_times = dma2frm + 1;
621
622 /* read 3d lut at frame end */
623 if (hw->is_single && is_upd &&
624 rkisp_read_reg_cache(dev, ISP_3DLUT_UPDATE) & 0x1) {
625 rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
626 is_3dlut_upd = true;
627 }
628 if (is_upd) {
629 val = rkisp_read(dev, ISP_CTRL, false);
630 val |= CIF_ISP_CTRL_ISP_CFG_UPD;
631 rkisp_write(dev, ISP_CTRL, val, true);
632 }
633 if (is_3dlut_upd)
634 rkisp_write(dev, ISP_3DLUT_UPDATE, 1, true);
635
636 memset(dev->filt_state, 0, sizeof(dev->filt_state));
637 dev->filt_state[RDBK_F_VS] = dma2frm;
638
639 val = rkisp_read(dev, CSI2RX_CTRL0, true);
640 val &= ~SW_IBUF_OP_MODE(0xf);
641 tmp = SW_IBUF_OP_MODE(dev->rd_mode);
642 val |= tmp | SW_CSI2RX_EN | SW_DMA_2FRM_MODE(dma2frm);
643 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
644 "readback frame:%d time:%d 0x%x\n",
645 cur_frame_id, dma2frm + 1, val);
646 if (!dma2frm)
647 rkisp_bridge_update_mi(dev, 0);
648 if (!hw->is_shutdown)
649 rkisp_unite_write(dev, CSI2RX_CTRL0, val, true, hw->is_unite);
650 }
651
rkisp_rdbk_trigger_handle(struct rkisp_device * dev,u32 cmd)652 static void rkisp_rdbk_trigger_handle(struct rkisp_device *dev, u32 cmd)
653 {
654 struct rkisp_hw_dev *hw = dev->hw_dev;
655 struct rkisp_device *isp = NULL;
656 struct isp2x_csi_trigger t = { 0 };
657 unsigned long lock_flags = 0;
658 int i, times = -1, max = 0, id = 0;
659 int len[DEV_MAX] = { 0 };
660 u32 mode = 0;
661
662 spin_lock_irqsave(&hw->rdbk_lock, lock_flags);
663 if (cmd == T_CMD_END)
664 hw->is_idle = true;
665 if (hw->is_shutdown)
666 hw->is_idle = false;
667 if (!hw->is_idle)
668 goto end;
669 if (hw->monitor.state & ISP_MIPI_ERROR && hw->monitor.is_en)
670 goto end;
671
672 for (i = 0; i < hw->dev_num; i++) {
673 isp = hw->isp[i];
674 if (!(isp->isp_state & ISP_START))
675 continue;
676 rkisp_rdbk_trigger_event(isp, T_CMD_LEN, &len[i]);
677 if (max < len[i]) {
678 max = len[i];
679 id = i;
680 }
681 }
682
683 if (max) {
684 v4l2_dbg(2, rkisp_debug, &dev->v4l2_dev,
685 "trigger fifo len:%d\n", max);
686 isp = hw->isp[id];
687 rkisp_rdbk_trigger_event(isp, T_CMD_DEQUEUE, &t);
688 isp->dmarx_dev.pre_frame = isp->dmarx_dev.cur_frame;
689 if (t.frame_id > isp->dmarx_dev.pre_frame.id &&
690 t.frame_id - isp->dmarx_dev.pre_frame.id > 1)
691 isp->isp_sdev.dbg.frameloss +=
692 t.frame_id - isp->dmarx_dev.pre_frame.id + 1;
693 isp->dmarx_dev.cur_frame.id = t.frame_id;
694 isp->dmarx_dev.cur_frame.sof_timestamp = t.sof_timestamp;
695 isp->dmarx_dev.cur_frame.timestamp = t.frame_timestamp;
696 isp->isp_sdev.frm_timestamp = t.sof_timestamp;
697 mode = t.mode;
698 times = t.times;
699 hw->cur_dev_id = id;
700 hw->is_idle = false;
701 }
702 end:
703 spin_unlock_irqrestore(&hw->rdbk_lock, lock_flags);
704 if (times >= 0)
705 rkisp_trigger_read_back(isp, times, mode, false);
706 }
707
rkisp_rdbk_trigger_event(struct rkisp_device * dev,u32 cmd,void * arg)708 int rkisp_rdbk_trigger_event(struct rkisp_device *dev, u32 cmd, void *arg)
709 {
710 struct kfifo *fifo = &dev->rdbk_kfifo;
711 struct isp2x_csi_trigger *trigger = NULL;
712 unsigned long lock_flags = 0;
713 int val, ret = 0;
714
715 if (dev->dmarx_dev.trigger != T_MANUAL)
716 return 0;
717
718 spin_lock_irqsave(&dev->rdbk_lock, lock_flags);
719 switch (cmd) {
720 case T_CMD_QUEUE:
721 trigger = arg;
722 if (!trigger)
723 break;
724 if (!kfifo_is_full(fifo))
725 kfifo_in(fifo, trigger, sizeof(*trigger));
726 else
727 v4l2_err(&dev->v4l2_dev, "rdbk fifo is full\n");
728 break;
729 case T_CMD_DEQUEUE:
730 if (!kfifo_is_empty(fifo))
731 ret = kfifo_out(fifo, arg, sizeof(struct isp2x_csi_trigger));
732 if (!ret)
733 ret = -EINVAL;
734 break;
735 case T_CMD_LEN:
736 val = kfifo_len(fifo) / sizeof(struct isp2x_csi_trigger);
737 *(u32 *)arg = val;
738 break;
739 default:
740 break;
741 }
742 spin_unlock_irqrestore(&dev->rdbk_lock, lock_flags);
743
744 if (cmd == T_CMD_QUEUE || cmd == T_CMD_END)
745 rkisp_rdbk_trigger_handle(dev, cmd);
746 return ret;
747 }
748
rkisp_check_idle(struct rkisp_device * dev,u32 irq)749 void rkisp_check_idle(struct rkisp_device *dev, u32 irq)
750 {
751 u32 val = 0;
752
753 dev->irq_ends |= (irq & dev->irq_ends_mask);
754 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
755 "%s irq:0x%x ends:0x%x mask:0x%x\n",
756 __func__, irq, dev->irq_ends, dev->irq_ends_mask);
757 if (dev->irq_ends == dev->irq_ends_mask && dev->hw_dev->monitor.is_en) {
758 dev->hw_dev->monitor.retry = 0;
759 dev->hw_dev->monitor.state |= ISP_FRAME_END;
760 if (!completion_done(&dev->hw_dev->monitor.cmpl))
761 complete(&dev->hw_dev->monitor.cmpl);
762 }
763 if (dev->irq_ends != dev->irq_ends_mask || !IS_HDR_RDBK(dev->rd_mode))
764 return;
765
766 /* check output stream is off */
767 val = ISP_FRAME_MP | ISP_FRAME_SP | ISP_FRAME_MPFBC | ISP_FRAME_BP;
768 if (!(dev->irq_ends_mask & val))
769 dev->isp_state = ISP_STOP;
770
771 val = 0;
772 dev->irq_ends = 0;
773 switch (dev->rd_mode) {
774 case HDR_RDBK_FRAME3://for rd1 rd0 rd2
775 val |= RAW1_RD_FRAME;
776 /* FALLTHROUGH */
777 case HDR_RDBK_FRAME2://for rd0 rd2
778 val |= RAW0_RD_FRAME;
779 /* FALLTHROUGH */
780 default:// for rd2
781 val |= RAW2_RD_FRAME;
782 /* FALLTHROUGH */
783 }
784 rkisp2_rawrd_isr(val, dev);
785 if (dev->dmarx_dev.trigger == T_MANUAL)
786 rkisp_rdbk_trigger_event(dev, T_CMD_END, NULL);
787 if (dev->isp_state == ISP_STOP)
788 wake_up(&dev->sync_onoff);
789 }
790
rkisp_set_state(u32 * state,u32 val)791 static void rkisp_set_state(u32 *state, u32 val)
792 {
793 u32 mask = 0xff;
794
795 if (val < ISP_STOP)
796 mask = 0xff00;
797 *state &= mask;
798 *state |= val;
799 }
800
801 /*
802 * Image Stabilization.
803 * This should only be called when configuring CIF
804 * or at the frame end interrupt
805 */
rkisp_config_ism(struct rkisp_device * dev)806 static void rkisp_config_ism(struct rkisp_device *dev)
807 {
808 struct v4l2_rect *out_crop = &dev->isp_sdev.out_crop;
809 u32 width = out_crop->width, mult = 1;
810 bool is_unite = dev->hw_dev->is_unite;
811
812 /* isp2.0 no ism */
813 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21)
814 return;
815
816 if (is_unite)
817 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
818 rkisp_unite_write(dev, CIF_ISP_IS_RECENTER, 0, false, is_unite);
819 rkisp_unite_write(dev, CIF_ISP_IS_MAX_DX, 0, false, is_unite);
820 rkisp_unite_write(dev, CIF_ISP_IS_MAX_DY, 0, false, is_unite);
821 rkisp_unite_write(dev, CIF_ISP_IS_DISPLACE, 0, false, is_unite);
822 rkisp_unite_write(dev, CIF_ISP_IS_H_OFFS, out_crop->left, false, is_unite);
823 rkisp_unite_write(dev, CIF_ISP_IS_V_OFFS, out_crop->top, false, is_unite);
824 rkisp_unite_write(dev, CIF_ISP_IS_H_SIZE, width, false, is_unite);
825 if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced)
826 mult = 2;
827 rkisp_unite_write(dev, CIF_ISP_IS_V_SIZE, out_crop->height / mult,
828 false, is_unite);
829
830 if (dev->isp_ver == ISP_V30)
831 return;
832
833 /* IS(Image Stabilization) is always on, working as output crop */
834 rkisp_write(dev, CIF_ISP_IS_CTRL, 1, false);
835 }
836
rkisp_reset_handle_v2x(struct rkisp_device * dev)837 static int rkisp_reset_handle_v2x(struct rkisp_device *dev)
838 {
839 void __iomem *base = dev->base_addr;
840 void *reg_buf = NULL;
841 u32 *reg, *reg1, i;
842 struct backup_reg backup[] = {
843 {
844 .base = MI_MP_WR_Y_BASE,
845 .shd = MI_MP_WR_Y_BASE_SHD,
846 }, {
847 .base = MI_MP_WR_CB_BASE,
848 .shd = MI_MP_WR_CB_BASE_SHD,
849 }, {
850 .base = MI_MP_WR_CR_BASE,
851 .shd = MI_MP_WR_CR_BASE_SHD,
852 }, {
853 .base = MI_SP_WR_Y_BASE,
854 .shd = MI_SP_WR_Y_BASE_SHD,
855 }, {
856 .base = MI_SP_WR_CB_BASE,
857 .shd = MI_SP_WR_CB_BASE_AD_SHD,
858 }, {
859 .base = MI_SP_WR_CR_BASE,
860 .shd = MI_SP_WR_CR_BASE_AD_SHD,
861 }, {
862 .base = MI_RAW0_WR_BASE,
863 .shd = MI_RAW0_WR_BASE_SHD,
864 }, {
865 .base = MI_RAW1_WR_BASE,
866 .shd = MI_RAW1_WR_BASE_SHD,
867 }, {
868 .base = MI_RAW2_WR_BASE,
869 .shd = MI_RAW2_WR_BASE_SHD,
870 }, {
871 .base = MI_RAW3_WR_BASE,
872 .shd = MI_RAW3_WR_BASE_SHD,
873 }, {
874 .base = MI_RAW0_RD_BASE,
875 .shd = MI_RAW0_RD_BASE_SHD,
876 }, {
877 .base = MI_RAW1_RD_BASE,
878 .shd = MI_RAW1_RD_BASE_SHD,
879 }, {
880 .base = MI_RAW2_RD_BASE,
881 .shd = MI_RAW2_RD_BASE_SHD,
882 }, {
883 .base = MI_GAIN_WR_BASE,
884 .shd = MI_GAIN_WR_BASE_SHD,
885 }
886 };
887
888 reg_buf = kzalloc(RKISP_ISP_SW_REG_SIZE, GFP_KERNEL);
889 if (!reg_buf)
890 return -ENOMEM;
891
892 dev_info(dev->dev, "%s enter\n", __func__);
893
894 memcpy_fromio(reg_buf, base, RKISP_ISP_SW_REG_SIZE);
895 rkisp_soft_reset(dev->hw_dev, true);
896
897 /* process special reg */
898 reg = reg_buf + ISP_CTRL;
899 *reg &= ~(CIF_ISP_CTRL_ISP_ENABLE |
900 CIF_ISP_CTRL_ISP_INFORM_ENABLE |
901 CIF_ISP_CTRL_ISP_CFG_UPD);
902 reg = reg_buf + MI_WR_INIT;
903 *reg = 0;
904 reg = reg_buf + CSI2RX_CTRL0;
905 *reg &= ~SW_CSI2RX_EN;
906 /* skip mmu range */
907 memcpy_toio(base, reg_buf, ISP21_MI_BAY3D_RD_BASE_SHD);
908 memcpy_toio(base + CSI2RX_CTRL0, reg_buf + CSI2RX_CTRL0,
909 RKISP_ISP_SW_REG_SIZE - CSI2RX_CTRL0);
910 /* config shd_reg to base_reg */
911 for (i = 0; i < ARRAY_SIZE(backup); i++) {
912 reg = reg_buf + backup[i].base;
913 reg1 = reg_buf + backup[i].shd;
914 backup[i].val = *reg;
915 writel(*reg1, base + backup[i].base);
916 }
917
918 /* clear state */
919 dev->isp_err_cnt = 0;
920 dev->isp_state &= ~ISP_ERROR;
921 rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
922 dev->hw_dev->monitor.state = ISP_FRAME_END;
923
924 /* update module */
925 reg = reg_buf + DUAL_CROP_CTRL;
926 if (*reg & 0xf)
927 writel(*reg | CIF_DUAL_CROP_CFG_UPD, base + DUAL_CROP_CTRL);
928 reg = reg_buf + SELF_RESIZE_CTRL;
929 if (*reg & 0xf)
930 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + SELF_RESIZE_CTRL);
931 reg = reg_buf + MAIN_RESIZE_CTRL;
932 if (*reg & 0xf)
933 writel(*reg | CIF_RSZ_CTRL_CFG_UPD, base + MAIN_RESIZE_CTRL);
934
935 /* update mi and isp, base_reg will update to shd_reg */
936 force_cfg_update(dev);
937 reg = reg_buf + ISP_CTRL;
938 *reg |= CIF_ISP_CTRL_ISP_ENABLE |
939 CIF_ISP_CTRL_ISP_INFORM_ENABLE |
940 CIF_ISP_CTRL_ISP_CFG_UPD;
941 writel(*reg, base + ISP_CTRL);
942 udelay(50);
943 /* config base_reg */
944 for (i = 0; i < ARRAY_SIZE(backup); i++)
945 writel(backup[i].val, base + backup[i].base);
946 /* mpfbc base_reg = shd_reg, write is base but read is shd */
947 if (dev->isp_ver == ISP_V20)
948 writel(rkisp_read_reg_cache(dev, ISP_MPFBC_HEAD_PTR),
949 base + ISP_MPFBC_HEAD_PTR);
950 rkisp_set_bits(dev, CIF_ISP_IMSC, 0, CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR, true);
951 if (IS_HDR_RDBK(dev->hdr.op_mode)) {
952 if (!dev->hw_dev->is_idle)
953 rkisp_trigger_read_back(dev, 1, 0, true);
954 else
955 rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, NULL);
956 }
957 kfree(reg_buf);
958 dev_info(dev->dev, "%s exit\n", __func__);
959 return 0;
960 }
961
rkisp_restart_monitor(struct work_struct * work)962 static void rkisp_restart_monitor(struct work_struct *work)
963 {
964 struct rkisp_monitor *monitor =
965 container_of(work, struct rkisp_monitor, work);
966 struct rkisp_hw_dev *hw = monitor->dev;
967 struct rkisp_device *isp;
968 struct rkisp_pipeline *p;
969 int ret, i, j, timeout = 5, mipi_irq_cnt = 0;
970
971 if (!monitor->reset_handle) {
972 monitor->is_en = false;
973 return;
974 }
975
976 dev_info(hw->dev, "%s enter\n", __func__);
977 while (!(monitor->state & ISP_STOP) && monitor->is_en) {
978 ret = wait_for_completion_timeout(&monitor->cmpl,
979 msecs_to_jiffies(100));
980 /* isp stop to exit
981 * isp err to reset
982 * mipi err wait isp idle, then reset
983 */
984 if (monitor->state & ISP_STOP ||
985 (ret && !(monitor->state & ISP_ERROR)) ||
986 (!ret &&
987 monitor->state & ISP_FRAME_END &&
988 !(monitor->state & ISP_MIPI_ERROR))) {
989 for (i = 0; i < hw->dev_num; i++) {
990 isp = hw->isp[i];
991 if (!(isp->isp_inp & INP_CSI))
992 continue;
993 if (!(isp->isp_state & ISP_START))
994 break;
995 if (isp->csi_dev.irq_cnt != mipi_irq_cnt) {
996 mipi_irq_cnt = isp->csi_dev.irq_cnt;
997 timeout = 5;
998 } else if (mipi_irq_cnt && timeout-- == 0) {
999 /* mipi no input */
1000 monitor->state |= ISP_MIPI_ERROR;
1001 }
1002 }
1003 continue;
1004 }
1005 dev_info(hw->dev, "isp%d to restart state:0x%x try:%d mipi_irq_cnt:%d\n",
1006 hw->cur_dev_id, monitor->state, monitor->retry, mipi_irq_cnt);
1007 if (monitor->retry++ > RKISP_MAX_RETRY_CNT || hw->is_shutdown) {
1008 monitor->is_en = false;
1009 break;
1010 }
1011 for (i = 0; i < hw->dev_num; i++) {
1012 isp = hw->isp[i];
1013 if (isp->isp_inp & INP_CSI ||
1014 isp->isp_inp & INP_DVP ||
1015 isp->isp_inp & INP_LVDS) {
1016 if (!(isp->isp_state & ISP_START))
1017 break;
1018 /* subdev stream off */
1019 p = &isp->pipe;
1020 for (j = p->num_subdevs - 1; j >= 0; j--)
1021 v4l2_subdev_call(p->subdevs[j], video, s_stream, 0);
1022 for (i = 0; i < ISP2X_MIPI_RAW_MAX; i++) {
1023 isp->luma_vdev.ystat_isrcnt[i] = 0;
1024 isp->luma_vdev.ystat_rdflg[i] = 0;
1025 }
1026 }
1027 }
1028
1029 /* restart isp */
1030 isp = hw->isp[hw->cur_dev_id];
1031 ret = monitor->reset_handle(isp);
1032 if (ret) {
1033 monitor->is_en = false;
1034 break;
1035 }
1036
1037 for (i = 0; i < hw->dev_num; i++) {
1038 isp = hw->isp[i];
1039 if (isp->isp_inp & INP_CSI ||
1040 isp->isp_inp & INP_DVP ||
1041 isp->isp_inp & INP_LVDS) {
1042 if (!(isp->isp_state & ISP_START))
1043 break;
1044 if (isp->isp_inp & INP_CSI) {
1045 rkisp_write(isp, CSI2RX_MASK_PHY, 0xF0FFFF, true);
1046 rkisp_write(isp, CSI2RX_MASK_PACKET, 0xF1FFFFF, true);
1047 rkisp_write(isp, CSI2RX_MASK_OVERFLOW, 0x7F7FF1, true);
1048 }
1049 /* subdev stream on */
1050 isp->csi_dev.err_cnt = 0;
1051 isp->isp_state &= ~ISP_MIPI_ERROR;
1052 p = &isp->pipe;
1053 for (j = 0; j < p->num_subdevs; j++)
1054 v4l2_subdev_call(p->subdevs[j], video, s_stream, 1);
1055 }
1056 }
1057 }
1058 dev_dbg(hw->dev, "%s exit\n", __func__);
1059 }
1060
rkisp_monitor_init(struct rkisp_device * dev)1061 static void rkisp_monitor_init(struct rkisp_device *dev)
1062 {
1063 struct rkisp_monitor *monitor = &dev->hw_dev->monitor;
1064
1065 monitor->dev = dev->hw_dev;
1066 monitor->reset_handle = NULL;
1067 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V21)
1068 monitor->reset_handle = rkisp_reset_handle_v2x;
1069
1070 init_completion(&monitor->cmpl);
1071 INIT_WORK(&monitor->work, rkisp_restart_monitor);
1072 }
1073
1074 /*
1075 * RGB to YUV color space, default BT601
1076 * BT601:
1077 * Y = 0.299R + 0.587G + 0.114B
1078 * CB = -0.1687R - 0.3313G + 0.5B
1079 * CR = 0.5R - 0.4187G - 0.0813B
1080 * BT709:
1081 * Y = 0.2126R + 0.7152G + 0.0722B
1082 * CB = -0.1146R - 0.3854G + 0.5B
1083 * CR = 0.5R - 0.4542G - 0.0458B
1084 * BT2020:
1085 * Y = 0.2627R + 0.678G + 0.0593B
1086 * CB = -0.1396R - 0.3604G + 0.5B
1087 * CR = 0.5R - 0.4598G - 0.0402B
1088 * 9 bit coeffs are signed integer values with 7 bit fractional
1089 */
rkisp_config_color_space(struct rkisp_device * dev)1090 static void rkisp_config_color_space(struct rkisp_device *dev)
1091 {
1092 u16 bt601_coeff[] = {
1093 0x0026, 0x004b, 0x000f,
1094 0x01ea, 0x01d6, 0x0040,
1095 0x0040, 0x01ca, 0x01f6
1096 };
1097 u16 bt709_coeff[] = {
1098 0x001b, 0x005c, 0x0009,
1099 0x01f1, 0x01cf, 0x0040,
1100 0x0040, 0x01c6, 0x01fa
1101 };
1102 u16 bt2020_coeff[] = {
1103 0x0022, 0x0057, 0x0008,
1104 0x01ee, 0x01d2, 0x0040,
1105 0x0040, 0x01c5, 0x01fb
1106 };
1107 u16 i, *coeff;
1108
1109 switch (dev->isp_sdev.colorspace) {
1110 case V4L2_COLORSPACE_REC709:
1111 coeff = bt709_coeff;
1112 break;
1113 case V4L2_COLORSPACE_BT2020:
1114 coeff = bt2020_coeff;
1115 break;
1116 case V4L2_COLORSPACE_SMPTE170M:
1117 default:
1118 coeff = bt601_coeff;
1119 break;
1120 }
1121
1122 for (i = 0; i < 9; i++)
1123 rkisp_unite_write(dev, CIF_ISP_CC_COEFF_0 + i * 4,
1124 *(coeff + i), false, dev->hw_dev->is_unite);
1125
1126 if (dev->isp_sdev.quantization == V4L2_QUANTIZATION_FULL_RANGE)
1127 rkisp_unite_set_bits(dev, CIF_ISP_CTRL, 0,
1128 CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1129 CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA,
1130 false, dev->hw_dev->is_unite);
1131 else
1132 rkisp_unite_clear_bits(dev, CIF_ISP_CTRL,
1133 CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA |
1134 CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA,
1135 false, dev->hw_dev->is_unite);
1136 }
1137
rkisp_config_cmsk_single(struct rkisp_device * dev,struct rkisp_cmsk_cfg * cfg)1138 static void rkisp_config_cmsk_single(struct rkisp_device *dev,
1139 struct rkisp_cmsk_cfg *cfg)
1140 {
1141 u32 i, val, ctrl = 0;
1142 u32 mp_en = cfg->win[0].win_en;
1143 u32 sp_en = cfg->win[1].win_en;
1144 u32 bp_en = cfg->win[2].win_en;
1145
1146 if (mp_en) {
1147 ctrl |= ISP3X_SW_CMSK_EN_MP;
1148 rkisp_write(dev, ISP3X_CMSK_CTRL1, mp_en, false);
1149 val = cfg->win[0].mode;
1150 rkisp_write(dev, ISP3X_CMSK_CTRL4, val, false);
1151 }
1152
1153 if (sp_en) {
1154 ctrl |= ISP3X_SW_CMSK_EN_SP;
1155 rkisp_write(dev, ISP3X_CMSK_CTRL2, sp_en, false);
1156 val = cfg->win[1].mode;
1157 rkisp_write(dev, ISP3X_CMSK_CTRL5, val, false);
1158 }
1159
1160 if (bp_en) {
1161 ctrl |= ISP3X_SW_CMSK_EN_BP;
1162 rkisp_write(dev, ISP3X_CMSK_CTRL3, bp_en, false);
1163 val = cfg->win[2].mode;
1164 rkisp_write(dev, ISP3X_CMSK_CTRL6, val, false);
1165 }
1166
1167 for (i = 0; i < RKISP_CMSK_WIN_MAX; i++) {
1168 if (!(mp_en & BIT(i)) && !(sp_en & BIT(i)) && !(bp_en & BIT(i)))
1169 continue;
1170
1171 val = ISP3X_SW_CMSK_YUV(cfg->win[i].cover_color_y,
1172 cfg->win[i].cover_color_u,
1173 cfg->win[i].cover_color_v);
1174 rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
1175
1176 val = ISP_PACK_2SHORT(cfg->win[i].h_offs, cfg->win[i].v_offs);
1177 rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
1178
1179 val = ISP_PACK_2SHORT(cfg->win[i].h_size, cfg->win[i].v_size);
1180 rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
1181 }
1182
1183 if (ctrl) {
1184 val = ISP_PACK_2SHORT(dev->isp_sdev.out_crop.width,
1185 dev->isp_sdev.out_crop.height);
1186 rkisp_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
1187 ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
1188 }
1189 rkisp_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
1190 }
1191
rkisp_config_cmsk_dual(struct rkisp_device * dev,struct rkisp_cmsk_cfg * cfg)1192 static void rkisp_config_cmsk_dual(struct rkisp_device *dev,
1193 struct rkisp_cmsk_cfg *cfg)
1194 {
1195 struct rkisp_cmsk_cfg left = *cfg;
1196 struct rkisp_cmsk_cfg right = *cfg;
1197 u32 width = dev->isp_sdev.out_crop.width;
1198 u32 height = dev->isp_sdev.out_crop.height;
1199 u32 w = width / 2;
1200 u32 i, val, h_offs, h_size, ctrl;
1201 u8 mp_en = cfg->win[0].win_en;
1202 u8 sp_en = cfg->win[1].win_en;
1203 u8 bp_en = cfg->win[2].win_en;
1204
1205 for (i = 0; i < RKISP_CMSK_WIN_MAX; i++) {
1206 if (!(mp_en & BIT(i)) && !(sp_en & BIT(i)) && !(bp_en & BIT(i)))
1207 continue;
1208
1209 h_offs = cfg->win[i].h_offs;
1210 h_size = cfg->win[i].h_size;
1211 if (h_offs + h_size <= w) {
1212 /* cmsk window at left isp */
1213 right.win[0].win_en &= ~BIT(i);
1214 right.win[1].win_en &= ~BIT(i);
1215 right.win[2].win_en &= ~BIT(i);
1216 } else if (h_offs >= w) {
1217 /* cmsk window at right isp */
1218 left.win[0].win_en &= ~BIT(i);
1219 left.win[1].win_en &= ~BIT(i);
1220 left.win[2].win_en &= ~BIT(i);
1221 } else {
1222 /* cmsk window at dual isp */
1223 left.win[i].h_size = ALIGN(w - h_offs, 8);
1224
1225 right.win[i].h_offs = RKMOUDLE_UNITE_EXTEND_PIXEL;
1226 val = h_offs + h_size - w;
1227 right.win[i].h_size = ALIGN(val, 8);
1228 right.win[i].h_offs -= right.win[i].h_size - val;
1229 }
1230
1231 val = ISP3X_SW_CMSK_YUV(left.win[i].cover_color_y,
1232 left.win[i].cover_color_u,
1233 left.win[i].cover_color_v);
1234 rkisp_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
1235 rkisp_next_write(dev, ISP3X_CMSK_YUV0 + i * 4, val, false);
1236
1237 val = ISP_PACK_2SHORT(left.win[i].h_offs, left.win[i].v_offs);
1238 rkisp_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
1239 val = ISP_PACK_2SHORT(left.win[i].h_size, left.win[i].v_size);
1240 rkisp_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
1241
1242 val = ISP_PACK_2SHORT(right.win[i].h_offs, right.win[i].v_offs);
1243 rkisp_next_write(dev, ISP3X_CMSK_OFFS0 + i * 8, val, false);
1244 val = ISP_PACK_2SHORT(right.win[i].h_size, right.win[i].v_size);
1245 rkisp_next_write(dev, ISP3X_CMSK_SIZE0 + i * 8, val, false);
1246 }
1247
1248 w += RKMOUDLE_UNITE_EXTEND_PIXEL;
1249 ctrl = 0;
1250 if (left.win[0].win_en) {
1251 ctrl |= ISP3X_SW_CMSK_EN_MP;
1252 rkisp_write(dev, ISP3X_CMSK_CTRL1, left.win[0].win_en, false);
1253 val = left.win[0].mode;
1254 rkisp_write(dev, ISP3X_CMSK_CTRL4, val, false);
1255 }
1256 if (left.win[1].win_en) {
1257 ctrl |= ISP3X_SW_CMSK_EN_SP;
1258 rkisp_write(dev, ISP3X_CMSK_CTRL2, left.win[1].win_en, false);
1259 val = left.win[1].mode;
1260 rkisp_write(dev, ISP3X_CMSK_CTRL5, val, false);
1261 }
1262 if (left.win[2].win_en) {
1263 ctrl |= ISP3X_SW_CMSK_EN_BP;
1264 rkisp_write(dev, ISP3X_CMSK_CTRL3, left.win[2].win_en, false);
1265 val = left.win[2].mode;
1266 rkisp_write(dev, ISP3X_CMSK_CTRL6, val, false);
1267 }
1268 if (ctrl) {
1269 val = ISP_PACK_2SHORT(w, height);
1270 rkisp_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
1271 ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
1272 }
1273 rkisp_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
1274
1275 ctrl = 0;
1276 if (right.win[0].win_en) {
1277 ctrl |= ISP3X_SW_CMSK_EN_MP;
1278 rkisp_next_write(dev, ISP3X_CMSK_CTRL1, right.win[0].win_en, false);
1279 val = right.win[0].mode;
1280 rkisp_next_write(dev, ISP3X_CMSK_CTRL4, val, false);
1281 }
1282 if (right.win[1].win_en) {
1283 ctrl |= ISP3X_SW_CMSK_EN_SP;
1284 rkisp_next_write(dev, ISP3X_CMSK_CTRL2, right.win[1].win_en, false);
1285 val = right.win[1].mode;
1286 rkisp_next_write(dev, ISP3X_CMSK_CTRL5, val, false);
1287 }
1288 if (right.win[2].win_en) {
1289 ctrl |= ISP3X_SW_CMSK_EN_BP;
1290 rkisp_next_write(dev, ISP3X_CMSK_CTRL3, right.win[2].win_en, false);
1291 val = right.win[2].mode;
1292 rkisp_next_write(dev, ISP3X_CMSK_CTRL6, val, false);
1293 }
1294 if (ctrl) {
1295 val = ISP_PACK_2SHORT(w, height);
1296 rkisp_next_write(dev, ISP3X_CMSK_PIC_SIZE, val, false);
1297 ctrl |= ISP3X_SW_CMSK_EN | ISP3X_SW_CMSK_ORDER_MODE;
1298 }
1299 rkisp_next_write(dev, ISP3X_CMSK_CTRL0, ctrl, false);
1300 }
1301
rkisp_config_cmsk(struct rkisp_device * dev)1302 static void rkisp_config_cmsk(struct rkisp_device *dev)
1303 {
1304 unsigned long lock_flags = 0;
1305 struct rkisp_cmsk_cfg cfg;
1306
1307 if (dev->isp_ver != ISP_V30)
1308 return;
1309
1310 spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
1311 if (!dev->is_cmsk_upd) {
1312 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1313 return;
1314 }
1315 dev->is_cmsk_upd = false;
1316 cfg = dev->cmsk_cfg;
1317 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1318
1319 if (!dev->hw_dev->is_unite)
1320 rkisp_config_cmsk_single(dev, &cfg);
1321 else
1322 rkisp_config_cmsk_dual(dev, &cfg);
1323 }
1324
1325 /*
1326 * configure isp blocks with input format, size......
1327 */
rkisp_config_isp(struct rkisp_device * dev)1328 static int rkisp_config_isp(struct rkisp_device *dev)
1329 {
1330 struct ispsd_in_fmt *in_fmt;
1331 struct ispsd_out_fmt *out_fmt;
1332 struct v4l2_rect *in_crop;
1333 struct rkisp_sensor_info *sensor;
1334 bool is_unite = dev->hw_dev->is_unite;
1335 u32 isp_ctrl = 0;
1336 u32 irq_mask = 0;
1337 u32 signal = 0;
1338 u32 acq_mult = 0;
1339 u32 acq_prop = 0;
1340 u32 extend_line = 0;
1341 u32 width;
1342
1343 sensor = dev->active_sensor;
1344 in_fmt = &dev->isp_sdev.in_fmt;
1345 out_fmt = &dev->isp_sdev.out_fmt;
1346 in_crop = &dev->isp_sdev.in_crop;
1347 width = in_crop->width;
1348
1349 if (in_fmt->fmt_type == FMT_BAYER) {
1350 acq_mult = 1;
1351 if (out_fmt->fmt_type == FMT_BAYER) {
1352 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
1353 isp_ctrl =
1354 CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
1355 else
1356 isp_ctrl =
1357 CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
1358 } else {
1359 /* demosaicing bypass for grey sensor */
1360 if (in_fmt->mbus_code == MEDIA_BUS_FMT_Y8_1X8 ||
1361 in_fmt->mbus_code == MEDIA_BUS_FMT_Y10_1X10 ||
1362 in_fmt->mbus_code == MEDIA_BUS_FMT_Y12_1X12) {
1363 if (dev->isp_ver == ISP_V20 ||
1364 dev->isp_ver == ISP_V21 ||
1365 dev->isp_ver == ISP_V30)
1366 rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1367 0, false, is_unite);
1368 else
1369 rkisp_write(dev, CIF_ISP_DEMOSAIC,
1370 CIF_ISP_DEMOSAIC_BYPASS |
1371 CIF_ISP_DEMOSAIC_TH(0xc), false);
1372 } else {
1373 if (dev->isp_ver == ISP_V20 ||
1374 dev->isp_ver == ISP_V21 ||
1375 dev->isp_ver == ISP_V30)
1376 rkisp_unite_write(dev, ISP_DEBAYER_CONTROL,
1377 SW_DEBAYER_EN |
1378 SW_DEBAYER_FILTER_G_EN |
1379 SW_DEBAYER_FILTER_C_EN,
1380 false, is_unite);
1381 else
1382 rkisp_write(dev, CIF_ISP_DEMOSAIC,
1383 CIF_ISP_DEMOSAIC_TH(0xc), false);
1384 }
1385
1386 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
1387 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
1388 else
1389 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
1390
1391 if (dev->isp_ver == ISP_V20 &&
1392 dev->rd_mode == HDR_RDBK_FRAME1)
1393 extend_line = RKMODULE_EXTEND_LINE;
1394 }
1395
1396 if (dev->isp_inp == INP_DMARX_ISP)
1397 acq_prop = CIF_ISP_ACQ_PROP_DMA_RGB;
1398 } else if (in_fmt->fmt_type == FMT_YUV) {
1399 acq_mult = 2;
1400 if (sensor &&
1401 (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY ||
1402 sensor->mbus.type == V4L2_MBUS_CCP2)) {
1403 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
1404 } else {
1405 if (sensor && sensor->mbus.type == V4L2_MBUS_BT656)
1406 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU656;
1407 else
1408 isp_ctrl = CIF_ISP_CTRL_ISP_MODE_ITU601;
1409
1410 }
1411
1412 irq_mask |= CIF_ISP_DATA_LOSS;
1413 if (dev->isp_inp == INP_DMARX_ISP)
1414 acq_prop = CIF_ISP_ACQ_PROP_DMA_YUV;
1415 }
1416
1417 /* Set up input acquisition properties */
1418 if (sensor && (sensor->mbus.type == V4L2_MBUS_BT656 ||
1419 sensor->mbus.type == V4L2_MBUS_PARALLEL)) {
1420 if (sensor->mbus.flags &
1421 V4L2_MBUS_PCLK_SAMPLE_RISING)
1422 signal = CIF_ISP_ACQ_PROP_POS_EDGE;
1423 }
1424
1425 if (sensor && sensor->mbus.type == V4L2_MBUS_PARALLEL) {
1426 if (sensor->mbus.flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1427 signal |= CIF_ISP_ACQ_PROP_VSYNC_LOW;
1428
1429 if (sensor->mbus.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1430 signal |= CIF_ISP_ACQ_PROP_HSYNC_LOW;
1431 }
1432
1433 rkisp_unite_write(dev, CIF_ISP_CTRL, isp_ctrl, false, is_unite);
1434 acq_prop |= signal | in_fmt->yuv_seq |
1435 CIF_ISP_ACQ_PROP_BAYER_PAT(in_fmt->bayer_pat) |
1436 CIF_ISP_ACQ_PROP_FIELD_SEL_ALL;
1437 rkisp_unite_write(dev, CIF_ISP_ACQ_PROP, acq_prop, false, is_unite);
1438 rkisp_unite_write(dev, CIF_ISP_ACQ_NR_FRAMES, 0, true, is_unite);
1439
1440 if (is_unite)
1441 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1442 /* Acquisition Size */
1443 rkisp_unite_write(dev, CIF_ISP_ACQ_H_OFFS, acq_mult * in_crop->left,
1444 false, is_unite);
1445 rkisp_unite_write(dev, CIF_ISP_ACQ_V_OFFS, in_crop->top,
1446 false, is_unite);
1447 rkisp_unite_write(dev, CIF_ISP_ACQ_H_SIZE, acq_mult * width,
1448 false, is_unite);
1449
1450 /* ISP Out Area differ with ACQ is only FIFO, so don't crop in this */
1451 rkisp_unite_write(dev, CIF_ISP_OUT_H_OFFS, 0, true, is_unite);
1452 rkisp_unite_write(dev, CIF_ISP_OUT_V_OFFS, 0, true, is_unite);
1453 rkisp_unite_write(dev, CIF_ISP_OUT_H_SIZE, width, false, is_unite);
1454
1455 if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
1456 rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height / 2,
1457 false, is_unite);
1458 rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height / 2,
1459 false, is_unite);
1460 } else {
1461 rkisp_unite_write(dev, CIF_ISP_ACQ_V_SIZE, in_crop->height + extend_line,
1462 false, is_unite);
1463 rkisp_unite_write(dev, CIF_ISP_OUT_V_SIZE, in_crop->height + extend_line,
1464 false, is_unite);
1465 }
1466
1467 /* interrupt mask */
1468 irq_mask |= CIF_ISP_FRAME | CIF_ISP_V_START | CIF_ISP_PIC_SIZE_ERROR |
1469 CIF_ISP_FRAME_IN;
1470 if (dev->isp_ver == ISP_V20 ||
1471 dev->isp_ver == ISP_V21 ||
1472 dev->isp_ver == ISP_V30)
1473 irq_mask |= ISP2X_LSC_LUT_ERR;
1474 if (is_unite)
1475 rkisp_next_write(dev, CIF_ISP_IMSC, irq_mask, true);
1476 else
1477 rkisp_write(dev, CIF_ISP_IMSC, irq_mask, true);
1478
1479 if ((dev->isp_ver == ISP_V20 ||
1480 dev->isp_ver == ISP_V21) &&
1481 IS_HDR_RDBK(dev->hdr.op_mode)) {
1482 irq_mask = ISP2X_3A_RAWAE_BIG;
1483 rkisp_write(dev, ISP_ISP3A_IMSC, irq_mask, true);
1484 }
1485
1486 if (out_fmt->fmt_type == FMT_BAYER) {
1487 rkisp_params_disable_isp(&dev->params_vdev);
1488 } else {
1489 rkisp_config_color_space(dev);
1490 rkisp_params_first_cfg(&dev->params_vdev, in_fmt,
1491 dev->isp_sdev.quantization);
1492 }
1493 if (!dev->hw_dev->is_single && atomic_read(&dev->hw_dev->refcnt) <= 1) {
1494 rkisp_update_regs(dev, CIF_ISP_ACQ_H_OFFS, CIF_ISP_ACQ_V_SIZE);
1495 rkisp_update_regs(dev, CIF_ISP_OUT_H_SIZE, CIF_ISP_OUT_V_SIZE);
1496 }
1497
1498 rkisp_config_cmsk(dev);
1499 return 0;
1500 }
1501
rkisp_config_dvp(struct rkisp_device * dev)1502 static int rkisp_config_dvp(struct rkisp_device *dev)
1503 {
1504 struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
1505 void __iomem *base = dev->base_addr;
1506 u32 val, input_sel, data_width;
1507
1508 switch (in_fmt->bus_width) {
1509 case 8:
1510 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
1511 data_width = ISP_CIF_DATA_WIDTH_8B;
1512 break;
1513 case 10:
1514 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
1515 data_width = ISP_CIF_DATA_WIDTH_10B;
1516 break;
1517 case 12:
1518 input_sel = CIF_ISP_ACQ_PROP_IN_SEL_12B;
1519 data_width = ISP_CIF_DATA_WIDTH_12B;
1520 break;
1521 default:
1522 v4l2_err(&dev->v4l2_dev, "Invalid bus width\n");
1523 return -EINVAL;
1524 }
1525
1526 val = readl(base + CIF_ISP_ACQ_PROP);
1527 writel(val | input_sel, base + CIF_ISP_ACQ_PROP);
1528
1529 if (!IS_ERR(dev->hw_dev->grf) &&
1530 (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13))
1531 regmap_update_bits(dev->hw_dev->grf, GRF_VI_CON0,
1532 ISP_CIF_DATA_WIDTH_MASK, data_width);
1533 return 0;
1534 }
1535
rkisp_config_lvds(struct rkisp_device * dev)1536 static int rkisp_config_lvds(struct rkisp_device *dev)
1537 {
1538 struct rkisp_sensor_info *sensor = dev->active_sensor;
1539 struct ispsd_in_fmt *in_fmt = &dev->isp_sdev.in_fmt;
1540 struct rkmodule_lvds_cfg cfg;
1541 struct v4l2_subdev *sd = NULL;
1542 u32 ret = 0, val, lane, data;
1543
1544 sd = get_remote_sensor(sensor->sd);
1545 ret = v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_LVDS_CFG, &cfg);
1546 if (ret)
1547 goto err;
1548
1549 switch (sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
1550 case V4L2_MBUS_CSI2_1_LANE:
1551 lane = 1;
1552 break;
1553 case V4L2_MBUS_CSI2_2_LANE:
1554 lane = 2;
1555 break;
1556 case V4L2_MBUS_CSI2_3_LANE:
1557 lane = 3;
1558 break;
1559 case V4L2_MBUS_CSI2_4_LANE:
1560 default:
1561 lane = 4;
1562 }
1563 lane = BIT(lane) - 1;
1564
1565 switch (in_fmt->bus_width) {
1566 case 8:
1567 data = 0;
1568 break;
1569 case 10:
1570 data = 1;
1571 break;
1572 case 12:
1573 data = 2;
1574 break;
1575 default:
1576 ret = -EINVAL;
1577 goto err;
1578 }
1579
1580 val = SW_LVDS_SAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.act.sav) |
1581 SW_LVDS_EAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.act.eav);
1582 writel(val, dev->base_addr + LVDS_SAV_EAV_ACT);
1583 val = SW_LVDS_SAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.blk.sav) |
1584 SW_LVDS_EAV(cfg.frm_sync_code[LVDS_CODE_GRP_LINEAR].odd_sync_code.blk.eav);
1585 writel(val, dev->base_addr + LVDS_SAV_EAV_BLK);
1586 val = SW_LVDS_EN | SW_LVDS_WIDTH(data) | SW_LVDS_LANE_EN(lane) | cfg.mode;
1587 writel(val, dev->base_addr + LVDS_CTRL);
1588 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1589 "lvds CTRL:0x%x ACT:0x%x BLK:0x%x\n",
1590 readl(dev->base_addr + LVDS_CTRL),
1591 readl(dev->base_addr + LVDS_SAV_EAV_ACT),
1592 readl(dev->base_addr + LVDS_SAV_EAV_BLK));
1593 return ret;
1594 err:
1595 v4l2_err(&dev->v4l2_dev, "%s error ret:%d\n", __func__, ret);
1596 return ret;
1597 }
1598
1599 /* Configure MUX */
rkisp_config_path(struct rkisp_device * dev)1600 static int rkisp_config_path(struct rkisp_device *dev)
1601 {
1602 struct rkisp_sensor_info *sensor = dev->active_sensor;
1603 int ret = 0;
1604 u32 dpcl = 0;
1605
1606 /* isp input interface selects */
1607 if ((sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) ||
1608 dev->isp_inp & (INP_RAWRD0 | INP_RAWRD1 | INP_RAWRD2 | INP_CIF)) {
1609 /* mipi sensor->isp or isp read from ddr */
1610 dpcl |= CIF_VI_DPCL_IF_SEL_MIPI;
1611 } else if (sensor &&
1612 (sensor->mbus.type == V4L2_MBUS_BT656 ||
1613 sensor->mbus.type == V4L2_MBUS_PARALLEL)) {
1614 /* dvp sensor->isp */
1615 ret = rkisp_config_dvp(dev);
1616 dpcl |= CIF_VI_DPCL_IF_SEL_PARALLEL;
1617 } else if (dev->isp_inp == INP_DMARX_ISP) {
1618 /* read from ddr, no sensor connect, debug only */
1619 dpcl |= CIF_VI_DPCL_DMA_SW_ISP;
1620 } else if (sensor && sensor->mbus.type == V4L2_MBUS_CCP2) {
1621 /* lvds sensor->isp */
1622 ret = rkisp_config_lvds(dev);
1623 dpcl |= VI_DPCL_IF_SEL_LVDS;
1624 } else {
1625 v4l2_err(&dev->v4l2_dev, "Invalid input\n");
1626 ret = -EINVAL;
1627 }
1628
1629 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true,
1630 dev->hw_dev->is_unite);
1631 return ret;
1632 }
1633
1634 /* Hareware configure Entry */
rkisp_config_cif(struct rkisp_device * dev)1635 static int rkisp_config_cif(struct rkisp_device *dev)
1636 {
1637 int ret = 0;
1638
1639 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1640 "%s CIF_ID:0x%x SP:%d, MP:%d\n", __func__,
1641 readl(dev->base_addr + CIF_VI_ID),
1642 dev->cap_dev.stream[RKISP_STREAM_SP].streaming,
1643 dev->cap_dev.stream[RKISP_STREAM_MP].streaming);
1644
1645 ret = rkisp_config_isp(dev);
1646 if (ret < 0)
1647 return ret;
1648 ret = rkisp_config_path(dev);
1649 if (ret < 0)
1650 return ret;
1651 rkisp_config_ism(dev);
1652
1653 return 0;
1654 }
1655
rkisp_is_need_3a(struct rkisp_device * dev)1656 static bool rkisp_is_need_3a(struct rkisp_device *dev)
1657 {
1658 struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev;
1659
1660 return isp_sdev->in_fmt.fmt_type == FMT_BAYER &&
1661 isp_sdev->out_fmt.fmt_type == FMT_YUV;
1662 }
1663
rkisp_start_3a_run(struct rkisp_device * dev)1664 static void rkisp_start_3a_run(struct rkisp_device *dev)
1665 {
1666 struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
1667 struct video_device *vdev = ¶ms_vdev->vnode.vdev;
1668 struct v4l2_event ev = {
1669 .type = CIFISP_V4L2_EVENT_STREAM_START,
1670 };
1671 int ret = 1000;
1672
1673 if (!rkisp_is_need_3a(dev) || dev->isp_ver == ISP_V20 ||
1674 !params_vdev->is_subs_evt)
1675 return;
1676
1677 v4l2_event_queue(vdev, &ev);
1678 /* rk3326/px30 require first params queued before
1679 * rkisp_params_configure_isp() called
1680 */
1681 ret = wait_event_timeout(dev->sync_onoff,
1682 params_vdev->streamon && !params_vdev->first_params,
1683 msecs_to_jiffies(ret));
1684 if (!ret)
1685 v4l2_warn(&dev->v4l2_dev,
1686 "waiting on params stream on event timeout\n");
1687 else
1688 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1689 "Waiting for 3A on use %d ms\n", 1000 - jiffies_to_msecs(ret));
1690 }
1691
rkisp_stop_3a_run(struct rkisp_device * dev)1692 static void rkisp_stop_3a_run(struct rkisp_device *dev)
1693 {
1694 struct rkisp_isp_params_vdev *params_vdev = &dev->params_vdev;
1695 struct video_device *vdev = ¶ms_vdev->vnode.vdev;
1696 struct v4l2_event ev = {
1697 .type = CIFISP_V4L2_EVENT_STREAM_STOP,
1698 };
1699 int ret = 1000;
1700
1701 if (!rkisp_is_need_3a(dev) || dev->isp_ver == ISP_V20 ||
1702 !params_vdev->is_subs_evt)
1703 return;
1704
1705 v4l2_event_queue(vdev, &ev);
1706 ret = wait_event_timeout(dev->sync_onoff, !params_vdev->streamon,
1707 msecs_to_jiffies(ret));
1708 if (!ret)
1709 v4l2_warn(&dev->v4l2_dev,
1710 "waiting on params stream off event timeout\n");
1711 else
1712 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1713 "Waiting for 3A off use %d ms\n", 1000 - jiffies_to_msecs(ret));
1714 }
1715
1716 /* Mess register operations to stop isp */
rkisp_isp_stop(struct rkisp_device * dev)1717 static int rkisp_isp_stop(struct rkisp_device *dev)
1718 {
1719 struct rkisp_hw_dev *hw = dev->hw_dev;
1720 void __iomem *base = dev->base_addr;
1721 unsigned long old_rate, safe_rate;
1722 u32 val;
1723 u32 i;
1724
1725 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1726 "%s refcnt:%d\n", __func__,
1727 atomic_read(&dev->hw_dev->refcnt));
1728
1729 if (atomic_read(&dev->hw_dev->refcnt) > 1)
1730 goto end;
1731
1732 if (dev->hw_dev->monitor.is_en) {
1733 dev->hw_dev->monitor.is_en = 0;
1734 dev->hw_dev->monitor.state = ISP_STOP;
1735 if (!completion_done(&dev->hw_dev->monitor.cmpl))
1736 complete(&dev->hw_dev->monitor.cmpl);
1737 }
1738 /*
1739 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
1740 * Stop ISP(isp) ->wait for ISP isp off
1741 */
1742 /* stop and clear MI, MIPI, and ISP interrupts */
1743 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
1744 writel(0, base + CIF_ISP_CSI0_MASK1);
1745 writel(0, base + CIF_ISP_CSI0_MASK2);
1746 writel(0, base + CIF_ISP_CSI0_MASK3);
1747 readl(base + CIF_ISP_CSI0_ERR1);
1748 readl(base + CIF_ISP_CSI0_ERR2);
1749 readl(base + CIF_ISP_CSI0_ERR3);
1750 } else if (dev->isp_ver == ISP_V20 ||
1751 dev->isp_ver == ISP_V21 ||
1752 dev->isp_ver == ISP_V30) {
1753 writel(0, base + CSI2RX_MASK_PHY);
1754 writel(0, base + CSI2RX_MASK_PACKET);
1755 writel(0, base + CSI2RX_MASK_OVERFLOW);
1756 writel(0, base + CSI2RX_MASK_STAT);
1757 readl(base + CSI2RX_ERR_PHY);
1758 readl(base + CSI2RX_ERR_PACKET);
1759 readl(base + CSI2RX_ERR_OVERFLOW);
1760 readl(base + CSI2RX_ERR_STAT);
1761 } else {
1762 writel(0, base + CIF_MIPI_IMSC);
1763 writel(~0, base + CIF_MIPI_ICR);
1764 }
1765
1766 writel(0, base + CIF_ISP_IMSC);
1767 writel(~0, base + CIF_ISP_ICR);
1768
1769 if (dev->isp_ver == ISP_V20 ||
1770 dev->isp_ver == ISP_V21 ||
1771 dev->isp_ver == ISP_V30) {
1772 writel(0, base + ISP_ISP3A_IMSC);
1773 writel(~0, base + ISP_ISP3A_ICR);
1774 }
1775
1776 writel(0, base + CIF_MI_IMSC);
1777 writel(~0, base + CIF_MI_ICR);
1778 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
1779 writel(0, base + CIF_ISP_CSI0_CTRL0);
1780 } else if (dev->isp_ver < ISP_V12) {
1781 val = readl(base + CIF_MIPI_CTRL);
1782 val = val & (~CIF_MIPI_CTRL_SHUTDOWNLANES(0xf));
1783 writel(val & (~CIF_MIPI_CTRL_OUTPUT_ENA), base + CIF_MIPI_CTRL);
1784 udelay(20);
1785 }
1786 /* stop lsc to avoid lsclut error */
1787 if (dev->isp_ver == ISP_V20 ||
1788 dev->isp_ver == ISP_V21 ||
1789 dev->isp_ver == ISP_V30)
1790 writel(0, base + ISP_LSC_CTRL);
1791 /* stop ISP */
1792 val = readl(base + CIF_ISP_CTRL);
1793 val &= ~(CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_ENABLE);
1794 writel(val, base + CIF_ISP_CTRL);
1795
1796 val = readl(base + CIF_ISP_CTRL);
1797 writel(val | CIF_ISP_CTRL_ISP_CFG_UPD, base + CIF_ISP_CTRL);
1798 if (hw->is_unite)
1799 rkisp_next_write(dev, CIF_ISP_CTRL,
1800 val | CIF_ISP_CTRL_ISP_CFG_UPD, true);
1801
1802 readx_poll_timeout_atomic(readl, base + CIF_ISP_RIS,
1803 val, val & CIF_ISP_OFF, 20, 100);
1804 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1805 "MI_CTRL:%x, ISP_CTRL:%x\n",
1806 readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
1807
1808 val = rkisp_read(dev, CTRL_VI_ISP_CLK_CTRL, true);
1809 if (!in_interrupt()) {
1810 /* normal case */
1811 /* check the isp_clk before isp reset operation */
1812 old_rate = clk_get_rate(hw->clks[0]);
1813 safe_rate = hw->clk_rate_tbl[0].clk_rate * 1000000UL;
1814 if (old_rate > safe_rate) {
1815 rkisp_set_clk_rate(hw->clks[0], safe_rate);
1816 if (hw->is_unite)
1817 rkisp_set_clk_rate(hw->clks[5], safe_rate);
1818 udelay(100);
1819 }
1820 rkisp_soft_reset(dev->hw_dev, false);
1821 }
1822 rkisp_write(dev, CTRL_VI_ISP_CLK_CTRL, val, true);
1823
1824 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
1825 writel(0, base + CIF_ISP_CSI0_CSI2_RESETN);
1826 writel(0, base + CIF_ISP_CSI0_CTRL0);
1827 writel(0, base + CIF_ISP_CSI0_MASK1);
1828 writel(0, base + CIF_ISP_CSI0_MASK2);
1829 writel(0, base + CIF_ISP_CSI0_MASK3);
1830 } else if (dev->isp_ver == ISP_V20 ||
1831 dev->isp_ver == ISP_V21 ||
1832 dev->isp_ver == ISP_V30) {
1833 writel(0, base + CSI2RX_CSI2_RESETN);
1834 if (hw->is_unite)
1835 rkisp_next_write(dev, CSI2RX_CSI2_RESETN, 0, true);
1836 }
1837
1838 dev->hw_dev->is_idle = true;
1839 dev->hw_dev->is_mi_update = false;
1840 end:
1841 dev->irq_ends_mask = 0;
1842 dev->hdr.op_mode = 0;
1843 rkisp_set_state(&dev->isp_state, ISP_STOP);
1844
1845 if (dev->isp_ver == ISP_V20 ||
1846 dev->isp_ver == ISP_V21 ||
1847 dev->isp_ver == ISP_V30)
1848 kfifo_reset(&dev->rdbk_kfifo);
1849 if (dev->isp_ver == ISP_V30)
1850 memset(&dev->cmsk_cfg, 0, sizeof(dev->cmsk_cfg));
1851 if (dev->emd_vc <= CIF_ISP_ADD_DATA_VC_MAX) {
1852 for (i = 0; i < RKISP_EMDDATA_FIFO_MAX; i++)
1853 kfifo_free(&dev->emd_data_fifo[i].mipi_kfifo);
1854 dev->emd_vc = 0xFF;
1855 }
1856
1857 if (dev->hdr.sensor)
1858 dev->hdr.sensor = NULL;
1859
1860 return 0;
1861 }
1862
1863 /* Mess register operations to start isp */
rkisp_isp_start(struct rkisp_device * dev)1864 static int rkisp_isp_start(struct rkisp_device *dev)
1865 {
1866 struct rkisp_sensor_info *sensor = dev->active_sensor;
1867 void __iomem *base = dev->base_addr;
1868 bool is_direct = true;
1869 u32 val;
1870
1871 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1872 "%s refcnt:%d\n", __func__,
1873 atomic_read(&dev->hw_dev->refcnt));
1874
1875 /* Activate MIPI */
1876 if (sensor && sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
1877 if (dev->isp_ver == ISP_V12 || dev->isp_ver == ISP_V13) {
1878 /* clear interrupts state */
1879 readl(base + CIF_ISP_CSI0_ERR1);
1880 readl(base + CIF_ISP_CSI0_ERR2);
1881 readl(base + CIF_ISP_CSI0_ERR3);
1882 /* csi2host enable */
1883 writel(1, base + CIF_ISP_CSI0_CTRL0);
1884 } else if (dev->isp_ver < ISP_V12) {
1885 val = readl(base + CIF_MIPI_CTRL);
1886 writel(val | CIF_MIPI_CTRL_OUTPUT_ENA,
1887 base + CIF_MIPI_CTRL);
1888 }
1889 }
1890 /* Activate ISP */
1891 val = rkisp_read(dev, CIF_ISP_CTRL, false);
1892 val |= CIF_ISP_CTRL_ISP_CFG_UPD | CIF_ISP_CTRL_ISP_ENABLE |
1893 CIF_ISP_CTRL_ISP_INFORM_ENABLE | CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT;
1894 if (dev->isp_ver == ISP_V20)
1895 val |= NOC_HURRY_PRIORITY(2) | NOC_HURRY_W_MODE(2) | NOC_HURRY_R_MODE(1);
1896 if (atomic_read(&dev->hw_dev->refcnt) > 1)
1897 is_direct = false;
1898 rkisp_unite_write(dev, CIF_ISP_CTRL, val, is_direct, dev->hw_dev->is_unite);
1899
1900 dev->isp_err_cnt = 0;
1901 dev->isp_isr_cnt = 0;
1902 dev->isp_state = ISP_START | ISP_FRAME_END;
1903 dev->irq_ends_mask |= ISP_FRAME_END | ISP_FRAME_IN;
1904 dev->irq_ends = 0;
1905
1906 /* XXX: Is the 1000us too long?
1907 * CIF spec says to wait for sufficient time after enabling
1908 * the MIPI interface and before starting the sensor output.
1909 */
1910 if (dev->hw_dev->is_single)
1911 usleep_range(1000, 1200);
1912
1913 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1914 "%s MI_CTRL 0x%08x ISP_CTRL 0x%08x\n", __func__,
1915 readl(base + CIF_MI_CTRL), readl(base + CIF_ISP_CTRL));
1916
1917 if (dev->hw_dev->monitor.is_en && atomic_read(&dev->hw_dev->refcnt) < 2) {
1918 dev->hw_dev->monitor.retry = 0;
1919 dev->hw_dev->monitor.state = ISP_FRAME_END;
1920 schedule_work(&dev->hw_dev->monitor.work);
1921 }
1922 return 0;
1923 }
1924
1925 /***************************** isp sub-devs *******************************/
1926
1927 static const struct ispsd_in_fmt rkisp_isp_input_formats[] = {
1928 {
1929 .name = "SBGGR10_1X10",
1930 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
1931 .fmt_type = FMT_BAYER,
1932 .mipi_dt = CIF_CSI2_DT_RAW10,
1933 .bayer_pat = RAW_BGGR,
1934 .bus_width = 10,
1935 }, {
1936 .name = "SRGGB10_1X10",
1937 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
1938 .fmt_type = FMT_BAYER,
1939 .mipi_dt = CIF_CSI2_DT_RAW10,
1940 .bayer_pat = RAW_RGGB,
1941 .bus_width = 10,
1942 }, {
1943 .name = "SGBRG10_1X10",
1944 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
1945 .fmt_type = FMT_BAYER,
1946 .mipi_dt = CIF_CSI2_DT_RAW10,
1947 .bayer_pat = RAW_GBRG,
1948 .bus_width = 10,
1949 }, {
1950 .name = "SGRBG10_1X10",
1951 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
1952 .fmt_type = FMT_BAYER,
1953 .mipi_dt = CIF_CSI2_DT_RAW10,
1954 .bayer_pat = RAW_GRBG,
1955 .bus_width = 10,
1956 }, {
1957 .name = "SRGGB12_1X12",
1958 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
1959 .fmt_type = FMT_BAYER,
1960 .mipi_dt = CIF_CSI2_DT_RAW12,
1961 .bayer_pat = RAW_RGGB,
1962 .bus_width = 12,
1963 }, {
1964 .name = "SBGGR12_1X12",
1965 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
1966 .fmt_type = FMT_BAYER,
1967 .mipi_dt = CIF_CSI2_DT_RAW12,
1968 .bayer_pat = RAW_BGGR,
1969 .bus_width = 12,
1970 }, {
1971 .name = "SGBRG12_1X12",
1972 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
1973 .fmt_type = FMT_BAYER,
1974 .mipi_dt = CIF_CSI2_DT_RAW12,
1975 .bayer_pat = RAW_GBRG,
1976 .bus_width = 12,
1977 }, {
1978 .name = "SGRBG12_1X12",
1979 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
1980 .fmt_type = FMT_BAYER,
1981 .mipi_dt = CIF_CSI2_DT_RAW12,
1982 .bayer_pat = RAW_GRBG,
1983 .bus_width = 12,
1984 }, {
1985 .name = "SRGGB8_1X8",
1986 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
1987 .fmt_type = FMT_BAYER,
1988 .mipi_dt = CIF_CSI2_DT_RAW8,
1989 .bayer_pat = RAW_RGGB,
1990 .bus_width = 8,
1991 }, {
1992 .name = "SBGGR8_1X8",
1993 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
1994 .fmt_type = FMT_BAYER,
1995 .mipi_dt = CIF_CSI2_DT_RAW8,
1996 .bayer_pat = RAW_BGGR,
1997 .bus_width = 8,
1998 }, {
1999 .name = "SGBRG8_1X8",
2000 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
2001 .fmt_type = FMT_BAYER,
2002 .mipi_dt = CIF_CSI2_DT_RAW8,
2003 .bayer_pat = RAW_GBRG,
2004 .bus_width = 8,
2005 }, {
2006 .name = "SGRBG8_1X8",
2007 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
2008 .fmt_type = FMT_BAYER,
2009 .mipi_dt = CIF_CSI2_DT_RAW8,
2010 .bayer_pat = RAW_GRBG,
2011 .bus_width = 8,
2012 }, {
2013 .name = "YUYV8_2X8",
2014 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
2015 .fmt_type = FMT_YUV,
2016 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2017 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2018 .bus_width = 8,
2019 }, {
2020 .name = "YVYU8_2X8",
2021 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
2022 .fmt_type = FMT_YUV,
2023 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2024 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
2025 .bus_width = 8,
2026 }, {
2027 .name = "UYVY8_2X8",
2028 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
2029 .fmt_type = FMT_YUV,
2030 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2031 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
2032 .bus_width = 8,
2033 }, {
2034 .name = "VYUY8_2X8",
2035 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
2036 .fmt_type = FMT_YUV,
2037 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2038 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
2039 .bus_width = 8,
2040 }, {
2041 .name = "YUYV10_2X10",
2042 .mbus_code = MEDIA_BUS_FMT_YUYV10_2X10,
2043 .fmt_type = FMT_YUV,
2044 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2045 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2046 .bus_width = 10,
2047 }, {
2048 .name = "YVYU10_2X10",
2049 .mbus_code = MEDIA_BUS_FMT_YVYU10_2X10,
2050 .fmt_type = FMT_YUV,
2051 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2052 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
2053 .bus_width = 10,
2054 }, {
2055 .name = "UYVY10_2X10",
2056 .mbus_code = MEDIA_BUS_FMT_UYVY10_2X10,
2057 .fmt_type = FMT_YUV,
2058 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2059 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
2060 .bus_width = 10,
2061 }, {
2062 .name = "VYUY10_2X10",
2063 .mbus_code = MEDIA_BUS_FMT_VYUY10_2X10,
2064 .fmt_type = FMT_YUV,
2065 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2066 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
2067 .bus_width = 10,
2068 }, {
2069 .name = "YUYV12_2X12",
2070 .mbus_code = MEDIA_BUS_FMT_YUYV12_2X12,
2071 .fmt_type = FMT_YUV,
2072 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2073 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2074 .bus_width = 12,
2075 }, {
2076 .name = "YVYU12_2X12",
2077 .mbus_code = MEDIA_BUS_FMT_YVYU12_2X12,
2078 .fmt_type = FMT_YUV,
2079 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2080 .yuv_seq = CIF_ISP_ACQ_PROP_YCRYCB,
2081 .bus_width = 12,
2082 }, {
2083 .name = "UYVY12_2X12",
2084 .mbus_code = MEDIA_BUS_FMT_UYVY12_2X12,
2085 .fmt_type = FMT_YUV,
2086 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2087 .yuv_seq = CIF_ISP_ACQ_PROP_CBYCRY,
2088 .bus_width = 12,
2089 }, {
2090 .name = "VYUY12_2X12",
2091 .mbus_code = MEDIA_BUS_FMT_VYUY12_2X12,
2092 .fmt_type = FMT_YUV,
2093 .mipi_dt = CIF_CSI2_DT_YUV422_8b,
2094 .yuv_seq = CIF_ISP_ACQ_PROP_CRYCBY,
2095 .bus_width = 12,
2096 }, {
2097 .name = "Y8_1X8",
2098 .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
2099 .fmt_type = FMT_BAYER,
2100 .mipi_dt = CIF_CSI2_DT_RAW8,
2101 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2102 .bus_width = 8,
2103 }, {
2104 .name = "Y10_1X8",
2105 .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
2106 .fmt_type = FMT_BAYER,
2107 .mipi_dt = CIF_CSI2_DT_RAW10,
2108 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2109 .bus_width = 10,
2110 }, {
2111 .name = "Y12_1X12",
2112 .mbus_code = MEDIA_BUS_FMT_Y12_1X12,
2113 .fmt_type = FMT_BAYER,
2114 .mipi_dt = CIF_CSI2_DT_RAW12,
2115 .yuv_seq = CIF_ISP_ACQ_PROP_YCBYCR,
2116 .bus_width = 12,
2117 }
2118 };
2119
2120 static const struct ispsd_out_fmt rkisp_isp_output_formats[] = {
2121 {
2122 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
2123 .fmt_type = FMT_YUV,
2124 }, {
2125 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
2126 .fmt_type = FMT_BAYER,
2127 }, {
2128 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
2129 .fmt_type = FMT_BAYER,
2130 }, {
2131 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
2132 .fmt_type = FMT_BAYER,
2133 }, {
2134 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
2135 .fmt_type = FMT_BAYER,
2136 }, {
2137 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
2138 .fmt_type = FMT_BAYER,
2139 }, {
2140 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
2141 .fmt_type = FMT_BAYER,
2142 }, {
2143 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
2144 .fmt_type = FMT_BAYER,
2145 }, {
2146 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
2147 .fmt_type = FMT_BAYER,
2148 }, {
2149 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
2150 .fmt_type = FMT_BAYER,
2151 }, {
2152 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
2153 .fmt_type = FMT_BAYER,
2154 }, {
2155 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
2156 .fmt_type = FMT_BAYER,
2157 }, {
2158 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
2159 .fmt_type = FMT_BAYER,
2160 },
2161 };
2162
find_in_fmt(u32 mbus_code)2163 static const struct ispsd_in_fmt *find_in_fmt(u32 mbus_code)
2164 {
2165 const struct ispsd_in_fmt *fmt;
2166 int i, array_size = ARRAY_SIZE(rkisp_isp_input_formats);
2167
2168 for (i = 0; i < array_size; i++) {
2169 fmt = &rkisp_isp_input_formats[i];
2170 if (fmt->mbus_code == mbus_code)
2171 return fmt;
2172 }
2173
2174 return NULL;
2175 }
2176
find_out_fmt(u32 mbus_code)2177 static const struct ispsd_out_fmt *find_out_fmt(u32 mbus_code)
2178 {
2179 const struct ispsd_out_fmt *fmt;
2180 int i, array_size = ARRAY_SIZE(rkisp_isp_output_formats);
2181
2182 for (i = 0; i < array_size; i++) {
2183 fmt = &rkisp_isp_output_formats[i];
2184 if (fmt->mbus_code == mbus_code)
2185 return fmt;
2186 }
2187
2188 return NULL;
2189 }
2190
rkisp_isp_sd_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)2191 static int rkisp_isp_sd_enum_mbus_code(struct v4l2_subdev *sd,
2192 struct v4l2_subdev_pad_config *cfg,
2193 struct v4l2_subdev_mbus_code_enum *code)
2194 {
2195 unsigned int i = code->index;
2196
2197 if (code->pad == RKISP_ISP_PAD_SINK) {
2198 if (i >= ARRAY_SIZE(rkisp_isp_input_formats))
2199 return -EINVAL;
2200 code->code = rkisp_isp_input_formats[i].mbus_code;
2201 } else {
2202 if (i >= ARRAY_SIZE(rkisp_isp_output_formats))
2203 return -EINVAL;
2204 code->code = rkisp_isp_output_formats[i].mbus_code;
2205 }
2206
2207 return 0;
2208 }
2209
2210 #define sd_to_isp_sd(_sd) container_of(_sd, struct rkisp_isp_subdev, sd)
rkisp_isp_sd_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)2211 static int rkisp_isp_sd_get_fmt(struct v4l2_subdev *sd,
2212 struct v4l2_subdev_pad_config *cfg,
2213 struct v4l2_subdev_format *fmt)
2214 {
2215 struct v4l2_mbus_framefmt *mf;
2216 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2217
2218 if (!fmt)
2219 goto err;
2220
2221 if (fmt->pad != RKISP_ISP_PAD_SINK &&
2222 fmt->pad != RKISP_ISP_PAD_SOURCE_PATH)
2223 goto err;
2224
2225 mf = &fmt->format;
2226 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2227 if (!cfg)
2228 goto err;
2229 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
2230 }
2231
2232 if (fmt->pad == RKISP_ISP_PAD_SINK) {
2233 *mf = isp_sd->in_frm;
2234 } else if (fmt->pad == RKISP_ISP_PAD_SOURCE_PATH) {
2235 /* format of source pad */
2236 mf->code = isp_sd->out_fmt.mbus_code;
2237 /* window size of source pad */
2238 mf->width = isp_sd->out_crop.width;
2239 mf->height = isp_sd->out_crop.height;
2240 mf->quantization = isp_sd->quantization;
2241 mf->colorspace = isp_sd->colorspace;
2242 }
2243 mf->field = V4L2_FIELD_NONE;
2244
2245 return 0;
2246 err:
2247 return -EINVAL;
2248 }
2249
rkisp_isp_sd_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)2250 static int rkisp_isp_sd_set_fmt(struct v4l2_subdev *sd,
2251 struct v4l2_subdev_pad_config *cfg,
2252 struct v4l2_subdev_format *fmt)
2253 {
2254 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2255 struct rkisp_isp_subdev *isp_sd = &isp_dev->isp_sdev;
2256 struct v4l2_mbus_framefmt *mf;
2257
2258 if (!fmt)
2259 goto err;
2260
2261 if (fmt->pad != RKISP_ISP_PAD_SINK &&
2262 fmt->pad != RKISP_ISP_PAD_SOURCE_PATH)
2263 goto err;
2264
2265 mf = &fmt->format;
2266 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
2267 if (!cfg)
2268 goto err;
2269 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
2270 }
2271
2272 if (fmt->pad == RKISP_ISP_PAD_SINK) {
2273 const struct ispsd_in_fmt *in_fmt;
2274
2275 in_fmt = find_in_fmt(mf->code);
2276 if (!in_fmt ||
2277 mf->width < CIF_ISP_INPUT_W_MIN ||
2278 mf->height < CIF_ISP_INPUT_H_MIN)
2279 goto err;
2280
2281 isp_sd->in_fmt = *in_fmt;
2282 isp_sd->in_frm = *mf;
2283 } else if (fmt->pad == RKISP_ISP_PAD_SOURCE_PATH) {
2284 const struct ispsd_out_fmt *out_fmt;
2285
2286 out_fmt = find_out_fmt(mf->code);
2287 if (!out_fmt)
2288 goto err;
2289 isp_sd->out_fmt = *out_fmt;
2290 /* window size is set in s_selection */
2291 mf->width = isp_sd->out_crop.width;
2292 mf->height = isp_sd->out_crop.height;
2293 /* full range by default */
2294 if (mf->quantization == V4L2_QUANTIZATION_DEFAULT)
2295 mf->quantization = V4L2_QUANTIZATION_FULL_RANGE;
2296 /* BT601 default */
2297 if (mf->colorspace != V4L2_COLORSPACE_SMPTE170M &&
2298 mf->colorspace != V4L2_COLORSPACE_REC709 &&
2299 mf->colorspace != V4L2_COLORSPACE_BT2020)
2300 mf->colorspace = V4L2_COLORSPACE_SMPTE170M;
2301 isp_sd->quantization = mf->quantization;
2302 isp_sd->colorspace = mf->colorspace;
2303 }
2304
2305 mf->field = V4L2_FIELD_NONE;
2306 return 0;
2307 err:
2308 return -EINVAL;
2309 }
2310
rkisp_isp_sd_try_crop(struct v4l2_subdev * sd,struct v4l2_rect * crop,u32 pad)2311 static void rkisp_isp_sd_try_crop(struct v4l2_subdev *sd,
2312 struct v4l2_rect *crop,
2313 u32 pad)
2314 {
2315 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2316 struct rkisp_device *dev = sd_to_isp_dev(sd);
2317 struct v4l2_rect in_crop = isp_sd->in_crop;
2318
2319 crop->left = ALIGN(crop->left, 2);
2320 crop->width = ALIGN(crop->width, 2);
2321
2322 if (pad == RKISP_ISP_PAD_SINK) {
2323 /* update sensor info if sensor link be changed */
2324 rkisp_update_sensor_info(dev);
2325 rkisp_align_sensor_resolution(dev, crop, true);
2326 } else if (pad == RKISP_ISP_PAD_SOURCE_PATH) {
2327 crop->left = clamp_t(u32, crop->left, 0, in_crop.width);
2328 crop->top = clamp_t(u32, crop->top, 0, in_crop.height);
2329 crop->width = clamp_t(u32, crop->width, CIF_ISP_OUTPUT_W_MIN,
2330 in_crop.width - crop->left);
2331 crop->height = clamp_t(u32, crop->height, CIF_ISP_OUTPUT_H_MIN,
2332 in_crop.height - crop->top);
2333 }
2334 }
2335
rkisp_isp_sd_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)2336 static int rkisp_isp_sd_get_selection(struct v4l2_subdev *sd,
2337 struct v4l2_subdev_pad_config *cfg,
2338 struct v4l2_subdev_selection *sel)
2339 {
2340 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2341 struct rkisp_device *dev = sd_to_isp_dev(sd);
2342 struct v4l2_rect *crop;
2343 u32 max_w, max_h;
2344
2345 if (!sel)
2346 goto err;
2347 if (sel->pad != RKISP_ISP_PAD_SOURCE_PATH &&
2348 sel->pad != RKISP_ISP_PAD_SINK)
2349 goto err;
2350
2351 crop = &sel->r;
2352 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
2353 if (!cfg)
2354 goto err;
2355 crop = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
2356 }
2357
2358 *crop = isp_sd->in_crop;
2359 switch (sel->target) {
2360 case V4L2_SEL_TGT_CROP_BOUNDS:
2361 crop->left = 0;
2362 crop->top = 0;
2363 if (sel->pad == RKISP_ISP_PAD_SINK) {
2364 switch (dev->isp_ver) {
2365 case ISP_V12:
2366 max_w = CIF_ISP_INPUT_W_MAX_V12;
2367 max_h = CIF_ISP_INPUT_H_MAX_V12;
2368 break;
2369 case ISP_V13:
2370 max_w = CIF_ISP_INPUT_W_MAX_V13;
2371 max_h = CIF_ISP_INPUT_H_MAX_V13;
2372 break;
2373 case ISP_V21:
2374 max_w = CIF_ISP_INPUT_W_MAX_V21;
2375 max_h = CIF_ISP_INPUT_H_MAX_V21;
2376 break;
2377 case ISP_V30:
2378 max_w = dev->hw_dev->is_unite ?
2379 CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
2380 max_h = dev->hw_dev->is_unite ?
2381 CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
2382 break;
2383 default:
2384 max_w = CIF_ISP_INPUT_W_MAX;
2385 max_h = CIF_ISP_INPUT_H_MAX;
2386 }
2387 crop->width = min_t(u32, isp_sd->in_frm.width, max_w);
2388 crop->height = min_t(u32, isp_sd->in_frm.height, max_h);
2389 }
2390 break;
2391 case V4L2_SEL_TGT_CROP:
2392 if (sel->pad == RKISP_ISP_PAD_SOURCE_PATH)
2393 *crop = isp_sd->out_crop;
2394 break;
2395 default:
2396 goto err;
2397 }
2398
2399 return 0;
2400 err:
2401 return -EINVAL;
2402 }
2403
rkisp_isp_sd_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)2404 static int rkisp_isp_sd_set_selection(struct v4l2_subdev *sd,
2405 struct v4l2_subdev_pad_config *cfg,
2406 struct v4l2_subdev_selection *sel)
2407 {
2408 struct rkisp_isp_subdev *isp_sd = sd_to_isp_sd(sd);
2409 struct rkisp_device *dev = sd_to_isp_dev(sd);
2410 struct v4l2_rect *crop;
2411
2412 if (!sel)
2413 goto err;
2414 if (sel->pad != RKISP_ISP_PAD_SOURCE_PATH &&
2415 sel->pad != RKISP_ISP_PAD_SINK)
2416 goto err;
2417 if (sel->target != V4L2_SEL_TGT_CROP)
2418 goto err;
2419
2420 crop = &sel->r;
2421 if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
2422 if (!cfg)
2423 goto err;
2424 crop = v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
2425 }
2426
2427 rkisp_isp_sd_try_crop(sd, crop, sel->pad);
2428
2429 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2430 "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, sel->pad,
2431 crop->left, crop->top, crop->width, crop->height);
2432
2433 if (sel->pad == RKISP_ISP_PAD_SINK) {
2434 isp_sd->in_crop = *crop;
2435 /* ISP20 don't have out crop */
2436 if (dev->isp_ver == ISP_V20 ||
2437 dev->isp_ver == ISP_V21 ||
2438 dev->isp_ver == ISP_V30) {
2439 isp_sd->out_crop = *crop;
2440 isp_sd->out_crop.left = 0;
2441 isp_sd->out_crop.top = 0;
2442 dev->br_dev.crop = isp_sd->out_crop;
2443 }
2444 } else {
2445 if (dev->isp_ver == ISP_V20 ||
2446 dev->isp_ver == ISP_V21 ||
2447 dev->isp_ver == ISP_V30)
2448 *crop = isp_sd->out_crop;
2449 isp_sd->out_crop = *crop;
2450 }
2451
2452 return 0;
2453 err:
2454 return -EINVAL;
2455 }
2456
rkisp_isp_read_add_fifo_data(struct rkisp_device * dev)2457 static void rkisp_isp_read_add_fifo_data(struct rkisp_device *dev)
2458 {
2459 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2460 void __iomem *base = dev->base_addr;
2461 u32 mipi_status = 0;
2462 u32 data_len = 0;
2463 u32 fifo_data = 0;
2464 u32 i, idx, cur_frame_id;
2465
2466 if (dev->isp_ver != ISP_V10 &&
2467 dev->isp_ver != ISP_V10_1)
2468 return;
2469
2470 cur_frame_id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
2471 idx = dev->emd_data_idx;
2472 dev->emd_data_fifo[idx].frame_id = 0;
2473 kfifo_reset_out(&dev->emd_data_fifo[idx].mipi_kfifo);
2474 for (i = 0; i < CIFISP_ADD_DATA_FIFO_SIZE / 4; i++) {
2475 mipi_status = readl(base + CIF_MIPI_STATUS);
2476 if (!(mipi_status & 0x01))
2477 break;
2478
2479 fifo_data = readl(base + CIF_MIPI_ADD_DATA_FIFO);
2480 kfifo_in(&dev->emd_data_fifo[idx].mipi_kfifo,
2481 &fifo_data, sizeof(fifo_data));
2482 data_len += 4;
2483
2484 if (kfifo_is_full(&dev->emd_data_fifo[idx].mipi_kfifo))
2485 v4l2_warn(v4l2_dev, "%s: mipi_kfifo is full!\n",
2486 __func__);
2487 }
2488
2489 if (data_len) {
2490 dev->emd_data_fifo[idx].frame_id = cur_frame_id;
2491 dev->emd_data_fifo[idx].data_len = data_len;
2492 dev->emd_data_idx = (idx + 1) % RKISP_EMDDATA_FIFO_MAX;
2493 }
2494
2495 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2496 "emd kfifo size: %d, frame_id %d\n",
2497 kfifo_len(&dev->emd_data_fifo[idx].mipi_kfifo),
2498 dev->emd_data_fifo[idx].frame_id);
2499 }
2500
rkisp_global_update_mi(struct rkisp_device * dev)2501 static void rkisp_global_update_mi(struct rkisp_device *dev)
2502 {
2503 struct rkisp_stream *stream;
2504 int i;
2505
2506 if (dev->hw_dev->is_mi_update)
2507 return;
2508
2509 rkisp_stats_first_ddr_config(&dev->stats_vdev);
2510 rkisp_config_dmatx_valid_buf(dev);
2511
2512 force_cfg_update(dev);
2513
2514 hdr_update_dmatx_buf(dev);
2515 if (dev->br_dev.en && dev->isp_ver == ISP_V20) {
2516 stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
2517 rkisp_update_spstream_buf(stream);
2518 }
2519 if (dev->hw_dev->is_single) {
2520 for (i = 0; i < RKISP_MAX_STREAM; i++) {
2521 stream = &dev->cap_dev.stream[i];
2522 if (stream->streaming)
2523 stream->ops->frame_end(stream);
2524 }
2525 }
2526 }
2527
rkisp_isp_sd_s_stream(struct v4l2_subdev * sd,int on)2528 static int rkisp_isp_sd_s_stream(struct v4l2_subdev *sd, int on)
2529 {
2530 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2531
2532 if (!on) {
2533 rkisp_stop_3a_run(isp_dev);
2534 wait_event_timeout(isp_dev->sync_onoff,
2535 isp_dev->irq_ends_mask == (ISP_FRAME_END | ISP_FRAME_IN) &&
2536 (!IS_HDR_RDBK(isp_dev->rd_mode) ||
2537 isp_dev->isp_state & ISP_STOP), msecs_to_jiffies(5));
2538 rkisp_isp_stop(isp_dev);
2539 atomic_dec(&isp_dev->hw_dev->refcnt);
2540 rkisp_params_stream_stop(&isp_dev->params_vdev);
2541 return 0;
2542 }
2543
2544 rkisp_start_3a_run(isp_dev);
2545 memset(&isp_dev->isp_sdev.dbg, 0, sizeof(isp_dev->isp_sdev.dbg));
2546 atomic_inc(&isp_dev->hw_dev->refcnt);
2547 atomic_set(&isp_dev->isp_sdev.frm_sync_seq, 0);
2548 rkisp_global_update_mi(isp_dev);
2549 rkisp_config_cif(isp_dev);
2550 rkisp_isp_start(isp_dev);
2551 rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, NULL);
2552 return 0;
2553 }
2554
rkisp_rx_buf_pool_free(struct rkisp_device * dev)2555 void rkisp_rx_buf_pool_free(struct rkisp_device *dev)
2556 {
2557 const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
2558 struct rkisp_rx_buf_pool *pool;
2559 int i;
2560
2561 for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
2562 pool = &dev->pv_pool[i];
2563 if (!pool->dbufs)
2564 break;
2565 if (pool->mem_priv) {
2566 g_ops->unmap_dmabuf(pool->mem_priv);
2567 g_ops->detach_dmabuf(pool->mem_priv);
2568 dma_buf_put(pool->dbufs->dbuf);
2569 pool->mem_priv = NULL;
2570 }
2571 pool->dbufs = NULL;
2572 }
2573 }
2574
rkisp_rx_buf_pool_init(struct rkisp_device * dev,struct rkisp_rx_buf * dbufs)2575 static int rkisp_rx_buf_pool_init(struct rkisp_device *dev,
2576 struct rkisp_rx_buf *dbufs)
2577 {
2578 const struct vb2_mem_ops *g_ops = dev->hw_dev->mem_ops;
2579 struct rkisp_stream *stream;
2580 struct rkisp_rx_buf_pool *pool;
2581 struct sg_table *sg_tbl;
2582 int i, ret;
2583 void *mem;
2584 u32 val;
2585
2586 for (i = 0; i < RKISP_RX_BUF_POOL_MAX; i++) {
2587 pool = &dev->pv_pool[i];
2588 if (!pool->dbufs)
2589 break;
2590 }
2591
2592 pool->dbufs = dbufs;
2593 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2594 "%s type:0x%x dbufs[%d]:%p", __func__, dbufs->type, i, dbufs);
2595
2596 mem = g_ops->attach_dmabuf(dev->hw_dev->dev, dbufs->dbuf,
2597 dbufs->dbuf->size, DMA_BIDIRECTIONAL);
2598 if (IS_ERR(mem)) {
2599 ret = PTR_ERR(mem);
2600 goto err;
2601 }
2602 pool->mem_priv = mem;
2603 ret = g_ops->map_dmabuf(mem);
2604 if (ret)
2605 goto err;
2606 if (dev->hw_dev->is_dma_sg_ops) {
2607 sg_tbl = (struct sg_table *)g_ops->cookie(mem);
2608 pool->dma = sg_dma_address(sg_tbl->sgl);
2609 } else {
2610 pool->dma = *((dma_addr_t *)g_ops->cookie(mem));
2611 }
2612 get_dma_buf(dbufs->dbuf);
2613 pool->vaddr = g_ops->vaddr(mem);
2614 dbufs->is_init = true;
2615
2616 switch (dbufs->type) {
2617 case BUF_SHORT:
2618 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
2619 break;
2620 case BUF_MIDDLE:
2621 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
2622 break;
2623 case BUF_LONG:
2624 default:
2625 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
2626
2627 }
2628 stream->ops->config_mi(stream);
2629 val = pool->dma;
2630 rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
2631 if (dev->hw_dev->is_unite) {
2632 val += (stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL) *
2633 stream->out_isp_fmt.bpp[0] / 8;
2634 rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
2635 }
2636 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2637 "%s dma:0x%x vaddr:%p", __func__, (u32)pool->dma, pool->vaddr);
2638 return 0;
2639 err:
2640 rkisp_rx_buf_pool_free(dev);
2641 return ret;
2642 }
2643
rkisp_sd_s_rx_buffer(struct v4l2_subdev * sd,void * buf,unsigned int * size)2644 static int rkisp_sd_s_rx_buffer(struct v4l2_subdev *sd,
2645 void *buf, unsigned int *size)
2646 {
2647 struct rkisp_device *dev = sd_to_isp_dev(sd);
2648 struct rkisp_rx_buf *dbufs;
2649 int ret = 0;
2650
2651 if (!buf)
2652 return -EINVAL;
2653
2654 dbufs = buf;
2655 if (!dbufs->is_init)
2656 ret = rkisp_rx_buf_pool_init(dev, dbufs);
2657
2658 /* TODO qbuf/debuf for more buffer */
2659
2660 return ret;
2661 }
2662
rkisp_isp_sd_s_power(struct v4l2_subdev * sd,int on)2663 static int rkisp_isp_sd_s_power(struct v4l2_subdev *sd, int on)
2664 {
2665 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2666 int ret;
2667
2668 v4l2_dbg(1, rkisp_debug, &isp_dev->v4l2_dev,
2669 "%s on:%d\n", __func__, on);
2670
2671 if (on) {
2672 if (isp_dev->isp_ver == ISP_V20 ||
2673 isp_dev->isp_ver == ISP_V21 ||
2674 isp_dev->isp_ver == ISP_V30)
2675 kfifo_reset(&isp_dev->rdbk_kfifo);
2676 ret = pm_runtime_get_sync(isp_dev->dev);
2677 } else {
2678 ret = pm_runtime_put_sync(isp_dev->dev);
2679 }
2680
2681 if (ret < 0)
2682 v4l2_err(sd, "%s on:%d failed:%d\n", __func__, on, ret);
2683 return ret;
2684 }
2685
rkisp_subdev_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)2686 static int rkisp_subdev_link_setup(struct media_entity *entity,
2687 const struct media_pad *local,
2688 const struct media_pad *remote,
2689 u32 flags)
2690 {
2691 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
2692 struct rkisp_device *dev;
2693 struct rkisp_stream *stream = NULL;
2694 u8 rawrd = INP_RAWRD0 | INP_RAWRD1 | INP_RAWRD2;
2695
2696 if (local->index != RKISP_ISP_PAD_SINK &&
2697 local->index != RKISP_ISP_PAD_SOURCE_PATH)
2698 return 0;
2699 if (!sd)
2700 return -ENODEV;
2701 dev = sd_to_isp_dev(sd);
2702 if (!dev)
2703 return -ENODEV;
2704
2705 if (!strcmp(remote->entity->name, DMA_VDEV_NAME)) {
2706 stream = &dev->dmarx_dev.stream[RKISP_STREAM_DMARX];
2707 if (flags & MEDIA_LNK_FL_ENABLED) {
2708 if (dev->isp_inp & ~INP_DMARX_ISP)
2709 goto err;
2710 dev->isp_inp = INP_DMARX_ISP;
2711 } else {
2712 if (dev->active_sensor)
2713 dev->active_sensor = NULL;
2714 dev->isp_inp = INP_INVAL;
2715 }
2716 } else if (!strcmp(remote->entity->name, CSI_DEV_NAME)) {
2717 if (flags & MEDIA_LNK_FL_ENABLED) {
2718 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
2719 goto err;
2720 dev->isp_inp |= INP_CSI;
2721 } else {
2722 if (dev->active_sensor)
2723 dev->active_sensor = NULL;
2724 dev->isp_inp &= ~INP_CSI;
2725 }
2726 } else if (!strcmp(remote->entity->name, DMARX0_VDEV_NAME)) {
2727 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
2728 if (flags & MEDIA_LNK_FL_ENABLED) {
2729 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
2730 goto err;
2731 dev->isp_inp |= INP_RAWRD0;
2732 } else {
2733 dev->isp_inp &= ~INP_RAWRD0;
2734 }
2735 } else if (!strcmp(remote->entity->name, DMARX1_VDEV_NAME)) {
2736 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
2737 if (flags & MEDIA_LNK_FL_ENABLED) {
2738 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
2739 goto err;
2740 dev->isp_inp |= INP_RAWRD1;
2741 } else {
2742 dev->isp_inp &= ~INP_RAWRD1;
2743 }
2744 } else if (!strcmp(remote->entity->name, DMARX2_VDEV_NAME)) {
2745 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
2746 if (flags & MEDIA_LNK_FL_ENABLED) {
2747 if (dev->isp_inp & ~(INP_CSI | INP_CIF | rawrd))
2748 goto err;
2749 dev->isp_inp |= INP_RAWRD2;
2750 } else {
2751 dev->isp_inp &= ~INP_RAWRD2;
2752 }
2753 } else if (!strcmp(remote->entity->name, SP_VDEV_NAME)) {
2754 stream = &dev->cap_dev.stream[RKISP_STREAM_SP];
2755 } else if (!strcmp(remote->entity->name, MP_VDEV_NAME)) {
2756 stream = &dev->cap_dev.stream[RKISP_STREAM_MP];
2757 if (flags & MEDIA_LNK_FL_ENABLED &&
2758 dev->br_dev.linked)
2759 goto err;
2760 } else if (!strcmp(remote->entity->name, BRIDGE_DEV_NAME)) {
2761 if (flags & MEDIA_LNK_FL_ENABLED &&
2762 dev->cap_dev.stream[RKISP_STREAM_MP].linked)
2763 goto err;
2764 dev->br_dev.linked = flags & MEDIA_LNK_FL_ENABLED;
2765 } else if (!strcmp(remote->entity->name, "rockchip-mipi-dphy-rx")) {
2766 if (flags & MEDIA_LNK_FL_ENABLED) {
2767 if (dev->isp_inp & ~INP_LVDS)
2768 goto err;
2769 dev->isp_inp |= INP_LVDS;
2770 } else {
2771 if (dev->active_sensor)
2772 dev->active_sensor = NULL;
2773 dev->isp_inp &= ~INP_LVDS;
2774 }
2775 } else if (strstr(remote->entity->name, "rkcif")) {
2776 if (flags & MEDIA_LNK_FL_ENABLED) {
2777 if (dev->isp_inp & ~(INP_CIF | rawrd))
2778 goto err;
2779 dev->isp_inp |= INP_CIF;
2780 } else {
2781 dev->isp_inp &= ~INP_CIF;
2782 }
2783 } else {
2784 if (flags & MEDIA_LNK_FL_ENABLED) {
2785 if (dev->isp_inp & ~INP_DVP)
2786 goto err;
2787 dev->isp_inp |= INP_DVP;
2788 } else {
2789 if (dev->active_sensor)
2790 dev->active_sensor = NULL;
2791 dev->isp_inp &= ~INP_INVAL;
2792 }
2793 }
2794
2795 if (stream)
2796 stream->linked = flags & MEDIA_LNK_FL_ENABLED;
2797 if (dev->isp_inp & rawrd)
2798 dev->dmarx_dev.trigger = T_MANUAL;
2799 else
2800 dev->dmarx_dev.trigger = T_AUTO;
2801
2802 if (dev->isp_inp & INP_CIF) {
2803 struct v4l2_subdev *remote = get_remote_sensor(sd);
2804 struct rkisp_vicap_mode mode;
2805
2806 mode.name = dev->name;
2807 mode.is_rdbk = !!(dev->isp_inp & rawrd);
2808 /* read back mode only */
2809 if (dev->isp_ver < ISP_V30 || !dev->hw_dev->is_single)
2810 mode.is_rdbk = true;
2811 v4l2_subdev_call(remote, core, ioctl,
2812 RKISP_VICAP_CMD_MODE, &mode);
2813 }
2814
2815 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
2816 "isp input:0x%x\n", dev->isp_inp);
2817 return 0;
2818 err:
2819 v4l2_err(sd, "link error %s -> %s\n"
2820 "\tcsi dvp lvds dmaread can't work together\n"
2821 "\trawrd can't work with dvp lvds dmaread\n"
2822 "\tbridge can't work with mainpath/selfpath\n",
2823 local->entity->name, remote->entity->name);
2824 return -EINVAL;
2825 }
2826
rkisp_subdev_link_validate(struct media_link * link)2827 static int rkisp_subdev_link_validate(struct media_link *link)
2828 {
2829 if (link->source->index == RKISP_ISP_PAD_SINK_PARAMS)
2830 return 0;
2831
2832 return v4l2_subdev_link_validate(link);
2833 }
2834
2835 #ifdef CONFIG_MEDIA_CONTROLLER
rkisp_subdev_fmt_link_validate(struct v4l2_subdev * sd,struct media_link * link,struct v4l2_subdev_format * source_fmt,struct v4l2_subdev_format * sink_fmt)2836 static int rkisp_subdev_fmt_link_validate(struct v4l2_subdev *sd,
2837 struct media_link *link,
2838 struct v4l2_subdev_format *source_fmt,
2839 struct v4l2_subdev_format *sink_fmt)
2840 {
2841 if (source_fmt->format.code != sink_fmt->format.code)
2842 return -EINVAL;
2843
2844 /* Crop is available */
2845 if (source_fmt->format.width < sink_fmt->format.width ||
2846 source_fmt->format.height < sink_fmt->format.height)
2847 return -EINVAL;
2848
2849 return 0;
2850 }
2851 #endif
2852
2853 void
rkisp_isp_queue_event_sof(struct rkisp_isp_subdev * isp)2854 rkisp_isp_queue_event_sof(struct rkisp_isp_subdev *isp)
2855 {
2856 struct v4l2_event event = {
2857 .type = V4L2_EVENT_FRAME_SYNC,
2858 .u.frame_sync.frame_sequence =
2859 atomic_inc_return(&isp->frm_sync_seq) - 1,
2860 };
2861
2862 v4l2_event_queue(isp->sd.devnode, &event);
2863 }
2864
rkisp_isp_sd_subs_evt(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)2865 static int rkisp_isp_sd_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
2866 struct v4l2_event_subscription *sub)
2867 {
2868 if (sub->type != V4L2_EVENT_FRAME_SYNC)
2869 return -EINVAL;
2870
2871 /* Line number. For now only zero accepted. */
2872 if (sub->id != 0)
2873 return -EINVAL;
2874
2875 return v4l2_event_subscribe(fh, sub, 0, NULL);
2876 }
2877
rkisp_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)2878 static long rkisp_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
2879 {
2880 struct rkisp_device *isp_dev = sd_to_isp_dev(sd);
2881 struct rkisp_thunderboot_resmem *resmem;
2882 struct rkisp_thunderboot_resmem_head *head;
2883 struct rkisp_thunderboot_shmem *shmem;
2884 struct isp2x_buf_idxfd *idxfd;
2885 void *resmem_va;
2886 long ret = 0;
2887
2888 if (!arg && cmd != RKISP_CMD_FREE_SHARED_BUF)
2889 return -EINVAL;
2890
2891 switch (cmd) {
2892 case RKISP_CMD_TRIGGER_READ_BACK:
2893 rkisp_rdbk_trigger_event(isp_dev, T_CMD_QUEUE, arg);
2894 break;
2895 case RKISP_CMD_GET_SHARED_BUF:
2896 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
2897 ret = -ENOIOCTLCMD;
2898 break;
2899 }
2900 resmem = (struct rkisp_thunderboot_resmem *)arg;
2901 resmem->resmem_padr = isp_dev->resmem_pa;
2902 resmem->resmem_size = isp_dev->resmem_size;
2903 if (!isp_dev->resmem_pa || !isp_dev->resmem_size) {
2904 v4l2_info(sd, "no reserved memory for thunderboot\n");
2905 break;
2906 }
2907
2908 rkisp_chk_tb_over(isp_dev);
2909 dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr,
2910 sizeof(struct rkisp_thunderboot_resmem_head),
2911 DMA_FROM_DEVICE);
2912
2913 resmem_va = phys_to_virt(isp_dev->resmem_pa);
2914 head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
2915 if (head->complete != RKISP_TB_OK) {
2916 resmem->resmem_size = 0;
2917 dma_unmap_single(isp_dev->dev, isp_dev->resmem_pa,
2918 sizeof(struct rkisp_thunderboot_resmem_head),
2919 DMA_FROM_DEVICE);
2920 free_reserved_area(phys_to_virt(isp_dev->resmem_pa),
2921 phys_to_virt(isp_dev->resmem_pa) + isp_dev->resmem_size,
2922 -1, "rkisp_thunderboot");
2923
2924 isp_dev->resmem_pa = 0;
2925 isp_dev->resmem_size = 0;
2926 }
2927 break;
2928 case RKISP_CMD_FREE_SHARED_BUF:
2929 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
2930 ret = -ENOIOCTLCMD;
2931 break;
2932 }
2933 if (isp_dev->resmem_pa && isp_dev->resmem_size) {
2934 dma_unmap_single(isp_dev->dev, isp_dev->resmem_pa,
2935 sizeof(struct rkisp_thunderboot_resmem_head),
2936 DMA_FROM_DEVICE);
2937 free_reserved_area(phys_to_virt(isp_dev->resmem_pa),
2938 phys_to_virt(isp_dev->resmem_pa) + isp_dev->resmem_size,
2939 -1, "rkisp_thunderboot");
2940 }
2941
2942 isp_dev->resmem_pa = 0;
2943 isp_dev->resmem_size = 0;
2944 break;
2945 case RKISP_CMD_GET_LDCHBUF_INFO:
2946 case RKISP_CMD_GET_MESHBUF_INFO:
2947 rkisp_params_get_meshbuf_inf(&isp_dev->params_vdev, arg);
2948 break;
2949 case RKISP_CMD_SET_LDCHBUF_SIZE:
2950 case RKISP_CMD_SET_MESHBUF_SIZE:
2951 rkisp_params_set_meshbuf_size(&isp_dev->params_vdev, arg);
2952 break;
2953 case RKISP_CMD_GET_SHM_BUFFD:
2954 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
2955 ret = -ENOIOCTLCMD;
2956 break;
2957 }
2958 shmem = (struct rkisp_thunderboot_shmem *)arg;
2959 ret = rkisp_tb_shm_ioctl(shmem);
2960 break;
2961 case RKISP_CMD_GET_FBCBUF_FD:
2962 idxfd = (struct isp2x_buf_idxfd *)arg;
2963 ret = rkisp_bridge_get_fbcbuf_fd(isp_dev, idxfd);
2964 break;
2965 default:
2966 ret = -ENOIOCTLCMD;
2967 }
2968
2969 return ret;
2970 }
2971
2972 #ifdef CONFIG_COMPAT
rkisp_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)2973 static long rkisp_compat_ioctl32(struct v4l2_subdev *sd,
2974 unsigned int cmd, unsigned long arg)
2975 {
2976 void __user *up = compat_ptr(arg);
2977 struct isp2x_csi_trigger trigger;
2978 struct rkisp_thunderboot_resmem resmem;
2979 struct rkisp_ldchbuf_info ldchbuf;
2980 struct rkisp_ldchbuf_size ldchsize;
2981 struct rkisp_meshbuf_info meshbuf;
2982 struct rkisp_meshbuf_size meshsize;
2983 struct rkisp_thunderboot_shmem shmem;
2984 struct isp2x_buf_idxfd idxfd;
2985 long ret = 0;
2986
2987 if (!up && cmd != RKISP_CMD_FREE_SHARED_BUF)
2988 return -EINVAL;
2989
2990 switch (cmd) {
2991 case RKISP_CMD_TRIGGER_READ_BACK:
2992 if (copy_from_user(&trigger, up, sizeof(trigger)))
2993 return -EFAULT;
2994 ret = rkisp_ioctl(sd, cmd, &trigger);
2995 break;
2996 case RKISP_CMD_GET_SHARED_BUF:
2997 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
2998 ret = -ENOIOCTLCMD;
2999 break;
3000 }
3001 ret = rkisp_ioctl(sd, cmd, &resmem);
3002 if (!ret && copy_to_user(up, &resmem, sizeof(resmem)))
3003 ret = -EFAULT;
3004 break;
3005 case RKISP_CMD_FREE_SHARED_BUF:
3006 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3007 ret = -ENOIOCTLCMD;
3008 break;
3009 }
3010 ret = rkisp_ioctl(sd, cmd, NULL);
3011 break;
3012 case RKISP_CMD_GET_LDCHBUF_INFO:
3013 ret = rkisp_ioctl(sd, cmd, &ldchbuf);
3014 if (!ret && copy_to_user(up, &ldchbuf, sizeof(ldchbuf)))
3015 ret = -EFAULT;
3016 break;
3017 case RKISP_CMD_SET_LDCHBUF_SIZE:
3018 if (copy_from_user(&ldchsize, up, sizeof(ldchsize)))
3019 return -EFAULT;
3020 ret = rkisp_ioctl(sd, cmd, &ldchsize);
3021 break;
3022 case RKISP_CMD_GET_MESHBUF_INFO:
3023 if (copy_from_user(&meshsize, up, sizeof(meshsize)))
3024 return -EFAULT;
3025 ret = rkisp_ioctl(sd, cmd, &meshbuf);
3026 if (!ret && copy_to_user(up, &meshbuf, sizeof(meshbuf)))
3027 ret = -EFAULT;
3028 break;
3029 case RKISP_CMD_SET_MESHBUF_SIZE:
3030 if (copy_from_user(&meshsize, up, sizeof(meshsize)))
3031 return -EFAULT;
3032 ret = rkisp_ioctl(sd, cmd, &meshsize);
3033 break;
3034 case RKISP_CMD_GET_SHM_BUFFD:
3035 if (!IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP)) {
3036 ret = -ENOIOCTLCMD;
3037 break;
3038 }
3039 if (copy_from_user(&shmem, up, sizeof(shmem)))
3040 return -EFAULT;
3041 ret = rkisp_ioctl(sd, cmd, &shmem);
3042 if (!ret && copy_to_user(up, &shmem, sizeof(shmem)))
3043 ret = -EFAULT;
3044 break;
3045 case RKISP_CMD_GET_FBCBUF_FD:
3046 ret = rkisp_ioctl(sd, cmd, &idxfd);
3047 if (!ret && copy_to_user(up, &idxfd, sizeof(idxfd)))
3048 ret = -EFAULT;
3049 break;
3050 default:
3051 ret = -ENOIOCTLCMD;
3052 }
3053
3054 return ret;
3055 }
3056 #endif
3057
3058 static const struct v4l2_subdev_pad_ops rkisp_isp_sd_pad_ops = {
3059 .enum_mbus_code = rkisp_isp_sd_enum_mbus_code,
3060 .get_selection = rkisp_isp_sd_get_selection,
3061 .set_selection = rkisp_isp_sd_set_selection,
3062 .get_fmt = rkisp_isp_sd_get_fmt,
3063 .set_fmt = rkisp_isp_sd_set_fmt,
3064 #ifdef CONFIG_MEDIA_CONTROLLER
3065 .link_validate = rkisp_subdev_fmt_link_validate,
3066 #endif
3067 };
3068
3069 static const struct media_entity_operations rkisp_isp_sd_media_ops = {
3070 .link_setup = rkisp_subdev_link_setup,
3071 .link_validate = rkisp_subdev_link_validate,
3072 };
3073
3074 static const struct v4l2_subdev_video_ops rkisp_isp_sd_video_ops = {
3075 .s_stream = rkisp_isp_sd_s_stream,
3076 .s_rx_buffer = rkisp_sd_s_rx_buffer,
3077 };
3078
3079 static const struct v4l2_subdev_core_ops rkisp_isp_core_ops = {
3080 .subscribe_event = rkisp_isp_sd_subs_evt,
3081 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3082 .s_power = rkisp_isp_sd_s_power,
3083 .ioctl = rkisp_ioctl,
3084 #ifdef CONFIG_COMPAT
3085 .compat_ioctl32 = rkisp_compat_ioctl32,
3086 #endif
3087 };
3088
3089 static struct v4l2_subdev_ops rkisp_isp_sd_ops = {
3090 .core = &rkisp_isp_core_ops,
3091 .video = &rkisp_isp_sd_video_ops,
3092 .pad = &rkisp_isp_sd_pad_ops,
3093 };
3094
rkisp_isp_sd_init_default_fmt(struct rkisp_isp_subdev * isp_sd)3095 static void rkisp_isp_sd_init_default_fmt(struct rkisp_isp_subdev *isp_sd)
3096 {
3097 struct v4l2_mbus_framefmt *in_frm = &isp_sd->in_frm;
3098 struct v4l2_rect *in_crop = &isp_sd->in_crop;
3099 struct v4l2_rect *out_crop = &isp_sd->out_crop;
3100 struct ispsd_in_fmt *in_fmt = &isp_sd->in_fmt;
3101 struct ispsd_out_fmt *out_fmt = &isp_sd->out_fmt;
3102
3103 *in_fmt = rkisp_isp_input_formats[0];
3104 in_frm->width = RKISP_DEFAULT_WIDTH;
3105 in_frm->height = RKISP_DEFAULT_HEIGHT;
3106 in_frm->code = in_fmt->mbus_code;
3107
3108 in_crop->width = in_frm->width;
3109 in_crop->height = in_frm->height;
3110 in_crop->left = 0;
3111 in_crop->top = 0;
3112
3113 /* propagate to source */
3114 *out_crop = *in_crop;
3115 *out_fmt = rkisp_isp_output_formats[0];
3116 isp_sd->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3117 isp_sd->colorspace = V4L2_COLORSPACE_SMPTE170M;
3118 }
3119
rkisp_register_isp_subdev(struct rkisp_device * isp_dev,struct v4l2_device * v4l2_dev)3120 int rkisp_register_isp_subdev(struct rkisp_device *isp_dev,
3121 struct v4l2_device *v4l2_dev)
3122 {
3123 struct rkisp_isp_subdev *isp_sdev = &isp_dev->isp_sdev;
3124 struct v4l2_subdev *sd = &isp_sdev->sd;
3125 int ret;
3126
3127 spin_lock_init(&isp_dev->cmsk_lock);
3128 spin_lock_init(&isp_dev->rdbk_lock);
3129 ret = kfifo_alloc(&isp_dev->rdbk_kfifo,
3130 16 * sizeof(struct isp2x_csi_trigger), GFP_KERNEL);
3131 if (ret < 0) {
3132 v4l2_err(v4l2_dev, "Failed to alloc csi kfifo %d", ret);
3133 return ret;
3134 }
3135
3136 v4l2_subdev_init(sd, &rkisp_isp_sd_ops);
3137 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3138 sd->entity.ops = &rkisp_isp_sd_media_ops;
3139 sd->entity.function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN;
3140 snprintf(sd->name, sizeof(sd->name), ISP_SUBDEV_NAME);
3141
3142 isp_sdev->pads[RKISP_ISP_PAD_SINK].flags =
3143 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
3144 isp_sdev->pads[RKISP_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
3145 isp_sdev->pads[RKISP_ISP_PAD_SOURCE_PATH].flags = MEDIA_PAD_FL_SOURCE;
3146 isp_sdev->pads[RKISP_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
3147 ret = media_entity_pads_init(&sd->entity, RKISP_ISP_PAD_MAX,
3148 isp_sdev->pads);
3149 if (ret < 0)
3150 goto free_kfifo;
3151
3152 sd->owner = THIS_MODULE;
3153 v4l2_set_subdevdata(sd, isp_dev);
3154
3155 sd->grp_id = GRP_ID_ISP;
3156 ret = v4l2_device_register_subdev(v4l2_dev, sd);
3157 if (ret < 0) {
3158 v4l2_err(sd, "Failed to register isp subdev\n");
3159 goto err_cleanup_media_entity;
3160 }
3161
3162 rkisp_isp_sd_init_default_fmt(isp_sdev);
3163 isp_dev->hdr.sensor = NULL;
3164 isp_dev->isp_state = ISP_STOP;
3165
3166 rkisp_monitor_init(isp_dev);
3167 return 0;
3168 err_cleanup_media_entity:
3169 media_entity_cleanup(&sd->entity);
3170 free_kfifo:
3171 kfifo_free(&isp_dev->rdbk_kfifo);
3172 return ret;
3173 }
3174
rkisp_unregister_isp_subdev(struct rkisp_device * isp_dev)3175 void rkisp_unregister_isp_subdev(struct rkisp_device *isp_dev)
3176 {
3177 struct v4l2_subdev *sd = &isp_dev->isp_sdev.sd;
3178
3179 kfifo_free(&isp_dev->rdbk_kfifo);
3180 v4l2_device_unregister_subdev(sd);
3181 media_entity_cleanup(&sd->entity);
3182 }
3183
3184 #define shm_head_poll_timeout(isp_dev, cond, sleep_us, timeout_us) \
3185 ({ \
3186 u64 __timeout_us = (timeout_us); \
3187 unsigned long __sleep_us = (sleep_us); \
3188 ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
3189 might_sleep_if((__sleep_us) != 0); \
3190 for (;;) { \
3191 dma_sync_single_for_cpu(isp_dev->dev, isp_dev->resmem_addr, \
3192 sizeof(struct rkisp_thunderboot_resmem_head), \
3193 DMA_FROM_DEVICE); \
3194 if (cond) \
3195 break; \
3196 if (__timeout_us && \
3197 ktime_compare(ktime_get(), __timeout) > 0) { \
3198 break; \
3199 } \
3200 if (__sleep_us) \
3201 usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
3202 } \
3203 (cond) ? 0 : -ETIMEDOUT; \
3204 })
3205
3206 #ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
rkisp_chk_tb_over(struct rkisp_device * isp_dev)3207 void rkisp_chk_tb_over(struct rkisp_device *isp_dev)
3208 {
3209 struct rkisp_thunderboot_resmem_head *head;
3210 enum rkisp_tb_state tb_state;
3211 void *resmem_va;
3212
3213 if (!isp_dev->resmem_pa || !isp_dev->resmem_size) {
3214 v4l2_info(&isp_dev->v4l2_dev,
3215 "no reserved memory for thunderboot\n");
3216 if (isp_dev->hw_dev->is_thunderboot) {
3217 rkisp_tb_set_state(RKISP_TB_NG);
3218 rkisp_tb_unprotect_clk();
3219 rkisp_register_irq(isp_dev->hw_dev);
3220 isp_dev->hw_dev->is_thunderboot = false;
3221 }
3222 return;
3223 }
3224
3225 resmem_va = phys_to_virt(isp_dev->resmem_pa);
3226 head = (struct rkisp_thunderboot_resmem_head *)resmem_va;
3227 if (isp_dev->hw_dev->is_thunderboot) {
3228 shm_head_poll_timeout(isp_dev, !!head->enable, 2000, 200 * USEC_PER_MSEC);
3229 shm_head_poll_timeout(isp_dev, !!head->complete, 5000, 500 * USEC_PER_MSEC);
3230 if (head->complete != RKISP_TB_OK)
3231 v4l2_info(&isp_dev->v4l2_dev,
3232 "wait thunderboot over timeout\n");
3233
3234 v4l2_info(&isp_dev->v4l2_dev,
3235 "thunderboot info: %d, %d, %d, %d, %d, %d, 0x%x\n",
3236 head->enable,
3237 head->complete,
3238 head->frm_total,
3239 head->hdr_mode,
3240 head->width,
3241 head->height,
3242 head->bus_fmt);
3243
3244 tb_state = RKISP_TB_OK;
3245 if (head->complete != RKISP_TB_OK) {
3246 head->frm_total = 0;
3247 tb_state = RKISP_TB_NG;
3248 }
3249
3250 rkisp_tb_set_state(tb_state);
3251 rkisp_tb_unprotect_clk();
3252 rkisp_register_irq(isp_dev->hw_dev);
3253 isp_dev->hw_dev->is_thunderboot = false;
3254 }
3255 }
3256 #endif
3257
3258 /**************** Interrupter Handler ****************/
3259
rkisp_mipi_isr(unsigned int mis,struct rkisp_device * dev)3260 void rkisp_mipi_isr(unsigned int mis, struct rkisp_device *dev)
3261 {
3262 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3263 void __iomem *base = dev->base_addr;
3264 u32 val;
3265
3266 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
3267 "mipi isr:0x%x\n", mis);
3268
3269 writel(~0, base + CIF_MIPI_ICR);
3270
3271 /*
3272 * Disable DPHY errctrl interrupt, because this dphy
3273 * erctrl signal is asserted until the next changes
3274 * of line state. This time is may be too long and cpu
3275 * is hold in this interrupt.
3276 */
3277 if (mis & CIF_MIPI_ERR_DPHY) {
3278 val = readl(base + CIF_MIPI_IMSC);
3279 writel(val & ~CIF_MIPI_ERR_DPHY, base + CIF_MIPI_IMSC);
3280 dev->isp_sdev.dphy_errctrl_disabled = true;
3281 }
3282
3283 /*
3284 * Enable DPHY errctrl interrupt again, if mipi have receive
3285 * the whole frame without any error.
3286 */
3287 if (mis == CIF_MIPI_FRAME_END) {
3288 /*
3289 * Enable DPHY errctrl interrupt again, if mipi have receive
3290 * the whole frame without any error.
3291 */
3292 if (dev->isp_sdev.dphy_errctrl_disabled) {
3293 val = readl(base + CIF_MIPI_IMSC);
3294 val |= CIF_MIPI_ERR_DPHY;
3295 writel(val, base + CIF_MIPI_IMSC);
3296 dev->isp_sdev.dphy_errctrl_disabled = false;
3297 }
3298 } else {
3299 v4l2_warn(v4l2_dev, "MIPI mis error: 0x%08x\n", mis);
3300 val = readl(base + CIF_MIPI_CTRL);
3301 writel(val | CIF_MIPI_CTRL_FLUSH_FIFO, base + CIF_MIPI_CTRL);
3302 }
3303 }
3304
rkisp_mipi_v13_isr(unsigned int err1,unsigned int err2,unsigned int err3,struct rkisp_device * dev)3305 void rkisp_mipi_v13_isr(unsigned int err1, unsigned int err2,
3306 unsigned int err3, struct rkisp_device *dev)
3307 {
3308 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3309 void __iomem *base = dev->base_addr;
3310 u32 val, mask;
3311
3312 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
3313 "mipi isr err1:0x%x err2:0x%x err3:0x%x\n",
3314 err1, err2, err3);
3315
3316 /*
3317 * Disable DPHY errctrl interrupt, because this dphy
3318 * erctrl signal is asserted until the next changes
3319 * of line state. This time is may be too long and cpu
3320 * is hold in this interrupt.
3321 */
3322 mask = CIF_ISP_CSI0_IMASK1_PHY_ERRSOTSYNC(0x0F) |
3323 CIF_ISP_CSI0_IMASK1_PHY_ERREOTSYNC(0x0F);
3324 if (mask & err1) {
3325 val = readl(base + CIF_ISP_CSI0_MASK1);
3326 writel(val & ~mask, base + CIF_ISP_CSI0_MASK1);
3327 dev->isp_sdev.dphy_errctrl_disabled = true;
3328 }
3329
3330 mask = CIF_ISP_CSI0_IMASK2_PHY_ERRSOTHS(0x0F) |
3331 CIF_ISP_CSI0_IMASK2_PHY_ERRCONTROL(0x0F);
3332 if (mask & err2) {
3333 val = readl(base + CIF_ISP_CSI0_MASK2);
3334 writel(val & ~mask, base + CIF_ISP_CSI0_MASK2);
3335 dev->isp_sdev.dphy_errctrl_disabled = true;
3336 }
3337
3338 mask = CIF_ISP_CSI0_IMASK_FRAME_END(0x3F);
3339 if ((err3 & mask) && !err1 && !err2) {
3340 /*
3341 * Enable DPHY errctrl interrupt again, if mipi have receive
3342 * the whole frame without any error.
3343 */
3344 if (dev->isp_sdev.dphy_errctrl_disabled) {
3345 writel(0x1FFFFFF0, base + CIF_ISP_CSI0_MASK1);
3346 writel(0x03FFFFFF, base + CIF_ISP_CSI0_MASK2);
3347 dev->isp_sdev.dphy_errctrl_disabled = false;
3348 }
3349 }
3350
3351 if (err1)
3352 v4l2_warn(v4l2_dev, "MIPI error: err1: 0x%08x\n", err1);
3353
3354 if (err2)
3355 v4l2_warn(v4l2_dev, "MIPI error: err2: 0x%08x\n", err2);
3356 }
3357
rkisp_isp_isr(unsigned int isp_mis,unsigned int isp3a_mis,struct rkisp_device * dev)3358 void rkisp_isp_isr(unsigned int isp_mis,
3359 unsigned int isp3a_mis,
3360 struct rkisp_device *dev)
3361 {
3362 struct rkisp_hw_dev *hw = dev->hw_dev;
3363 void __iomem *base = !hw->is_unite ?
3364 hw->base_addr : hw->base_next_addr;
3365 unsigned int isp_mis_tmp = 0;
3366 unsigned int isp_err = 0;
3367 u32 si3a_isr_mask = ISP2X_SIAWB_DONE | ISP2X_SIAF_FIN |
3368 ISP2X_YUVAE_END | ISP2X_SIHST_RDY;
3369 u32 raw3a_isr_mask = ISP2X_3A_RAWAE_BIG | ISP2X_3A_RAWAE_CH0 |
3370 ISP2X_3A_RAWAE_CH1 | ISP2X_3A_RAWAE_CH2 |
3371 ISP2X_3A_RAWHIST_BIG | ISP2X_3A_RAWHIST_CH0 |
3372 ISP2X_3A_RAWHIST_CH1 | ISP2X_3A_RAWHIST_CH2 |
3373 ISP2X_3A_RAWAF_SUM | ISP2X_3A_RAWAF_LUM |
3374 ISP2X_3A_RAWAF | ISP2X_3A_RAWAWB;
3375 bool sof_event_later = false;
3376
3377 /*
3378 * The last time that rx perform 'back read' don't clear done flag
3379 * in advance, otherwise the statistics will be abnormal.
3380 */
3381 if (isp3a_mis & ISP2X_3A_RAWAE_BIG && dev->params_vdev.rdbk_times > 0)
3382 writel(BIT(31), base + RAWAE_BIG1_BASE + RAWAE_BIG_CTRL);
3383
3384 if (hw->is_unite) {
3385 u32 val = rkisp_read(dev, ISP3X_ISP_RIS, true);
3386
3387 if (val) {
3388 rkisp_write(dev, ISP3X_ISP_ICR, val, true);
3389 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
3390 "left isp isr:0x%x\n", val);
3391 }
3392 }
3393 v4l2_dbg(3, rkisp_debug, &dev->v4l2_dev,
3394 "isp isr:0x%x, 0x%x\n", isp_mis, isp3a_mis);
3395 dev->isp_isr_cnt++;
3396 /* start edge of v_sync */
3397 if (isp_mis & CIF_ISP_V_START) {
3398 if (dev->isp_state & ISP_FRAME_END) {
3399 u64 tmp = dev->isp_sdev.dbg.interval +
3400 dev->isp_sdev.dbg.timestamp;
3401
3402 dev->isp_sdev.dbg.timestamp = ktime_get_ns();
3403 /* v-blank: frame_end - frame_start */
3404 dev->isp_sdev.dbg.delay = dev->isp_sdev.dbg.timestamp - tmp;
3405 }
3406 rkisp_set_state(&dev->isp_state, ISP_FRAME_VS);
3407 if (dev->hw_dev->monitor.is_en) {
3408 rkisp_set_state(&dev->hw_dev->monitor.state, ISP_FRAME_VS);
3409 if (!completion_done(&dev->hw_dev->monitor.cmpl))
3410 complete(&dev->hw_dev->monitor.cmpl);
3411 }
3412 /* last vsync to config next buf */
3413 if (!dev->filt_state[RDBK_F_VS])
3414 rkisp_bridge_update_mi(dev, isp_mis);
3415 else
3416 dev->filt_state[RDBK_F_VS]--;
3417 if (IS_HDR_RDBK(dev->hdr.op_mode)) {
3418 /* read 3d lut at isp readback */
3419 if (!dev->hw_dev->is_single)
3420 rkisp_write(dev, ISP_3DLUT_UPDATE, 0, true);
3421 rkisp_stats_rdbk_enable(&dev->stats_vdev, true);
3422 goto vs_skip;
3423 }
3424 if (dev->cap_dev.stream[RKISP_STREAM_SP].interlaced) {
3425 /* 0 = ODD 1 = EVEN */
3426 if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
3427 void __iomem *addr = NULL;
3428
3429 if (dev->isp_ver == ISP_V10 ||
3430 dev->isp_ver == ISP_V10_1)
3431 addr = base + CIF_MIPI_FRAME;
3432 else if (dev->isp_ver == ISP_V12 ||
3433 dev->isp_ver == ISP_V13)
3434 addr = base + CIF_ISP_CSI0_FRAME_NUM_RO;
3435
3436 if (addr)
3437 dev->cap_dev.stream[RKISP_STREAM_SP].u.sp.field =
3438 (readl(addr) >> 16) % 2;
3439 } else {
3440 dev->cap_dev.stream[RKISP_STREAM_SP].u.sp.field =
3441 (readl(base + CIF_ISP_FLAGS_SHD) >> 2) & BIT(0);
3442 }
3443 }
3444
3445 if (isp_mis & CIF_ISP_FRAME)
3446 sof_event_later = true;
3447 if (dev->vs_irq < 0 && !sof_event_later) {
3448 dev->isp_sdev.frm_timestamp = ktime_get_ns();
3449 rkisp_isp_queue_event_sof(&dev->isp_sdev);
3450 }
3451 vs_skip:
3452 writel(CIF_ISP_V_START, base + CIF_ISP_ICR);
3453 isp_mis_tmp = readl(base + CIF_ISP_MIS);
3454 if (isp_mis_tmp & CIF_ISP_V_START)
3455 v4l2_err(&dev->v4l2_dev, "isp icr v_statr err: 0x%x\n",
3456 isp_mis_tmp);
3457 }
3458
3459 if ((isp_mis & (CIF_ISP_DATA_LOSS | CIF_ISP_PIC_SIZE_ERROR))) {
3460 if ((isp_mis & CIF_ISP_PIC_SIZE_ERROR)) {
3461 /* Clear pic_size_error */
3462 writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR);
3463 isp_err = readl(base + CIF_ISP_ERR);
3464 v4l2_err(&dev->v4l2_dev,
3465 "CIF_ISP_PIC_SIZE_ERROR (0x%08x)", isp_err);
3466 writel(isp_err, base + CIF_ISP_ERR_CLR);
3467 }
3468
3469 if ((isp_mis & CIF_ISP_DATA_LOSS)) {
3470 /* Clear data_loss */
3471 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
3472 v4l2_err(&dev->v4l2_dev, "CIF_ISP_DATA_LOSS\n");
3473 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
3474 }
3475
3476 if (dev->isp_err_cnt++ > RKISP_CONTI_ERR_MAX) {
3477 if (!(dev->isp_state & ISP_ERROR)) {
3478 rkisp_set_state(&dev->isp_state, ISP_ERROR);
3479 rkisp_clear_bits(dev, CIF_ISP_IMSC,
3480 CIF_ISP_DATA_LOSS |
3481 CIF_ISP_PIC_SIZE_ERROR, true);
3482 writel(CIF_ISP_PIC_SIZE_ERROR, base + CIF_ISP_ICR);
3483 writel(CIF_ISP_DATA_LOSS, base + CIF_ISP_ICR);
3484 if (dev->hw_dev->monitor.is_en) {
3485 rkisp_set_state(&dev->hw_dev->monitor.state, ISP_ERROR);
3486 if (!completion_done(&dev->hw_dev->monitor.cmpl))
3487 complete(&dev->hw_dev->monitor.cmpl);
3488 }
3489 }
3490 }
3491 }
3492
3493 if (isp_mis & ISP2X_LSC_LUT_ERR) {
3494 writel(ISP2X_LSC_LUT_ERR, base + CIF_ISP_ICR);
3495
3496 isp_err = readl(base + CIF_ISP_ERR);
3497 v4l2_err(&dev->v4l2_dev,
3498 "ISP2X_LSC_LUT_ERR. ISP_ERR 0x%x\n", isp_err);
3499 writel(isp_err, base + CIF_ISP_ERR_CLR);
3500 }
3501
3502 /* sampled input frame is complete */
3503 if (isp_mis & CIF_ISP_FRAME_IN) {
3504 rkisp_set_state(&dev->isp_state, ISP_FRAME_IN);
3505 writel(CIF_ISP_FRAME_IN, base + CIF_ISP_ICR);
3506 isp_mis_tmp = readl(base + CIF_ISP_MIS);
3507 if (isp_mis_tmp & CIF_ISP_FRAME_IN)
3508 v4l2_err(&dev->v4l2_dev, "isp icr frame_in err: 0x%x\n",
3509 isp_mis_tmp);
3510
3511 dev->isp_err_cnt = 0;
3512 dev->isp_state &= ~ISP_ERROR;
3513 }
3514
3515 /* frame was completely put out */
3516 if (isp_mis & CIF_ISP_FRAME) {
3517 dev->isp_sdev.dbg.interval =
3518 ktime_get_ns() - dev->isp_sdev.dbg.timestamp;
3519 /* Clear Frame In (ISP) */
3520 rkisp_set_state(&dev->isp_state, ISP_FRAME_END);
3521 writel(CIF_ISP_FRAME, base + CIF_ISP_ICR);
3522 isp_mis_tmp = readl(base + CIF_ISP_MIS);
3523 if (isp_mis_tmp & CIF_ISP_FRAME)
3524 v4l2_err(&dev->v4l2_dev,
3525 "isp icr frame end err: 0x%x\n", isp_mis_tmp);
3526 rkisp_dmarx_get_frame(dev, &dev->isp_sdev.dbg.id, NULL, NULL, true);
3527 rkisp_isp_read_add_fifo_data(dev);
3528 }
3529
3530 if ((isp_mis & (CIF_ISP_FRAME | si3a_isr_mask)) ||
3531 (isp3a_mis & raw3a_isr_mask)) {
3532 u32 irq = isp_mis;
3533
3534 /* FRAME to get EXP and HIST together */
3535 if (isp_mis & CIF_ISP_FRAME)
3536 irq |= ((CIF_ISP_EXP_END |
3537 CIF_ISP_HIST_MEASURE_RDY) &
3538 readl(base + CIF_ISP_RIS));
3539
3540 rkisp_stats_isr(&dev->stats_vdev, irq, isp3a_mis);
3541
3542 if ((isp_mis & CIF_ISP_FRAME) && dev->stats_vdev.rdbk_mode)
3543 rkisp_stats_rdbk_enable(&dev->stats_vdev, false);
3544
3545 if (!IS_HDR_RDBK(dev->hdr.op_mode))
3546 rkisp_config_cmsk(dev);
3547 }
3548
3549 /*
3550 * Then update changed configs. Some of them involve
3551 * lot of register writes. Do those only one per frame.
3552 * Do the updates in the order of the processing flow.
3553 */
3554 rkisp_params_isr(&dev->params_vdev, isp_mis);
3555
3556 /* cur frame end and next frame start irq togeter */
3557 if (dev->vs_irq < 0 && sof_event_later) {
3558 dev->isp_sdev.frm_timestamp = ktime_get_ns();
3559 rkisp_isp_queue_event_sof(&dev->isp_sdev);
3560 }
3561
3562 if (isp_mis & CIF_ISP_FRAME_IN)
3563 rkisp_check_idle(dev, ISP_FRAME_IN);
3564 if (isp_mis & CIF_ISP_FRAME)
3565 rkisp_check_idle(dev, ISP_FRAME_END);
3566 }
3567
rkisp_vs_isr_handler(int irq,void * ctx)3568 irqreturn_t rkisp_vs_isr_handler(int irq, void *ctx)
3569 {
3570 struct device *dev = ctx;
3571 struct rkisp_device *rkisp_dev = dev_get_drvdata(dev);
3572
3573 if (rkisp_dev->vs_irq >= 0)
3574 rkisp_isp_queue_event_sof(&rkisp_dev->isp_sdev);
3575
3576 return IRQ_HANDLED;
3577 }
3578