1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/clk.h>
5 #include <linux/delay.h>
6 #include <linux/pm_runtime.h>
7 #include <linux/slab.h>
8 #include <media/v4l2-common.h>
9 #include <media/v4l2-event.h>
10 #include <media/v4l2-fh.h>
11 #include <media/v4l2-ioctl.h>
12 #include <media/v4l2-mc.h>
13 #include <media/v4l2-subdev.h>
14 #include <media/videobuf2-dma-contig.h>
15 #include <media/videobuf2-dma-sg.h>
16 #include <linux/rkisp1-config.h>
17
18 #include "dev.h"
19 #include "regs.h"
20
set_y_addr(struct rkispp_stream * stream,u32 val)21 static void set_y_addr(struct rkispp_stream *stream, u32 val)
22 {
23 rkispp_write(stream->isppdev, stream->config->reg.cur_y_base, val);
24 }
25
set_uv_addr(struct rkispp_stream * stream,u32 val)26 static void set_uv_addr(struct rkispp_stream *stream, u32 val)
27 {
28 rkispp_write(stream->isppdev, stream->config->reg.cur_uv_base, val);
29 }
30
31
update_mi(struct rkispp_stream * stream)32 static void update_mi(struct rkispp_stream *stream)
33 {
34 struct rkispp_device *dev = stream->isppdev;
35 struct rkispp_dummy_buffer *dummy_buf;
36 u32 val;
37
38 if (stream->curr_buf) {
39 val = stream->curr_buf->buff_addr[RKISPP_PLANE_Y];
40 set_y_addr(stream, val);
41 val = stream->curr_buf->buff_addr[RKISPP_PLANE_UV];
42 set_uv_addr(stream, val);
43 }
44
45 if (stream->type == STREAM_OUTPUT && !stream->curr_buf) {
46 dummy_buf = &dev->hw_dev->dummy_buf;
47 set_y_addr(stream, dummy_buf->dma_addr);
48 set_uv_addr(stream, dummy_buf->dma_addr);
49 }
50
51 v4l2_dbg(2, rkispp_debug, &stream->isppdev->v4l2_dev,
52 "%s stream:%d Y:0x%x UV:0x%x\n",
53 __func__, stream->id,
54 rkispp_read(dev, stream->config->reg.cur_y_base),
55 rkispp_read(dev, stream->config->reg.cur_uv_base));
56 }
57
config_fec(struct rkispp_device * dev)58 static int config_fec(struct rkispp_device *dev)
59 {
60 struct rkispp_stream_vdev *vdev;
61 struct rkispp_stream *stream = NULL;
62 struct rkispp_fec_head *fec_data;
63 struct rkispp_hw_dev *hw = dev->hw_dev;
64 u32 fmt, mult = 1, mesh_size;
65 u32 in_width, in_height;
66 u32 addr_offs, max_w, max_h;
67 u32 addryf, addrxf, addryi, addrxi;
68
69 vdev = &dev->stream_vdev;
70 vdev->fec.is_end = true;
71 if (!(vdev->module_ens & ISPP_MODULE_FEC))
72 return 0;
73
74 if (dev->inp == INP_DDR) {
75 stream = &vdev->stream[STREAM_II];
76 fmt = stream->out_cap_fmt.wr_fmt;
77 } else {
78 fmt = FMT_YUV422;
79 }
80
81 in_width = dev->ispp_sdev.in_fmt.width;
82 in_height = dev->ispp_sdev.in_fmt.height;
83 max_w = hw->max_in.w ? hw->max_in.w : in_width;
84 max_h = hw->max_in.h ? hw->max_in.h : in_height;
85 addr_offs = max_w * max_h;
86 vdev->fec.uv_offset = addr_offs;
87
88 if (stream) {
89 stream->config->frame_end_id = FEC_INT;
90 stream->config->reg.cur_y_base = RKISPP_FEC_RD_Y_BASE;
91 stream->config->reg.cur_uv_base = RKISPP_FEC_RD_UV_BASE;
92 stream->config->reg.cur_y_base_shd = RKISPP_FEC_RD_Y_BASE_SHD;
93 stream->config->reg.cur_uv_base_shd = RKISPP_FEC_RD_UV_BASE_SHD;
94 }
95
96
97 if (fmt & FMT_YUYV)
98 mult = 2;
99 rkispp_set_bits(dev, RKISPP_FEC_CTRL, FMT_RD_MASK, fmt);
100
101 rkispp_write(dev, RKISPP_FEC_RD_VIR_STRIDE, ALIGN(in_width * mult, 16) >> 2);
102 rkispp_write(dev, RKISPP_FEC_SRC_SIZE, in_height << 16 | in_width);
103
104 fec_data = (struct rkispp_fec_head *)dev->params_vdev.buf_fec[0].vaddr;
105 if (fec_data) {
106 rkispp_prepare_buffer(dev, &dev->params_vdev.buf_fec[0]);
107 addrxf =
108 dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshxf_oft;
109 addryf =
110 dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshyf_oft;
111 addrxi =
112 dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshxi_oft;
113 addryi =
114 dev->params_vdev.buf_fec[0].dma_addr + fec_data->meshyi_oft;
115 rkispp_write(dev, RKISPP_FEC_MESH_XFRA_BASE, addrxf);
116 rkispp_write(dev, RKISPP_FEC_MESH_YFRA_BASE, addryf);
117 rkispp_write(dev, RKISPP_FEC_MESH_XINT_BASE, addrxi);
118 rkispp_write(dev, RKISPP_FEC_MESH_YINT_BASE, addryi);
119
120 stream = &vdev->stream[STREAM_MB];
121 if (stream->out_fmt.width > 1920) {
122 mesh_size = cal_fec_mesh(stream->out_fmt.width, stream->out_fmt.height, 1);
123 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x20, SW_MESH_DENSITY);
124 } else {
125 mesh_size = cal_fec_mesh(stream->out_fmt.width, stream->out_fmt.height, 0);
126 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x20, 0);
127 }
128 rkispp_write(dev, RKISPP_FEC_MESH_SIZE, mesh_size);
129 }
130
131 stream = &vdev->stream[STREAM_MB];
132 if (!stream->streaming) {
133 rkispp_write(dev, RKISPP_FEC_WR_Y_BASE, hw->dummy_buf.dma_addr);
134 rkispp_write(dev, RKISPP_FEC_WR_UV_BASE, hw->dummy_buf.dma_addr);
135 }
136
137 if (vdev->monitor.is_en) {
138 init_completion(&vdev->monitor.fec.cmpl);
139 schedule_work(&vdev->monitor.fec.work);
140 }
141 rkispp_set_clk_rate(dev->hw_dev->clks[0], dev->hw_dev->core_clk_max);
142 v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
143 "%s size:%dx%d ctrl:0x%x core_ctrl:0x%x\n",
144 __func__, in_width, in_height,
145 rkispp_read(dev, RKISPP_FEC_CTRL),
146 rkispp_read(dev, RKISPP_FEC_CORE_CTRL));
147 return 0;
148 }
149
fec_free_buf(struct rkispp_device * dev)150 static void fec_free_buf(struct rkispp_device *dev)
151 {
152 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
153 struct list_head *list = &vdev->fec.list_rd;
154 struct rkisp_ispp_buf *dbufs;
155
156 if (vdev->fec.cur_rd)
157 vdev->fec.cur_rd = NULL;
158 while (!list_empty(list)) {
159 dbufs = get_list_buf(list, true);
160 if (dbufs->is_isp)
161 v4l2_subdev_call(dev->ispp_sdev.remote_sd,
162 video, s_rx_buffer, dbufs, NULL);
163 else
164 get_list_buf(list, false);
165 }
166 }
167
config_modules(struct rkispp_device * dev)168 static int config_modules(struct rkispp_device *dev)
169 {
170 int ret;
171
172 v4l2_dbg(1, rkispp_debug, &dev->v4l2_dev,
173 "stream module ens:0x%x\n", dev->stream_vdev.module_ens);
174 dev->stream_vdev.monitor.monitoring_module = 0;
175 dev->stream_vdev.monitor.restart_module = 0;
176 dev->stream_vdev.monitor.is_restart = false;
177 dev->stream_vdev.monitor.retry = 0;
178 init_completion(&dev->stream_vdev.monitor.cmpl);
179
180 ret = config_fec(dev);
181 if (ret < 0)
182 goto free_fec;
183
184 /* config default params */
185 dev->params_vdev.params_ops->rkispp_params_cfg(&dev->params_vdev, 0);
186
187 return 0;
188 free_fec:
189 fec_free_buf(dev);
190 return ret;
191 }
192
fec_work_event(struct rkispp_device * dev,void * buff_rd,bool is_isr,bool is_quick)193 static void fec_work_event(struct rkispp_device *dev,
194 void *buff_rd,
195 bool is_isr, bool is_quick)
196 {
197 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
198 struct rkispp_monitor *monitor = &vdev->monitor;
199 struct list_head *list = &vdev->fec.list_rd;
200 void __iomem *base = dev->hw_dev->base_addr;
201 struct rkispp_stream *stream = &vdev->stream[STREAM_II];
202 unsigned long lock_flags = 0, lock_flags1 = 0;
203 bool is_start = false;
204 struct rkisp_ispp_reg *reg_buf = NULL;
205 struct rkispp_buffer *inbuf;
206 struct v4l2_subdev *sd = NULL;
207 u32 val;
208 struct rkisp_ispp_buf *buf_rd = buff_rd;
209
210 if (!(vdev->module_ens & ISPP_MODULE_FEC))
211 return;
212 if (dev->inp == INP_ISP)
213 sd = dev->ispp_sdev.remote_sd;
214 spin_lock_irqsave(&vdev->fec.buf_lock, lock_flags);
215 /* event from fec frame end */
216 if (!buf_rd && is_isr) {
217 vdev->fec.is_end = true;
218 if (vdev->fec.cur_rd) {
219 if (sd) {
220 v4l2_subdev_call(sd, video, s_rx_buffer, vdev->fec.cur_rd, NULL);
221 } else if (stream->streaming && vdev->fec.cur_rd->priv) {
222 inbuf = vdev->fec.cur_rd->priv;
223 vb2_buffer_done(&inbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);
224 }
225 vdev->fec.cur_rd = NULL;
226 }
227 }
228 spin_lock_irqsave(&monitor->lock, lock_flags1);
229 if (monitor->is_restart && buf_rd) {
230 list_add_tail(&buf_rd->list, list);
231 goto restart_unlock;
232 }
233
234 if (buf_rd && vdev->fec.is_end && list_empty(list)) {
235 /* fec read buf from nr */
236 vdev->fec.cur_rd = buf_rd;
237 } else if (vdev->fec.is_end && !list_empty(list)) {
238 /* fec read buf from list
239 * fec processing slow than nr
240 * new read buf from nr into list
241 */
242 vdev->fec.cur_rd = get_list_buf(list, true);
243 if (buf_rd)
244 list_add_tail(&buf_rd->list, list);
245 } else if (!vdev->fec.is_end && buf_rd) {
246 /* fec no idle
247 * new read buf from nr into list
248 */
249 list_add_tail(&buf_rd->list, list);
250 }
251
252 if (vdev->fec.cur_rd && vdev->fec.is_end) {
253 if (vdev->fec.cur_rd->priv) {
254 inbuf = vdev->fec.cur_rd->priv;
255 val = inbuf->buff_addr[RKISPP_PLANE_Y];
256 rkispp_write(dev, RKISPP_FEC_RD_Y_BASE, val);
257 val = inbuf->buff_addr[RKISPP_PLANE_UV];
258 rkispp_write(dev, RKISPP_FEC_RD_UV_BASE, val);
259 } else {
260 struct rkispp_isp_buf_pool *buf;
261
262 buf = get_pool_buf(dev, vdev->fec.cur_rd);
263 val = buf->dma[GROUP_BUF_PIC];
264 rkispp_write(dev, RKISPP_FEC_RD_Y_BASE, val);
265 val += vdev->fec.uv_offset;
266 rkispp_write(dev, RKISPP_FEC_RD_UV_BASE, val);
267 }
268 is_start = true;
269 }
270
271 if (is_start) {
272 u32 seq = 0;
273 u64 timestamp = 0;
274
275 if (vdev->fec.cur_rd) {
276 seq = vdev->fec.cur_rd->frame_id;
277 timestamp = vdev->fec.cur_rd->frame_timestamp;
278 dev->ispp_sdev.frm_sync_seq = seq;
279 dev->ispp_sdev.frame_timestamp = timestamp;
280 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x00, SW_FEC_EN);
281 }
282
283 stream = &vdev->stream[STREAM_MB];
284 if (stream->streaming && !stream->is_cfg)
285 secure_config_mb(stream);
286
287 if (!dev->hw_dev->is_single)
288 rkispp_update_regs(dev, RKISPP_CTRL, RKISPP_FEC_SRC_SIZE);
289 writel(FEC_FORCE_UPD, base + RKISPP_CTRL_UPDATE);
290
291 v4l2_dbg(3, rkispp_debug, &dev->v4l2_dev,
292 "FEC start seq:%d | Y_SHD rd:0x%x\n",
293 seq, readl(base + RKISPP_FEC_RD_Y_BASE_SHD));
294 v4l2_dbg(2, rkispp_debug, &stream->isppdev->v4l2_dev,
295 "%s stream:%d Y:0x%x UV:0x%x\n",
296 __func__, stream->id,
297 rkispp_read(dev, stream->config->reg.cur_y_base),
298 rkispp_read(dev, stream->config->reg.cur_uv_base));
299 vdev->fec.dbg.id = seq;
300 vdev->fec.dbg.timestamp = ktime_get_ns();
301 if (monitor->is_en) {
302 monitor->fec.time = vdev->fec.dbg.interval / 1000 / 1000;
303 monitor->monitoring_module |= MONITOR_FEC;
304 if (!completion_done(&monitor->fec.cmpl))
305 complete(&monitor->fec.cmpl);
306 }
307
308 if (stream->is_reg_withstream)
309 rkispp_find_regbuf_by_id(dev, ®_buf, dev->dev_id, seq);
310
311 if (!dev->hw_dev->is_shutdown)
312 writel(FEC_ST, base + RKISPP_CTRL_STRT);
313
314 vdev->fec.is_end = false;
315 }
316 restart_unlock:
317 spin_unlock_irqrestore(&monitor->lock, lock_flags1);
318 spin_unlock_irqrestore(&vdev->fec.buf_lock, lock_flags);
319
320 }
321
rkispp_module_work_event(struct rkispp_device * dev,void * buf_rd,void * buf_wr,u32 module,bool is_isr)322 static void rkispp_module_work_event(struct rkispp_device *dev,
323 void *buf_rd, void *buf_wr,
324 u32 module, bool is_isr)
325 {
326
327 if (dev->hw_dev->is_shutdown)
328 return;
329
330 if (dev->ispp_sdev.state != ISPP_STOP)
331 fec_work_event(dev, buf_rd, is_isr, false);
332
333 /* cur frame (tnr->nr->fec) done for next frame
334 * fec start at nr end if fec enable, and fec can async with
335 * tnr different frames for single device.
336 * tnr->nr->fec frame0
337 * |->tnr->nr->fec frame1
338 */
339 if (is_isr && !buf_rd && !buf_wr) {
340 dev->stream_vdev.monitor.retry = 0;
341 rkispp_event_handle(dev, CMD_QUEUE_DMABUF, NULL);
342
343 }
344
345 if (dev->ispp_sdev.state == ISPP_STOP) {
346 if ((module & ISPP_MODULE_FEC) && buf_rd) {
347 struct rkisp_ispp_buf *buf = buf_rd;
348
349 if (buf->is_isp)
350 v4l2_subdev_call(dev->ispp_sdev.remote_sd,
351 video, s_rx_buffer, buf, NULL);
352 }
353 if (!dev->hw_dev->is_idle)
354 dev->hw_dev->is_idle = true;
355 }
356 }
357
rkispp_destroy_buf(struct rkispp_stream * stream)358 static void rkispp_destroy_buf(struct rkispp_stream *stream)
359 {
360 struct rkispp_device *dev = stream->isppdev;
361 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
362
363 if (atomic_read(&vdev->refcnt) == 1) {
364 vdev->irq_ends = 0;
365 fec_free_buf(dev);
366 rkispp_event_handle(dev, CMD_FREE_POOL, NULL);
367 }
368 }
369
start_isp(struct rkispp_device * dev)370 static int start_isp(struct rkispp_device *dev)
371 {
372 struct rkispp_subdev *ispp_sdev = &dev->ispp_sdev;
373 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
374 struct rkispp_stream *stream;
375 struct rkisp_ispp_mode mode;
376 int ret;
377
378 if (dev->inp != INP_ISP || ispp_sdev->state)
379 return 0;
380
381 if (dev->stream_sync) {
382 stream = &vdev->stream[STREAM_MB];
383 if (stream->linked && !stream->streaming)
384 return 0;
385 } else if (atomic_read(&vdev->refcnt) > 1) {
386 return 0;
387 }
388
389 rkispp_start_3a_run(dev);
390
391 mutex_lock(&dev->hw_dev->dev_lock);
392
393 mode.work_mode = ISP_ISPP_422;
394 mode.buf_num = 1;
395 mode.buf_num += RKISP_BUF_MAX + 2 * (dev->hw_dev->dev_num - 1);
396
397 ret = v4l2_subdev_call(ispp_sdev->remote_sd, core, ioctl,
398 RKISP_ISPP_CMD_SET_MODE, &mode);
399 if (ret)
400 goto err;
401
402 ret = config_modules(dev);
403 if (ret) {
404 rkispp_event_handle(dev, CMD_FREE_POOL, NULL);
405 mode.work_mode = ISP_ISPP_INIT_FAIL;
406 v4l2_subdev_call(ispp_sdev->remote_sd, core, ioctl,
407 RKISP_ISPP_CMD_SET_MODE, &mode);
408 goto err;
409 }
410
411 if (dev->hw_dev->is_single)
412 writel(ALL_FORCE_UPD, dev->hw_dev->base_addr + RKISPP_CTRL_UPDATE);
413 stream = &vdev->stream[STREAM_MB];
414 if (stream->streaming)
415 stream->is_upd = true;
416 if (dev->isp_mode & ISP_ISPP_QUICK)
417 rkispp_set_bits(dev, RKISPP_CTRL_QUICK, 0, GLB_QUICK_EN);
418
419 dev->isr_cnt = 0;
420 dev->isr_err_cnt = 0;
421 ret = v4l2_subdev_call(&ispp_sdev->sd, video, s_stream, true);
422 err:
423 mutex_unlock(&dev->hw_dev->dev_lock);
424 return ret;
425 }
426
check_to_force_update(struct rkispp_device * dev,u32 mis_val)427 static void check_to_force_update(struct rkispp_device *dev, u32 mis_val)
428 {
429 struct rkispp_stream_vdev *vdev = &dev->stream_vdev;
430 struct rkispp_stream *stream;
431 u32 mask = FEC_INT;
432
433 vdev->irq_ends |= (mis_val & mask);
434 v4l2_dbg(3, rkispp_debug, &dev->v4l2_dev,
435 "irq_ends:0x%x mask:0x%x\n",
436 vdev->irq_ends, mask);
437 if (vdev->irq_ends != mask)
438 return;
439 vdev->irq_ends = 0;
440 if (mis_val & FEC_INT)
441 rkispp_module_work_event(dev, NULL, NULL,
442 ISPP_MODULE_FEC, true);
443
444 stream = &vdev->stream[STREAM_MB];
445 if (stream->streaming)
446 stream->is_upd = true;
447
448 }
449
450 static struct rkispp_stream_ops rkispp_stream_ops = {
451 .config_modules = config_modules,
452 .destroy_buf = rkispp_destroy_buf,
453 .fec_work_event = fec_work_event,
454 .start_isp = start_isp,
455 .check_to_force_update = check_to_force_update,
456 .update_mi = update_mi,
457 .rkispp_module_work_event = rkispp_module_work_event,
458 };
459
rkispp_stream_init_ops_v20(struct rkispp_stream_vdev * stream_vdev)460 void rkispp_stream_init_ops_v20(struct rkispp_stream_vdev *stream_vdev)
461 {
462 stream_vdev->stream_ops = &rkispp_stream_ops;
463 }
464