1 /*
2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include <linux/phy/phy.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/mfd/syscon.h>
28
29 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
30
31 /*
32 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
33 * is the first address, the other from the bit4 to bit0 is the second address.
34 * when you configure the registers, you must set both of them. The Clock Lane
35 * and Data Lane use the same registers with the same second address, but the
36 * first address is different.
37 */
38 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
39 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
40 #define INNO_PHY_REG(first, second) (FIRST_ADDRESS(first) | \
41 SECOND_ADDRESS(second))
42
43 /* Analog Register Part: reg00 */
44 #define BANDGAP_POWER_MASK BIT(7)
45 #define BANDGAP_POWER_DOWN BIT(7)
46 #define BANDGAP_POWER_ON 0
47 #define LANE_EN_MASK GENMASK(6, 2)
48 #define LANE_EN_CK BIT(6)
49 #define LANE_EN_3 BIT(5)
50 #define LANE_EN_2 BIT(4)
51 #define LANE_EN_1 BIT(3)
52 #define LANE_EN_0 BIT(2)
53 #define POWER_WORK_MASK GENMASK(1, 0)
54 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
55 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
56 /* Analog Register Part: reg01 */
57 #define REG_SYNCRST_MASK BIT(2)
58 #define REG_SYNCRST_RESET BIT(2)
59 #define REG_SYNCRST_NORMAL 0
60 #define REG_LDOPD_MASK BIT(1)
61 #define REG_LDOPD_POWER_DOWN BIT(1)
62 #define REG_LDOPD_POWER_ON 0
63 #define REG_PLLPD_MASK BIT(0)
64 #define REG_PLLPD_POWER_DOWN BIT(0)
65 #define REG_PLLPD_POWER_ON 0
66 /* Analog Register Part: reg03 */
67 #define REG_FBDIV_HI_MASK BIT(5)
68 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
69 #define REG_PREDIV_MASK GENMASK(4, 0)
70 #define REG_PREDIV(x) UPDATE(x, 4, 0)
71 /* Analog Register Part: reg04 */
72 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
73 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
74 /* Analog Register Part: reg05 */
75 #define CLK_LANE_SKEW_PHASE_SET_MASK GENMASK(2, 0)
76 #define CLK_LANE_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
77 /* Analog Register Part: reg06 */
78 #define LDO_OUTPUT_SET_HI_MASK BIT(7)
79 #define LDO_OUTPUT_SET_HI(x) UPDATE(x, 7, 7)
80 #define LANE_3_SKEW_PHASE_SET_MASK GENMASK(6, 4)
81 #define LANE_3_SKEW_PHASE_SET(x) UPDATE(x, 6, 4)
82 #define LDO_OUTPUT_SET_LO_MASK BIT(3)
83 #define LDO_OUTPUT_SET_LO(x) UPDATE(x, 3, 3)
84 #define LANE_2_SKEW_PHASE_SET_MASK GENMASK(2, 0)
85 #define LANE_2_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
86 /* Analog Register Part: reg07 */
87 #define PRE_EMPHASIS_RANGE_SET_HI_MASK BIT(7)
88 #define PRE_EMPHASIS_RANGE_SET_HI(x) UPDATE(x, 7, 7)
89 #define LANE_1_SKEW_PHASE_SET_MASK GENMASK(6, 4)
90 #define LANE_1_SKEW_PHASE_SET(x) UPDATE(x, 6, 4)
91 #define PRE_EMPHASIS_RANGE_SET_LO_MASK BIT(3)
92 #define PRE_EMPHASIS_RANGE_SET_LO(x) UPDATE(x, 3, 3)
93 #define LANE_0_SKEW_PHASE_SET_MASK GENMASK(2, 0)
94 #define LANE_0_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
95 /* Analog Register Part: reg08 */
96 #define PRE_EMPHASIS_ENABLE_MASK BIT(7)
97 #define PRE_EMPHASIS_ENABLE BIT(7)
98 #define PRE_EMPHASIS_DISABLE 0
99 #define PLL_POST_DIV_ENABLE_MASK BIT(5)
100 #define PLL_POST_DIV_ENABLE BIT(5)
101 #define PLL_POST_DIV_DISABLE 0
102 #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
103 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
104 /* Analog Register Part: reg0b */
105 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
106 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
107 #define VOD_MIN_RANGE 0x1
108 #define VOD_MID_RANGE 0x3
109 #define VOD_BIG_RANGE 0x7
110 #define VOD_MAX_RANGE 0xf
111 /* Analog Register Part: reg11 */
112 #define DATA_SAMPLE_PHASE_SET_MASK GENMASK(7, 6)
113 #define DATA_SAMPLE_PHASE_SET(x) UPDATE(x, 7, 6)
114 /* Digital Register Part: reg00 */
115 #define REG_DIG_RSTN_MASK BIT(0)
116 #define REG_DIG_RSTN_NORMAL BIT(0)
117 #define REG_DIG_RSTN_RESET 0
118 /* Digital Register Part: reg01 */
119 #define INV_PIN_TXCLKESC_0_ENABLE_MASK BIT(1)
120 #define INV_PIN_TXCLKESC_0_ENABLE BIT(1)
121 #define INV_PIN_TXCLKESC_0_DISABLE 0
122 #define INV_PIN_TXBYTECLKHS_ENABLE_MASK BIT(0)
123 #define INV_PIN_TXBYTECLKHS_ENABLE BIT(0)
124 #define INV_PIN_TXBYTECLKHS_DISABLE 0
125 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg00 */
126 #define DIFF_SIGNAL_SWAP_ENABLE_MASK BIT(4)
127 #define DIFF_SIGNAL_SWAP_ENABLE BIT(4)
128 #define DIFF_SIGNAL_SWAP_DISABLE 0
129 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
130 #define T_LPX_CNT_MASK GENMASK(5, 0)
131 #define T_LPX_CNT(x) UPDATE(x, 5, 0)
132 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
133 #define T_HS_ZERO_CNT_HI_MASK BIT(7)
134 #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
135 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
136 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
137 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
138 #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
139 #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
140 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
141 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
142 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
143 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
144 #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
145 #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
146 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
147 #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
148 #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
149 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
150 #define LPDT_TX_PPI_SYNC_ENABLE_MASK BIT(2)
151 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
152 #define LPDT_TX_PPI_SYNC_DISABLE 0
153 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
154 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
155 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
156 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
157 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
158 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
159 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
160 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
161 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
162 #define T_CLK_POST_HI_MASK GENMASK(7, 6)
163 #define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
164 #define T_TA_GO_CNT_MASK GENMASK(5, 0)
165 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
166 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
167 #define T_HS_EXIT_CNT_HI_MASK BIT(6)
168 #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
169 #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
170 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
171 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
172 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
173 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
174
175 #define PSEC_PER_NSEC 1000L
176 #define PSECS_PER_SEC 1000000000000LL
177
178 enum inno_video_phy_functions {
179 INNO_PHY_PADCTL_FUNC_MIPI,
180 INNO_PHY_PADCTL_FUNC_LVDS,
181 INNO_PHY_PADCTL_FUNC_TTL,
182 INNO_PHY_PADCTL_FUNC_IDLE,
183 };
184
185 struct mipi_dphy_timing {
186 unsigned int clkmiss;
187 unsigned int clkpost;
188 unsigned int clkpre;
189 unsigned int clkprepare;
190 unsigned int clksettle;
191 unsigned int clktermen;
192 unsigned int clktrail;
193 unsigned int clkzero;
194 unsigned int dtermen;
195 unsigned int eot;
196 unsigned int hsexit;
197 unsigned int hsprepare;
198 unsigned int hszero;
199 unsigned int hssettle;
200 unsigned int hsskip;
201 unsigned int hstrail;
202 unsigned int init;
203 unsigned int lpx;
204 unsigned int taget;
205 unsigned int tago;
206 unsigned int tasure;
207 unsigned int wakeup;
208 };
209
210 struct inno_mipi_dphy_timing {
211 unsigned int max_lane_mbps;
212 u8 lpx;
213 u8 hs_prepare;
214 u8 clk_lane_hs_zero;
215 u8 data_lane_hs_zero;
216 u8 hs_trail;
217 };
218
219 struct inno_mipi_dphy {
220 struct device *dev;
221 struct clk *ref_clk;
222 struct clk *pclk;
223 struct regmap *regmap;
224 struct reset_control *rst;
225 struct regmap *grf;
226
227 unsigned int lanes;
228 unsigned long lane_rate;
229
230 struct {
231 struct clk_hw hw;
232 u8 prediv;
233 u16 fbdiv;
234 } pll;
235 };
236
237 enum {
238 REGISTER_PART_ANALOG,
239 REGISTER_PART_DIGITAL,
240 REGISTER_PART_CLOCK_LANE,
241 REGISTER_PART_DATA0_LANE,
242 REGISTER_PART_DATA1_LANE,
243 REGISTER_PART_DATA2_LANE,
244 REGISTER_PART_DATA3_LANE,
245 };
246
247 static const
248 struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table[] = {
249 { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
250 { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
251 { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
252 { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
253 { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
254 { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
255 { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
256 { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
257 { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
258 { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
259 {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
260 {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
261 {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
262 {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
263 {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
264 {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
265 {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
266 {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
267 {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
268 };
269
hw_to_inno(struct clk_hw * hw)270 static inline struct inno_mipi_dphy *hw_to_inno(struct clk_hw *hw)
271 {
272 return container_of(hw, struct inno_mipi_dphy, pll.hw);
273 }
274
inno_update_bits(struct inno_mipi_dphy * inno,u8 first,u8 second,u8 mask,u8 val)275 static void inno_update_bits(struct inno_mipi_dphy *inno, u8 first, u8 second,
276 u8 mask, u8 val)
277 {
278 u32 reg = INNO_PHY_REG(first, second) << 2;
279
280 regmap_update_bits(inno->regmap, reg, mask, val);
281 }
282
inno_mipi_dphy_reset(struct inno_mipi_dphy * inno)283 static void inno_mipi_dphy_reset(struct inno_mipi_dphy *inno)
284 {
285 /* Reset analog */
286 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
287 REG_SYNCRST_MASK, REG_SYNCRST_RESET);
288 udelay(1);
289 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
290 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
291 /* Reset digital */
292 inno_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
293 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
294 udelay(1);
295 inno_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
296 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
297 }
298
inno_mipi_dphy_power_work_enable(struct inno_mipi_dphy * inno)299 static void inno_mipi_dphy_power_work_enable(struct inno_mipi_dphy *inno)
300 {
301 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
302 POWER_WORK_MASK, POWER_WORK_ENABLE);
303 }
304
inno_mipi_dphy_power_work_disable(struct inno_mipi_dphy * inno)305 static void inno_mipi_dphy_power_work_disable(struct inno_mipi_dphy *inno)
306 {
307 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
308 POWER_WORK_MASK, POWER_WORK_DISABLE);
309 }
310
inno_mipi_dphy_bandgap_power_enable(struct inno_mipi_dphy * inno)311 static void inno_mipi_dphy_bandgap_power_enable(struct inno_mipi_dphy *inno)
312 {
313 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
314 BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
315 }
316
inno_mipi_dphy_bandgap_power_disable(struct inno_mipi_dphy * inno)317 static void inno_mipi_dphy_bandgap_power_disable(struct inno_mipi_dphy *inno)
318 {
319 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
320 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
321 }
322
inno_mipi_dphy_lane_enable(struct inno_mipi_dphy * inno)323 static void inno_mipi_dphy_lane_enable(struct inno_mipi_dphy *inno)
324 {
325 u8 val = LANE_EN_CK;
326
327 switch (inno->lanes) {
328 case 1:
329 val |= LANE_EN_0;
330 break;
331 case 2:
332 val |= LANE_EN_1 | LANE_EN_0;
333 break;
334 case 3:
335 val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
336 break;
337 case 4:
338 default:
339 val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
340 break;
341 }
342
343 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
344 }
345
inno_mipi_dphy_lane_disable(struct inno_mipi_dphy * inno)346 static void inno_mipi_dphy_lane_disable(struct inno_mipi_dphy *inno)
347 {
348 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
349 }
350
inno_mipi_dphy_pll_enable(struct inno_mipi_dphy * inno)351 static void inno_mipi_dphy_pll_enable(struct inno_mipi_dphy *inno)
352 {
353 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
354 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
355 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
356 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
357 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
358 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
359 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
360 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
361 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
362 CLOCK_LANE_VOD_RANGE_SET_MASK,
363 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
364 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
365 REG_LDOPD_MASK | REG_PLLPD_MASK,
366 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
367 }
368
inno_mipi_dphy_pll_disable(struct inno_mipi_dphy * inno)369 static void inno_mipi_dphy_pll_disable(struct inno_mipi_dphy *inno)
370 {
371 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
372 REG_LDOPD_MASK | REG_PLLPD_MASK,
373 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
374 }
375
mipi_dphy_timing_get_default(struct mipi_dphy_timing * timing,unsigned long period)376 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
377 unsigned long period)
378 {
379 /* Global Operation Timing Parameters */
380 timing->clkmiss = 0;
381 /*
382 * The D-PHY spec define the clk post min time is 60ns + 52UI and
383 * no define max time, so we set 200 + 52UI leave move margin.
384 */
385 timing->clkpost = 200 + 52 * period / PSEC_PER_NSEC;
386 timing->clkpre = 8 * period / PSEC_PER_NSEC;
387 timing->clkprepare = 65;
388 timing->clksettle = 95;
389 timing->clktermen = 0;
390 timing->clktrail = 80;
391 timing->clkzero = 260;
392 timing->dtermen = 0;
393 timing->eot = 0;
394 timing->hsexit = 120;
395 timing->hsprepare = 65 + 4 * period / PSEC_PER_NSEC;
396 timing->hszero = 145 + 6 * period / PSEC_PER_NSEC;
397 timing->hssettle = 85 + 6 * period / PSEC_PER_NSEC;
398 timing->hsskip = 40;
399 timing->hstrail = max(8 * period / PSEC_PER_NSEC,
400 60 + 4 * period / PSEC_PER_NSEC);
401 timing->init = 100000;
402 timing->lpx = 60;
403 timing->taget = 5 * timing->lpx;
404 timing->tago = 4 * timing->lpx;
405 timing->tasure = 2 * timing->lpx;
406 timing->wakeup = 1000000;
407 }
408
409 static const struct inno_mipi_dphy_timing *
inno_mipi_dphy_get_timing(struct inno_mipi_dphy * inno)410 inno_mipi_dphy_get_timing(struct inno_mipi_dphy *inno)
411 {
412 const struct inno_mipi_dphy_timing *timings;
413 unsigned int num_timings;
414 unsigned int lane_mbps = inno->lane_rate / USEC_PER_SEC;
415 unsigned int i;
416
417 timings = inno_mipi_dphy_timing_table;
418 num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table);
419
420 for (i = 0; i < num_timings; i++)
421 if (lane_mbps <= timings[i].max_lane_mbps)
422 break;
423
424 if (i == num_timings)
425 --i;
426
427 return &timings[i];
428 }
429
inno_mipi_dphy_timing_init(struct inno_mipi_dphy * inno)430 static void inno_mipi_dphy_timing_init(struct inno_mipi_dphy *inno)
431 {
432 struct mipi_dphy_timing gotp;
433 const struct inno_mipi_dphy_timing *timing;
434 unsigned long txbyteclk, txclkesc, ui, sys_clk;
435 unsigned int esc_clk_div;
436 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
437 u32 hs_prepare, hs_trail, hs_zero;
438 unsigned int i;
439
440 memset(&gotp, 0, sizeof(gotp));
441
442 txbyteclk = inno->lane_rate / 8;
443 sys_clk = clk_get_rate(inno->pclk);
444 esc_clk_div = DIV_ROUND_UP(txbyteclk, 20000000);
445 txclkesc = txbyteclk / esc_clk_div;
446 ui = DIV_ROUND_CLOSEST_ULL(PSECS_PER_SEC, inno->lane_rate);
447
448 dev_dbg(inno->dev, "txbyteclk=%ld, ui=%ld, sys_clk=%ld\n",
449 txbyteclk, ui, sys_clk);
450
451 mipi_dphy_timing_get_default(&gotp, ui);
452 timing = inno_mipi_dphy_get_timing(inno);
453
454 hs_exit = DIV_ROUND_UP(gotp.hsexit * txbyteclk, NSEC_PER_SEC);
455 clk_post = DIV_ROUND_UP(gotp.clkpost * txbyteclk, NSEC_PER_SEC);
456 clk_pre = DIV_ROUND_UP(gotp.clkpre * txbyteclk, NSEC_PER_SEC);
457
458 wakeup = DIV_ROUND_UP(gotp.wakeup * sys_clk, NSEC_PER_SEC);
459 if (wakeup > 0x3ff)
460 wakeup = 0x3ff;
461
462 ta_go = DIV_ROUND_UP(gotp.tago * txclkesc, NSEC_PER_SEC);
463 ta_sure = DIV_ROUND_UP(gotp.tasure * txclkesc, NSEC_PER_SEC);
464 ta_wait = DIV_ROUND_UP(gotp.taget * txclkesc, NSEC_PER_SEC);
465
466 lpx = timing->lpx;
467 hs_prepare = timing->hs_prepare;
468 hs_trail = timing->hs_trail;
469
470 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
471 if (i == REGISTER_PART_CLOCK_LANE)
472 hs_zero = timing->clk_lane_hs_zero;
473 else
474 hs_zero = timing->data_lane_hs_zero;
475
476 dev_dbg(inno->dev, "lpx=%x\n", lpx);
477 dev_dbg(inno->dev,
478 "hs_trail=%x, hs_exit=%x, hs_prepare=%x, hs_zero=%x\n",
479 hs_trail, hs_exit, hs_prepare, hs_zero);
480 dev_dbg(inno->dev, "clk_pre=%x, clk_post=%x\n",
481 clk_pre, clk_post);
482 dev_dbg(inno->dev, "ta_go=%x, ta_sure=%x, ta_wait=%x\n",
483 ta_go, ta_sure, ta_wait);
484
485 inno_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
486 T_LPX_CNT(lpx));
487 inno_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
488 T_HS_PREPARE_CNT(hs_prepare));
489 inno_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
490 T_HS_ZERO_CNT_HI(hs_zero >> 6));
491 inno_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
492 T_HS_ZERO_CNT_LO(hs_zero));
493 inno_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
494 T_HS_TRAIL_CNT(hs_trail));
495 inno_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
496 T_HS_EXIT_CNT_HI(hs_exit >> 5));
497 inno_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
498 T_HS_EXIT_CNT_LO(hs_exit));
499 inno_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
500 T_CLK_POST_HI(clk_post >> 4));
501 inno_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
502 T_CLK_POST_CNT_LO(clk_post));
503 inno_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
504 T_CLK_PRE_CNT(clk_pre));
505 inno_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
506 T_WAKEUP_CNT_HI(wakeup >> 8));
507 inno_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
508 T_WAKEUP_CNT_LO(wakeup));
509 inno_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
510 T_TA_GO_CNT(ta_go));
511 inno_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
512 T_TA_SURE_CNT(ta_sure));
513 inno_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
514 T_TA_WAIT_CNT(ta_wait));
515 }
516 }
517
inno_mipi_dphy_pll_round_rate(struct inno_mipi_dphy * inno,unsigned long prate,unsigned long rate,u8 * prediv,u16 * fbdiv)518 static unsigned long inno_mipi_dphy_pll_round_rate(struct inno_mipi_dphy *inno,
519 unsigned long prate,
520 unsigned long rate,
521 u8 *prediv, u16 *fbdiv)
522 {
523 const struct inno_mipi_dphy_timing *timings;
524 unsigned int num_timings;
525 unsigned long best_freq = 0;
526 unsigned int fin, fout, max_fout;
527 u8 min_prediv, max_prediv;
528 u8 _prediv, best_prediv = 1;
529 u16 _fbdiv, best_fbdiv = 1;
530 u32 min_delta = UINT_MAX;
531
532 timings = inno_mipi_dphy_timing_table;
533 num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table);
534
535 /*
536 * The PLL output frequency can be calculated using a simple formula:
537 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
538 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
539 */
540 fin = prate / USEC_PER_SEC;
541 fout = 2 * (rate / USEC_PER_SEC);
542 max_fout = 2 * timings[num_timings - 1].max_lane_mbps;
543 if (fout > max_fout)
544 fout = max_fout;
545
546 /* constraint: 5Mhz < Fref / prediv < 40MHz */
547 min_prediv = DIV_ROUND_UP(fin, 40);
548 max_prediv = fin / 5;
549
550 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
551 u32 delta, tmp;
552
553 _fbdiv = fout * _prediv / fin;
554 /*
555 * The all possible settings of feedback divider are
556 * 12, 13, 14, 16, ~ 511
557 */
558 if ((_fbdiv == 15) || (_fbdiv < 12) || (_fbdiv > 511))
559 continue;
560
561 tmp = _fbdiv * fin / _prediv;
562 delta = abs(fout - tmp);
563 if (delta < min_delta) {
564 best_prediv = _prediv;
565 best_fbdiv = _fbdiv;
566 min_delta = delta;
567 best_freq = tmp * USEC_PER_SEC;
568 }
569 }
570
571 if (best_freq) {
572 *prediv = best_prediv;
573 *fbdiv = best_fbdiv;
574 }
575
576 return best_freq / 2;
577 }
578
inno_mipi_dphy_power_on(struct phy * phy)579 static int inno_mipi_dphy_power_on(struct phy *phy)
580 {
581 struct inno_mipi_dphy *inno = phy_get_drvdata(phy);
582
583 clk_prepare_enable(inno->pclk);
584 pm_runtime_get_sync(inno->dev);
585 inno_mipi_dphy_bandgap_power_enable(inno);
586 inno_mipi_dphy_power_work_enable(inno);
587 inno_mipi_dphy_pll_enable(inno);
588 inno_mipi_dphy_lane_enable(inno);
589 inno_mipi_dphy_reset(inno);
590 inno_mipi_dphy_timing_init(inno);
591 udelay(1);
592
593 return 0;
594 }
595
inno_mipi_dphy_power_off(struct phy * phy)596 static int inno_mipi_dphy_power_off(struct phy *phy)
597 {
598 struct inno_mipi_dphy *inno = phy_get_drvdata(phy);
599
600 inno_mipi_dphy_lane_disable(inno);
601 inno_mipi_dphy_pll_disable(inno);
602 inno_mipi_dphy_power_work_disable(inno);
603 inno_mipi_dphy_bandgap_power_disable(inno);
604 pm_runtime_put(inno->dev);
605 clk_disable_unprepare(inno->pclk);
606
607 return 0;
608 }
609
610 static const struct phy_ops inno_mipi_dphy_ops = {
611 .power_on = inno_mipi_dphy_power_on,
612 .power_off = inno_mipi_dphy_power_off,
613 .owner = THIS_MODULE,
614 };
615
inno_mipi_dphy_pll_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)616 static long inno_mipi_dphy_pll_clk_round_rate(struct clk_hw *hw,
617 unsigned long rate,
618 unsigned long *prate)
619 {
620 struct inno_mipi_dphy *inno = hw_to_inno(hw);
621 unsigned long fin = *prate;
622 unsigned long fout;
623 u16 fbdiv = 1;
624 u8 prediv = 1;
625
626 fout = inno_mipi_dphy_pll_round_rate(inno, fin, rate,
627 &prediv, &fbdiv);
628
629 dev_dbg(inno->dev, "%s: fin=%lu, req_rate=%lu\n",
630 __func__, *prate, rate);
631 dev_dbg(inno->dev, "%s: fout=%lu, prediv=%u, fbdiv=%u\n",
632 __func__, fout, prediv, fbdiv);
633
634 inno->pll.prediv = prediv;
635 inno->pll.fbdiv = fbdiv;
636
637 return fout;
638 }
639
inno_mipi_dphy_pll_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)640 static int inno_mipi_dphy_pll_clk_set_rate(struct clk_hw *hw,
641 unsigned long rate,
642 unsigned long parent_rate)
643 {
644 struct inno_mipi_dphy *inno = hw_to_inno(hw);
645
646 dev_dbg(inno->dev, "%s: rate: %lu Hz\n", __func__, rate);
647
648 inno->lane_rate = rate;
649
650 return 0;
651 }
652
653 static unsigned long
inno_mipi_dphy_pll_clk_recalc_rate(struct clk_hw * hw,unsigned long prate)654 inno_mipi_dphy_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
655 {
656 struct inno_mipi_dphy *inno = hw_to_inno(hw);
657
658 dev_dbg(inno->dev, "%s: rate: %lu Hz\n", __func__, inno->lane_rate);
659
660 return inno->lane_rate;
661 }
662
663 static const struct clk_ops inno_mipi_dphy_pll_clk_ops = {
664 .round_rate = inno_mipi_dphy_pll_clk_round_rate,
665 .set_rate = inno_mipi_dphy_pll_clk_set_rate,
666 .recalc_rate = inno_mipi_dphy_pll_clk_recalc_rate,
667 };
668
inno_mipi_dphy_pll_register(struct inno_mipi_dphy * inno)669 static int inno_mipi_dphy_pll_register(struct inno_mipi_dphy *inno)
670 {
671 struct device *dev = inno->dev;
672 struct device_node *np = dev->of_node;
673 struct clk *clk;
674 const char *parent_name;
675 struct clk_init_data init = {};
676 int ret;
677
678 parent_name = __clk_get_name(inno->ref_clk);
679
680 ret = of_property_read_string(np, "clock-output-names", &init.name);
681 if (ret < 0) {
682 dev_err(dev, "Missing clock-output-names property: %d\n", ret);
683 return ret;
684 }
685
686 init.ops = &inno_mipi_dphy_pll_clk_ops;
687 init.parent_names = (const char * const *)&parent_name;
688 init.num_parents = 1;
689 init.flags = 0;
690
691 inno->pll.hw.init = &init;
692 clk = devm_clk_register(dev, &inno->pll.hw);
693 if (IS_ERR(clk)) {
694 ret = PTR_ERR(clk);
695 dev_err(dev, "failed to register PLL: %d\n", ret);
696 return ret;
697 }
698
699 return of_clk_add_provider(np, of_clk_src_simple_get, clk);
700 }
701
inno_mipi_dphy_pll_unregister(struct inno_mipi_dphy * inno)702 static void inno_mipi_dphy_pll_unregister(struct inno_mipi_dphy *inno)
703 {
704 of_clk_del_provider(inno->dev->of_node);
705 }
706
inno_mipi_dphy_parse_dt(struct inno_mipi_dphy * inno)707 static int inno_mipi_dphy_parse_dt(struct inno_mipi_dphy *inno)
708 {
709 struct device *dev = inno->dev;
710
711 if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes))
712 inno->lanes = 4;
713
714 return 0;
715 }
716
717 static const struct regmap_config inno_mipi_dphy_regmap_config = {
718 .reg_bits = 32,
719 .val_bits = 32,
720 .reg_stride = 4,
721 .max_register = 0x3ac,
722 };
723
inno_mipi_dphy_probe(struct platform_device * pdev)724 static int inno_mipi_dphy_probe(struct platform_device *pdev)
725 {
726 struct device *dev = &pdev->dev;
727 struct inno_mipi_dphy *inno;
728 struct phy_provider *phy_provider;
729 struct phy *phy;
730 struct resource *res;
731 void __iomem *regs;
732 int ret;
733
734 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
735 if (!inno)
736 return -ENOMEM;
737
738 inno->dev = dev;
739 platform_set_drvdata(pdev, inno);
740
741 ret = inno_mipi_dphy_parse_dt(inno);
742 if (ret) {
743 dev_err(dev, "failed to parse DT\n");
744 return ret;
745 }
746
747 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
748 regs = devm_ioremap_resource(dev, res);
749 if (IS_ERR(regs))
750 return PTR_ERR(regs);
751
752 inno->regmap = devm_regmap_init_mmio(dev, regs,
753 &inno_mipi_dphy_regmap_config);
754 if (IS_ERR(inno->regmap)) {
755 ret = PTR_ERR(inno->regmap);
756 dev_err(dev, "failed to init regmap: %d\n", ret);
757 return ret;
758 }
759
760 inno->ref_clk = devm_clk_get(dev, "ref");
761 if (IS_ERR(inno->ref_clk)) {
762 dev_err(dev, "failed to get reference clock\n");
763 return PTR_ERR(inno->ref_clk);
764 }
765
766 inno->pclk = devm_clk_get(dev, "pclk");
767 if (IS_ERR(inno->pclk)) {
768 dev_err(dev, "failed to get pclk\n");
769 return PTR_ERR(inno->pclk);
770 }
771
772 inno->rst = devm_reset_control_get(dev, "apb");
773 if (IS_ERR(inno->rst)) {
774 dev_err(dev, "failed to get system reset control\n");
775 return PTR_ERR(inno->rst);
776 }
777
778 inno->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
779 "rockchip,grf");
780 if (IS_ERR(inno->grf)) {
781 dev_err(dev, "failed to get grf regmap\n");
782 return PTR_ERR(inno->grf);
783 }
784
785 phy = devm_phy_create(dev, NULL, &inno_mipi_dphy_ops);
786 if (IS_ERR(phy)) {
787 dev_err(dev, "failed to create MIPI D-PHY\n");
788 return PTR_ERR(phy);
789 }
790
791 phy_set_drvdata(phy, inno);
792
793 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
794 if (IS_ERR(phy_provider)) {
795 dev_err(dev, "failed to register phy provider\n");
796 return PTR_ERR(phy_provider);
797 }
798
799 ret = inno_mipi_dphy_pll_register(inno);
800 if (ret)
801 return ret;
802
803 pm_runtime_enable(dev);
804
805 return 0;
806 }
807
inno_mipi_dphy_remove(struct platform_device * pdev)808 static int inno_mipi_dphy_remove(struct platform_device *pdev)
809 {
810 struct inno_mipi_dphy *inno = platform_get_drvdata(pdev);
811
812 inno_mipi_dphy_pll_unregister(inno);
813 pm_runtime_disable(inno->dev);
814
815 return 0;
816 }
817
818 static const struct of_device_id inno_mipi_dphy_of_match[] = {
819 { .compatible = "rockchip,rk1808-mipi-dphy", },
820 { .compatible = "rockchip,rk3568-mipi-dphy", },
821 { .compatible = "rockchip,rv1126-mipi-dphy", },
822 {}
823 };
824 MODULE_DEVICE_TABLE(of, inno_mipi_dphy_of_match);
825
826 static struct platform_driver inno_mipi_dphy_driver = {
827 .driver = {
828 .name = "inno-mipi-dphy",
829 .of_match_table = of_match_ptr(inno_mipi_dphy_of_match),
830 },
831 .probe = inno_mipi_dphy_probe,
832 .remove = inno_mipi_dphy_remove,
833 };
834
835 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
inno_mipi_dphy_driver_init(void)836 static int __init inno_mipi_dphy_driver_init(void)
837 {
838 return platform_driver_register(&inno_mipi_dphy_driver);
839 }
840 fs_initcall(inno_mipi_dphy_driver_init);
841
inno_mipi_dphy_driver_exit(void)842 static void __exit inno_mipi_dphy_driver_exit(void)
843 {
844 platform_driver_unregister(&inno_mipi_dphy_driver);
845 }
846 module_exit(inno_mipi_dphy_driver_exit);
847 #else
848 module_platform_driver(inno_mipi_dphy_driver);
849 #endif
850
851 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
852 MODULE_DESCRIPTION("Innosilicon MIPI D-PHY Driver");
853 MODULE_LICENSE("GPL v2");
854