1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip PCIE3.0 phy driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/pcie.h>
17 #include <linux/phy/phy.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 #include <dt-bindings/phy/phy-snps-pcie3.h>
21
22 /* Register for RK3568 */
23 #define GRF_PCIE30PHY_CON1 0x4
24 #define GRF_PCIE30PHY_CON6 0x18
25 #define GRF_PCIE30PHY_CON9 0x24
26 #define GRF_PCIE30PHY_STATUS0 0x80
27 #define SRAM_INIT_DONE(reg) (reg & BIT(14))
28
29 /* Register for RK3588 */
30 #define PHP_GRF_PCIESEL_CON 0x100
31 #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
32 #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
33 #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
34 #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
35
36 struct rockchip_p3phy_ops;
37
38 struct rockchip_p3phy_priv {
39 const struct rockchip_p3phy_ops *ops;
40 void __iomem *mmio;
41 /* mode: RC, EP */
42 int mode;
43 /* pcie30_phymode: Aggregation, Bifurcation */
44 int pcie30_phymode;
45 struct regmap *phy_grf;
46 struct regmap *pipe_grf;
47 struct reset_control *p30phy;
48 struct phy *phy;
49 struct clk_bulk_data *clks;
50 int num_clks;
51 bool is_bifurcation;
52 };
53
54 struct rockchip_p3phy_ops {
55 int (*phy_init)(struct rockchip_p3phy_priv *priv);
56 };
57
rockchip_p3phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)58 static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
59 {
60 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
61
62 /* Acutally We don't care EP/RC mode, but just record it */
63 switch (submode) {
64 case PHY_MODE_PCIE_RC:
65 priv->mode = PHY_MODE_PCIE_RC;
66 break;
67 case PHY_MODE_PCIE_EP:
68 priv->mode = PHY_MODE_PCIE_EP;
69 break;
70 case PHY_MODE_PCIE_BIFURCATION:
71 priv->is_bifurcation = true;
72 break;
73 default:
74 pr_info("%s, invalid mode\n", __func__);
75 return -EINVAL;
76 }
77
78 return 0;
79 }
80
rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv * priv)81 static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
82 {
83 int ret = 0;
84 u32 reg;
85
86 /* Deassert PCIe PMA output clamp mode */
87 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
88 (0x1 << 15) | (0x1 << 31));
89 /* Set bifurcation if needed, and it doesn't care RC/EP */
90 if (priv->is_bifurcation) {
91 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
92 0x1 | (0xf << 16));
93 regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
94 (0x1 << 15) | (0x1 << 31));
95 }
96
97 reset_control_deassert(priv->p30phy);
98
99 ret = regmap_read_poll_timeout(priv->phy_grf,
100 GRF_PCIE30PHY_STATUS0,
101 reg, SRAM_INIT_DONE(reg),
102 0, 500);
103 if (ret)
104 pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
105 __func__, reg);
106 return ret;
107 }
108
109 static const struct rockchip_p3phy_ops rk3568_ops = {
110 .phy_init = rockchip_p3phy_rk3568_init,
111 };
112
rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv * priv)113 static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
114 {
115 int ret = 0;
116 u32 reg;
117
118 /* Deassert PCIe PMA output clamp mode */
119 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
120 (0x1 << 8) | (0x1 << 24));
121
122 reset_control_deassert(priv->p30phy);
123
124 ret = regmap_read_poll_timeout(priv->phy_grf,
125 RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
126 reg, RK3588_SRAM_INIT_DONE(reg),
127 0, 500);
128 ret |= regmap_read_poll_timeout(priv->phy_grf,
129 RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
130 reg, RK3588_SRAM_INIT_DONE(reg),
131 0, 500);
132 if (ret)
133 pr_err("%s: lock failed 0x%x, check input refclk and power supply\n",
134 __func__, reg);
135 return ret;
136 }
137
138 static const struct rockchip_p3phy_ops rk3588_ops = {
139 .phy_init = rockchip_p3phy_rk3588_init,
140 };
141
rochchip_p3phy_init(struct phy * phy)142 static int rochchip_p3phy_init(struct phy *phy)
143 {
144 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
145 int ret;
146
147 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
148 if (ret) {
149 pr_err("failed to enable PCIe bulk clks %d\n", ret);
150 return ret;
151 }
152
153 reset_control_assert(priv->p30phy);
154 udelay(1);
155
156 if (priv->ops->phy_init) {
157 ret = priv->ops->phy_init(priv);
158 if (ret)
159 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
160 };
161
162 return ret;
163 }
164
rochchip_p3phy_exit(struct phy * phy)165 static int rochchip_p3phy_exit(struct phy *phy)
166 {
167 struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
168 clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
169 reset_control_assert(priv->p30phy);
170 return 0;
171 }
172
173 static const struct phy_ops rochchip_p3phy_ops = {
174 .init = rochchip_p3phy_init,
175 .exit = rochchip_p3phy_exit,
176 .set_mode = rockchip_p3phy_set_mode,
177 .owner = THIS_MODULE,
178 };
179
rockchip_p3phy_probe(struct platform_device * pdev)180 static int rockchip_p3phy_probe(struct platform_device *pdev)
181 {
182 struct phy_provider *phy_provider;
183 struct device *dev = &pdev->dev;
184 struct rockchip_p3phy_priv *priv;
185 struct device_node *np = dev->of_node;
186 struct resource *res;
187 int ret;
188 u32 val, reg;
189
190 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
191 if (!priv)
192 return -ENOMEM;
193
194 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
195 priv->mmio = devm_ioremap_resource(dev, res);
196 if (IS_ERR(priv->mmio)) {
197 ret = PTR_ERR(priv->mmio);
198 return ret;
199 }
200
201 priv->ops = of_device_get_match_data(&pdev->dev);
202 if (!priv->ops) {
203 dev_err(&pdev->dev, "no of match data provided\n");
204 return -EINVAL;
205 }
206
207 priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
208 if (IS_ERR(priv->phy_grf)) {
209 dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
210 return PTR_ERR(priv->phy_grf);
211 }
212
213 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
214 "rockchip,pipe-grf");
215 if (IS_ERR(priv->pipe_grf))
216 dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
217
218 ret = device_property_read_u32(dev, "rockchip,pcie30-phymode", &val);
219 if (!ret)
220 priv->pcie30_phymode = val;
221 else
222 priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
223
224 /* Select correct pcie30_phymode */
225 if (priv->pcie30_phymode > 4)
226 priv->pcie30_phymode = PHY_MODE_PCIE_AGGREGATION;
227
228 regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
229 (0x7<<16) | priv->pcie30_phymode);
230
231 /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
232 if (!IS_ERR(priv->pipe_grf)) {
233 reg = priv->pcie30_phymode & 3;
234 if (reg)
235 regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
236 (reg << 16) | reg);
237 };
238
239 priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
240 if (IS_ERR(priv->phy)) {
241 dev_err(dev, "failed to create combphy\n");
242 return PTR_ERR(priv->phy);
243 }
244
245 priv->p30phy = devm_reset_control_get(dev, "phy");
246 if (IS_ERR(priv->p30phy)) {
247 dev_warn(dev, "no phy reset control specified\n");
248 priv->p30phy = NULL;
249 }
250
251 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
252 if (priv->num_clks < 1)
253 return -ENODEV;
254
255 dev_set_drvdata(dev, priv);
256 phy_set_drvdata(priv->phy, priv);
257 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
258 return PTR_ERR_OR_ZERO(phy_provider);
259 }
260
261 static const struct of_device_id rockchip_p3phy_of_match[] = {
262 { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
263 { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
264 { },
265 };
266 MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
267
268 static struct platform_driver rockchip_p3phy_driver = {
269 .probe = rockchip_p3phy_probe,
270 .driver = {
271 .name = "rockchip-snps-pcie3-phy",
272 .of_match_table = rockchip_p3phy_of_match,
273 },
274 };
275 module_platform_driver(rockchip_p3phy_driver);
276 MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
277 MODULE_LICENSE("GPL v2");
278