1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RGA_DRIVER_H_ 3 #define _RGA_DRIVER_H_ 4 5 #include <linux/mutex.h> 6 #include <linux/scatterlist.h> 7 #include <linux/dma-buf.h> 8 9 10 #define RGA_BLIT_SYNC 0x5017 11 #define RGA_BLIT_ASYNC 0x5018 12 #define RGA_FLUSH 0x5019 13 #define RGA_GET_RESULT 0x501a 14 #define RGA_GET_VERSION 0x501b 15 #define RGA_CACHE_FLUSH 0x501c 16 17 #define RGA2_BLIT_SYNC 0x6017 18 #define RGA2_BLIT_ASYNC 0x6018 19 #define RGA2_FLUSH 0x6019 20 #define RGA2_GET_RESULT 0x601a 21 #define RGA2_GET_VERSION 0x601b 22 23 24 #define RGA2_REG_CTRL_LEN 0x8 /* 8 */ 25 #define RGA2_REG_CMD_LEN 0x20 /* 32 */ 26 #define RGA2_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 27 28 #define RGA2_OUT_OF_RESOURCES -10 29 #define RGA2_MALLOC_ERROR -11 30 31 #define SCALE_DOWN_LARGE 1 32 33 #define rgaIS_ERROR(status) (status < 0) 34 #define rgaNO_ERROR(status) (status >= 0) 35 #define rgaIS_SUCCESS(status) (status == 0) 36 37 #define RGA_BUF_GEM_TYPE_MASK 0xC0 38 #define RGA_BUF_GEM_TYPE_DMA 0x80 39 #define RGA2_MAJOR_VERSION_MASK (0xFF000000) 40 #define RGA2_MINOR_VERSION_MASK (0x00F00000) 41 #define RGA2_SVN_VERSION_MASK (0x000FFFFF) 42 43 /* RGA2 process mode enum */ 44 enum 45 { 46 bitblt_mode = 0x0, 47 color_palette_mode = 0x1, 48 color_fill_mode = 0x2, 49 update_palette_table_mode = 0x3, 50 update_patten_buff_mode = 0x4, 51 }; /*render mode*/ 52 53 enum 54 { 55 A_B_B =0x0, 56 A_B_C =0x1, 57 }; //bitblt_mode select 58 59 enum 60 { 61 rop_enable_mask = 0x2, 62 dither_enable_mask = 0x8, 63 fading_enable_mask = 0x10, 64 PD_enbale_mask = 0x20, 65 }; 66 67 68 69 /* 70 // Alpha Red Green Blue 71 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 72 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 73 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 74 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 75 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 76 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 77 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 78 { 2, 16, {{ 0, 0, 5, 0 11, 5, 16,11}}, GGL_BGR }, // RK_FORMAT_BGR_565 79 { 2, 16, {{ 1, 0, 6, 1, 11, 6, 16,11}}, GGL_BGRA }, // RK_FORMAT_BGRA_5551 80 { 2, 16, {{ 4, 0, 8, 4, 12, 8, 16,12}}, GGL_BGRA }, // RK_FORMAT_BGRA_4444 81 82 */ 83 enum 84 { 85 RGA2_FORMAT_RGBA_8888 = 0x0, 86 RGA2_FORMAT_RGBX_8888 = 0x1, 87 RGA2_FORMAT_RGB_888 = 0x2, 88 RGA2_FORMAT_BGRA_8888 = 0x3, 89 RGA2_FORMAT_BGRX_8888 = 0x4, 90 RGA2_FORMAT_BGR_888 = 0x5, 91 RGA2_FORMAT_RGB_565 = 0x6, 92 RGA2_FORMAT_RGBA_5551 = 0x7, 93 RGA2_FORMAT_RGBA_4444 = 0x8, 94 RGA2_FORMAT_BGR_565 = 0x9, 95 RGA2_FORMAT_BGRA_5551 = 0xa, 96 RGA2_FORMAT_BGRA_4444 = 0xb, 97 98 RGA2_FORMAT_Y4 = 0xe, 99 RGA2_FORMAT_YCbCr_400 = 0xf, 100 101 RGA2_FORMAT_YCbCr_422_SP = 0x10, 102 RGA2_FORMAT_YCbCr_422_P = 0x11, 103 RGA2_FORMAT_YCbCr_420_SP = 0x12, 104 RGA2_FORMAT_YCbCr_420_P = 0x13, 105 RGA2_FORMAT_YCrCb_422_SP = 0x14, 106 RGA2_FORMAT_YCrCb_422_P = 0x15, 107 RGA2_FORMAT_YCrCb_420_SP = 0x16, 108 RGA2_FORMAT_YCrCb_420_P = 0x17, 109 110 RGA2_FORMAT_YVYU_422 = 0x18, 111 RGA2_FORMAT_YVYU_420 = 0x19, 112 RGA2_FORMAT_VYUY_422 = 0x1a, 113 RGA2_FORMAT_VYUY_420 = 0x1b, 114 RGA2_FORMAT_YUYV_422 = 0x1c, 115 RGA2_FORMAT_YUYV_420 = 0x1d, 116 RGA2_FORMAT_UYVY_422 = 0x1e, 117 RGA2_FORMAT_UYVY_420 = 0x1f, 118 119 RGA2_FORMAT_YCbCr_420_SP_10B = 0x20, 120 RGA2_FORMAT_YCrCb_420_SP_10B = 0x21, 121 RGA2_FORMAT_YCbCr_422_SP_10B = 0x22, 122 RGA2_FORMAT_YCrCb_422_SP_10B = 0x23, 123 124 RGA2_FORMAT_BPP_1 = 0x24, 125 RGA2_FORMAT_BPP_2 = 0x25, 126 RGA2_FORMAT_BPP_4 = 0x26, 127 RGA2_FORMAT_BPP_8 = 0x27, 128 129 RGA2_FORMAT_ARGB_8888 = 0x28, 130 RGA2_FORMAT_XRGB_8888 = 0x29, 131 RGA2_FORMAT_ARGB_5551 = 0x2a, 132 RGA2_FORMAT_ARGB_4444 = 0x2b, 133 RGA2_FORMAT_ABGR_8888 = 0x2c, 134 RGA2_FORMAT_XBGR_8888 = 0x2d, 135 RGA2_FORMAT_ABGR_5551 = 0x2e, 136 RGA2_FORMAT_ABGR_4444 = 0x2f, 137 }; 138 139 typedef struct mdp_img 140 { 141 u16 width; 142 u16 height; 143 u32 format; 144 u32 mem_addr; 145 } 146 mdp_img; 147 148 typedef struct mdp_img_act 149 { 150 u16 width; // width 151 u16 height; // height 152 s16 x_off; // x offset for the vir 153 s16 y_off; // y offset for the vir 154 s16 uv_x_off; 155 s16 uv_y_off; 156 } 157 mdp_img_act; 158 159 typedef struct mdp_img_vir 160 { 161 u16 width; 162 u16 height; 163 u32 format; 164 u32 mem_addr; 165 u32 uv_addr; 166 u32 v_addr; 167 } 168 mdp_img_vir; 169 170 171 typedef struct MMU_INFO 172 { 173 unsigned long src0_base_addr; 174 unsigned long src1_base_addr; 175 unsigned long dst_base_addr; 176 unsigned long els_base_addr; 177 178 u8 src0_mmu_flag; /* [0] src0 mmu enable [1] src0_flush [2] src0_prefetch_en [3] src0_prefetch dir */ 179 u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir */ 180 u8 dst_mmu_flag; /* [0] dst mmu enable [1] dst_flush [2] dst_prefetch_en [3] dst_prefetch dir */ 181 u8 els_mmu_flag; /* [0] els mmu enable [1] els_flush [2] els_prefetch_en [3] els_prefetch dir */ 182 } MMU_INFO; 183 184 185 enum 186 { 187 MMU_DIS = 0x0, 188 MMU_EN = 0x1 189 }; 190 enum 191 { 192 MMU_FLUSH_DIS = 0x0, 193 MMU_FLUSH_EN = 0x2 194 }; 195 enum 196 { 197 MMU_PRE_DIS = 0x0, 198 MMU_PRE_EN = 0x4 199 }; 200 enum 201 { 202 MMU_PRE_DIR_FORW = 0x0, 203 MMU_PRE_DIR_BACK = 0x8 204 }; 205 typedef struct COLOR_FILL 206 { 207 s16 gr_x_a; 208 s16 gr_y_a; 209 s16 gr_x_b; 210 s16 gr_y_b; 211 s16 gr_x_g; 212 s16 gr_y_g; 213 s16 gr_x_r; 214 s16 gr_y_r; 215 } 216 COLOR_FILL; 217 218 enum 219 { 220 ALPHA_ORIGINAL = 0x0, 221 ALPHA_NO_128 = 0x1 222 }; 223 224 enum 225 { 226 R2_BLACK = 0x00, 227 R2_COPYPEN = 0xf0, 228 R2_MASKNOTPEN = 0x0a, 229 R2_MASKPEN = 0xa0, 230 R2_MASKPENNOT = 0x50, 231 R2_MERGENOTPEN = 0xaf, 232 R2_MERGEPEN = 0xfa, 233 R2_MERGEPENNOT = 0xf5, 234 R2_NOP = 0xaa, 235 R2_NOT = 0x55, 236 R2_NOTCOPYPEN = 0x0f, 237 R2_NOTMASKPEN = 0x5f, 238 R2_NOTMERGEPEN = 0x05, 239 R2_NOTXORPEN = 0xa5, 240 R2_WHITE = 0xff, 241 R2_XORPEN = 0x5a 242 }; 243 244 245 /***************************************/ 246 /* porting from rga.h for msg convert */ 247 /***************************************/ 248 249 typedef struct FADING 250 { 251 uint8_t b; 252 uint8_t g; 253 uint8_t r; 254 uint8_t res; 255 } 256 FADING; 257 258 typedef struct MMU 259 { 260 unsigned char mmu_en; 261 unsigned long base_addr; 262 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ 263 } MMU; 264 265 typedef struct MMU_32 266 { 267 unsigned char mmu_en; 268 uint32_t base_addr; 269 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/ 270 } MMU_32; 271 272 typedef struct RECT 273 { 274 unsigned short xmin; 275 unsigned short xmax; // width - 1 276 unsigned short ymin; 277 unsigned short ymax; // height - 1 278 } RECT; 279 280 typedef struct POINT 281 { 282 unsigned short x; 283 unsigned short y; 284 } 285 POINT; 286 287 typedef struct line_draw_t 288 { 289 POINT start_point; /* LineDraw_start_point */ 290 POINT end_point; /* LineDraw_end_point */ 291 uint32_t color; /* LineDraw_color */ 292 uint32_t flag; /* (enum) LineDrawing mode sel */ 293 uint32_t line_width; /* range 1~16 */ 294 } 295 line_draw_t; 296 297 /* color space convert coefficient. */ 298 typedef struct csc_coe_t { 299 int16_t r_v; 300 int16_t g_y; 301 int16_t b_u; 302 int32_t off; 303 } csc_coe_t; 304 305 typedef struct full_csc_t { 306 unsigned char flag; 307 csc_coe_t coe_y; 308 csc_coe_t coe_u; 309 csc_coe_t coe_v; 310 } full_csc_t; 311 312 typedef struct rga_img_info_t 313 { 314 unsigned long yrgb_addr; /* yrgb mem addr */ 315 unsigned long uv_addr; /* cb/cr mem addr */ 316 unsigned long v_addr; /* cr mem addr */ 317 unsigned int format; //definition by RK_FORMAT 318 319 unsigned short act_w; 320 unsigned short act_h; 321 unsigned short x_offset; 322 unsigned short y_offset; 323 324 unsigned short vir_w; 325 unsigned short vir_h; 326 327 unsigned short endian_mode; //for BPP 328 unsigned short alpha_swap; /* not use */ 329 } 330 rga_img_info_t; 331 332 typedef struct rga_img_info_32_t 333 { 334 uint32_t yrgb_addr; /* yrgb mem addr */ 335 uint32_t uv_addr; /* cb/cr mem addr */ 336 uint32_t v_addr; /* cr mem addr */ 337 unsigned int format; //definition by RK_FORMAT 338 unsigned short act_w; 339 unsigned short act_h; 340 unsigned short x_offset; 341 unsigned short y_offset; 342 unsigned short vir_w; 343 unsigned short vir_h; 344 unsigned short endian_mode; //for BPP 345 unsigned short alpha_swap; 346 } 347 rga_img_info_32_t; 348 349 struct rga_dma_buffer_t { 350 /* DMABUF information */ 351 struct dma_buf *dma_buf; 352 struct dma_buf_attachment *attach; 353 struct sg_table *sgt; 354 355 dma_addr_t iova; 356 unsigned long size; 357 void *vaddr; 358 enum dma_data_direction dir; 359 }; 360 361 struct rga_req { 362 uint8_t render_mode; /* (enum) process mode sel */ 363 364 rga_img_info_t src; /* src image info */ 365 rga_img_info_t dst; /* dst image info */ 366 rga_img_info_t pat; /* patten image info */ 367 368 unsigned long rop_mask_addr; /* rop4 mask addr */ 369 unsigned long LUT_addr; /* LUT addr */ 370 371 RECT clip; /* dst clip window default value is dst_vir */ 372 /* value from [0, w-1] / [0, h-1]*/ 373 374 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 375 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 376 377 uint16_t alpha_rop_flag; /* alpha rop process flag */ 378 /* ([0] = 1 alpha_rop_enable) */ 379 /* ([1] = 1 rop enable) */ 380 /* ([2] = 1 fading_enable) */ 381 /* ([3] = 1 PD_enable) */ 382 /* ([4] = 1 alpha cal_mode_sel) */ 383 /* ([5] = 1 dither_enable) */ 384 /* ([6] = 1 gradient fill mode sel) */ 385 /* ([7] = 1 AA_enable) */ 386 387 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 388 389 uint32_t color_key_max; /* color key max */ 390 uint32_t color_key_min; /* color key min */ 391 392 uint32_t fg_color; /* foreground color */ 393 uint32_t bg_color; /* background color */ 394 395 COLOR_FILL gr_color; /* color fill use gradient */ 396 397 line_draw_t line_draw_info; 398 399 FADING fading; 400 401 uint8_t PD_mode; /* porter duff alpha mode sel */ 402 403 uint8_t alpha_global_value; /* global alpha value */ 404 405 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ 406 407 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 408 409 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 410 411 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 412 413 uint8_t endian_mode; /* 0/big endian 1/little endian*/ 414 415 uint8_t rotate_mode; /* (enum) rotate mode */ 416 /* 0x0, no rotate */ 417 /* 0x1, rotate */ 418 /* 0x2, x_mirror */ 419 /* 0x3, y_mirror */ 420 421 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 422 423 MMU mmu_info; /* mmu information */ 424 425 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 426 /* ([2~3] rop mode) */ 427 /* ([4] zero mode en) */ 428 /* ([5] dst alpha mode) */ 429 /* ([6] alpha output mode sel) 0 src / 1 dst*/ 430 431 uint8_t src_trans_mode; 432 433 uint8_t dither_mode; 434 435 full_csc_t full_csc; /* full color space convert */ 436 }; 437 struct rga_req_32 438 { 439 uint8_t render_mode; /* (enum) process mode sel */ 440 rga_img_info_32_t src; /* src image info */ 441 rga_img_info_32_t dst; /* dst image info */ 442 rga_img_info_32_t pat; /* patten image info */ 443 uint32_t rop_mask_addr; /* rop4 mask addr */ 444 uint32_t LUT_addr; /* LUT addr */ 445 RECT clip; /* dst clip window default value is dst_vir */ 446 /* value from [0, w-1] / [0, h-1]*/ 447 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 448 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 449 uint16_t alpha_rop_flag; /* alpha rop process flag */ 450 /* ([0] = 1 alpha_rop_enable) */ 451 /* ([1] = 1 rop enable) */ 452 /* ([2] = 1 fading_enable) */ 453 /* ([3] = 1 PD_enable) */ 454 /* ([4] = 1 alpha cal_mode_sel) */ 455 /* ([5] = 1 dither_enable) */ 456 /* ([6] = 1 gradient fill mode sel) */ 457 /* ([7] = 1 AA_enable) */ 458 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 459 uint32_t color_key_max; /* color key max */ 460 uint32_t color_key_min; /* color key min */ 461 uint32_t fg_color; /* foreground color */ 462 uint32_t bg_color; /* background color */ 463 COLOR_FILL gr_color; /* color fill use gradient */ 464 line_draw_t line_draw_info; 465 FADING fading; 466 uint8_t PD_mode; /* porter duff alpha mode sel */ 467 uint8_t alpha_global_value; /* global alpha value */ 468 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/ 469 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/ 470 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 471 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 472 uint8_t endian_mode; /* 0/big endian 1/little endian*/ 473 uint8_t rotate_mode; /* (enum) rotate mode */ 474 /* 0x0, no rotate */ 475 /* 0x1, rotate */ 476 /* 0x2, x_mirror */ 477 /* 0x3, y_mirror */ 478 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 479 MMU_32 mmu_info; /* mmu information */ 480 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 481 /* ([2~3] rop mode) */ 482 /* ([4] zero mode en) */ 483 /* ([5] dst alpha mode) */ 484 /* ([6] alpha output mode sel) 0 src / 1 dst*/ 485 uint8_t src_trans_mode; 486 487 uint8_t dither_mode; 488 489 full_csc_t full_csc; /* full color space convert */ 490 }; 491 492 493 494 struct rga2_req 495 { 496 u8 render_mode; /* (enum) process mode sel */ 497 498 rga_img_info_t src; // src active window 499 rga_img_info_t src1; // src1 active window 500 rga_img_info_t dst; // dst active window 501 rga_img_info_t pat; // patten active window 502 503 unsigned long rop_mask_addr; // rop4 mask addr 504 unsigned long LUT_addr; // LUT addr 505 506 u32 rop_mask_stride; 507 508 u8 bitblt_mode; /* 0: SRC + DST => DST */ 509 /* 1: SRC + SRC1 => DST */ 510 511 u8 rotate_mode; /* [1:0] */ 512 /* 0 degree 0x0 */ 513 /* 90 degree 0x1 */ 514 /* 180 degree 0x2 */ 515 /* 270 degree 0x3 */ 516 /* [5:4] */ 517 /* none 0x0 */ 518 /* x_mirror 0x1 */ 519 /* y_mirror 0x2 */ 520 /* x_mirror + y_mirror 0x3 */ 521 522 u16 alpha_rop_flag; /* alpha rop process flag */ 523 /* ([0] = 1 alpha_rop_enable) */ 524 /* ([1] = 1 rop enable) */ 525 /* ([2] = 1 fading_enable) */ 526 /* ([3] = 1 alpha cal_mode_sel) */ 527 /* ([4] = 1 src_dither_up_enable) */ 528 /* ([5] = 1 dst_dither_up_enable) */ 529 /* ([6] = 1 dither_down_enable) */ 530 /* ([7] = 1 gradient fill mode sel) */ 531 532 533 u16 alpha_mode_0; /* [0] SrcAlphaMode0 */ 534 /* [2:1] SrcGlobalAlphaMode0 */ 535 /* [3] SrcAlphaSelectMode0 */ 536 /* [6:4] SrcFactorMode0 */ 537 /* [7] SrcColorMode */ 538 539 /* [8] DstAlphaMode0 */ 540 /* [10:9] DstGlobalAlphaMode0 */ 541 /* [11] DstAlphaSelectMode0 */ 542 /* [14:12] DstFactorMode0 */ 543 /* [15] DstColorMode0 */ 544 545 u16 alpha_mode_1; /* [0] SrcAlphaMode1 */ 546 /* [2:1] SrcGlobalAlphaMode1 */ 547 /* [3] SrcAlphaSelectMode1 */ 548 /* [6:4] SrcFactorMode1 */ 549 550 /* [8] DstAlphaMode1 */ 551 /* [10:9] DstGlobalAlphaMode1 */ 552 /* [11] DstAlphaSelectMode1 */ 553 /* [14:12] DstFactorMode1 */ 554 555 u8 scale_bicu_mode; /* 0 1 2 3 */ 556 557 u32 color_key_max; /* color key max */ 558 u32 color_key_min; /* color key min */ 559 560 u32 fg_color; /* foreground color */ 561 u32 bg_color; /* background color */ 562 563 u8 color_fill_mode; 564 COLOR_FILL gr_color; /* color fill use gradient */ 565 566 u8 fading_alpha_value; /* Fading value */ 567 u8 fading_r_value; 568 u8 fading_g_value; 569 u8 fading_b_value; 570 571 u8 src_a_global_val; /* src global alpha value */ 572 u8 dst_a_global_val; /* dst global alpha value */ 573 574 u8 rop_mode; /* rop mode select 0 : rop2 1 : rop3 2 : rop4 */ 575 u16 rop_code; /* rop2/3/4 code */ 576 577 u8 palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/ 578 579 u8 yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 580 /* [1:0] src0 csc mode */ 581 /* [3:2] dst csc mode */ 582 /* [4] dst csc clip enable */ 583 /* [6:5] src1 csc mdoe */ 584 /* [7] src1 csc clip enable */ 585 full_csc_t full_csc; /* full color space convert */ 586 587 u8 endian_mode; /* 0/little endian 1/big endian */ 588 589 u8 CMD_fin_int_enable; 590 591 MMU_INFO mmu_info; /* mmu infomation */ 592 593 u8 alpha_zero_key; 594 u8 src_trans_mode; 595 596 u8 alpha_swp; /* not use */ 597 u8 dither_mode; 598 599 u8 rgb2yuv_mode; 600 601 u8 buf_type; 602 }; 603 604 struct rga2_mmu_buf_t { 605 int32_t front; 606 int32_t back; 607 int32_t size; 608 int32_t curr; 609 unsigned int *buf; 610 unsigned int *buf_virtual; 611 612 struct page **pages; 613 614 u8 buf_order; 615 u8 pages_order; 616 }; 617 618 enum 619 { 620 BB_ROTATE_OFF = 0x0, /* no rotate */ 621 BB_ROTATE_90 = 0x1, /* rotate 90 */ 622 BB_ROTATE_180 = 0x2, /* rotate 180 */ 623 BB_ROTATE_270 = 0x3, /* rotate 270 */ 624 }; /*rotate mode*/ 625 626 enum 627 { 628 BB_MIRROR_OFF = (0x0 << 4), /* no mirror */ 629 BB_MIRROR_X = (0x1 << 4), /* x mirror */ 630 BB_MIRROR_Y = (0x2 << 4), /* y mirror */ 631 BB_MIRROR_XY = (0x3 << 4), /* xy mirror */ 632 }; /*mirror mode*/ 633 634 enum 635 { 636 BB_COPY_USE_TILE = (0x1 << 6), /* bitblt mode copy but use Tile mode */ 637 }; 638 639 enum 640 { 641 //BYPASS = 0x0, 642 BT_601_RANGE0 = 0x1, 643 BT_601_RANGE1 = 0x2, 644 BT_709_RANGE0 = 0x3, 645 }; /*yuv2rgb_mode*/ 646 647 enum 648 { 649 BPP1 = 0x0, /* BPP1 */ 650 BPP2 = 0x1, /* BPP2 */ 651 BPP4 = 0x2, /* BPP4 */ 652 BPP8 = 0x3 /* BPP8 */ 653 }; /*palette_mode*/ 654 655 enum 656 { 657 SOLID_COLOR = 0x0, //color fill mode; ROP4: SOLID_rop4_mask_addr COLOR 658 PATTERN_COLOR = 0x1 //pattern_fill_mode;ROP4:PATTERN_COLOR 659 }; /*color fill mode*/ 660 661 enum 662 { 663 COLOR_FILL_CLIP = 0x0, 664 COLOR_FILL_NOT_CLIP = 0x1 665 }; 666 667 enum 668 { 669 CATROM = 0x0, 670 MITCHELL = 0x1, 671 HERMITE = 0x2, 672 B_SPLINE = 0x3, 673 }; /*bicubic coefficient*/ 674 675 enum 676 { 677 ROP2 = 0x0, 678 ROP3 = 0x1, 679 ROP4 = 0x2 680 }; /*ROP mode*/ 681 682 enum 683 { 684 BIG_ENDIAN = 0x0, 685 LITTLE_ENDIAN = 0x1 686 }; /*endian mode*/ 687 688 enum 689 { 690 MMU_TABLE_4KB = 0x0, 691 MMU_TABLE_64KB = 0x1, 692 }; /*MMU table size*/ 693 694 enum 695 { 696 RGB_2_666 = 0x0, 697 RGB_2_565 = 0x1, 698 RGB_2_555 = 0x2, 699 RGB_2_444 = 0x3, 700 }; /*dither down mode*/ 701 702 703 704 /** 705 * struct for process session which connect to rga 706 * 707 * @author ZhangShengqin (2012-2-15) 708 */ 709 typedef struct rga2_session { 710 /* a linked list of data so we can access them for debugging */ 711 struct list_head list_session; 712 /* a linked list of register data waiting for process */ 713 struct list_head waiting; 714 /* a linked list of register data in processing */ 715 struct list_head running; 716 /* all coommand this thread done */ 717 atomic_t done; 718 wait_queue_head_t wait; 719 pid_t pid; 720 atomic_t task_running; 721 atomic_t num_done; 722 } rga2_session; 723 724 struct rga2_reg { 725 rga2_session *session; 726 struct list_head session_link; 727 struct list_head status_link; 728 uint32_t sys_reg[8]; 729 uint32_t csc_reg[12]; 730 uint32_t cmd_reg[32]; 731 732 uint32_t *MMU_src0_base; 733 uint32_t *MMU_src1_base; 734 uint32_t *MMU_dst_base; 735 uint32_t MMU_src0_count; 736 uint32_t MMU_src1_count; 737 uint32_t MMU_dst_count; 738 739 uint32_t MMU_len; 740 bool MMU_map; 741 742 struct rga_dma_buffer_t dma_buffer_src0; 743 struct rga_dma_buffer_t dma_buffer_src1; 744 struct rga_dma_buffer_t dma_buffer_dst; 745 struct rga_dma_buffer_t dma_buffer_els; 746 }; 747 748 struct rga2_service_info { 749 struct mutex lock; 750 struct timer_list timer; /* timer for power off */ 751 struct list_head waiting; /* link to link_reg in struct vpu_reg */ 752 struct list_head running; /* link to link_reg in struct vpu_reg */ 753 struct list_head done; /* link to link_reg in struct vpu_reg */ 754 struct list_head session; /* link to list_session in struct vpu_session */ 755 atomic_t total_running; 756 757 struct rga2_reg *reg; 758 759 uint32_t cmd_buff[32*8];/* cmd_buff for rga */ 760 uint32_t *pre_scale_buf; 761 atomic_t int_disable; /* 0 int enable 1 int disable */ 762 atomic_t cmd_num; 763 atomic_t src_format_swt; 764 int last_prc_src_format; 765 atomic_t rga_working; 766 bool enable; 767 uint32_t dev_mode; 768 769 //struct rga_req req[10]; 770 771 struct mutex mutex; // mutex 772 }; 773 774 #define RGA2_TEST_CASE 0 775 776 //General Registers 777 #define RGA2_SYS_CTRL 0x000 778 #define RGA2_CMD_CTRL 0x004 779 #define RGA2_CMD_BASE 0x008 780 #define RGA2_STATUS 0x00c 781 #define RGA2_INT 0x010 782 #define RGA2_MMU_CTRL0 0x018 783 #define RGA2_MMU_CMD_BASE 0x01c 784 785 //Full Csc Coefficient 786 #define RGA2_CSC_COE_BASE 0x60 787 788 //Command code start 789 #define RGA2_MODE_CTRL 0x100 790 #define RGA_BLIT_COMPLETE_EVENT 1 791 792 #endif /*_RK29_IPP_DRIVER_H_*/ 793