1 /*
2 * Copyright (C) 2012 ROCKCHIP, Inc.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15 #define pr_fmt(fmt) "rga2: " fmt
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/sched.h>
21 #include <linux/mutex.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <asm/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/delay.h>
27 #include <asm/io.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/fs.h>
31 #include <linux/uaccess.h>
32 #include <linux/miscdevice.h>
33 #include <linux/poll.h>
34 #include <linux/delay.h>
35 #include <linux/wait.h>
36 #include <linux/syscalls.h>
37 #include <linux/timer.h>
38 #include <linux/time.h>
39 #include <asm/cacheflush.h>
40 #include <linux/slab.h>
41 #include <linux/fb.h>
42 #include <linux/wakelock.h>
43 #include <linux/scatterlist.h>
44 #include <linux/version.h>
45
46 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
47 #include <linux/pm_runtime.h>
48 #include <linux/dma-buf-cache.h>
49 #endif
50
51 #include "rga2.h"
52 #include "rga2_reg_info.h"
53 #include "rga2_mmu_info.h"
54 #include "RGA2_API.h"
55 #include "rga2_debugger.h"
56
57 #if IS_ENABLED(CONFIG_ION_ROCKCHIP) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
58 #include <linux/rockchip_ion.h>
59 #endif
60
61 #if ((defined(CONFIG_RK_IOMMU) || defined(CONFIG_ROCKCHIP_IOMMU)) && defined(CONFIG_ION_ROCKCHIP))
62 #define CONFIG_RGA_IOMMU
63 #endif
64
65 #define RGA2_TEST_FLUSH_TIME 0
66 #define RGA2_INFO_BUS_ERROR 1
67 #define RGA2_POWER_OFF_DELAY 4*HZ /* 4s */
68 #define RGA2_TIMEOUT_DELAY (HZ / 2) /* 500ms */
69 #define RGA2_MAJOR 255
70 #define RGA2_RESET_TIMEOUT 1000
71 /*
72 * The maximum input is 8192*8192, the maximum output is 4096*4096
73 * The size of physical pages requested is:
74 * ( ( maximum_input_value * maximum_input_value * format_bpp ) / 4K_page_size ) + 1
75 */
76 #define RGA2_PHY_PAGE_SIZE (((8192 * 8192 * 4) / 4096) + 1)
77
78 ktime_t rga2_start;
79 ktime_t rga2_end;
80 int rga2_flag;
81 int first_RGA2_proc;
82 static int rk3368;
83
84 rga2_session rga2_session_global;
85 long (*rga2_ioctl_kernel_p)(struct rga_req *);
86
87 struct rga2_drvdata_t *rga2_drvdata;
88 struct rga2_service_info rga2_service;
89 struct rga2_mmu_buf_t rga2_mmu_buf;
90
91 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
92 extern struct ion_client *rockchip_ion_client_create(const char *name);
93 #endif
94
95 static int rga2_blit_async(rga2_session *session, struct rga2_req *req);
96 static void rga2_del_running_list(void);
97 static void rga2_del_running_list_timeout(void);
98 static void rga2_try_set_reg(void);
99
100 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
rga2_get_cmd_mode_str(u32 cmd)101 static const char *rga2_get_cmd_mode_str(u32 cmd)
102 {
103 switch (cmd) {
104 /* RGA1 */
105 case RGA_BLIT_SYNC:
106 return "RGA_BLIT_SYNC";
107 case RGA_BLIT_ASYNC:
108 return "RGA_BLIT_ASYNC";
109 case RGA_FLUSH:
110 return "RGA_FLUSH";
111 case RGA_GET_RESULT:
112 return "RGA_GET_RESULT";
113 case RGA_GET_VERSION:
114 return "RGA_GET_VERSION";
115 /* RGA2 */
116 case RGA2_BLIT_SYNC:
117 return "RGA2_BLIT_SYNC";
118 case RGA2_BLIT_ASYNC:
119 return "RGA2_BLIT_ASYNC";
120 case RGA2_FLUSH:
121 return "RGA2_FLUSH";
122 case RGA2_GET_RESULT:
123 return "RGA2_GET_RESULT";
124 case RGA2_GET_VERSION:
125 return "RGA2_GET_VERSION";
126 default:
127 return "UNF";
128 }
129 }
130
rga2_get_blend_mode_str(u16 alpha_rop_flag,u16 alpha_mode_0,u16 alpha_mode_1)131 static const char *rga2_get_blend_mode_str(u16 alpha_rop_flag, u16 alpha_mode_0,
132 u16 alpha_mode_1)
133 {
134 if (alpha_rop_flag == 0) {
135 return "no blend";
136 } else if (alpha_rop_flag == 0x9) {
137 if (alpha_mode_0 == 0x381A && alpha_mode_1 == 0x381A)
138 return "105 src + (1-src.a)*dst";
139 else if (alpha_mode_0 == 0x483A && alpha_mode_1 == 0x483A)
140 return "405 src.a * src + (1-src.a) * dst";
141 else
142 return "check reg for more imformation";
143 } else {
144 return "check reg for more imformation";
145 }
146 }
147
rga2_get_render_mode_str(u8 mode)148 static const char *rga2_get_render_mode_str(u8 mode)
149 {
150 switch (mode) {
151 case 0x0:
152 return "bitblt";
153 case 0x1:
154 return "color_palette";
155 case 0x2:
156 return "color_fill";
157 case 0x3:
158 return "update_palette_table";
159 case 0x4:
160 return "update_patten_buff";
161 default:
162 return "UNF";
163 }
164 }
165
rga2_get_rotate_mode_str(u8 mode)166 static const char *rga2_get_rotate_mode_str(u8 mode)
167 {
168 switch (mode) {
169 case 0x0:
170 return "0";
171 case 0x1:
172 return "90 degree";
173 case 0x2:
174 return "180 degree";
175 case 0x3:
176 return "270 degree";
177 case 0x10:
178 return "xmirror";
179 case 0x20:
180 return "ymirror";
181 case 0x30:
182 return "xymirror";
183 default:
184 return "UNF";
185 }
186 }
187
rga2_is_yuv10bit_format(uint32_t format)188 static bool rga2_is_yuv10bit_format(uint32_t format)
189 {
190 bool ret = false;
191
192 switch (format) {
193 case RGA2_FORMAT_YCbCr_420_SP_10B:
194 case RGA2_FORMAT_YCrCb_420_SP_10B:
195 case RGA2_FORMAT_YCbCr_422_SP_10B:
196 case RGA2_FORMAT_YCrCb_422_SP_10B:
197 ret = true;
198 break;
199 }
200 return ret;
201 }
202
rga2_is_yuv8bit_format(uint32_t format)203 static bool rga2_is_yuv8bit_format(uint32_t format)
204 {
205 bool ret = false;
206
207 switch (format) {
208 case RGA2_FORMAT_YCbCr_422_SP:
209 case RGA2_FORMAT_YCbCr_422_P:
210 case RGA2_FORMAT_YCbCr_420_SP:
211 case RGA2_FORMAT_YCbCr_420_P:
212 case RGA2_FORMAT_YCrCb_422_SP:
213 case RGA2_FORMAT_YCrCb_422_P:
214 case RGA2_FORMAT_YCrCb_420_SP:
215 case RGA2_FORMAT_YCrCb_420_P:
216 ret = true;
217 break;
218 }
219 return ret;
220 }
221
rga2_get_format_name(uint32_t format)222 static const char *rga2_get_format_name(uint32_t format)
223 {
224 switch (format) {
225 case RGA2_FORMAT_RGBA_8888:
226 return "RGBA8888";
227 case RGA2_FORMAT_RGBX_8888:
228 return "RGBX8888";
229 case RGA2_FORMAT_RGB_888:
230 return "RGB888";
231 case RGA2_FORMAT_BGRA_8888:
232 return "BGRA8888";
233 case RGA2_FORMAT_BGRX_8888:
234 return "BGRX8888";
235 case RGA2_FORMAT_BGR_888:
236 return "BGR888";
237 case RGA2_FORMAT_RGB_565:
238 return "RGB565";
239 case RGA2_FORMAT_RGBA_5551:
240 return "RGBA5551";
241 case RGA2_FORMAT_RGBA_4444:
242 return "RGBA4444";
243 case RGA2_FORMAT_BGR_565:
244 return "BGR565";
245 case RGA2_FORMAT_BGRA_5551:
246 return "BGRA5551";
247 case RGA2_FORMAT_BGRA_4444:
248 return "BGRA4444";
249
250 case RGA2_FORMAT_ARGB_8888:
251 return "ARGB8888";
252 case RGA2_FORMAT_XRGB_8888:
253 return "XBGR8888";
254 case RGA2_FORMAT_ARGB_5551:
255 return "ARGB5551";
256 case RGA2_FORMAT_ARGB_4444:
257 return "ARGB4444";
258 case RGA2_FORMAT_ABGR_8888:
259 return "ABGR8888";
260 case RGA2_FORMAT_XBGR_8888:
261 return "XBGR8888";
262 case RGA2_FORMAT_ABGR_5551:
263 return "ABGR5551";
264 case RGA2_FORMAT_ABGR_4444:
265 return "ABGR4444";
266
267 case RGA2_FORMAT_YCbCr_422_SP:
268 return "YCbCr422SP";
269 case RGA2_FORMAT_YCbCr_422_P:
270 return "YCbCr422P";
271 case RGA2_FORMAT_YCbCr_420_SP:
272 return "YCbCr420SP";
273 case RGA2_FORMAT_YCbCr_420_P:
274 return "YCbCr420P";
275 case RGA2_FORMAT_YCrCb_422_SP:
276 return "YCrCb422SP";
277 case RGA2_FORMAT_YCrCb_422_P:
278 return "YCrCb422P";
279 case RGA2_FORMAT_YCrCb_420_SP:
280 return "YCrCb420SP";
281 case RGA2_FORMAT_YCrCb_420_P:
282 return "YCrCb420P";
283
284 case RGA2_FORMAT_YVYU_422:
285 return "YVYU422";
286 case RGA2_FORMAT_YVYU_420:
287 return "YVYU420";
288 case RGA2_FORMAT_VYUY_422:
289 return "VYUY422";
290 case RGA2_FORMAT_VYUY_420:
291 return "VYUY420";
292 case RGA2_FORMAT_YUYV_422:
293 return "YUYV422";
294 case RGA2_FORMAT_YUYV_420:
295 return "YUYV420";
296 case RGA2_FORMAT_UYVY_422:
297 return "UYVY422";
298 case RGA2_FORMAT_UYVY_420:
299 return "UYVY420";
300
301 case RGA2_FORMAT_YCbCr_420_SP_10B:
302 return "YCrCb420SP10B";
303 case RGA2_FORMAT_YCrCb_420_SP_10B:
304 return "YCbCr420SP10B";
305 case RGA2_FORMAT_YCbCr_422_SP_10B:
306 return "YCbCr422SP10B";
307 case RGA2_FORMAT_YCrCb_422_SP_10B:
308 return "YCrCb422SP10B";
309 case RGA2_FORMAT_BPP_1:
310 return "BPP1";
311 case RGA2_FORMAT_BPP_2:
312 return "BPP2";
313 case RGA2_FORMAT_BPP_4:
314 return "BPP4";
315 case RGA2_FORMAT_BPP_8:
316 return "BPP8";
317 case RGA2_FORMAT_YCbCr_400:
318 return "YCbCr400";
319 case RGA2_FORMAT_Y4:
320 return "y4";
321 default:
322 return "UNF";
323 }
324 }
325
print_debug_info(struct rga2_req * req)326 static void print_debug_info(struct rga2_req *req)
327 {
328 INFO("render_mode:%s,bitblit_mode=%d,rotate_mode:%s\n",
329 rga2_get_render_mode_str(req->render_mode), req->bitblt_mode,
330 rga2_get_rotate_mode_str(req->rotate_mode));
331 INFO("src : y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d format=%s\n",
332 req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,
333 req->src.act_w, req->src.act_h, req->src.vir_w, req->src.vir_h,
334 req->src.x_offset, req->src.y_offset,
335 rga2_get_format_name(req->src.format));
336 if (req->src1.yrgb_addr != 0 ||
337 req->src1.uv_addr != 0 ||
338 req->src1.v_addr != 0) {
339 INFO("src1 : y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d format=%s\n",
340 req->src1.yrgb_addr, req->src1.uv_addr, req->src1.v_addr,
341 req->src1.act_w, req->src1.act_h, req->src1.vir_w, req->src1.vir_h,
342 req->src1.x_offset, req->src1.y_offset,
343 rga2_get_format_name(req->src1.format));
344 }
345 INFO("dst : y=%lx uv=%lx v=%lx aw=%d ah=%d vw=%d vh=%d xoff=%d yoff=%d format=%s\n",
346 req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,
347 req->dst.act_w, req->dst.act_h, req->dst.vir_w, req->dst.vir_h,
348 req->dst.x_offset, req->dst.y_offset,
349 rga2_get_format_name(req->dst.format));
350 INFO("mmu : src=%.2x src1=%.2x dst=%.2x els=%.2x\n",
351 req->mmu_info.src0_mmu_flag, req->mmu_info.src1_mmu_flag,
352 req->mmu_info.dst_mmu_flag, req->mmu_info.els_mmu_flag);
353 INFO("alpha : flag %x mode0=%x mode1=%x\n",
354 req->alpha_rop_flag, req->alpha_mode_0, req->alpha_mode_1);
355 INFO("blend mode is %s\n",
356 rga2_get_blend_mode_str(req->alpha_rop_flag,
357 req->alpha_mode_0, req->alpha_mode_1));
358 INFO("yuv2rgb mode is %x\n", req->yuv2rgb_mode);
359 }
360
rga2_align_check(struct rga2_req * req)361 static int rga2_align_check(struct rga2_req *req)
362 {
363 if (rga2_is_yuv10bit_format(req->src.format))
364 if ((req->src.vir_w % 16) || (req->src.x_offset % 2) ||
365 (req->src.act_w % 2) || (req->src.y_offset % 2) ||
366 (req->src.act_h % 2) || (req->src.vir_h % 2))
367 INFO("err src wstride is not align to 16 or yuv not align to 2");
368 if (rga2_is_yuv10bit_format(req->dst.format))
369 if ((req->dst.vir_w % 16) || (req->dst.x_offset % 2) ||
370 (req->dst.act_w % 2) || (req->dst.y_offset % 2) ||
371 (req->dst.act_h % 2) || (req->dst.vir_h % 2))
372 INFO("err dst wstride is not align to 16 or yuv not align to 2");
373 if (rga2_is_yuv8bit_format(req->src.format))
374 if ((req->src.vir_w % 8) || (req->src.x_offset % 2) ||
375 (req->src.act_w % 2) || (req->src.y_offset % 2) ||
376 (req->src.act_h % 2) || (req->src.vir_h % 2))
377 INFO("err src wstride is not align to 8 or yuv not align to 2");
378 if (rga2_is_yuv8bit_format(req->dst.format))
379 if ((req->dst.vir_w % 8) || (req->dst.x_offset % 2) ||
380 (req->dst.act_w % 2) || (req->dst.y_offset % 2) ||
381 (req->dst.act_h % 2) || (req->dst.vir_h % 2))
382 INFO("err dst wstride is not align to 8 or yuv not align to 2");
383 INFO("rga align check over!\n");
384 return 0;
385 }
386
rga2_scale_check(struct rga2_req * req)387 int rga2_scale_check(struct rga2_req *req)
388 {
389 u32 saw, sah, daw, dah;
390 struct rga2_drvdata_t *data = rga2_drvdata;
391
392 saw = req->src.act_w;
393 sah = req->src.act_h;
394 daw = req->dst.act_w;
395 dah = req->dst.act_h;
396
397 if (strncmp(data->version, "2.20", 4) == 0) {
398 if (((saw >> 4) >= daw) || ((sah >> 4) >= dah))
399 INFO("unsupported to scaling less than 1/16 times.\n");
400 if (((daw >> 4) >= saw) || ((dah >> 4) >= sah))
401 INFO("unsupported to scaling more than 16 times.\n");
402 } else {
403 if (((saw >> 3) >= daw) || ((sah >> 3) >= dah))
404 INFO("unsupported to scaling less than 1/8 tiems.\n");
405 if (((daw >> 3) >= saw) || ((dah >> 3) >= sah))
406 INFO("unsupported to scaling more than 8 times.\n");
407 }
408 INFO("rga2 scale check over.\n");
409 return 0;
410 }
411 #endif
412
rga2_printf_cmd_buf(u32 * cmd_buf)413 static void rga2_printf_cmd_buf(u32 *cmd_buf)
414 {
415 u32 reg_p[32];
416 u32 i = 0;
417 u32 src_stride, dst_stride, src_format, dst_format;
418 u32 src_aw, src_ah, dst_aw, dst_ah;
419
420 for (i = 0; i < 32; i++)
421 reg_p[i] = *(cmd_buf + i);
422
423 src_stride = reg_p[6];
424 dst_stride = reg_p[18];
425
426 src_format = reg_p[1] & (~0xfffffff0);
427 dst_format = reg_p[14] & (~0xfffffff0);
428
429 src_aw = (reg_p[7] & (~0xffff0000)) + 1;
430 src_ah = ((reg_p[7] & (~0x0000ffff)) >> 16) + 1;
431
432 dst_aw = (reg_p[19] & (~0xffff0000)) + 1;
433 dst_ah = ((reg_p[19] & (~0x0000ffff)) >> 16) + 1;
434
435 DBG("src : aw = %d ah = %d stride = %d format is %x\n",
436 src_aw, src_ah, src_stride, src_format);
437 DBG("dst : aw = %d ah = %d stride = %d format is %x\n",
438 dst_aw, dst_ah, dst_stride, dst_format);
439 }
440
rga2_write(u32 b,u32 r)441 static inline void rga2_write(u32 b, u32 r)
442 {
443 *((volatile unsigned int *)(rga2_drvdata->rga_base + r)) = b;
444 }
445
rga2_read(u32 r)446 static inline u32 rga2_read(u32 r)
447 {
448 return *((volatile unsigned int *)(rga2_drvdata->rga_base + r));
449 }
450
451 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
rga2_init_version(void)452 static inline int rga2_init_version(void)
453 {
454 struct rga2_drvdata_t *rga = rga2_drvdata;
455 u32 major_version, minor_version, svn_version;
456 u32 reg_version;
457
458 if (!rga) {
459 pr_err("rga2_drvdata is null\n");
460 return -EINVAL;
461 }
462 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
463 pm_runtime_get_sync(rga2_drvdata->dev);
464 #endif
465
466 clk_prepare_enable(rga2_drvdata->aclk_rga2);
467 clk_prepare_enable(rga2_drvdata->hclk_rga2);
468
469 reg_version = rga2_read(0x028);
470
471 clk_disable_unprepare(rga2_drvdata->aclk_rga2);
472 clk_disable_unprepare(rga2_drvdata->hclk_rga2);
473
474 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
475 pm_runtime_put(rga2_drvdata->dev);
476 #endif
477
478 major_version = (reg_version & RGA2_MAJOR_VERSION_MASK) >> 24;
479 minor_version = (reg_version & RGA2_MINOR_VERSION_MASK) >> 20;
480 svn_version = (reg_version & RGA2_SVN_VERSION_MASK);
481
482 /*
483 * some old rga ip has no rga version register, so force set to 2.00
484 */
485 if (!major_version && !minor_version)
486 major_version = 2;
487 snprintf(rga->version, 10, "%x.%01x.%05x", major_version, minor_version, svn_version);
488
489 return 0;
490 }
491 #endif
rga2_soft_reset(void)492 static void rga2_soft_reset(void)
493 {
494 u32 i;
495 u32 reg;
496
497 rga2_write((1 << 3) | (1 << 4) | (1 << 6), RGA2_SYS_CTRL);
498
499 for(i = 0; i < RGA2_RESET_TIMEOUT; i++)
500 {
501 reg = rga2_read(RGA2_SYS_CTRL) & 1; //RGA_SYS_CTRL
502
503 if(reg == 0)
504 break;
505
506 udelay(1);
507 }
508
509 if(i == RGA2_RESET_TIMEOUT)
510 ERR("soft reset timeout.\n");
511 }
512
rga2_dump(void)513 static void rga2_dump(void)
514 {
515 int running;
516 struct rga2_reg *reg, *reg_tmp;
517 rga2_session *session, *session_tmp;
518
519 running = atomic_read(&rga2_service.total_running);
520 printk("rga total_running %d\n", running);
521 list_for_each_entry_safe(session, session_tmp, &rga2_service.session,
522 list_session)
523 {
524 printk("session pid %d:\n", session->pid);
525 running = atomic_read(&session->task_running);
526 printk("task_running %d\n", running);
527 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link)
528 {
529 printk("waiting register set 0x %.lu\n", (unsigned long)reg);
530 }
531 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link)
532 {
533 printk("running register set 0x %.lu\n", (unsigned long)reg);
534 }
535 }
536 }
537
rga2_queue_power_off_work(void)538 static inline void rga2_queue_power_off_work(void)
539 {
540 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
541 queue_delayed_work(system_wq, &rga2_drvdata->power_off_work,
542 RGA2_POWER_OFF_DELAY);
543 #else
544 queue_delayed_work(system_nrt_wq, &rga2_drvdata->power_off_work,
545 RGA2_POWER_OFF_DELAY);
546 #endif
547 }
548
549 /* Caller must hold rga_service.lock */
rga2_power_on(void)550 static void rga2_power_on(void)
551 {
552 static ktime_t last;
553 ktime_t now = ktime_get();
554
555 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
556 cancel_delayed_work_sync(&rga2_drvdata->power_off_work);
557 rga2_queue_power_off_work();
558 last = now;
559 }
560
561 if (rga2_service.enable)
562 return;
563
564 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
565 pm_runtime_get_sync(rga2_drvdata->dev);
566 #else
567 clk_prepare_enable(rga2_drvdata->pd_rga2);
568 #endif
569 clk_prepare_enable(rga2_drvdata->clk_rga2);
570 clk_prepare_enable(rga2_drvdata->aclk_rga2);
571 clk_prepare_enable(rga2_drvdata->hclk_rga2);
572 wake_lock(&rga2_drvdata->wake_lock);
573 rga2_service.enable = true;
574 }
575
576 /* Caller must hold rga_service.lock */
rga2_power_off(void)577 static void rga2_power_off(void)
578 {
579 int total_running;
580
581 if (!rga2_service.enable) {
582 return;
583 }
584
585 total_running = atomic_read(&rga2_service.total_running);
586 if (total_running) {
587 pr_err("power off when %d task running!!\n", total_running);
588 mdelay(50);
589 pr_err("delay 50 ms for running task\n");
590 rga2_dump();
591 }
592
593 clk_disable_unprepare(rga2_drvdata->clk_rga2);
594 clk_disable_unprepare(rga2_drvdata->aclk_rga2);
595 clk_disable_unprepare(rga2_drvdata->hclk_rga2);
596
597 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
598 pm_runtime_put(rga2_drvdata->dev);
599 #else
600 clk_disable_unprepare(rga2_drvdata->pd_rga2);
601 #endif
602
603 wake_unlock(&rga2_drvdata->wake_lock);
604 first_RGA2_proc = 0;
605 rga2_service.enable = false;
606 }
607
rga2_power_off_work(struct work_struct * work)608 static void rga2_power_off_work(struct work_struct *work)
609 {
610 if (mutex_trylock(&rga2_service.lock)) {
611 rga2_power_off();
612 mutex_unlock(&rga2_service.lock);
613 } else {
614 /* Come back later if the device is busy... */
615 rga2_queue_power_off_work();
616 }
617 }
618
rga2_flush(rga2_session * session,unsigned long arg)619 static int rga2_flush(rga2_session *session, unsigned long arg)
620 {
621 int ret = 0;
622 int ret_timeout;
623
624 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
625 ktime_t start = ktime_set(0, 0);
626 ktime_t end = ktime_set(0, 0);
627
628 if (RGA2_TEST_TIME)
629 start = ktime_get();
630 #endif
631 ret_timeout = wait_event_timeout(session->wait, atomic_read(&session->done), RGA2_TIMEOUT_DELAY);
632
633 if (unlikely(ret_timeout < 0)) {
634 u32 i;
635 u32 *p;
636
637 p = rga2_service.cmd_buff;
638 pr_err("flush pid %d wait task ret %d\n", session->pid, ret);
639 pr_err("interrupt = %x status = %x\n", rga2_read(RGA2_INT),
640 rga2_read(RGA2_STATUS));
641 rga2_printf_cmd_buf(p);
642 DBG("rga2 CMD\n");
643 for (i = 0; i < 7; i++)
644 DBG("%.8x %.8x %.8x %.8x\n",
645 p[0 + i * 4], p[1 + i * 4],
646 p[2 + i * 4], p[3 + i * 4]);
647 mutex_lock(&rga2_service.lock);
648 rga2_del_running_list();
649 mutex_unlock(&rga2_service.lock);
650 ret = ret_timeout;
651 } else if (0 == ret_timeout) {
652 u32 i;
653 u32 *p;
654
655 p = rga2_service.cmd_buff;
656 pr_err("flush pid %d wait %d task done timeout\n",
657 session->pid, atomic_read(&session->task_running));
658 pr_err("interrupt = %x status = %x\n",
659 rga2_read(RGA2_INT), rga2_read(RGA2_STATUS));
660 rga2_printf_cmd_buf(p);
661 DBG("rga2 CMD\n");
662 for (i = 0; i < 7; i++)
663 DBG("%.8x %.8x %.8x %.8x\n",
664 p[0 + i * 4], p[1 + i * 4],
665 p[2 + i * 4], p[3 + i * 4]);
666 mutex_lock(&rga2_service.lock);
667 rga2_del_running_list_timeout();
668 rga2_try_set_reg();
669 mutex_unlock(&rga2_service.lock);
670 ret = -ETIMEDOUT;
671 }
672
673 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
674 if (RGA2_TEST_TIME) {
675 end = ktime_get();
676 end = ktime_sub(end, start);
677 DBG("one flush wait time %d\n", (int)ktime_to_us(end));
678 }
679 #endif
680 return ret;
681 }
682
683
rga2_get_result(rga2_session * session,unsigned long arg)684 static int rga2_get_result(rga2_session *session, unsigned long arg)
685 {
686 int ret = 0;
687 int num_done;
688
689 num_done = atomic_read(&session->num_done);
690 if (unlikely(copy_to_user((void __user *)arg, &num_done, sizeof(int)))) {
691 printk("copy_to_user failed\n");
692 ret = -EFAULT;
693 }
694 return ret;
695 }
696
697
rga2_check_param(const struct rga2_req * req)698 static int rga2_check_param(const struct rga2_req *req)
699 {
700 if(!((req->render_mode == color_fill_mode)))
701 {
702 if (unlikely((req->src.act_w <= 0) || (req->src.act_w > 8192) || (req->src.act_h <= 0) || (req->src.act_h > 8192)))
703 {
704 printk("invalid source resolution act_w = %d, act_h = %d\n", req->src.act_w, req->src.act_h);
705 return -EINVAL;
706 }
707 }
708
709 if(!((req->render_mode == color_fill_mode)))
710 {
711 if (unlikely((req->src.vir_w <= 0) || (req->src.vir_w > 8192) || (req->src.vir_h <= 0) || (req->src.vir_h > 8192)))
712 {
713 printk("invalid source resolution vir_w = %d, vir_h = %d\n", req->src.vir_w, req->src.vir_h);
714 return -EINVAL;
715 }
716 }
717
718 //check dst width and height
719 if (unlikely((req->dst.act_w <= 0) || (req->dst.act_w > 4096) || (req->dst.act_h <= 0) || (req->dst.act_h > 4096)))
720 {
721 printk("invalid destination resolution act_w = %d, act_h = %d\n", req->dst.act_w, req->dst.act_h);
722 return -EINVAL;
723 }
724
725 if (unlikely((req->dst.vir_w <= 0) || (req->dst.vir_w > 4096) || (req->dst.vir_h <= 0) || (req->dst.vir_h > 4096)))
726 {
727 printk("invalid destination resolution vir_w = %d, vir_h = %d\n", req->dst.vir_w, req->dst.vir_h);
728 return -EINVAL;
729 }
730
731 //check src_vir_w
732 if(unlikely(req->src.vir_w < req->src.act_w)){
733 printk("invalid src_vir_w act_w = %d, vir_w = %d\n", req->src.act_w, req->src.vir_w);
734 return -EINVAL;
735 }
736
737 //check dst_vir_w
738 if(unlikely(req->dst.vir_w < req->dst.act_w)){
739 if(req->rotate_mode != 1)
740 {
741 printk("invalid dst_vir_w act_h = %d, vir_h = %d\n", req->dst.act_w, req->dst.vir_w);
742 return -EINVAL;
743 }
744 }
745
746 return 0;
747 }
748
rga2_copy_reg(struct rga2_reg * reg,uint32_t offset)749 static void rga2_copy_reg(struct rga2_reg *reg, uint32_t offset)
750 {
751 uint32_t i;
752 uint32_t *cmd_buf;
753 uint32_t *reg_p;
754
755 if(atomic_read(®->session->task_running) != 0)
756 printk(KERN_ERR "task_running is no zero\n");
757
758 atomic_add(1, &rga2_service.cmd_num);
759 atomic_add(1, ®->session->task_running);
760
761 cmd_buf = (uint32_t *)rga2_service.cmd_buff + offset*32;
762 reg_p = (uint32_t *)reg->cmd_reg;
763
764 for(i=0; i<32; i++)
765 cmd_buf[i] = reg_p[i];
766 }
767
768
rga2_reg_init(rga2_session * session,struct rga2_req * req)769 static struct rga2_reg * rga2_reg_init(rga2_session *session, struct rga2_req *req)
770 {
771 int32_t ret;
772
773 /* Alloc 4k size for rga2_reg use. */
774 struct rga2_reg *reg = (struct rga2_reg *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
775
776 if (NULL == reg) {
777 pr_err("get_zeroed_page fail in rga_reg_init\n");
778 return NULL;
779 }
780
781 reg->session = session;
782 INIT_LIST_HEAD(®->session_link);
783 INIT_LIST_HEAD(®->status_link);
784
785 ret = rga2_get_dma_info(reg, req);
786 if (ret < 0) {
787 pr_err("fail to get dma buffer info!\n");
788 free_page((unsigned long)reg);
789
790 return NULL;
791 }
792
793 if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1)
794 || (req->mmu_info.dst_mmu_flag & 1) || (req->mmu_info.els_mmu_flag & 1))
795 {
796 ret = rga2_set_mmu_info(reg, req);
797 if(ret < 0) {
798 printk("%s, [%d] set mmu info error \n", __FUNCTION__, __LINE__);
799 free_page((unsigned long)reg);
800
801 return NULL;
802 }
803 }
804
805 if (RGA2_gen_reg_info((uint8_t *)reg->cmd_reg, (uint8_t *)reg->csc_reg, req) == -1) {
806 printk("gen reg info error\n");
807 free_page((unsigned long)reg);
808
809 return NULL;
810 }
811
812 mutex_lock(&rga2_service.lock);
813 list_add_tail(®->status_link, &rga2_service.waiting);
814 list_add_tail(®->session_link, &session->waiting);
815 mutex_unlock(&rga2_service.lock);
816
817 return reg;
818 }
819
820
821 /* Caller must hold rga_service.lock */
rga2_reg_deinit(struct rga2_reg * reg)822 static void rga2_reg_deinit(struct rga2_reg *reg)
823 {
824 list_del_init(®->session_link);
825 list_del_init(®->status_link);
826 free_page((unsigned long)reg);
827 }
828
829 /* Caller must hold rga_service.lock */
rga2_reg_from_wait_to_run(struct rga2_reg * reg)830 static void rga2_reg_from_wait_to_run(struct rga2_reg *reg)
831 {
832 list_del_init(®->status_link);
833 list_add_tail(®->status_link, &rga2_service.running);
834
835 list_del_init(®->session_link);
836 list_add_tail(®->session_link, ®->session->running);
837 }
838
839 /* Caller must hold rga_service.lock */
rga2_service_session_clear(rga2_session * session)840 static void rga2_service_session_clear(rga2_session *session)
841 {
842 struct rga2_reg *reg, *n;
843
844 list_for_each_entry_safe(reg, n, &session->waiting, session_link)
845 {
846 rga2_reg_deinit(reg);
847 }
848
849 list_for_each_entry_safe(reg, n, &session->running, session_link)
850 {
851 rga2_reg_deinit(reg);
852 }
853 }
854
855 /* Caller must hold rga_service.lock */
rga2_try_set_reg(void)856 static void rga2_try_set_reg(void)
857 {
858 int i;
859 struct rga2_reg *reg ;
860
861 if (list_empty(&rga2_service.running))
862 {
863 if (!list_empty(&rga2_service.waiting))
864 {
865 /* RGA is idle */
866 reg = list_entry(rga2_service.waiting.next, struct rga2_reg, status_link);
867
868 rga2_power_on();
869 udelay(1);
870
871 rga2_copy_reg(reg, 0);
872 rga2_reg_from_wait_to_run(reg);
873
874 rga2_dma_flush_range(®->cmd_reg[0], ®->cmd_reg[32]);
875
876 //rga2_soft_reset();
877
878 rga2_write(0x0, RGA2_SYS_CTRL);
879
880 /* CMD buff */
881 rga2_write(virt_to_phys(reg->cmd_reg), RGA2_CMD_BASE);
882
883 /* full csc reg */
884 for (i = 0; i < 12; i++) {
885 rga2_write(reg->csc_reg[i], RGA2_CSC_COE_BASE + i * 4);
886 }
887
888 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
889 if (RGA2_TEST_REG) {
890 if (rga2_flag) {
891 int32_t *p;
892
893 p = rga2_service.cmd_buff;
894 INFO("CMD_REG\n");
895 for (i=0; i<8; i++)
896 INFO("%.8x %.8x %.8x %.8x\n",
897 p[0 + i * 4], p[1 + i * 4],
898 p[2 + i * 4], p[3 + i * 4]);
899
900 p = reg->csc_reg;
901 INFO("CSC_REG\n");
902 for (i = 0; i < 3; i++)
903 INFO("%.8x %.8x %.8x %.8x\n",
904 p[0 + i * 4], p[1 + i * 4],
905 p[2 + i * 4], p[3 + i * 4]);
906 }
907 }
908 #endif
909
910 /* master mode */
911 rga2_write((0x1<<1)|(0x1<<2)|(0x1<<5)|(0x1<<6), RGA2_SYS_CTRL);
912
913 /* All CMD finish int */
914 rga2_write(rga2_read(RGA2_INT)|(0x1<<10)|(0x1<<9)|(0x1<<8), RGA2_INT);
915
916 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
917 if (RGA2_TEST_TIME)
918 rga2_start = ktime_get();
919 #endif
920
921 /* Start proc */
922 atomic_set(®->session->done, 0);
923 rga2_write(0x1, RGA2_CMD_CTRL);
924 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
925 if (RGA2_TEST_REG) {
926 if (rga2_flag) {
927 INFO("CMD_READ_BACK_REG\n");
928 for (i=0; i<8; i++)
929 INFO("%.8x %.8x %.8x %.8x\n",
930 rga2_read(0x100 + i * 16 + 0),
931 rga2_read(0x100 + i * 16 + 4),
932 rga2_read(0x100 + i * 16 + 8),
933 rga2_read(0x100 + i * 16 + 12));
934
935 INFO("CSC_READ_BACK_REG\n");
936 for (i = 0; i < 3; i++)
937 INFO("%.8x %.8x %.8x %.8x\n",
938 rga2_read(RGA2_CSC_COE_BASE + i * 16 + 0),
939 rga2_read(RGA2_CSC_COE_BASE + i * 16 + 4),
940 rga2_read(RGA2_CSC_COE_BASE + i * 16 + 8),
941 rga2_read(RGA2_CSC_COE_BASE + i * 16 + 12));
942 }
943
944 }
945 #endif
946 }
947 }
948 }
949
rga2_del_running_list(void)950 static void rga2_del_running_list(void)
951 {
952 struct rga2_mmu_buf_t *tbuf = &rga2_mmu_buf;
953 struct rga2_reg *reg;
954
955 while (!list_empty(&rga2_service.running)) {
956 reg = list_entry(rga2_service.running.next, struct rga2_reg,
957 status_link);
958 if (reg->MMU_len && tbuf) {
959 if (tbuf->back + reg->MMU_len > 2 * tbuf->size)
960 tbuf->back = reg->MMU_len + tbuf->size;
961 else
962 tbuf->back += reg->MMU_len;
963 }
964 rga2_put_dma_info(reg);
965 atomic_sub(1, ®->session->task_running);
966 atomic_sub(1, &rga2_service.total_running);
967
968 if(list_empty(®->session->waiting))
969 {
970 atomic_set(®->session->done, 1);
971 wake_up(®->session->wait);
972 }
973
974 rga2_reg_deinit(reg);
975 }
976 }
977
rga2_del_running_list_timeout(void)978 static void rga2_del_running_list_timeout(void)
979 {
980 struct rga2_mmu_buf_t *tbuf = &rga2_mmu_buf;
981 struct rga2_reg *reg;
982
983 while (!list_empty(&rga2_service.running)) {
984 reg = list_entry(rga2_service.running.next, struct rga2_reg,
985 status_link);
986 #if 0
987 kfree(reg->MMU_base);
988 #endif
989 if (reg->MMU_len && tbuf) {
990 if (tbuf->back + reg->MMU_len > 2 * tbuf->size)
991 tbuf->back = reg->MMU_len + tbuf->size;
992 else
993 tbuf->back += reg->MMU_len;
994 }
995 rga2_put_dma_info(reg);
996 atomic_sub(1, ®->session->task_running);
997 atomic_sub(1, &rga2_service.total_running);
998 rga2_soft_reset();
999 if (list_empty(®->session->waiting)) {
1000 atomic_set(®->session->done, 1);
1001 wake_up(®->session->wait);
1002 }
1003 rga2_reg_deinit(reg);
1004 }
1005 return;
1006 }
1007
rga2_blit_flush_cache(rga2_session * session,struct rga2_req * req)1008 static int rga2_blit_flush_cache(rga2_session *session, struct rga2_req *req)
1009 {
1010 int ret = 0;
1011 /* Alloc 4k size for rga2_reg use. */
1012 struct rga2_reg *reg = (struct rga2_reg *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
1013 struct rga2_mmu_buf_t *tbuf = &rga2_mmu_buf;
1014
1015 if (!reg) {
1016 pr_err("%s, [%d] kzalloc error\n", __func__, __LINE__);
1017 ret = -ENOMEM;
1018 goto err_free_reg;
1019 }
1020
1021 ret = rga2_get_dma_info(reg, req);
1022 if (ret < 0) {
1023 pr_err("fail to get dma buffer info!\n");
1024 goto err_free_reg;
1025 }
1026
1027 if ((req->mmu_info.src0_mmu_flag & 1) || (req->mmu_info.src1_mmu_flag & 1) ||
1028 (req->mmu_info.dst_mmu_flag & 1) || (req->mmu_info.els_mmu_flag & 1)) {
1029 reg->MMU_map = true;
1030 ret = rga2_set_mmu_info(reg, req);
1031 if (ret < 0) {
1032 pr_err("%s, [%d] set mmu info error\n", __func__, __LINE__);
1033 ret = -EFAULT;
1034 goto err_free_reg;
1035 }
1036 }
1037 if (reg->MMU_len && tbuf) {
1038 if (tbuf->back + reg->MMU_len > 2 * tbuf->size)
1039 tbuf->back = reg->MMU_len + tbuf->size;
1040 else
1041 tbuf->back += reg->MMU_len;
1042 }
1043 err_free_reg:
1044 free_page((unsigned long)reg);
1045
1046 return ret;
1047 }
1048
rga2_blit(rga2_session * session,struct rga2_req * req)1049 static int rga2_blit(rga2_session *session, struct rga2_req *req)
1050 {
1051 int ret = -1;
1052 int num = 0;
1053 struct rga2_reg *reg;
1054
1055 /* check value if legal */
1056 ret = rga2_check_param(req);
1057 if (ret == -EINVAL) {
1058 pr_err("req argument is inval\n");
1059 return ret;
1060 }
1061
1062 reg = rga2_reg_init(session, req);
1063 if (reg == NULL) {
1064 pr_err("init reg fail\n");
1065 return -EFAULT;
1066 }
1067
1068 num = 1;
1069 mutex_lock(&rga2_service.lock);
1070 atomic_add(num, &rga2_service.total_running);
1071 rga2_try_set_reg();
1072 mutex_unlock(&rga2_service.lock);
1073
1074 return 0;
1075 }
1076
rga2_blit_async(rga2_session * session,struct rga2_req * req)1077 static int rga2_blit_async(rga2_session *session, struct rga2_req *req)
1078 {
1079 int ret = -1;
1080 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1081 if (RGA2_TEST_MSG) {
1082 if (1) {
1083 print_debug_info(req);
1084 rga2_flag = 1;
1085 INFO("*** rga_blit_async proc ***\n");
1086 } else {
1087 rga2_flag = 0;
1088 }
1089 }
1090 #endif
1091 atomic_set(&session->done, 0);
1092 ret = rga2_blit(session, req);
1093
1094 return ret;
1095 }
1096
rga2_blit_sync(rga2_session * session,struct rga2_req * req)1097 static int rga2_blit_sync(rga2_session *session, struct rga2_req *req)
1098 {
1099 struct rga2_req req_bak;
1100 int restore = 0;
1101 int try = 10;
1102 int ret = -1;
1103 int ret_timeout = 0;
1104
1105 memcpy(&req_bak, req, sizeof(req_bak));
1106 retry:
1107
1108 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1109 if (RGA2_TEST_MSG) {
1110 if (1) {
1111 print_debug_info(req);
1112 rga2_flag = 1;
1113 INFO("*** rga2_blit_sync proc ***\n");
1114 } else {
1115 rga2_flag = 0;
1116 }
1117 }
1118 if (RGA2_CHECK_MODE) {
1119 rga2_align_check(req);
1120 /*rga2_scale_check(req);*/
1121 }
1122 #endif
1123
1124 atomic_set(&session->done, 0);
1125
1126 ret = rga2_blit(session, req);
1127 if(ret < 0)
1128 return ret;
1129
1130 if (rk3368)
1131 ret_timeout = wait_event_timeout(session->wait,
1132 atomic_read(&session->done),
1133 RGA2_TIMEOUT_DELAY / 4);
1134 else
1135 ret_timeout = wait_event_timeout(session->wait,
1136 atomic_read(&session->done),
1137 RGA2_TIMEOUT_DELAY);
1138
1139 if (unlikely(ret_timeout < 0)) {
1140 u32 i;
1141 u32 *p;
1142
1143 p = rga2_service.cmd_buff;
1144 pr_err("Rga sync pid %d wait task ret %d\n", session->pid,
1145 ret_timeout);
1146 pr_err("interrupt = %x status = %x\n",
1147 rga2_read(RGA2_INT), rga2_read(RGA2_STATUS));
1148 rga2_printf_cmd_buf(p);
1149 DBG("rga2 CMD\n");
1150 for (i = 0; i < 7; i++)
1151 DBG("%.8x %.8x %.8x %.8x\n",
1152 p[0 + i * 4], p[1 + i * 4],
1153 p[2 + i * 4], p[3 + i * 4]);
1154 mutex_lock(&rga2_service.lock);
1155 rga2_del_running_list();
1156 mutex_unlock(&rga2_service.lock);
1157 ret = ret_timeout;
1158 } else if (ret_timeout == 0) {
1159 u32 i;
1160 u32 *p;
1161
1162 p = rga2_service.cmd_buff;
1163 pr_err("Rga sync pid %d wait %d task done timeout\n",
1164 session->pid, atomic_read(&session->task_running));
1165 pr_err("interrupt = %x status = %x\n",
1166 rga2_read(RGA2_INT), rga2_read(RGA2_STATUS));
1167 rga2_printf_cmd_buf(p);
1168 DBG("rga2 CMD\n");
1169 for (i = 0; i < 7; i++)
1170 DBG("%.8x %.8x %.8x %.8x\n",
1171 p[0 + i * 4], p[1 + i * 4],
1172 p[2 + i * 4], p[3 + i * 4]);
1173 mutex_lock(&rga2_service.lock);
1174 rga2_del_running_list_timeout();
1175 rga2_try_set_reg();
1176 mutex_unlock(&rga2_service.lock);
1177 ret = -ETIMEDOUT;
1178 }
1179
1180 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1181 if (RGA2_TEST_TIME) {
1182 rga2_end = ktime_get();
1183 rga2_end = ktime_sub(rga2_end, rga2_start);
1184 DBG("sync one cmd end time %d\n", (int)ktime_to_us(rga2_end));
1185 }
1186 #endif
1187 if (ret == -ETIMEDOUT && try--) {
1188 memcpy(req, &req_bak, sizeof(req_bak));
1189 /*
1190 * if rga work timeout with scaling, need do a non-scale work
1191 * first, restore hardware status, then do actually work.
1192 */
1193 if (req->src.act_w != req->dst.act_w ||
1194 req->src.act_h != req->dst.act_h) {
1195 req->src.act_w = MIN(320, MIN(req->src.act_w,
1196 req->dst.act_w));
1197 req->src.act_h = MIN(240, MIN(req->src.act_h,
1198 req->dst.act_h));
1199 req->dst.act_w = req->src.act_w;
1200 req->dst.act_h = req->src.act_h;
1201 restore = 1;
1202 }
1203 goto retry;
1204 }
1205 if (!ret && restore) {
1206 memcpy(req, &req_bak, sizeof(req_bak));
1207 restore = 0;
1208 goto retry;
1209 }
1210
1211 return ret;
1212 }
1213
rga_ioctl(struct file * file,uint32_t cmd,unsigned long arg)1214 static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
1215 {
1216 struct rga2_drvdata_t *rga = rga2_drvdata;
1217 struct rga2_req req, req_first;
1218 struct rga_req req_rga;
1219 int ret = 0;
1220 int major_version = 0, minor_version = 0;
1221 char version[16] = {0};
1222 rga2_session *session;
1223
1224 if (!rga) {
1225 pr_err("rga2_drvdata is null, rga2 is not init\n");
1226 return -ENODEV;
1227 }
1228 memset(&req, 0x0, sizeof(req));
1229
1230 mutex_lock(&rga2_service.mutex);
1231
1232 session = (rga2_session *)file->private_data;
1233
1234 if (NULL == session)
1235 {
1236 printk("%s [%d] rga thread session is null\n",__FUNCTION__,__LINE__);
1237 mutex_unlock(&rga2_service.mutex);
1238 return -EINVAL;
1239 }
1240
1241 memset(&req, 0x0, sizeof(req));
1242 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1243 if (RGA2_TEST_MSG)
1244 INFO("cmd is %s\n", rga2_get_cmd_mode_str(cmd));
1245 if (RGA2_NONUSE) {
1246 mutex_unlock(&rga2_service.mutex);
1247 return 0;
1248 }
1249 #endif
1250 switch (cmd)
1251 {
1252 case RGA_BLIT_SYNC:
1253 if (unlikely(copy_from_user(&req_rga, (struct rga_req*)arg, sizeof(struct rga_req))))
1254 {
1255 ERR("copy_from_user failed\n");
1256 ret = -EFAULT;
1257 break;
1258 }
1259 RGA_MSG_2_RGA2_MSG(&req_rga, &req);
1260
1261 if (first_RGA2_proc == 0 && req.render_mode == bitblt_mode && rga2_service.dev_mode == 1) {
1262 memcpy(&req_first, &req, sizeof(struct rga2_req));
1263 if ((req_first.src.act_w != req_first.dst.act_w)
1264 || (req_first.src.act_h != req_first.dst.act_h)) {
1265 req_first.src.act_w = MIN(320, MIN(req_first.src.act_w, req_first.dst.act_w));
1266 req_first.src.act_h = MIN(240, MIN(req_first.src.act_h, req_first.dst.act_h));
1267 req_first.dst.act_w = req_first.src.act_w;
1268 req_first.dst.act_h = req_first.src.act_h;
1269 ret = rga2_blit_async(session, &req_first);
1270 }
1271 ret = rga2_blit_sync(session, &req);
1272 first_RGA2_proc = 1;
1273 }
1274 else {
1275 ret = rga2_blit_sync(session, &req);
1276 }
1277 break;
1278 case RGA_BLIT_ASYNC:
1279 if (unlikely(copy_from_user(&req_rga, (struct rga_req*)arg, sizeof(struct rga_req))))
1280 {
1281 ERR("copy_from_user failed\n");
1282 ret = -EFAULT;
1283 break;
1284 }
1285
1286 RGA_MSG_2_RGA2_MSG(&req_rga, &req);
1287 if (first_RGA2_proc == 0 && req.render_mode == bitblt_mode && rga2_service.dev_mode == 1) {
1288 memcpy(&req_first, &req, sizeof(struct rga2_req));
1289 if ((req_first.src.act_w != req_first.dst.act_w)
1290 || (req_first.src.act_h != req_first.dst.act_h)
1291 || rk3368) {
1292 req_first.src.act_w = MIN(320, MIN(req_first.src.act_w, req_first.dst.act_w));
1293 req_first.src.act_h = MIN(240, MIN(req_first.src.act_h, req_first.dst.act_h));
1294 req_first.dst.act_w = req_first.src.act_w;
1295 req_first.dst.act_h = req_first.src.act_h;
1296 if (rk3368)
1297 ret = rga2_blit_sync(session, &req_first);
1298 else
1299 ret = rga2_blit_async(session, &req_first);
1300 }
1301 ret = rga2_blit_async(session, &req);
1302 first_RGA2_proc = 1;
1303 }
1304 else {
1305 if (rk3368)
1306 {
1307 memcpy(&req_first, &req, sizeof(struct rga2_req));
1308
1309 /*
1310 * workround for gts
1311 * run gts --skip-all-system-status-check --ignore-business-logic-failure -m GtsMediaTestCases -t com.google.android.media.gts.WidevineYouTubePerformanceTests#testClear1080P30
1312 */
1313 if ((req_first.src.act_w == 1920) && (req_first.src.act_h == 1008) && (req_first.src.act_h == req_first.dst.act_w)) {
1314 printk("src : aw=%d ah=%d vw=%d vh=%d \n",
1315 req_first.src.act_w, req_first.src.act_h, req_first.src.vir_w, req_first.src.vir_h);
1316 printk("dst : aw=%d ah=%d vw=%d vh=%d \n",
1317 req_first.dst.act_w, req_first.dst.act_h, req_first.dst.vir_w, req_first.dst.vir_h);
1318 } else {
1319 req_first.src.act_w = MIN(320, MIN(req_first.src.act_w, req_first.dst.act_w));
1320 req_first.src.act_h = MIN(240, MIN(req_first.src.act_h, req_first.dst.act_h));
1321 req_first.dst.act_w = req_first.src.act_w;
1322 req_first.dst.act_h = req_first.src.act_h;
1323 ret = rga2_blit_sync(session, &req_first);
1324 }
1325 }
1326 ret = rga2_blit_async(session, &req);
1327 }
1328 break;
1329 case RGA_CACHE_FLUSH:
1330 if (unlikely(copy_from_user(&req_rga, (struct rga_req*)arg, sizeof(struct rga_req))))
1331 {
1332 ERR("copy_from_user failed\n");
1333 ret = -EFAULT;
1334 break;
1335 }
1336 RGA_MSG_2_RGA2_MSG(&req_rga, &req);
1337 ret = rga2_blit_flush_cache(session, &req);
1338 break;
1339 case RGA2_BLIT_SYNC:
1340 if (unlikely(copy_from_user(&req, (struct rga2_req*)arg, sizeof(struct rga2_req))))
1341 {
1342 ERR("copy_from_user failed\n");
1343 ret = -EFAULT;
1344 break;
1345 }
1346 ret = rga2_blit_sync(session, &req);
1347 break;
1348 case RGA2_BLIT_ASYNC:
1349 if (unlikely(copy_from_user(&req, (struct rga2_req*)arg, sizeof(struct rga2_req))))
1350 {
1351 ERR("copy_from_user failed\n");
1352 ret = -EFAULT;
1353 break;
1354 }
1355
1356 if((atomic_read(&rga2_service.total_running) > 16))
1357 {
1358 ret = rga2_blit_sync(session, &req);
1359 }
1360 else
1361 {
1362 ret = rga2_blit_async(session, &req);
1363 }
1364 break;
1365 case RGA_FLUSH:
1366 case RGA2_FLUSH:
1367 ret = rga2_flush(session, arg);
1368 break;
1369 case RGA_GET_RESULT:
1370 case RGA2_GET_RESULT:
1371 ret = rga2_get_result(session, arg);
1372 break;
1373 case RGA_GET_VERSION:
1374 sscanf(rga->version, "%x.%x.%*x", &major_version, &minor_version);
1375 snprintf(version, 5, "%x.%02x", major_version, minor_version);
1376
1377 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1378 ret = copy_to_user((void *)arg, version, sizeof(rga->version));
1379 #else
1380 ret = copy_to_user((void *)arg, RGA2_VERSION, sizeof(RGA2_VERSION));
1381 #endif
1382 if (ret != 0)
1383 ret = -EFAULT;
1384 break;
1385 case RGA2_GET_VERSION:
1386 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1387 ret = copy_to_user((void *)arg, rga->version, sizeof(rga->version));
1388 #else
1389 ret = copy_to_user((void *)arg, RGA2_VERSION, sizeof(RGA2_VERSION));
1390 #endif
1391 if (ret != 0)
1392 ret = -EFAULT;
1393 break;
1394 default:
1395 ERR("unknown ioctl cmd!\n");
1396 ret = -EINVAL;
1397 break;
1398 }
1399
1400 mutex_unlock(&rga2_service.mutex);
1401
1402 return ret;
1403 }
1404
1405 #ifdef CONFIG_COMPAT
compat_rga_ioctl(struct file * file,uint32_t cmd,unsigned long arg)1406 static long compat_rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)
1407 {
1408 struct rga2_drvdata_t *rga = rga2_drvdata;
1409 struct rga2_req req, req_first;
1410 struct rga_req_32 req_rga;
1411 int ret = 0;
1412 rga2_session *session;
1413
1414 if (!rga) {
1415 pr_err("rga2_drvdata is null, rga2 is not init\n");
1416 return -ENODEV;
1417 }
1418 memset(&req, 0x0, sizeof(req));
1419
1420 mutex_lock(&rga2_service.mutex);
1421
1422 session = (rga2_session *)file->private_data;
1423
1424 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1425 if (RGA2_TEST_MSG)
1426 INFO("using %s\n", __func__);
1427 #endif
1428
1429 if (NULL == session) {
1430 ERR("%s [%d] rga thread session is null\n", __func__, __LINE__);
1431 mutex_unlock(&rga2_service.mutex);
1432 return -EINVAL;
1433 }
1434
1435 memset(&req, 0x0, sizeof(req));
1436
1437 switch (cmd) {
1438 case RGA_BLIT_SYNC:
1439 if (unlikely(copy_from_user(&req_rga, compat_ptr((compat_uptr_t)arg), sizeof(struct rga_req_32))))
1440 {
1441 ERR("copy_from_user failed\n");
1442 ret = -EFAULT;
1443 break;
1444 }
1445
1446 RGA_MSG_2_RGA2_MSG_32(&req_rga, &req);
1447
1448 if (first_RGA2_proc == 0 && req.render_mode == bitblt_mode && rga2_service.dev_mode == 1) {
1449 memcpy(&req_first, &req, sizeof(struct rga2_req));
1450 if ((req_first.src.act_w != req_first.dst.act_w)
1451 || (req_first.src.act_h != req_first.dst.act_h)) {
1452 req_first.src.act_w = MIN(320, MIN(req_first.src.act_w, req_first.dst.act_w));
1453 req_first.src.act_h = MIN(240, MIN(req_first.src.act_h, req_first.dst.act_h));
1454 req_first.dst.act_w = req_first.src.act_w;
1455 req_first.dst.act_h = req_first.src.act_h;
1456 ret = rga2_blit_async(session, &req_first);
1457 }
1458 ret = rga2_blit_sync(session, &req);
1459 first_RGA2_proc = 1;
1460 }
1461 else {
1462 ret = rga2_blit_sync(session, &req);
1463 }
1464 break;
1465 case RGA_BLIT_ASYNC:
1466 if (unlikely(copy_from_user(&req_rga, compat_ptr((compat_uptr_t)arg), sizeof(struct rga_req_32))))
1467 {
1468 ERR("copy_from_user failed\n");
1469 ret = -EFAULT;
1470 break;
1471 }
1472 RGA_MSG_2_RGA2_MSG_32(&req_rga, &req);
1473
1474 if (first_RGA2_proc == 0 && req.render_mode == bitblt_mode && rga2_service.dev_mode == 1) {
1475 memcpy(&req_first, &req, sizeof(struct rga2_req));
1476 if ((req_first.src.act_w != req_first.dst.act_w)
1477 || (req_first.src.act_h != req_first.dst.act_h)) {
1478 req_first.src.act_w = MIN(320, MIN(req_first.src.act_w, req_first.dst.act_w));
1479 req_first.src.act_h = MIN(240, MIN(req_first.src.act_h, req_first.dst.act_h));
1480 req_first.dst.act_w = req_first.src.act_w;
1481 req_first.dst.act_h = req_first.src.act_h;
1482 ret = rga2_blit_async(session, &req_first);
1483 }
1484 ret = rga2_blit_sync(session, &req);
1485 first_RGA2_proc = 1;
1486 }
1487 else {
1488 ret = rga2_blit_sync(session, &req);
1489 }
1490
1491 //if((atomic_read(&rga2_service.total_running) > 8))
1492 // ret = rga2_blit_sync(session, &req);
1493 //else
1494 // ret = rga2_blit_async(session, &req);
1495
1496 break;
1497 case RGA2_BLIT_SYNC:
1498 if (unlikely(copy_from_user(&req, compat_ptr((compat_uptr_t)arg), sizeof(struct rga2_req))))
1499 {
1500 ERR("copy_from_user failed\n");
1501 ret = -EFAULT;
1502 break;
1503 }
1504 ret = rga2_blit_sync(session, &req);
1505 break;
1506 case RGA2_BLIT_ASYNC:
1507 if (unlikely(copy_from_user(&req, compat_ptr((compat_uptr_t)arg), sizeof(struct rga2_req))))
1508 {
1509 ERR("copy_from_user failed\n");
1510 ret = -EFAULT;
1511 break;
1512 }
1513
1514 if((atomic_read(&rga2_service.total_running) > 16))
1515 ret = rga2_blit_sync(session, &req);
1516 else
1517 ret = rga2_blit_async(session, &req);
1518
1519 break;
1520 case RGA_FLUSH:
1521 case RGA2_FLUSH:
1522 ret = rga2_flush(session, arg);
1523 break;
1524 case RGA_GET_RESULT:
1525 case RGA2_GET_RESULT:
1526 ret = rga2_get_result(session, arg);
1527 break;
1528 case RGA_GET_VERSION:
1529 case RGA2_GET_VERSION:
1530 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1531 ret = copy_to_user((void *)arg, rga->version, 16);
1532 #else
1533 ret = copy_to_user((void *)arg, RGA2_VERSION, sizeof(RGA2_VERSION));
1534 #endif
1535 if (ret != 0)
1536 ret = -EFAULT;
1537 break;
1538 default:
1539 ERR("unknown ioctl cmd!\n");
1540 ret = -EINVAL;
1541 break;
1542 }
1543
1544 mutex_unlock(&rga2_service.mutex);
1545
1546 return ret;
1547 }
1548 #endif
1549
1550
rga2_ioctl_kernel(struct rga_req * req_rga)1551 static long rga2_ioctl_kernel(struct rga_req *req_rga)
1552 {
1553 int ret = 0;
1554 rga2_session *session;
1555 struct rga2_req req;
1556
1557 memset(&req, 0x0, sizeof(req));
1558 mutex_lock(&rga2_service.mutex);
1559 session = &rga2_session_global;
1560 if (NULL == session)
1561 {
1562 ERR("%s [%d] rga thread session is null\n", __func__, __LINE__);
1563 mutex_unlock(&rga2_service.mutex);
1564 return -EINVAL;
1565 }
1566
1567 RGA_MSG_2_RGA2_MSG(req_rga, &req);
1568 ret = rga2_blit_sync(session, &req);
1569 mutex_unlock(&rga2_service.mutex);
1570
1571 return ret;
1572 }
1573
1574
rga2_open(struct inode * inode,struct file * file)1575 static int rga2_open(struct inode *inode, struct file *file)
1576 {
1577 rga2_session *session = kzalloc(sizeof(rga2_session), GFP_KERNEL);
1578
1579 if (NULL == session) {
1580 pr_err("unable to allocate memory for rga_session.");
1581 return -ENOMEM;
1582 }
1583
1584 session->pid = current->pid;
1585 INIT_LIST_HEAD(&session->waiting);
1586 INIT_LIST_HEAD(&session->running);
1587 INIT_LIST_HEAD(&session->list_session);
1588 init_waitqueue_head(&session->wait);
1589 mutex_lock(&rga2_service.lock);
1590 list_add_tail(&session->list_session, &rga2_service.session);
1591 mutex_unlock(&rga2_service.lock);
1592 atomic_set(&session->task_running, 0);
1593 atomic_set(&session->num_done, 0);
1594 file->private_data = (void *)session;
1595
1596 return nonseekable_open(inode, file);
1597 }
1598
rga2_release(struct inode * inode,struct file * file)1599 static int rga2_release(struct inode *inode, struct file *file)
1600 {
1601 int task_running;
1602 rga2_session *session = (rga2_session *)file->private_data;
1603
1604 if (NULL == session)
1605 return -EINVAL;
1606
1607 task_running = atomic_read(&session->task_running);
1608 if (task_running)
1609 {
1610 pr_err("rga2_service session %d still has %d task running when closing\n", session->pid, task_running);
1611 msleep(100);
1612 }
1613
1614 wake_up(&session->wait);
1615 mutex_lock(&rga2_service.lock);
1616 list_del(&session->list_session);
1617 rga2_service_session_clear(session);
1618 kfree(session);
1619 mutex_unlock(&rga2_service.lock);
1620
1621 return 0;
1622 }
1623
RGA2_flush_page(void)1624 static void RGA2_flush_page(void)
1625 {
1626 struct rga2_reg *reg;
1627 int i;
1628
1629 reg = list_entry(rga2_service.running.prev,
1630 struct rga2_reg, status_link);
1631
1632 if (reg == NULL)
1633 return;
1634
1635 if (reg->MMU_src0_base != NULL) {
1636 for (i = 0; i < reg->MMU_src0_count; i++)
1637 rga2_dma_flush_page(phys_to_page(reg->MMU_src0_base[i]),
1638 MMU_UNMAP_CLEAN);
1639 }
1640
1641 if (reg->MMU_src1_base != NULL) {
1642 for (i = 0; i < reg->MMU_src1_count; i++)
1643 rga2_dma_flush_page(phys_to_page(reg->MMU_src1_base[i]),
1644 MMU_UNMAP_CLEAN);
1645 }
1646
1647 if (reg->MMU_dst_base != NULL) {
1648 for (i = 0; i < reg->MMU_dst_count; i++)
1649 rga2_dma_flush_page(phys_to_page(reg->MMU_dst_base[i]),
1650 MMU_UNMAP_INVALID);
1651 }
1652 }
1653
rga2_irq_thread(int irq,void * dev_id)1654 static irqreturn_t rga2_irq_thread(int irq, void *dev_id)
1655 {
1656 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1657 if (RGA2_INT_FLAG)
1658 INFO("irqthread INT[%x],STATS[%x]\n", rga2_read(RGA2_INT),
1659 rga2_read(RGA2_STATUS));
1660 #endif
1661 RGA2_flush_page();
1662 mutex_lock(&rga2_service.lock);
1663 if (rga2_service.enable) {
1664 rga2_del_running_list();
1665 rga2_try_set_reg();
1666 }
1667 mutex_unlock(&rga2_service.lock);
1668
1669 return IRQ_HANDLED;
1670 }
1671
rga2_irq(int irq,void * dev_id)1672 static irqreturn_t rga2_irq(int irq, void *dev_id)
1673 {
1674 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1675 if (RGA2_INT_FLAG)
1676 INFO("irq INT[%x], STATS[%x]\n", rga2_read(RGA2_INT),
1677 rga2_read(RGA2_STATUS));
1678 #endif
1679 /*if error interrupt then soft reset hardware*/
1680 if (rga2_read(RGA2_INT) & 0x01) {
1681 pr_err("Rga err irq! INT[%x],STATS[%x]\n",
1682 rga2_read(RGA2_INT), rga2_read(RGA2_STATUS));
1683 rga2_soft_reset();
1684 }
1685 /*clear INT */
1686 rga2_write(rga2_read(RGA2_INT) | (0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7), RGA2_INT);
1687
1688 return IRQ_WAKE_THREAD;
1689 }
1690
1691 struct file_operations rga2_fops = {
1692 .owner = THIS_MODULE,
1693 .open = rga2_open,
1694 .release = rga2_release,
1695 .unlocked_ioctl = rga_ioctl,
1696 #ifdef CONFIG_COMPAT
1697 .compat_ioctl = compat_rga_ioctl,
1698 #endif
1699 };
1700
1701 static struct miscdevice rga2_dev ={
1702 .minor = RGA2_MAJOR,
1703 .name = "rga",
1704 .fops = &rga2_fops,
1705 };
1706
1707 static const struct of_device_id rockchip_rga_dt_ids[] = {
1708 { .compatible = "rockchip,rga2", },
1709 {},
1710 };
1711
1712 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
rga2_debugger_init(struct rga_debugger ** debugger_p)1713 static int rga2_debugger_init(struct rga_debugger **debugger_p)
1714 {
1715 struct rga_debugger *debugger;
1716
1717 *debugger_p = kzalloc(sizeof(struct rga_debugger), GFP_KERNEL);
1718 if (*debugger_p == NULL) {
1719 ERR("can not alloc for rga2 debugger\n");
1720 return -ENOMEM;
1721 }
1722
1723 debugger = *debugger_p;
1724
1725 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUG_FS
1726 mutex_init(&debugger->debugfs_lock);
1727 INIT_LIST_HEAD(&debugger->debugfs_entry_list);
1728 #endif
1729
1730 #ifdef CONFIG_ROCKCHIP_RGA2_PROC_FS
1731 mutex_init(&debugger->procfs_lock);
1732 INIT_LIST_HEAD(&debugger->procfs_entry_list);
1733 #endif
1734
1735 rga2_debugfs_init();
1736 rga2_procfs_init();
1737
1738 return 0;
1739 }
1740
rga2_debugger_remove(struct rga_debugger ** debugger_p)1741 static int rga2_debugger_remove(struct rga_debugger **debugger_p)
1742 {
1743 rga2_debugfs_remove();
1744 rga2_procfs_remove();
1745
1746 kfree(*debugger_p);
1747 *debugger_p = NULL;
1748
1749 return 0;
1750 }
1751 #endif
1752
rga2_drv_probe(struct platform_device * pdev)1753 static int rga2_drv_probe(struct platform_device *pdev)
1754 {
1755 struct rga2_drvdata_t *data;
1756 struct resource *res;
1757 int ret = 0;
1758 struct device_node *np = pdev->dev.of_node;
1759
1760 mutex_init(&rga2_service.lock);
1761 mutex_init(&rga2_service.mutex);
1762 atomic_set(&rga2_service.total_running, 0);
1763 atomic_set(&rga2_service.src_format_swt, 0);
1764 rga2_service.last_prc_src_format = 1; /* default is yuv first*/
1765 rga2_service.enable = false;
1766
1767 rga2_ioctl_kernel_p = rga2_ioctl_kernel;
1768
1769 data = devm_kzalloc(&pdev->dev, sizeof(struct rga2_drvdata_t), GFP_KERNEL);
1770 if(NULL == data)
1771 {
1772 ERR("failed to allocate driver data.\n");
1773 return -ENOMEM;
1774 }
1775
1776 INIT_DELAYED_WORK(&data->power_off_work, rga2_power_off_work);
1777 wake_lock_init(&data->wake_lock, WAKE_LOCK_SUSPEND, "rga");
1778
1779 data->clk_rga2 = devm_clk_get(&pdev->dev, "clk_rga");
1780 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1781 pm_runtime_enable(&pdev->dev);
1782 #else
1783 data->pd_rga2 = devm_clk_get(&pdev->dev, "pd_rga");
1784 #endif
1785 data->aclk_rga2 = devm_clk_get(&pdev->dev, "aclk_rga");
1786 data->hclk_rga2 = devm_clk_get(&pdev->dev, "hclk_rga");
1787
1788 /* map the registers */
1789 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1790 data->rga_base = devm_ioremap_resource(&pdev->dev, res);
1791 if (!data->rga_base) {
1792 ERR("rga ioremap failed\n");
1793 ret = -ENOENT;
1794 goto err_ioremap;
1795 }
1796
1797 /* get the IRQ */
1798 data->irq = platform_get_irq(pdev, 0);
1799 if (data->irq <= 0) {
1800 ERR("failed to get rga irq resource (%d).\n", data->irq);
1801 ret = data->irq;
1802 goto err_irq;
1803 }
1804
1805 /* request the IRQ */
1806 ret = devm_request_threaded_irq(&pdev->dev, data->irq, rga2_irq, rga2_irq_thread, 0, "rga", pdev);
1807 if (ret)
1808 {
1809 ERR("rga request_irq failed (%d).\n", ret);
1810 goto err_irq;
1811 }
1812
1813 platform_set_drvdata(pdev, data);
1814 data->dev = &pdev->dev;
1815 rga2_drvdata = data;
1816 of_property_read_u32(np, "dev_mode", &rga2_service.dev_mode);
1817 if (of_machine_is_compatible("rockchip,rk3368"))
1818 rk3368 = 1;
1819
1820 #if defined(CONFIG_ION_ROCKCHIP) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
1821 data->ion_client = rockchip_ion_client_create("rga");
1822 if (IS_ERR(data->ion_client)) {
1823 dev_err(&pdev->dev, "failed to create ion client for rga");
1824 return PTR_ERR(data->ion_client);
1825 } else {
1826 dev_info(&pdev->dev, "rga ion client create success!\n");
1827 }
1828 #endif
1829
1830 ret = misc_register(&rga2_dev);
1831 if(ret)
1832 {
1833 ERR("cannot register miscdev (%d)\n", ret);
1834 goto err_misc_register;
1835 }
1836
1837 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1838 rga2_debugger_init(&rga2_drvdata->debugger);
1839 #endif
1840
1841 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
1842 rga2_init_version();
1843 INFO("Driver loaded successfully ver:%s\n", rga2_drvdata->version);
1844 #else
1845 INFO("Driver loaded successfully\n");
1846 #endif
1847 return 0;
1848
1849 err_misc_register:
1850 free_irq(data->irq, pdev);
1851 err_irq:
1852 iounmap(data->rga_base);
1853 err_ioremap:
1854 wake_lock_destroy(&data->wake_lock);
1855 //kfree(data);
1856
1857 return ret;
1858 }
1859
rga2_drv_remove(struct platform_device * pdev)1860 static int rga2_drv_remove(struct platform_device *pdev)
1861 {
1862 struct rga2_drvdata_t *data = platform_get_drvdata(pdev);
1863 DBG("%s [%d]\n",__FUNCTION__,__LINE__);
1864
1865 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
1866 rga2_debugger_remove(&data->debugger);
1867 #endif
1868
1869 wake_lock_destroy(&data->wake_lock);
1870 misc_deregister(&(data->miscdev));
1871 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
1872 free_irq(data->irq, &data->miscdev);
1873 iounmap((void __iomem *)(data->rga_base));
1874
1875 devm_clk_put(&pdev->dev, data->clk_rga2);
1876 devm_clk_put(&pdev->dev, data->aclk_rga2);
1877 devm_clk_put(&pdev->dev, data->hclk_rga2);
1878 pm_runtime_disable(&pdev->dev);
1879 #endif
1880
1881 //kfree(data);
1882 return 0;
1883 }
1884
1885 static struct platform_driver rga2_driver = {
1886 .probe = rga2_drv_probe,
1887 .remove = rga2_drv_remove,
1888 .driver = {
1889 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0))
1890 .owner = THIS_MODULE,
1891 #endif
1892 .name = "rga2",
1893 .of_match_table = of_match_ptr(rockchip_rga_dt_ids),
1894 },
1895 };
1896
1897 #ifdef CONFIG_ROCKCHIP_RGA2_DEBUGGER
rga2_slt(void)1898 void rga2_slt(void)
1899 {
1900 int i;
1901 int src_size, dst_size, src_order, dst_order;
1902 int err_count = 0, right_count = 0;
1903 int task_running;
1904 unsigned int srcW, srcH, dstW, dstH;
1905 unsigned int *pstd, *pnow;
1906 unsigned long *src_vir, *dst_vir;
1907 struct rga2_req req;
1908 rga2_session session;
1909
1910 srcW = 400;
1911 srcH = 200;
1912 dstW = 400;
1913 dstH = 200;
1914
1915 src_size = srcW * srcH * 4;
1916 dst_size = dstW * dstH * 4;
1917
1918 src_order = get_order(src_size);
1919 src_vir = (unsigned long *)__get_free_pages(GFP_KERNEL | GFP_DMA32, src_order);
1920 if (src_vir == NULL) {
1921 ERR("%s[%d], can not alloc pages for src, order = %d\n",
1922 __func__, __LINE__, src_order);
1923 return;
1924 }
1925
1926 dst_order = get_order(dst_size);
1927 dst_vir = (unsigned long *)__get_free_pages(GFP_KERNEL | GFP_DMA32, dst_order);
1928 if (dst_vir == NULL) {
1929 ERR("%s[%d], can not alloc pages for dst, order = %d\n",
1930 __func__, __LINE__, dst_order);
1931 return;
1932 }
1933
1934 /* Init session */
1935 session.pid = current->pid;
1936
1937 INIT_LIST_HEAD(&session.waiting);
1938 INIT_LIST_HEAD(&session.running);
1939 INIT_LIST_HEAD(&session.list_session);
1940 init_waitqueue_head(&session.wait);
1941 mutex_lock(&rga2_service.lock);
1942 list_add_tail(&session.list_session, &rga2_service.session);
1943 mutex_unlock(&rga2_service.lock);
1944 atomic_set(&session.task_running, 0);
1945 atomic_set(&session.num_done, 0);
1946
1947 INFO("**********************************\n");
1948 INFO("************ RGA_TEST ************\n");
1949 INFO("**********************************\n");
1950
1951 memset(src_vir, 0x50, src_size);
1952 memset(dst_vir, 0x50, dst_size);
1953
1954 rga2_dma_flush_range(src_vir, src_vir + src_size);
1955 rga2_dma_flush_range(dst_vir, dst_vir + dst_size);
1956
1957 memset(&req, 0, sizeof(struct rga2_req));
1958 req.src.x_offset = 0;
1959 req.src.y_offset = 0;
1960 req.src.act_w = srcW;
1961 req.src.act_h = srcH;
1962 req.src.vir_w = srcW;
1963 req.src.vir_h = srcW;
1964 req.src.format = RGA2_FORMAT_RGBA_8888;
1965
1966 req.src.yrgb_addr = 0;
1967 req.src.uv_addr = (unsigned long)virt_to_phys(src_vir);
1968 req.src.v_addr = req.src.uv_addr + srcH * srcW;
1969
1970 req.dst.x_offset = 0;
1971 req.dst.y_offset = 0;
1972 req.dst.act_w = dstW;
1973 req.dst.act_h = dstH;
1974 req.dst.vir_w = dstW;
1975 req.dst.vir_h = dstH;
1976 req.dst.format = RGA2_FORMAT_RGBA_8888;
1977
1978 req.dst.yrgb_addr = 0;
1979 req.dst.uv_addr = (unsigned long)virt_to_phys(dst_vir);
1980 req.dst.v_addr = req.dst.uv_addr + dstH * dstW;
1981
1982 rga2_blit_sync(&session, &req);
1983
1984 /* Check buffer */
1985 pstd = (unsigned int *)src_vir;
1986 pnow = (unsigned int *)dst_vir;
1987
1988 INFO("[ num : srcInfo dstInfo ]\n");
1989 for (i = 0; i < dst_size / 4; i++) {
1990 if (*pstd != *pnow) {
1991 INFO("[X%.8d : 0x%x 0x%x]", i, *pstd, *pnow);
1992 if (i % 4 == 0)
1993 INFO("\n");
1994 err_count++;
1995 } else {
1996 if (i % (640 * 1024) == 0)
1997 INFO("[Y%.8d : 0x%.8x 0x%.8x]\n",
1998 i, *pstd, *pnow);
1999 right_count++;
2000 }
2001 pstd++;
2002 pnow++;
2003 if (err_count > 64)
2004 break;
2005 }
2006
2007 INFO("err_count=%d, right_count=%d\n", err_count, right_count);
2008 if (err_count != 0)
2009 INFO("rga slt err !!\n");
2010 else
2011 INFO("rga slt success !!\n");
2012
2013 /* Deinit session */
2014 task_running = atomic_read(&session.task_running);
2015 if (task_running) {
2016 pr_err("%s[%d], session %d still has %d task running when closing\n",
2017 __func__, __LINE__, session.pid, task_running);
2018 msleep(100);
2019 }
2020 wake_up(&session.wait);
2021 mutex_lock(&rga2_service.lock);
2022 list_del(&session.list_session);
2023 rga2_service_session_clear(&session);
2024 mutex_unlock(&rga2_service.lock);
2025
2026 free_pages((unsigned long)src_vir, src_order);
2027 free_pages((unsigned long)dst_vir, dst_order);
2028 }
2029 #endif
2030
2031 void rga2_test_0(void);
2032
rga2_init(void)2033 static int __init rga2_init(void)
2034 {
2035 int ret;
2036 int order = 0;
2037 uint32_t *buf_p;
2038 uint32_t *buf;
2039
2040 /*
2041 * malloc pre scale mid buf mmu table:
2042 * RGA2_PHY_PAGE_SIZE * channel_num * address_size
2043 */
2044 order = get_order(RGA2_PHY_PAGE_SIZE * 3 * sizeof(buf_p));
2045 buf_p = (uint32_t *)__get_free_pages(GFP_KERNEL | GFP_DMA32, order);
2046 if (buf_p == NULL) {
2047 ERR("Can not alloc pages for mmu_page_table\n");
2048 }
2049
2050 rga2_mmu_buf.buf_virtual = buf_p;
2051 rga2_mmu_buf.buf_order = order;
2052 #if (defined(CONFIG_ARM) && defined(CONFIG_ARM_LPAE))
2053 buf = (uint32_t *)(uint32_t)virt_to_phys((void *)((unsigned long)buf_p));
2054 #else
2055 buf = (uint32_t *)virt_to_phys((void *)((unsigned long)buf_p));
2056 #endif
2057 rga2_mmu_buf.buf = buf;
2058 rga2_mmu_buf.front = 0;
2059 rga2_mmu_buf.back = RGA2_PHY_PAGE_SIZE * 3;
2060 rga2_mmu_buf.size = RGA2_PHY_PAGE_SIZE * 3;
2061
2062 order = get_order(RGA2_PHY_PAGE_SIZE * sizeof(struct page *));
2063 rga2_mmu_buf.pages = (struct page **)__get_free_pages(GFP_KERNEL | GFP_DMA32, order);
2064 if (rga2_mmu_buf.pages == NULL) {
2065 ERR("Can not alloc pages for rga2_mmu_buf.pages\n");
2066 }
2067 rga2_mmu_buf.pages_order = order;
2068
2069 ret = platform_driver_register(&rga2_driver);
2070 if (ret != 0) {
2071 printk(KERN_ERR "Platform device register failed (%d).\n", ret);
2072 return ret;
2073 }
2074
2075 rga2_session_global.pid = 0x0000ffff;
2076 INIT_LIST_HEAD(&rga2_session_global.waiting);
2077 INIT_LIST_HEAD(&rga2_session_global.running);
2078 INIT_LIST_HEAD(&rga2_session_global.list_session);
2079
2080 INIT_LIST_HEAD(&rga2_service.waiting);
2081 INIT_LIST_HEAD(&rga2_service.running);
2082 INIT_LIST_HEAD(&rga2_service.done);
2083 INIT_LIST_HEAD(&rga2_service.session);
2084 init_waitqueue_head(&rga2_session_global.wait);
2085 //mutex_lock(&rga_service.lock);
2086 list_add_tail(&rga2_session_global.list_session, &rga2_service.session);
2087 //mutex_unlock(&rga_service.lock);
2088 atomic_set(&rga2_session_global.task_running, 0);
2089 atomic_set(&rga2_session_global.num_done, 0);
2090
2091 #if RGA2_TEST_CASE
2092 rga2_test_0();
2093 #endif
2094 INFO("Module initialized.\n");
2095
2096 return 0;
2097 }
2098
rga2_exit(void)2099 static void __exit rga2_exit(void)
2100 {
2101 rga2_power_off();
2102
2103 free_pages((unsigned long)rga2_mmu_buf.buf_virtual, rga2_mmu_buf.buf_order);
2104 free_pages((unsigned long)rga2_mmu_buf.pages, rga2_mmu_buf.pages_order);
2105
2106 platform_driver_unregister(&rga2_driver);
2107 }
2108
2109
2110 #if RGA2_TEST_CASE
2111
rga2_test_0(void)2112 void rga2_test_0(void)
2113 {
2114 struct rga2_req req;
2115 rga2_session session;
2116 unsigned int *src, *dst;
2117
2118 session.pid = current->pid;
2119 INIT_LIST_HEAD(&session.waiting);
2120 INIT_LIST_HEAD(&session.running);
2121 INIT_LIST_HEAD(&session.list_session);
2122 init_waitqueue_head(&session.wait);
2123 /* no need to protect */
2124 list_add_tail(&session.list_session, &rga2_service.session);
2125 atomic_set(&session.task_running, 0);
2126 atomic_set(&session.num_done, 0);
2127
2128 memset(&req, 0, sizeof(struct rga2_req));
2129 src = kmalloc(800*480*4, GFP_KERNEL);
2130 dst = kmalloc(800*480*4, GFP_KERNEL);
2131
2132 printk("\n********************************\n");
2133 printk("************ RGA2_TEST ************\n");
2134 printk("********************************\n\n");
2135
2136 #if 1
2137 memset(src, 0x80, 800 * 480 * 4);
2138 memset(dst, 0xcc, 800 * 480 * 4);
2139 #endif
2140 #if 0
2141 dmac_flush_range(src, &src[800 * 480]);
2142 outer_flush_range(virt_to_phys(src), virt_to_phys(&src[800 * 480]));
2143
2144 dmac_flush_range(dst, &dst[800 * 480]);
2145 outer_flush_range(virt_to_phys(dst), virt_to_phys(&dst[800 * 480]));
2146 #endif
2147
2148 #if 0
2149 req.pat.act_w = 16;
2150 req.pat.act_h = 16;
2151 req.pat.vir_w = 16;
2152 req.pat.vir_h = 16;
2153 req.pat.yrgb_addr = virt_to_phys(src);
2154 req.render_mode = 0;
2155 rga2_blit_sync(&session, &req);
2156 #endif
2157 {
2158 uint32_t i, j;
2159 uint8_t *sp;
2160
2161 sp = (uint8_t *)src;
2162 for (j = 0; j < 240; j++) {
2163 sp = (uint8_t *)src + j * 320 * 10 / 8;
2164 for (i = 0; i < 320; i++) {
2165 if ((i & 3) == 0) {
2166 sp[i * 5 / 4] = 0;
2167 sp[i * 5 / 4+1] = 0x1;
2168 } else if ((i & 3) == 1) {
2169 sp[i * 5 / 4+1] = 0x4;
2170 } else if ((i & 3) == 2) {
2171 sp[i * 5 / 4+1] = 0x10;
2172 } else if ((i & 3) == 3) {
2173 sp[i * 5 / 4+1] = 0x40;
2174 }
2175 }
2176 }
2177 sp = (uint8_t *)src;
2178 for (j = 0; j < 100; j++)
2179 printk("src %.2x\n", sp[j]);
2180 }
2181 req.src.act_w = 320;
2182 req.src.act_h = 240;
2183
2184 req.src.vir_w = 320;
2185 req.src.vir_h = 240;
2186 req.src.yrgb_addr = 0;//(uint32_t)virt_to_phys(src);
2187 req.src.uv_addr = (unsigned long)virt_to_phys(src);
2188 req.src.v_addr = 0;
2189 req.src.format = RGA2_FORMAT_YCbCr_420_SP_10B;
2190
2191 req.dst.act_w = 320;
2192 req.dst.act_h = 240;
2193 req.dst.x_offset = 0;
2194 req.dst.y_offset = 0;
2195
2196 req.dst.vir_w = 320;
2197 req.dst.vir_h = 240;
2198
2199 req.dst.yrgb_addr = 0;//((uint32_t)virt_to_phys(dst));
2200 req.dst.uv_addr = (unsigned long)virt_to_phys(dst);
2201 req.dst.format = RGA2_FORMAT_YCbCr_420_SP;
2202
2203 //dst = dst0;
2204
2205 //req.render_mode = color_fill_mode;
2206 //req.fg_color = 0x80ffffff;
2207
2208 req.rotate_mode = 0;
2209 req.scale_bicu_mode = 2;
2210
2211 #if 0
2212 //req.alpha_rop_flag = 0;
2213 //req.alpha_rop_mode = 0x19;
2214 //req.PD_mode = 3;
2215
2216 //req.mmu_info.mmu_flag = 0x21;
2217 //req.mmu_info.mmu_en = 1;
2218
2219 //printk("src = %.8x\n", req.src.yrgb_addr);
2220 //printk("src = %.8x\n", req.src.uv_addr);
2221 //printk("dst = %.8x\n", req.dst.yrgb_addr);
2222 #endif
2223
2224 rga2_blit_sync(&session, &req);
2225
2226 #if 0
2227 uint32_t j;
2228 for (j = 0; j < 320 * 240 * 10 / 8; j++) {
2229 if (src[j] != dst[j])
2230 printk("error value dst not equal src j %d, s %.2x d %.2x\n",
2231 j, src[j], dst[j]);
2232 }
2233 #endif
2234
2235 #if 1
2236 {
2237 uint32_t j;
2238 uint8_t *dp = (uint8_t *)dst;
2239
2240 for (j = 0; j < 100; j++)
2241 printk("%d %.2x\n", j, dp[j]);
2242 }
2243 #endif
2244
2245 kfree(src);
2246 kfree(dst);
2247 }
2248 #endif
2249
2250 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
2251 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
2252 module_init(rga2_init);
2253 #else
2254 late_initcall(rga2_init);
2255 #endif
2256 #else
2257 fs_initcall(rga2_init);
2258 #endif
2259 module_exit(rga2_exit);
2260
2261 /* Module information */
2262 MODULE_AUTHOR("zsq@rock-chips.com");
2263 MODULE_DESCRIPTION("Driver for rga device");
2264 MODULE_LICENSE("GPL");
2265