1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_H 3 #define _DT_BINDINGS_CLOCK_ROCKCHIP_H 4 5 #ifndef BIT 6 #define BIT(nr) (1 << (nr)) 7 #endif 8 9 #define CLK_DIVIDER_PLUS_ONE (0) 10 #define CLK_DIVIDER_ONE_BASED BIT(0) 11 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 12 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 13 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 14 15 /* Rockchip special defined */ 16 //#define CLK_DIVIDER_FIXED BIT(6) 17 #define CLK_DIVIDER_USER_DEFINE BIT(7) 18 19 /* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32 #define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent 33 and set_div on rate change */ 34 35 36 37 /* Rockchip pll flags */ 38 #define CLK_PLL_3188 BIT(0) 39 #define CLK_PLL_3188_APLL BIT(1) 40 #define CLK_PLL_3188PLUS BIT(2) 41 #define CLK_PLL_3188PLUS_APLL BIT(3) 42 #define CLK_PLL_3288_APLL BIT(4) 43 #define CLK_PLL_3188PLUS_AUTO BIT(5) 44 #define CLK_PLL_3036_APLL BIT(6) 45 #define CLK_PLL_3036PLUS_AUTO BIT(7) 46 #define CLK_PLL_312XPLUS BIT(8) 47 #define CLK_PLL_3368_APLLB BIT(9) 48 #define CLK_PLL_3368_APLLL BIT(10) 49 #define CLK_PLL_3368_LOW_JITTER BIT(11) 50 51 52 /* rate_ops index */ 53 #define CLKOPS_RATE_MUX_DIV 1 54 #define CLKOPS_RATE_EVENDIV 2 55 #define CLKOPS_RATE_MUX_EVENDIV 3 56 #define CLKOPS_RATE_I2S_FRAC 4 57 #define CLKOPS_RATE_FRAC 5 58 #define CLKOPS_RATE_I2S 6 59 #define CLKOPS_RATE_CIFOUT 7 60 #define CLKOPS_RATE_UART 8 61 #define CLKOPS_RATE_HSADC 9 62 #define CLKOPS_RATE_MAC_REF 10 63 #define CLKOPS_RATE_CORE 11 64 #define CLKOPS_RATE_CORE_CHILD 12 65 #define CLKOPS_RATE_DDR 13 66 #define CLKOPS_RATE_RK3288_I2S 14 67 #define CLKOPS_RATE_RK3288_USB480M 15 68 #define CLKOPS_RATE_RK3288_DCLK_LCDC0 16 69 #define CLKOPS_RATE_RK3288_DCLK_LCDC1 17 70 #define CLKOPS_RATE_DDR_DIV2 18 71 #define CLKOPS_RATE_DDR_DIV4 19 72 #define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20 73 #define CLKOPS_RATE_RK3368_DCLK_LCDC 21 74 #define CLKOPS_RATE_RK3368_DDR 22 75 76 #define CLKOPS_TABLE_END (~0) 77 78 /* pd id */ 79 #define CLK_PD_BCPU 0 80 #define CLK_PD_BDSP 1 81 #define CLK_PD_BUS 2 82 #define CLK_PD_CPU_0 3 83 #define CLK_PD_CPU_1 4 84 #define CLK_PD_CPU_2 5 85 #define CLK_PD_CPU_3 6 86 #define CLK_PD_CS 7 87 #define CLK_PD_GPU 8 88 #define CLK_PD_HEVC 9 89 #define CLK_PD_PERI 10 90 #define CLK_PD_SCU 11 91 #define CLK_PD_VIDEO 12 92 #define CLK_PD_VIO 13 93 #define CLK_PD_GPU_0 14 94 #define CLK_PD_GPU_1 15 95 96 #define CLK_PD_VIRT 255 97 98 /* reset flag */ 99 #define ROCKCHIP_RESET_HIWORD_MASK BIT(0) 100 101 #endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */ 102