1 /* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12 #ifndef __ROCKCHIP_SIP_H
13 #define __ROCKCHIP_SIP_H
14
15 #include <linux/arm-smccc.h>
16 #include <linux/io.h>
17
18 /* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */
19 #define SIP_ATF_VERSION 0x82000001
20 #define SIP_ACCESS_REG 0x82000002
21 #define SIP_SUSPEND_MODE 0x82000003
22 #define SIP_PENDING_CPUS 0x82000004
23 #define SIP_UARTDBG_CFG 0x82000005
24 #define SIP_UARTDBG_CFG64 0xc2000005
25 #define SIP_MCU_EL3FIQ_CFG 0x82000006
26 #define SIP_ACCESS_CHIP_STATE64 0xc2000006
27 #define SIP_SECURE_MEM_CONFIG 0x82000007
28 #define SIP_ACCESS_CHIP_EXTRA_STATE64 0xc2000007
29 #define SIP_DRAM_CONFIG 0x82000008
30 #define SIP_SHARE_MEM 0x82000009
31 #define SIP_SIP_VERSION 0x8200000a
32 #define SIP_REMOTECTL_CFG 0x8200000b
33 #define PSCI_SIP_VPU_RESET 0x8200000c
34 #define SIP_BUS_CFG 0x8200000d
35 #define SIP_LAST_LOG 0x8200000e
36 #define SIP_SCMI_AGENT0 0x82000010
37 #define SIP_SCMI_AGENT1 0x82000011
38 #define SIP_SCMI_AGENT2 0x82000012
39 #define SIP_SCMI_AGENT3 0x82000013
40 #define SIP_SCMI_AGENT4 0x82000014
41 #define SIP_SCMI_AGENT5 0x82000015
42 #define SIP_SCMI_AGENT6 0x82000016
43 #define SIP_SCMI_AGENT7 0x82000017
44 #define SIP_SCMI_AGENT8 0x82000018
45 #define SIP_SCMI_AGENT9 0x82000019
46 #define SIP_SCMI_AGENT10 0x8200001a
47 #define SIP_SCMI_AGENT11 0x8200001b
48 #define SIP_SCMI_AGENT12 0x8200001c
49 #define SIP_SCMI_AGENT13 0x8200001d
50 #define SIP_SCMI_AGENT14 0x8200001e
51 #define SIP_SCMI_AGENT15 0x8200001f
52 #define SIP_SDEI_FIQ_DBG_SWITCH_CPU 0x82000020
53 #define SIP_SDEI_FIQ_DBG_GET_EVENT_ID 0x82000021
54 #define RK_SIP_FIQ_CTRL 0x82000024
55
56 /* Rockchip Sip version */
57 #define SIP_IMPLEMENT_V1 (1)
58 #define SIP_IMPLEMENT_V2 (2)
59
60 /* Trust firmware version */
61 #define ATF_VER_MAJOR(ver) (((ver) >> 16) & 0xffff)
62 #define ATF_VER_MINOR(ver) (((ver) >> 0) & 0xffff)
63
64 /* SIP_ACCESS_REG: read or write */
65 #define SECURE_REG_RD 0x0
66 #define SECURE_REG_WR 0x1
67
68 /* Fiq debugger share memory: 8KB enough */
69 #define FIQ_UARTDBG_PAGE_NUMS 2
70 #define FIQ_UARTDBG_SHARE_MEM_SIZE ((FIQ_UARTDBG_PAGE_NUMS) * 4096)
71
72 /* Error return code */
73 #define IS_SIP_ERROR(x) (!!(x))
74
75 #define SIP_RET_SUCCESS 0
76 #define SIP_RET_SMC_UNKNOWN -1
77 #define SIP_RET_NOT_SUPPORTED -2
78 #define SIP_RET_INVALID_PARAMS -3
79 #define SIP_RET_INVALID_ADDRESS -4
80 #define SIP_RET_DENIED -5
81 #define SIP_RET_SET_RATE_TIMEOUT -6
82
83 /* SIP_UARTDBG_CFG64 call types */
84 #define UARTDBG_CFG_INIT 0xf0
85 #define UARTDBG_CFG_OSHDL_TO_OS 0xf1
86 #define UARTDBG_CFG_OSHDL_CPUSW 0xf3
87 #define UARTDBG_CFG_OSHDL_DEBUG_ENABLE 0xf4
88 #define UARTDBG_CFG_OSHDL_DEBUG_DISABLE 0xf5
89 #define UARTDBG_CFG_PRINT_PORT 0xf7
90 #define UARTDBG_CFG_FIQ_ENABEL 0xf8
91 #define UARTDBG_CFG_FIQ_DISABEL 0xf9
92
93 /* SIP_SUSPEND_MODE32 call types */
94 #define SUSPEND_MODE_CONFIG 0x01
95 #define WKUP_SOURCE_CONFIG 0x02
96 #define PWM_REGULATOR_CONFIG 0x03
97 #define GPIO_POWER_CONFIG 0x04
98 #define SUSPEND_DEBUG_ENABLE 0x05
99 #define APIOS_SUSPEND_CONFIG 0x06
100 #define VIRTUAL_POWEROFF 0x07
101 #define SUSPEND_WFI_TIME_MS 0x08
102 #define LINUX_PM_STATE 0x09
103
104 /* SIP_REMOTECTL_CFG call types */
105 #define REMOTECTL_SET_IRQ 0xf0
106 #define REMOTECTL_SET_PWM_CH 0xf1
107 #define REMOTECTL_SET_PWRKEY 0xf2
108 #define REMOTECTL_GET_WAKEUP_STATE 0xf3
109 #define REMOTECTL_ENABLE 0xf4
110 /* wakeup state */
111 #define REMOTECTL_PWRKEY_WAKEUP 0xdeadbeaf
112
113 struct dram_addrmap_info {
114 u64 ch_mask[2];
115 u64 bk_mask[4];
116 u64 bg_mask[2];
117 u64 cs_mask[2];
118 u32 reserved[20];
119 u32 bank_bit_first;
120 u32 bank_bit_mask;
121 };
122
123 enum {
124 FIRMWARE_NONE,
125 FIRMWARE_TEE_32BIT,
126 FIRMWARE_ATF_32BIT,
127 FIRMWARE_ATF_64BIT,
128 FIRMWARE_END,
129 };
130
131 /* Share mem page types */
132 typedef enum {
133 SHARE_PAGE_TYPE_INVALID = 0,
134 SHARE_PAGE_TYPE_UARTDBG,
135 SHARE_PAGE_TYPE_DDR,
136 SHARE_PAGE_TYPE_DDRDBG,
137 SHARE_PAGE_TYPE_DDRECC,
138 SHARE_PAGE_TYPE_DDRFSP,
139 SHARE_PAGE_TYPE_DDR_ADDRMAP,
140 SHARE_PAGE_TYPE_LAST_LOG,
141 SHARE_PAGE_TYPE_MAX,
142 } share_page_type_t;
143
144 /* fiq control sub func */
145 enum {
146 RK_SIP_FIQ_CTRL_FIQ_EN = 1,
147 RK_SIP_FIQ_CTRL_FIQ_DIS,
148 RK_SIP_FIQ_CTRL_SET_AFF
149 };
150
151 /*
152 * Rules: struct arm_smccc_res contains result and data, details:
153 *
154 * a0: error code(0: success, !0: error);
155 * a1~a3: data
156 */
157 #if IS_ENABLED(CONFIG_ROCKCHIP_SIP)
158 struct arm_smccc_res sip_smc_get_atf_version(void);
159 struct arm_smccc_res sip_smc_get_sip_version(void);
160 struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
161 struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
162 share_page_type_t page_type);
163 struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2);
164 struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2);
165 struct arm_smccc_res sip_smc_get_suspend_info(u32 info);
166 struct arm_smccc_res sip_smc_lastlog_request(void);
167
168 int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2);
169 int sip_smc_virtual_poweroff(void);
170 int sip_smc_remotectl_config(u32 func, u32 data);
171
172 int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
173 u32 sip_smc_secure_reg_read(u32 addr_phy);
174 struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2);
175 struct dram_addrmap_info *sip_smc_get_dram_map(void);
176
177 /***************************fiq debugger **************************************/
178 void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);
179 void sip_fiq_debugger_enable_debug(bool enable);
180 int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, void *callback_fn);
181 int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate);
182 int sip_fiq_debugger_request_share_memory(void);
183 int sip_fiq_debugger_get_target_cpu(void);
184 int sip_fiq_debugger_switch_cpu(u32 cpu);
185 int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag);
186 int sip_fiq_debugger_is_enabled(void);
187 int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag);
188 int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data);
189 #else
sip_smc_get_atf_version(void)190 static inline struct arm_smccc_res sip_smc_get_atf_version(void)
191 {
192 struct arm_smccc_res tmp = {0};
193 return tmp;
194 }
195
sip_smc_get_sip_version(void)196 static inline struct arm_smccc_res sip_smc_get_sip_version(void)
197 {
198 struct arm_smccc_res tmp = {0};
199 return tmp;
200 }
201
sip_smc_dram(u32 arg0,u32 arg1,u32 arg2)202 static inline struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
203 {
204 struct arm_smccc_res tmp = {0};
205 return tmp;
206 }
207
sip_smc_request_share_mem(u32 page_num,share_page_type_t page_type)208 static inline struct arm_smccc_res sip_smc_request_share_mem
209 (u32 page_num, share_page_type_t page_type)
210 {
211 struct arm_smccc_res tmp = {0};
212 return tmp;
213 }
214
sip_smc_mcu_el3fiq(u32 arg0,u32 arg1,u32 arg2)215 static inline struct arm_smccc_res sip_smc_mcu_el3fiq
216 (u32 arg0, u32 arg1, u32 arg2)
217 {
218 struct arm_smccc_res tmp = {0};
219 return tmp;
220 }
221
222 static inline struct arm_smccc_res
sip_smc_vpu_reset(u32 arg0,u32 arg1,u32 arg2)223 sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
224 {
225 struct arm_smccc_res tmp = {0};
226 return tmp;
227 }
228
sip_smc_lastlog_request(void)229 static inline struct arm_smccc_res sip_smc_lastlog_request(void)
230 {
231 struct arm_smccc_res tmp = {0};
232 return tmp;
233 }
234
sip_smc_set_suspend_mode(u32 ctrl,u32 config1,u32 config2)235 static inline int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
236 {
237 return 0;
238 }
239
sip_smc_get_suspend_info(u32 info)240 static inline int sip_smc_get_suspend_info(u32 info)
241 {
242 return 0;
243 }
244
sip_smc_virtual_poweroff(void)245 static inline int sip_smc_virtual_poweroff(void) { return 0; }
sip_smc_remotectl_config(u32 func,u32 data)246 static inline int sip_smc_remotectl_config(u32 func, u32 data) { return 0; }
sip_smc_secure_reg_read(u32 addr_phy)247 static inline u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; }
sip_smc_secure_reg_write(u32 addr_phy,u32 val)248 static inline int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; }
sip_smc_soc_bus_div(u32 arg0,u32 arg1,u32 arg2)249 static inline int sip_smc_soc_bus_div(u32 arg0, u32 arg1, u32 arg2)
250 {
251 return 0;
252 }
sip_smc_get_dram_map(void)253 static inline struct dram_addrmap_info *sip_smc_get_dram_map(void)
254 {
255 return NULL;
256 }
257
258 /***************************fiq debugger **************************************/
sip_fiq_debugger_enable_fiq(bool enable,uint32_t tgt_cpu)259 static inline void sip_fiq_debugger_enable_fiq
260 (bool enable, uint32_t tgt_cpu) { return; }
261
sip_fiq_debugger_enable_debug(bool enable)262 static inline void sip_fiq_debugger_enable_debug(bool enable) { return; }
sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,void * callback_fn)263 static inline int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,
264 void *callback_fn)
265 {
266 return 0;
267 }
268
sip_fiq_debugger_set_print_port(u32 port_phyaddr,u32 baudrate)269 static inline int sip_fiq_debugger_set_print_port(u32 port_phyaddr,
270 u32 baudrate)
271 {
272 return 0;
273 }
274
sip_fiq_debugger_request_share_memory(void)275 static inline int sip_fiq_debugger_request_share_memory(void) { return 0; }
sip_fiq_debugger_get_target_cpu(void)276 static inline int sip_fiq_debugger_get_target_cpu(void) { return 0; }
sip_fiq_debugger_switch_cpu(u32 cpu)277 static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; }
sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu,u32 target_cpu,u32 flag)278 static inline int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu,
279 u32 flag) { return 0; }
sip_fiq_debugger_is_enabled(void)280 static inline int sip_fiq_debugger_is_enabled(void) { return 0; }
sip_fiq_control(u32 sub_func,u32 irq,unsigned long data)281 static inline int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data)
282 {
283 return 0;
284 }
285 #endif
286
287 /* 32-bit OP-TEE context, never change order of members! */
288 struct sm_nsec_ctx {
289 u32 usr_sp;
290 u32 usr_lr;
291 u32 irq_spsr;
292 u32 irq_sp;
293 u32 irq_lr;
294 u32 fiq_spsr;
295 u32 fiq_sp;
296 u32 fiq_lr;
297 u32 svc_spsr;
298 u32 svc_sp;
299 u32 svc_lr;
300 u32 abt_spsr;
301 u32 abt_sp;
302 u32 abt_lr;
303 u32 und_spsr;
304 u32 und_sp;
305 u32 und_lr;
306 u32 mon_lr;
307 u32 mon_spsr;
308 u32 r4;
309 u32 r5;
310 u32 r6;
311 u32 r7;
312 u32 r8;
313 u32 r9;
314 u32 r10;
315 u32 r11;
316 u32 r12;
317 u32 r0;
318 u32 r1;
319 u32 r2;
320 u32 r3;
321 };
322
323 /* 64-bit ATF context, never change order of members! */
324 struct gp_regs_ctx {
325 u64 x0;
326 u64 x1;
327 u64 x2;
328 u64 x3;
329 u64 x4;
330 u64 x5;
331 u64 x6;
332 u64 x7;
333 u64 x8;
334 u64 x9;
335 u64 x10;
336 u64 x11;
337 u64 x12;
338 u64 x13;
339 u64 x14;
340 u64 x15;
341 u64 x16;
342 u64 x17;
343 u64 x18;
344 u64 x19;
345 u64 x20;
346 u64 x21;
347 u64 x22;
348 u64 x23;
349 u64 x24;
350 u64 x25;
351 u64 x26;
352 u64 x27;
353 u64 x28;
354 u64 x29;
355 u64 lr;
356 u64 sp_el0;
357 u64 scr_el3;
358 u64 runtime_sp;
359 u64 spsr_el3;
360 u64 elr_el3;
361 };
362
363 #endif
364