1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd 4 */ 5 #ifndef __SOC_ROCKCHIP_PERFORMANCE_H 6 #define __SOC_ROCKCHIP_PERFORMANCE_H 7 8 #ifdef CONFIG_ROCKCHIP_PERFORMANCE 9 extern int rockchip_perf_get_level(void); 10 extern int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask); 11 extern bool rockchip_perf_misfit_rt(int cpu); 12 extern void rockchip_perf_uclamp_sync_util_min_rt_default(void); 13 #else rockchip_perf_get_level(void)14static inline int rockchip_perf_get_level(void) { return 1; } rockchip_perf_select_rt_cpu(int prev_cpu,struct cpumask * lowest_mask)15static inline int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask) 16 { 17 return prev_cpu; 18 } rockchip_perf_misfit_rt(int cpu)19static inline bool rockchip_perf_misfit_rt(int cpu) { return false; } rockchip_perf_uclamp_sync_util_min_rt_default(void)20static inline void rockchip_perf_uclamp_sync_util_min_rt_default(void) {} 21 #endif 22 23 #endif 24