1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 frank@allwinnertech.com
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of_address.h>
10 #include <linux/platform_device.h>
11
12 #include "ccu_common.h"
13 #include "ccu_reset.h"
14
15 #include "ccu_div.h"
16 #include "ccu_gate.h"
17 #include "ccu_mp.h"
18 #include "ccu_mult.h"
19 #include "ccu_nk.h"
20 #include "ccu_nkm.h"
21 #include "ccu_nkmp.h"
22 #include "ccu_nm.h"
23
24 #include "ccu-sun50iw9.h"
25
26 /*
27 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
28 * P should only be used for output frequencies lower than 288 MHz.
29 *
30 * For now we can just model it as a multiplier clock, and force P to /1.
31 *
32 * The M factor is present in the register's description, but not in the
33 * frequency formula, and it's documented as "M is only used for backdoor
34 * testing", so it's not modelled and then force to 0.
35 */
36 #define SUN50IW9_PLL_CPUX_REG 0x000
37 static struct ccu_mult pll_cpux_clk = {
38 .enable = BIT(27),
39 .lock = BIT(28),
40 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
41 .common = {
42 .reg = 0x000,
43 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
44 &ccu_mult_ops,
45 CLK_SET_RATE_UNGATE),
46 },
47 };
48
49 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
50 #define SUN50IW9_PLL_DDR0_REG 0x010
51 static struct ccu_nkmp pll_ddr0_clk = {
52 .enable = BIT(27),
53 .lock = BIT(28),
54 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
55 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
56 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
57 .common = {
58 .reg = 0x010,
59 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
60 &ccu_nkmp_ops,
61 CLK_SET_RATE_UNGATE |
62 CLK_IS_CRITICAL),
63 },
64 };
65
66 #define SUN50IW9_PLL_DDR1_REG 0x018
67 static struct ccu_nkmp pll_ddr1_clk = {
68 .enable = BIT(27),
69 .lock = BIT(28),
70 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
71 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
72 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
73 .common = {
74 .reg = 0x018,
75 .hw.init = CLK_HW_INIT("pll-ddr1", "dcxo24M",
76 &ccu_nkmp_ops,
77 CLK_SET_RATE_UNGATE |
78 CLK_IS_CRITICAL),
79 },
80 };
81
82 #define SUN50IW9_PLL_PERIPH0_REG 0x020
83 static struct ccu_nkmp pll_periph0_clk = {
84 .enable = BIT(27),
85 .lock = BIT(28),
86 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
87 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
88 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
89 .fixed_post_div = 2,
90 .common = {
91 .reg = 0x020,
92 .features = CCU_FEATURE_FIXED_POSTDIV,
93 .hw.init = CLK_HW_INIT("pll-periph0", "dcxo24M",
94 &ccu_nkmp_ops,
95 CLK_SET_RATE_UNGATE),
96 },
97 };
98
99 #define SUN50IW9_PLL_PERIPH1_REG 0x028
100 static struct ccu_nkmp pll_periph1_clk = {
101 .enable = BIT(27),
102 .lock = BIT(28),
103 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
104 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
105 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
106 .fixed_post_div = 2,
107 .common = {
108 .reg = 0x028,
109 .features = CCU_FEATURE_FIXED_POSTDIV,
110 .hw.init = CLK_HW_INIT("pll-periph1", "dcxo24M",
111 &ccu_nkmp_ops,
112 CLK_SET_RATE_UNGATE),
113 },
114 };
115
116 #define SUN50IW9_PLL_GPU_REG 0x030
117 static struct ccu_nkmp pll_gpu_clk = {
118 .enable = BIT(27),
119 .lock = BIT(28),
120 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
121 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
122 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
123 .common = {
124 .reg = 0x030,
125 .hw.init = CLK_HW_INIT("pll-gpu", "dcxo24M",
126 &ccu_nkmp_ops,
127 CLK_SET_RATE_UNGATE),
128 },
129 };
130
131 /*
132 * For Video PLLs, the output divider is described as "used for testing"
133 * in the user manual. So it's not modelled and forced to 0.
134 */
135 #define SUN50IW9_PLL_VIDEO0_REG 0x040
136 static struct ccu_nm pll_video0_clk = {
137 .enable = BIT(27),
138 .lock = BIT(28),
139 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
140 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
141 .fixed_post_div = 4,
142 .min_rate = 288000000,
143 .max_rate = 2400000000UL,
144 .common = {
145 .reg = 0x040,
146 .features = CCU_FEATURE_FIXED_POSTDIV,
147 .hw.init = CLK_HW_INIT("pll-video0", "dcxo24M",
148 &ccu_nm_ops,
149 CLK_SET_RATE_UNGATE),
150 },
151 };
152
153 #define SUN50IW9_PLL_VIDEO1_REG 0x048
154 static struct ccu_nm pll_video1_clk = {
155 .enable = BIT(27),
156 .lock = BIT(28),
157 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
158 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
159 .fixed_post_div = 4,
160 .min_rate = 288000000,
161 .max_rate = 2400000000UL,
162 .common = {
163 .reg = 0x048,
164 .features = CCU_FEATURE_FIXED_POSTDIV,
165 .hw.init = CLK_HW_INIT("pll-video1", "dcxo24M",
166 &ccu_nm_ops,
167 CLK_SET_RATE_UNGATE),
168 },
169 };
170
171 #define SUN50IW9_PLL_VIDEO2_REG 0x050
172 static struct ccu_nm pll_video2_clk = {
173 .enable = BIT(27),
174 .lock = BIT(28),
175 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
176 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
177 .fixed_post_div = 4,
178 .min_rate = 288000000,
179 .max_rate = 2400000000UL,
180 .common = {
181 .reg = 0x050,
182 .features = CCU_FEATURE_FIXED_POSTDIV,
183 .hw.init = CLK_HW_INIT("pll-video2", "dcxo24M",
184 &ccu_nm_ops,
185 CLK_SET_RATE_UNGATE),
186 },
187 };
188
189 #define SUN50IW9_PLL_VE_REG 0x058
190 static struct ccu_nkmp pll_ve_clk = {
191 .enable = BIT(27),
192 .lock = BIT(28),
193 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
194 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
195 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
196 .common = {
197 .reg = 0x058,
198 .hw.init = CLK_HW_INIT("pll-ve", "dcxo24M",
199 &ccu_nkmp_ops,
200 CLK_SET_RATE_UNGATE),
201 },
202 };
203
204 #define SUN50IW9_PLL_DE_REG 0x060
205 static struct ccu_nkmp pll_de_clk = {
206 .enable = BIT(27),
207 .lock = BIT(28),
208 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
209 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
210 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
211 .common = {
212 .reg = 0x060,
213 .hw.init = CLK_HW_INIT("pll-de", "dcxo24M",
214 &ccu_nkmp_ops,
215 CLK_SET_RATE_UNGATE),
216 },
217 };
218
219 /* for pm resume */
220 #define SUN50IW9_PLL_PERIPH1_PATTERN0_REG 0x128
221 static struct ccu_common pll_periph1_pattern0_common = {
222 .reg = 0x128,
223 };
224
225 /*
226 * The Audio PLL has m0, m1 dividers in addition to the usual N, M
227 * factors. Since we only need 4 frequencies from this PLL: 22.5792 MHz,
228 * 24.576 MHz, 90.3168MHz and 98.304MHz ignore them for now.
229 * Enforce the default for them, which is m0 = 1, m1 = 0.
230 */
231 #define SUN50IW9_PLL_AUDIO_REG 0x078
232 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
233 { .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
234 { .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
235 { .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
236 { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
237 };
238
239 static struct ccu_nm pll_audio_4x_clk = {
240 .enable = BIT(27),
241 .lock = BIT(28),
242 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
243 .m = _SUNXI_CCU_DIV(16, 6),
244 .fixed_post_div = 2,
245 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
246 0x178, BIT(31)),
247 .common = {
248 .reg = 0x078,
249 .features = CCU_FEATURE_FIXED_POSTDIV |
250 CCU_FEATURE_SIGMA_DELTA_MOD,
251 .hw.init = CLK_HW_INIT("pll-audio-4x", "dcxo24M",
252 &ccu_nm_ops,
253 CLK_SET_RATE_UNGATE),
254 },
255 };
256
257 #define SUN50IW9_PLL_CSI_REG 0x0e0
258 static struct ccu_nkmp pll_csi_clk = {
259 .enable = BIT(27),
260 .lock = BIT(28),
261 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
262 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
263 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
264 .common = {
265 .reg = 0x0e0,
266 .hw.init = CLK_HW_INIT("pll-csi", "dcxo24M",
267 &ccu_nkmp_ops,
268 CLK_SET_RATE_UNGATE),
269 },
270 };
271
272 static const char * const cpux_parents[] = { "dcxo24M", "osc32k",
273 "iosc", "pll-cpux",
274 "pll-periph0" };
275 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
276 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
277 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
278 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
279
280 static const char * const psi_ahb1_ahb2_parents[] = { "dcxo24M", "osc32k",
281 "iosc", "pll-periph0" };
282 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
283 psi_ahb1_ahb2_parents,
284 0x510,
285 0, 2, /* M */
286 8, 2, /* P */
287 24, 2, /* mux */
288 0);
289
290 static const char * const ahb3_apb1_apb2_parents[] = { "dcxo24M", "osc32k",
291 "psi-ahb1-ahb2",
292 "pll-periph0" };
293 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
294 0, 2, /* M */
295 8, 2, /* P */
296 24, 2, /* mux */
297 0);
298
299 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
300 0, 2, /* M */
301 8, 2, /* P */
302 24, 2, /* mux */
303 0);
304
305 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
306 0, 2, /* M */
307 8, 2, /* P */
308 24, 2, /* mux */
309 0);
310
311 static const char * const mbus_parents[] = { "dcxo24M", "pll-periph0-2x",
312 "pll-ddr0", "pll-ddr1" };
313 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
314 0, 3, /* M */
315 24, 2, /* mux */
316 BIT(31), /* gate */
317 CLK_IS_CRITICAL);
318
319 static const char * const de_di_g2d_parents[] = { "pll-de", "pll-periph0-2x" };
320 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_di_g2d_parents, 0x600,
321 0, 4, /* M */
322 24, 1, /* mux */
323 BIT(31), /* gate */
324 CLK_SET_RATE_NO_REPARENT);
325
326 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
327 0x60c, BIT(0), 0);
328
329 static SUNXI_CCU_M_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
330 0, 4, /* M */
331 24, 1, /* mux */
332 BIT(31), /* gate */
333 0);
334
335 static SUNXI_CCU_GATE(bus_di_clk, "bus-di", "psi-ahb1-ahb2",
336 0x62c, BIT(0), 0);
337
338 static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", de_di_g2d_parents, 0x630,
339 0, 4, /* M */
340 24, 1, /* mux */
341 BIT(31), /* gate */
342 0);
343
344 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2",
345 0x63c, BIT(0), 0);
346
347 static const char * const gpu_parents[] = { "pll-gpu", "gpu1" };
348 static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0", gpu_parents, 0x670,
349 0, 2, /* M */
350 24, 1, /* mux */
351 BIT(31), /* gate */
352 0);
353
354 static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x",
355 0x674, 0, 2, BIT(31), 0);
356
357 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
358 0x67c, BIT(0), 0);
359
360 static const char * const ce_parents[] = { "dcxo24M", "pll-periph0-2x" };
361 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
362 0, 4, /* M */
363 8, 2, /* P */
364 24, 1, /* mux */
365 BIT(31), /* gate */
366 0);
367
368 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
369 0x68c, BIT(0), 0);
370 /*
371 * delete the mux because it has only one parent
372 */
373 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
374 0x690, 0, 3,
375 BIT(31), CLK_SET_RATE_PARENT);
376
377 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
378 0x69c, BIT(0), 0);
379
380 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
381 0x70c, BIT(0), 0);
382
383 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
384 0x73c, BIT(0), 0);
385
386 static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
387
388 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "dcxo24M",
389 0x78c, BIT(0), 0);
390
391 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
392 0x79c, BIT(0), 0);
393
394 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
395
396 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
397
398 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
399 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
400 0x800, 0, 2, 24, 2, CLK_IS_CRITICAL);
401
402 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
403 0x804, BIT(0), 0);
404 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
405 0x804, BIT(1), 0);
406 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
407 0x804, BIT(2), 0);
408 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
409 0x804, BIT(3), 0);
410 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
411 0x804, BIT(5), 0);
412 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
413 0x804, BIT(8), 0);
414 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
415 0x804, BIT(10), 0);
416
417 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
418 0x80c, BIT(0), CLK_IS_CRITICAL);
419
420 static const char * const nand_spi_parents[] = { "dcxo24M",
421 "pll-periph0",
422 "pll-periph1",
423 "pll-periph0-2x",
424 "pll-periph1-2x" };
425 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
426 0, 4, /* M */
427 8, 2, /* P */
428 24, 3, /* mux */
429 BIT(31), /* gate */
430 0);
431
432 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
433 0, 4, /* M */
434 8, 2, /* P */
435 24, 3, /* mux */
436 BIT(31), /* gate */
437 0);
438
439 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
440
441 /* don't use postdiv for bsp kernel */
442 static const char * const mmc_parents[] = { "dcxo24M", "pll-periph0-2x",
443 "pll-periph1-2x" };
444 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_parents, 0x830,
445 0, 4, /* M */
446 8, 2, /* P */
447 24, 2, /* mux */
448 BIT(31), /* gate */
449 CLK_SET_RATE_NO_REPARENT);
450
451 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_parents, 0x834,
452 0, 4, /* M */
453 8, 2, /* P */
454 24, 2, /* mux */
455 BIT(31), /* gate */
456 CLK_SET_RATE_NO_REPARENT);
457
458 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_parents, 0x838,
459 0, 4, /* M */
460 8, 2, /* P */
461 24, 2, /* mux */
462 BIT(31), /* gate */
463 CLK_SET_RATE_NO_REPARENT);
464
465 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
466 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
467 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
468
469 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
470 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
471 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
472 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
473 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0);
474 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0);
475
476 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
477 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
478 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
479 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
480 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0);
481
482 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 0x93c, BIT(0), 0);
483
484 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
485 0, 4, /* M */
486 8, 2, /* P */
487 24, 3, /* mux */
488 BIT(31), /* gate */
489 0);
490
491 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
492 0, 4, /* M */
493 8, 2, /* P */
494 24, 3, /* mux */
495 BIT(31), /* gate */
496 0);
497
498 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
499 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
500
501 static SUNXI_CCU_GATE(emac_25m_clk, "emac0-25m", "ahb3", 0x970,
502 BIT(31) | BIT(30), 0);
503
504 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0);
505 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0);
506
507 static const char * const ts_parents[] = { "dcxo24M", "pll-periph0" };
508 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
509 0, 4, /* M */
510 8, 2, /* P */
511 24, 1, /* mux */
512 BIT(31), /* gate */
513 0);
514
515 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
516
517 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "dcxo24M", 0x9ec, BIT(0), 0);
518
519 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "dcxo24M", 0x9fc, BIT(0), 0);
520
521 /*
522 * No one uses the pll-audio-hs, we do not support this clock.
523 */
524 static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x",
525 "pll-audio-4x" };
526 static struct ccu_div spdif_clk = {
527 .enable = BIT(31),
528 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
529 .mux = _SUNXI_CCU_MUX(24, 2),
530 .common = {
531 .reg = 0xa20,
532 .hw.init = CLK_HW_INIT_PARENTS("spdif",
533 audio_parents,
534 &ccu_div_ops,
535 0),
536 },
537 };
538
539 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
540
541 static struct ccu_div dmic_clk = {
542 .enable = BIT(31),
543 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
544 .mux = _SUNXI_CCU_MUX(24, 2),
545 .common = {
546 .reg = 0xa40,
547 .hw.init = CLK_HW_INIT_PARENTS("dmic",
548 audio_parents,
549 &ccu_div_ops,
550 0),
551 },
552 };
553
554 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
555
556 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_clk, "audio-codec",
557 audio_parents, 0xa50,
558 0, 4, /* M */
559 24, 2, /* mux */
560 BIT(31), /* gate */
561 0);
562
563 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x",
564 audio_parents, 0xa54,
565 0, 4, /* M */
566 24, 2, /* mux */
567 BIT(31), /* gate */
568 0);
569
570 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1",
571 0xa5c, BIT(0), 0);
572
573 static struct ccu_div audio_hub_clk = {
574 .enable = BIT(31),
575 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
576 .mux = _SUNXI_CCU_MUX(24, 2),
577 .common = {
578 .reg = 0xa60,
579 .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
580 audio_parents,
581 &ccu_div_ops,
582 0),
583 },
584 };
585
586 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1",
587 0xa6c, BIT(0), 0);
588
589 /*
590 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
591 * We will force them to 0 (12M divided from 48M).
592 */
593 #define SUN50IW9_USB0_CLK_REG 0xa70
594 #define SUN50IW9_USB1_CLK_REG 0xa74
595 #define SUN50IW9_USB2_CLK_REG 0xa78
596 #define SUN50IW9_USB3_CLK_REG 0xa7c
597
598 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
599 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "dcxo24M", 0xa70, BIT(29), 0);
600
601 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
602 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "dcxo24M", 0xa74, BIT(29), 0);
603
604 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0);
605 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "dcxo24M", 0xa78, BIT(29), 0);
606
607 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
608 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "dcxo24M", 0xa7c, BIT(29), 0);
609
610 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
611 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0);
612 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0);
613 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
614 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
615 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0);
616 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0);
617 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
618 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
619
620 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "ahb3", 0xa9c, BIT(0), 0);
621
622 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x",
623 "pll-video2", "pll-video2-4x" };
624 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
625 0, 4, /* M */
626 24, 2, /* mux */
627 BIT(31), /* gate */
628 CLK_SET_RATE_NO_REPARENT);
629
630 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "dcxo24M", 0xb04, BIT(31), 0);
631
632 static struct ccu_gate pll_periph0_2x_div_clk = {
633 .enable = BIT(30),
634 .common = {
635 .reg = 0xb10,
636 .prediv = 36621,
637 .features = CCU_FEATURE_ALL_PREDIV,
638 .hw.init = CLK_HW_INIT("pll-periph0-2x-div",
639 "pll-periph0-2x",
640 &ccu_gate_ops, 0),
641 }
642 };
643
644 static const char * const hdmi_cec_parents[] = { "osc32k",
645 "pll-periph0-2x-div" };
646 static SUNXI_CCU_MUX_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents,
647 0xb10, 24, 2, BIT(31), 0);
648
649 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
650
651 static SUNXI_CCU_GATE(bus_display_if_top_clk, "bus-display-if-top", "ahb3",
652 0xb5c, BIT(0), 0);
653
654 static const char * const video_parents[] = { "pll-video0", "pll-video0-4x",
655 "pll-video1", "pll-video1-4x" };
656 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", video_parents,
657 0xb60, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
658
659 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", video_parents,
660 0xb64, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
661
662 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
663 0xb7c, BIT(0), 0);
664 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb3",
665 0xb7c, BIT(1), 0);
666
667 /*
668 * "pll-video2", "pll-video2-4x" undocemented.
669 */
670 static const char * const tcon_tv_parents[] = { "pll-video0",
671 "pll-video0-4x",
672 "pll-video1",
673 "pll-video1-4x",
674 "pll-video2",
675 "pll-video2-4x" };
676 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
677 tcon_tv_parents, 0xb80,
678 0, 4, /* M */
679 8, 2, /* P */
680 24, 3, /* mux */
681 BIT(31), /* gate */
682 CLK_SET_RATE_NO_REPARENT);
683
684 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1",
685 tcon_tv_parents, 0xb84,
686 0, 4, /* M */
687 8, 2, /* P */
688 24, 3, /* mux */
689 BIT(31), /* gate */
690 0);
691
692 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
693 0xb9c, BIT(0), 0);
694 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3",
695 0xb9c, BIT(1), 0);
696
697 static SUNXI_CCU_MP_WITH_MUX_GATE(tve_clk, "tve", video_parents, 0xbb0,
698 0, 4, /* M */
699 8, 2, /* P */
700 24, 3, /* mux */
701 BIT(31), /* gate */
702 0);
703
704 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb3", 0xbbc, BIT(1), 0);
705
706 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3",
707 0xbbc, BIT(0), 0);
708
709 static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
710 "pll-periph0", "pll-csi" };
711 static const u8 csi_top_table[] = { 0, 2, 3, 4 };
712
713 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
714 csi_top_parents, csi_top_table,
715 0xc04, 0, 4,
716 24, 3,
717 BIT(31), 0);
718
719 static const char * const csi_mclk_parents[] = { "dcxo24M", "pll-video0",
720 "pll-periph0-2x",
721 "pll-periph1", "pll-csi"};
722 static const u8 csi_mclk_table[] = { 0, 1, 2, 3, 5};
723
724 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi-mclk0",
725 csi_mclk_parents, csi_mclk_table,
726 0xc08, 0, 5,
727 24, 3,
728 BIT(31), 0);
729
730 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi-mclk1",
731 csi_mclk_parents, csi_mclk_table,
732 0xc0c, 0, 5,
733 24, 3,
734 BIT(31), 0);
735
736 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
737
738 static const char * const hdmi_hdcp_parents[] = { "pll-periph0",
739 "pll-periph1" };
740 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_hdcp_clk, "hdmi-hdcp",
741 hdmi_hdcp_parents, 0xc40,
742 0, 4, /* M */
743 24, 2, /* mux */
744 BIT(31), /* gate */
745 0);
746
747
748 static SUNXI_CCU_GATE(bus_hdmi_hdcp_clk, "bus-hdmi-hdcp", "ahb3",
749 0xc4c, BIT(0), 0);
750
751 /* Fixed factor clocks */
752 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
753
754 static const struct clk_hw *clk_parent_pll_audio[] = {
755 &pll_audio_4x_clk.common.hw
756 };
757
758 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
759 clk_parent_pll_audio,
760 4, 1, CLK_SET_RATE_PARENT);
761 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
762 clk_parent_pll_audio,
763 2, 1, CLK_SET_RATE_PARENT);
764
765 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
766 &pll_periph0_clk.common.hw,
767 1, 2, 0);
768
769 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
770 &pll_periph1_clk.common.hw,
771 1, 2, 0);
772
773 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
774 &pll_video0_clk.common.hw,
775 1, 4, CLK_SET_RATE_PARENT);
776 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
777 &pll_video1_clk.common.hw,
778 1, 4, CLK_SET_RATE_PARENT);
779 static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x",
780 &pll_video2_clk.common.hw,
781 1, 4, CLK_SET_RATE_PARENT);
782
783 static struct ccu_common *sun50iw9_ccu_clks[] = {
784 &pll_cpux_clk.common,
785 &pll_ddr0_clk.common,
786 &pll_ddr1_clk.common,
787 &pll_periph0_clk.common,
788 &pll_periph1_pattern0_common, /* for pm resume */
789 &pll_periph1_clk.common,
790 &pll_gpu_clk.common,
791 &pll_video0_clk.common,
792 &pll_video1_clk.common,
793 &pll_video2_clk.common,
794 &pll_ve_clk.common,
795 &pll_de_clk.common,
796 &pll_audio_4x_clk.common,
797 &pll_csi_clk.common,
798 &cpux_clk.common,
799 &axi_clk.common,
800 &cpux_apb_clk.common,
801 &psi_ahb1_ahb2_clk.common,
802 &ahb3_clk.common,
803 &apb1_clk.common,
804 &apb2_clk.common,
805 &mbus_clk.common,
806 &de_clk.common,
807 &bus_de_clk.common,
808 &di_clk.common,
809 &bus_di_clk.common,
810 &g2d_clk.common,
811 &bus_g2d_clk.common,
812 &gpu0_clk.common,
813 &gpu1_clk.common,
814 &bus_gpu_clk.common,
815 &ce_clk.common,
816 &bus_ce_clk.common,
817 &ve_clk.common,
818 &bus_ve_clk.common,
819 &bus_dma_clk.common,
820 &bus_hstimer_clk.common,
821 &avs_clk.common,
822 &bus_dbg_clk.common,
823 &bus_psi_clk.common,
824 &bus_pwm_clk.common,
825 &bus_iommu_clk.common,
826 &dram_clk.common,
827 &mbus_dma_clk.common,
828 &mbus_ve_clk.common,
829 &mbus_ce_clk.common,
830 &mbus_ts_clk.common,
831 &mbus_nand_clk.common,
832 &mbus_csi_clk.common,
833 &mbus_g2d_clk.common,
834 &bus_dram_clk.common,
835 &nand0_clk.common,
836 &nand1_clk.common,
837 &bus_nand_clk.common,
838 &mmc0_clk.common,
839 &mmc1_clk.common,
840 &mmc2_clk.common,
841 &bus_mmc0_clk.common,
842 &bus_mmc1_clk.common,
843 &bus_mmc2_clk.common,
844 &bus_uart0_clk.common,
845 &bus_uart1_clk.common,
846 &bus_uart2_clk.common,
847 &bus_uart3_clk.common,
848 &bus_uart4_clk.common,
849 &bus_uart5_clk.common,
850 &bus_i2c0_clk.common,
851 &bus_i2c1_clk.common,
852 &bus_i2c2_clk.common,
853 &bus_i2c3_clk.common,
854 &bus_i2c4_clk.common,
855 &bus_scr_clk.common,
856 &spi0_clk.common,
857 &spi1_clk.common,
858 &bus_spi0_clk.common,
859 &bus_spi1_clk.common,
860 &emac_25m_clk.common,
861 &bus_emac0_clk.common,
862 &bus_emac1_clk.common,
863 &ts_clk.common,
864 &bus_ts_clk.common,
865 &bus_gpadc_clk.common,
866 &bus_ths_clk.common,
867 &spdif_clk.common,
868 &bus_spdif_clk.common,
869 &dmic_clk.common,
870 &bus_dmic_clk.common,
871 &audio_codec_clk.common,
872 &audio_codec_4x_clk.common,
873 &bus_audio_codec_clk.common,
874 &audio_hub_clk.common,
875 &bus_audio_hub_clk.common,
876 &usb_ohci0_clk.common,
877 &usb_phy0_clk.common,
878 &usb_ohci1_clk.common,
879 &usb_phy1_clk.common,
880 &usb_ohci2_clk.common,
881 &usb_phy2_clk.common,
882 &usb_ohci3_clk.common,
883 &usb_phy3_clk.common,
884 &bus_ohci0_clk.common,
885 &bus_ohci1_clk.common,
886 &bus_ohci2_clk.common,
887 &bus_ohci3_clk.common,
888 &bus_ehci0_clk.common,
889 &bus_ehci1_clk.common,
890 &bus_ehci2_clk.common,
891 &bus_ehci3_clk.common,
892 &bus_otg_clk.common,
893 &bus_lradc_clk.common,
894 &hdmi_clk.common,
895 &hdmi_slow_clk.common,
896 &pll_periph0_2x_div_clk.common,
897 &hdmi_cec_clk.common,
898 &bus_hdmi_clk.common,
899 &bus_display_if_top_clk.common,
900 &tcon_lcd0_clk.common,
901 &tcon_lcd1_clk.common,
902 &bus_tcon_lcd0_clk.common,
903 &bus_tcon_lcd1_clk.common,
904 &tcon_tv0_clk.common,
905 &tcon_tv1_clk.common,
906 &bus_tcon_tv0_clk.common,
907 &bus_tcon_tv1_clk.common,
908 &tve_clk.common,
909 &bus_tve_clk.common,
910 &bus_tve_top_clk.common,
911 &csi_top_clk.common,
912 &csi0_mclk_clk.common,
913 &csi1_mclk_clk.common,
914 &bus_csi_clk.common,
915 &hdmi_hdcp_clk.common,
916 &bus_hdmi_hdcp_clk.common,
917 };
918
919 static struct clk_hw_onecell_data sun50iw9_hw_clks = {
920 .hws = {
921 [CLK_OSC12M] = &osc12M_clk.hw,
922 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
923 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
924 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
925 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
926 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
927 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
928 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
929 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
930 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
931 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
932 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
933 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
934 [CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw,
935 [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw,
936 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
937 [CLK_PLL_DE] = &pll_de_clk.common.hw,
938 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
939 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
940 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.common.hw,
941 [CLK_PLL_CSI] = &pll_csi_clk.common.hw,
942 [CLK_CPUX] = &cpux_clk.common.hw,
943 [CLK_AXI] = &axi_clk.common.hw,
944 [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
945 [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
946 [CLK_AHB3] = &ahb3_clk.common.hw,
947 [CLK_APB1] = &apb1_clk.common.hw,
948 [CLK_APB2] = &apb2_clk.common.hw,
949 [CLK_MBUS] = &mbus_clk.common.hw,
950 [CLK_DE] = &de_clk.common.hw,
951 [CLK_BUS_DE] = &bus_de_clk.common.hw,
952 [CLK_DI] = &di_clk.common.hw,
953 [CLK_BUS_DI] = &bus_di_clk.common.hw,
954 [CLK_G2D] = &g2d_clk.common.hw,
955 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
956 [CLK_GPU0] = &gpu0_clk.common.hw,
957 [CLK_GPU1] = &gpu1_clk.common.hw,
958 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
959 [CLK_CE] = &ce_clk.common.hw,
960 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
961 [CLK_VE] = &ve_clk.common.hw,
962 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
963 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
964 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
965 [CLK_AVS] = &avs_clk.common.hw,
966 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
967 [CLK_BUS_PSI] = &bus_psi_clk.common.hw,
968 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
969 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
970 [CLK_DRAM] = &dram_clk.common.hw,
971 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
972 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
973 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
974 [CLK_MBUS_TS] = &mbus_ts_clk.common.hw,
975 [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
976 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
977 [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
978 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
979 [CLK_NAND0] = &nand0_clk.common.hw,
980 [CLK_NAND1] = &nand1_clk.common.hw,
981 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
982 [CLK_MMC0] = &mmc0_clk.common.hw,
983 [CLK_MMC1] = &mmc1_clk.common.hw,
984 [CLK_MMC2] = &mmc2_clk.common.hw,
985 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
986 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
987 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
988 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
989 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
990 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
991 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
992 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
993 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
994 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
995 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
996 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
997 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
998 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
999 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
1000 [CLK_SPI0] = &spi0_clk.common.hw,
1001 [CLK_SPI1] = &spi1_clk.common.hw,
1002 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1003 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1004 [CLK_EMAC_25M] = &emac_25m_clk.common.hw,
1005 [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw,
1006 [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw,
1007 [CLK_TS] = &ts_clk.common.hw,
1008 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
1009 [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
1010 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1011 [CLK_SPDIF] = &spdif_clk.common.hw,
1012 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1013 [CLK_DMIC] = &dmic_clk.common.hw,
1014 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
1015 [CLK_AUDIO] = &audio_codec_clk.common.hw,
1016 [CLK_AUDIO_4X] = &audio_codec_4x_clk.common.hw,
1017 [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
1018 [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw,
1019 [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw,
1020 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1021 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1022 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1023 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1024 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1025 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1026 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
1027 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
1028 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1029 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1030 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
1031 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
1032 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1033 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1034 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
1035 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
1036 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1037 [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
1038 [CLK_HDMI] = &hdmi_clk.common.hw,
1039 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
1040 [CLK_PLL_PERIPH0_2X_DIV] = &pll_periph0_2x_div_clk.common.hw,
1041 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
1042 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
1043 [CLK_BUS_DISPLAY_IF_TOP] = &bus_display_if_top_clk.common.hw,
1044 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1045 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
1046 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1047 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
1048 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
1049 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
1050 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
1051 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
1052 [CLK_TVE] = &tve_clk.common.hw,
1053 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
1054 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1055 [CLK_CSI_TOP] = &csi_top_clk.common.hw,
1056 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1057 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1058 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
1059 [CLK_HDMI_HDCP] = &hdmi_hdcp_clk.common.hw,
1060 [CLK_BUS_HDMI_HDCP] = &bus_hdmi_hdcp_clk.common.hw,
1061 },
1062 .num = CLK_NUMBER,
1063 };
1064
1065 static struct ccu_reset_map sun50iw9_ccu_resets[] = {
1066 [RST_MBUS] = { 0x540, BIT(30) },
1067
1068 [RST_BUS_DE] = { 0x60c, BIT(16) },
1069 [RST_BUS_DI] = { 0x62c, BIT(16) },
1070 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1071 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1072 [RST_BUS_CE] = { 0x68c, BIT(16) },
1073 [RST_BUS_VE] = { 0x69c, BIT(16) },
1074 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1075 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1076 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1077 [RST_BUS_PSI] = { 0x79c, BIT(16) },
1078 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1079 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1080 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1081 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1082 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1083 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1084 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1085 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1086 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1087 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1088 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1089 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1090 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1091 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1092 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1093 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1094 [RST_BUS_I2C4] = { 0x91c, BIT(20) },
1095 [RST_BUS_SCR] = { 0x93c, BIT(16) },
1096 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1097 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1098 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1099 [RST_BUS_EMAC1] = { 0x97c, BIT(17) },
1100 [RST_BUS_TS] = { 0x9bc, BIT(16) },
1101 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1102 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1103 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1104 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1105 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
1106 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
1107
1108 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1109 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1110 [RST_USB_PHY2] = { 0xa78, BIT(30) },
1111 [RST_USB_PHY3] = { 0xa7c, BIT(30) },
1112
1113 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1114 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1115 [RST_BUS_OHCI2] = { 0xa8c, BIT(18) },
1116 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
1117 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1118 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1119 [RST_BUS_EHCI2] = { 0xa8c, BIT(22) },
1120 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
1121 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1122
1123 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1124 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1125 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1126 [RST_BUS_DISPLAY_IF_TOP] = { 0xb5c, BIT(16) },
1127 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1128 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
1129 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1130 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1131 [RST_BUS_LVDS] = { 0xbac, BIT(16) },
1132 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1133 [RST_BUS_TVE] = { 0xbbc, BIT(17) },
1134 [RST_BUS_CSI] = { 0xc2c, BIT(16) },
1135 [RST_BUS_HDMI_HDCP] = { 0xc4c, BIT(16) },
1136 };
1137
1138 static const struct sunxi_ccu_desc sun50iw9_ccu_desc = {
1139 .ccu_clks = sun50iw9_ccu_clks,
1140 .num_ccu_clks = ARRAY_SIZE(sun50iw9_ccu_clks),
1141
1142 .hw_clks = &sun50iw9_hw_clks,
1143
1144 .resets = sun50iw9_ccu_resets,
1145 .num_resets = ARRAY_SIZE(sun50iw9_ccu_resets),
1146 };
1147
1148 static const u32 sun50iw9_pll_regs[] = {
1149 SUN50IW9_PLL_CPUX_REG,
1150 SUN50IW9_PLL_DDR0_REG,
1151 SUN50IW9_PLL_DDR1_REG,
1152 SUN50IW9_PLL_PERIPH0_REG,
1153 SUN50IW9_PLL_PERIPH1_REG,
1154 SUN50IW9_PLL_GPU_REG,
1155 SUN50IW9_PLL_VIDEO0_REG,
1156 SUN50IW9_PLL_VIDEO1_REG,
1157 SUN50IW9_PLL_VIDEO2_REG,
1158 SUN50IW9_PLL_VE_REG,
1159 SUN50IW9_PLL_DE_REG,
1160 SUN50IW9_PLL_AUDIO_REG,
1161 SUN50IW9_PLL_CSI_REG,
1162 };
1163
1164 static const u32 sun50iw9_pll_video_regs[] = {
1165 SUN50IW9_PLL_VIDEO0_REG,
1166 SUN50IW9_PLL_VIDEO1_REG,
1167 SUN50IW9_PLL_VIDEO2_REG,
1168 };
1169
1170 static const u32 sun50iw9_usb_clk_regs[] = {
1171 SUN50IW9_USB0_CLK_REG,
1172 SUN50IW9_USB1_CLK_REG,
1173 SUN50IW9_USB2_CLK_REG,
1174 SUN50IW9_USB3_CLK_REG,
1175 };
1176
1177 static struct ccu_pll_nb sun50iw9_pll_cpu_nb = {
1178 .common = &pll_cpux_clk.common,
1179 /* copy from pll_cpux_clk */
1180 .enable = BIT(27),
1181 .lock = BIT(28),
1182 };
1183
1184 static struct ccu_mux_nb sun50iw9_cpu_nb = {
1185 .common = &cpux_clk.common,
1186 .cm = &cpux_clk.mux,
1187 .delay_us = 1,
1188 .bypass_index = 4, /* index of pll periph0 */
1189 };
1190
sun50iw9_ccu_probe(struct platform_device * pdev)1191 static int sun50iw9_ccu_probe(struct platform_device *pdev)
1192 {
1193 void __iomem *reg;
1194 int ret;
1195 int i;
1196
1197 reg = devm_platform_ioremap_resource(pdev, 0);
1198 if (IS_ERR(reg))
1199 return PTR_ERR(reg);
1200
1201 /* Enable the lock bits on all PLLs */
1202 for (i = 0; i < ARRAY_SIZE(sun50iw9_pll_regs); i++) {
1203 set_reg(reg + sun50iw9_pll_regs[i], 1, 1, 29);
1204 }
1205
1206 /*
1207 * In order to pass the EMI certification, the SDM function of
1208 * the peripheral 1 bus is enabled, and the frequency is still
1209 * calculated using the previous division factor.
1210 */
1211 set_reg(reg + SUN50IW9_PLL_PERIPH1_PATTERN0_REG, 0xd1303333, 32, 0);
1212 set_reg(reg + SUN50IW9_PLL_PERIPH1_REG, 1, 1, 24);
1213
1214 /*
1215 * Force the output divider of video PLLs to 0.
1216 *
1217 * See the comment before pll-video0 definition for the reason.
1218 */
1219 for (i = 0; i < ARRAY_SIZE(sun50iw9_pll_video_regs); i++) {
1220 set_reg(reg + sun50iw9_pll_video_regs[i], 0x0, 1, 0);
1221 }
1222
1223 /* Enforce m1 = 0, m0 = 1 for Audio PLL */
1224 set_reg(reg + SUN50IW9_PLL_AUDIO_REG, 0x1, 2, 0);
1225
1226 /*
1227 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
1228 *
1229 * This clock mux is still mysterious, and the code just enforces
1230 * it to have a valid clock parent.
1231 */
1232 for (i = 0; i < ARRAY_SIZE(sun50iw9_usb_clk_regs); i++) {
1233 set_reg(reg + sun50iw9_usb_clk_regs[i], 0x0, 2, 24);
1234 }
1235
1236 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50iw9_ccu_desc);
1237 if (ret)
1238 return ret;
1239
1240 /* Gate then ungate PLL CPU after any rate changes */
1241 ccu_pll_notifier_register(&sun50iw9_pll_cpu_nb);
1242
1243 /* Reparent CPU during PLL CPU rate changes */
1244 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1245 &sun50iw9_cpu_nb);
1246
1247 sunxi_ccu_sleep_init(reg, sun50iw9_ccu_clks,
1248 ARRAY_SIZE(sun50iw9_ccu_clks),
1249 NULL, 0);
1250
1251 return 0;
1252 }
1253
1254 static const struct of_device_id sun50iw9_ccu_ids[] = {
1255 { .compatible = "allwinner,sun50iw9-ccu" },
1256 { }
1257 };
1258
1259 static struct platform_driver sun50iw9_ccu_driver = {
1260 .probe = sun50iw9_ccu_probe,
1261 .driver = {
1262 .name = "sun50iw9-ccu",
1263 .of_match_table = sun50iw9_ccu_ids,
1264 },
1265 };
1266
sunxi_ccu_sun50iw9_init(void)1267 static int __init sunxi_ccu_sun50iw9_init(void)
1268 {
1269 return platform_driver_register(&sun50iw9_ccu_driver);
1270 }
1271 core_initcall(sunxi_ccu_sun50iw9_init);
1272
sunxi_ccu_sun50iw9_exit(void)1273 static void __exit sunxi_ccu_sun50iw9_exit(void)
1274 {
1275 return platform_driver_unregister(&sun50iw9_ccu_driver);
1276 }
1277 module_exit(sunxi_ccu_sun50iw9_exit);
1278
1279 MODULE_DESCRIPTION("Allwinner sun50iw9 clk driver");
1280 MODULE_LICENSE("GPL v2");
1281 MODULE_VERSION("1.0.5");
1282