1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 huangzhenwei@allwinnertech.com
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of_address.h>
10 #include <linux/platform_device.h>
11
12 #include "ccu_common.h"
13 #include "ccu_reset.h"
14
15 #include "ccu_div.h"
16 #include "ccu_gate.h"
17 #include "ccu_mp.h"
18 #include "ccu_mult.h"
19 #include "ccu_nk.h"
20 #include "ccu_nkm.h"
21 #include "ccu_nkmp.h"
22 #include "ccu_nm.h"
23
24 #include "ccu-sun8iw20.h"
25
26 /* ccu_des_start */
27 /*
28 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
29 * P should only be used for output frequencies lower than 288 MHz.
30 *
31 * For now we can just model it as a multiplier clock, and force P to /1.
32 *
33 * The M factor is present in the register's description, but not in the
34 * frequency formula, and it's documented as "M is only used for backdoor
35 * testing", so it's not modelled and then force to 0.
36 */
37 #define SUN8IW20_PLL_CPUX_REG 0x000
38 static struct ccu_mult pll_cpux_clk = {
39 .enable = BIT(27),
40 .lock = BIT(28),
41 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
42 .common = {
43 .reg = 0x000,
44 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
45 &ccu_mult_ops,
46 CLK_SET_RATE_UNGATE),
47 },
48 };
49
50 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
51 #define SUN8IW20_PLL_DDR0_REG 0x010
52 static struct ccu_nkmp pll_ddr0_clk = {
53 .enable = BIT(27),
54 .lock = BIT(28),
55 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
56 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
57 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
58 .common = {
59 .reg = 0x010,
60 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
61 &ccu_nkmp_ops,
62 CLK_SET_RATE_UNGATE |
63 CLK_IS_CRITICAL),
64 },
65 };
66
67 #define SUN8IW20_PLL_PERIPH0_REG 0x020
68 static struct ccu_nm pll_periph0_parent_clk = {
69 .enable = BIT(27),
70 .lock = BIT(28),
71 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
72 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
73 .common = {
74 .reg = 0x020,
75 .hw.init = CLK_HW_INIT("pll-periph0-parent", "dcxo24M",
76 &ccu_nm_ops,
77 CLK_SET_RATE_UNGATE),
78 },
79 };
80
81 static SUNXI_CCU_M(pll_periph0_2x_clk, "pll-periph0-2x",
82 "pll-periph0-parent", 0x020, 16, 3, 0);
83
84 static SUNXI_CCU_M(pll_periph0_800m_clk, "pll-periph0-800m",
85 "pll-periph0-parent", 0x020, 20, 3, 0);
86
87 /*
88 * For Video PLLs, the output divider is described as "used for testing"
89 * in the user manual. So it's not modelled and forced to 0.
90 */
91 #define SUN8IW20_PLL_VIDEO0_REG 0x040
92 static struct ccu_nm pll_video0_clk = {
93 .enable = BIT(27),
94 .lock = BIT(28),
95 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
96 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
97 .fixed_post_div = 4,
98 .min_rate = 288000000,
99 .max_rate = 2400000000UL,
100 .common = {
101 .reg = 0x040,
102 .features = CCU_FEATURE_FIXED_POSTDIV,
103 .hw.init = CLK_HW_INIT("pll-video0", "dcxo24M",
104 &ccu_nm_ops,
105 CLK_SET_RATE_UNGATE),
106 },
107 };
108
109 #define SUN8IW20_PLL_VIDEO1_REG 0x048
110 static struct ccu_nm pll_video1_clk = {
111 .enable = BIT(27),
112 .lock = BIT(28),
113 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
114 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
115 .fixed_post_div = 4,
116 .min_rate = 288000000,
117 .max_rate = 2400000000UL,
118 .common = {
119 .reg = 0x048,
120 .features = CCU_FEATURE_FIXED_POSTDIV,
121 .hw.init = CLK_HW_INIT("pll-video1", "dcxo24M",
122 &ccu_nm_ops,
123 CLK_SET_RATE_UNGATE),
124 },
125 };
126
127 #define SUN8IW20_PLL_VE_REG 0x058
128 static struct ccu_nkmp pll_ve_clk = {
129 .enable = BIT(27),
130 .lock = BIT(28),
131 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
132 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
133 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
134 .common = {
135 .reg = 0x058,
136 .hw.init = CLK_HW_INIT("pll-ve", "dcxo24M",
137 &ccu_nkmp_ops,
138 CLK_SET_RATE_UNGATE),
139 },
140 };
141
142 /*
143 * The Audio PLL has m0, m1 dividers in addition to the usual N, M
144 * factors. Since we only need 4 frequencies from this PLL: 22.5792 MHz,
145 * 24.576 MHz, 90.3168MHz and 98.304MHz ignore them for now.
146 * Enforce the default for them, which is d1 = 0, d2 = 1.
147 */
148 #define SUN8IW20_PLL_AUDIO0_REG 0x078
149 static struct ccu_sdm_setting pll_audio0_sdm_table[] = {
150 { .rate = 45158400, .pattern = 0xc001bcd3, .m = 18, .n = 33 },
151 { .rate = 49152000, .pattern = 0xc001eb85, .m = 20, .n = 40 },
152 { .rate = 180633600, .pattern = 0xc001288d, .m = 3, .n = 22 },
153 { .rate = 196608000, .pattern = 0xc001eb85, .m = 5, .n = 40 },
154 };
155
156 static struct ccu_nm pll_audio0_4x_clk = {
157 .enable = BIT(27),
158 .lock = BIT(28),
159 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
160 .m = _SUNXI_CCU_DIV(16, 6),
161 .fixed_post_div = 2,
162 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
163 0x178, BIT(31)),
164 .common = {
165 .reg = 0x078,
166 .features = CCU_FEATURE_FIXED_POSTDIV |
167 CCU_FEATURE_SIGMA_DELTA_MOD,
168 .hw.init = CLK_HW_INIT("pll-audio0-4x", "dcxo24M",
169 &ccu_nm_ops,
170 CLK_SET_RATE_UNGATE),
171 },
172 };
173
174 /*
175 * PLL_AUDIO1 don't need Fractional-N. The output is usually 614.4M for audio
176 * The codec-adc or dac should be divided by themself to output the 24.576M
177 */
178 #define SUN8IW20_PLL_AUDIO1_REG 0x080
179 static struct ccu_nm pll_audio1_clk = {
180 .enable = BIT(27),
181 .lock = BIT(28),
182 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
183 .m = _SUNXI_CCU_DIV(1, 1),
184 .common = {
185 .reg = 0x080,
186 .hw.init = CLK_HW_INIT("pll-audio1", "dcxo24M",
187 &ccu_nm_ops,
188 CLK_SET_RATE_UNGATE),
189 },
190 };
191 static SUNXI_CCU_M(pll_audio1_div2_clk, "pll-audio1-div2", "pll-audio1", 0x080, 16, 3, 0);
192 static SUNXI_CCU_M(pll_audio1_div5_clk, "pll-audio1-div5", "pll-audio1", 0x080, 20, 3, 0);
193
194 static struct clk_div_table pll_cpux_div_table[] = {
195 { .val = 0, .div = 1 },
196 { .val = 1, .div = 2 },
197 { .val = 2, .div = 4 },
198 { /* Sentinel */ },
199 };
200 /* TODO: do not use P unless cpux-clk under 288Mhz */
201 static SUNXI_CCU_DIV_TABLE(pll_cpux_div, "pll-cpux-div",
202 "pll-cpux", 0x500, 16, 2,
203 pll_cpux_div_table, CLK_SET_RATE_PARENT);
204
205 static const char * const cpux_parents[] = { "dcxo24M", "osc32k",
206 "iosc", "pll-cpux-div",
207 "pll-periph0", "pll-periph0-2x",
208 "pll-periph0-800M" };
209
210 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
211 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
212
213 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
214
215 static SUNXI_CCU_M(apb_clk, "apb", "cpux", 0x500, 8, 2, 0);
216
217 static const char * const psi_ahb_parents[] = { "dcxo24M", "osc32k",
218 "iosc", "pll-periph0" };
219 static SUNXI_CCU_MP_WITH_MUX(psi_ahb_clk, "psi-ahb",
220 psi_ahb_parents,
221 0x510,
222 0, 2, /* M */
223 8, 2, /* P */
224 24, 2, /* mux */
225 0);
226
227 static const char * const apb0_apb1_parents[] = { "dcxo24M", "osc32k",
228 "psi-ahb", "pll-periph0" };
229 static SUNXI_CCU_MP_WITH_MUX(apb0_clk, "apb0", apb0_apb1_parents, 0x520,
230 0, 5, /* M */
231 8, 2, /* P */
232 24, 2, /* mux */
233 0);
234
235 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb0_apb1_parents, 0x524,
236 0, 5, /* M */
237 8, 2, /* P */
238 24, 2, /* mux */
239 0);
240
241 static const char * const de_di_g2d_parents[] = { "pll-periph0-2x", "pll-video0-4x",
242 "pll-video1-4x", "pll-audio1-div2" };
243 static SUNXI_CCU_M_WITH_MUX_GATE(de0_clk, "de0", de_di_g2d_parents, 0x600,
244 0, 5, /* M */
245 24, 3, /* mux */
246 BIT(31), /* gate */
247 CLK_SET_RATE_PARENT);
248
249 static SUNXI_CCU_GATE(bus_de0_clk, "bus-de0", "psi-ahb",
250 0x60c, BIT(0), 0);
251
252 static SUNXI_CCU_M_WITH_MUX_GATE(di_clk, "di", de_di_g2d_parents, 0x620,
253 0, 5, /* M */
254 24, 3, /* mux */
255 BIT(31), /* gate */
256 CLK_SET_RATE_PARENT);
257
258 static SUNXI_CCU_GATE(bus_di_clk, "bus-di", "psi-ahb",
259 0x62c, BIT(0), 0);
260
261 static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d",
262 de_di_g2d_parents,
263 0x630,
264 0, 5, /* M */
265 24, 3, /* mux */
266 BIT(31), /* gate */
267 0);
268
269 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb",
270 0x63c, BIT(0), 0);
271
272 static const char * const ce_parents[] = { "dcxo24M", "pll-periph0-2x",
273 "pll-periph0" };
274 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
275 0, 4, /* M */
276 8, 2, /* P */
277 24, 3, /* mux */
278 BIT(31), /* gate */
279 0);
280
281 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb",
282 0x68c, BIT(0), 0);
283
284 static const char * const ve_parents[] = { "pll-ve", "pll-periph0-2x" };
285 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
286 0, 5, /* M */
287 24, 1, /* mux */
288 BIT(31), /* gate */
289 CLK_SET_RATE_PARENT);
290
291 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb",
292 0x69c, BIT(0), 0);
293
294 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb",
295 0x70c, BIT(0), 0);
296
297 static SUNXI_CCU_GATE(bus_msgbox0_clk, "bus-msgbox0", "psi-ahb",
298 0x71c, BIT(0), 0);
299
300 static SUNXI_CCU_GATE(bus_msgbox1_clk, "bus-msgbox1", "psi-ahb",
301 0x71c, BIT(1), 0);
302
303 static SUNXI_CCU_GATE(bus_msgbox2_clk, "bus-msgbox2", "psi-ahb",
304 0x71c, BIT(2), 0);
305
306 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb",
307 0x72c, BIT(0), 0);
308
309 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb",
310 0x73c, BIT(0), 0);
311
312 static SUNXI_CCU_GATE(avs_clk, "avs", "dcxo24M", 0x740, BIT(31), 0);
313
314 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb",
315 0x78c, BIT(0), 0);
316
317 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb0", 0x7ac, BIT(0), 0);
318
319 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb0", 0x7bc, BIT(0), 0);
320
321 static const char * const dram_parents[] = { "pll-ddr0", "pll-audio1-div2",
322 "pll-periph0-2x", "pll-periph0-800m" };
323 static SUNXI_CCU_MP_WITH_MUX_GATE(dram_clk, "dram-clk",
324 dram_parents, 0x800,
325 0, 2, /* M */
326 8, 2, /* P */
327 24, 2, /* MUX */
328 BIT(31), 0);
329
330 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
331 0x804, BIT(0), 0);
332 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
333 0x804, BIT(1), 0);
334 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
335 0x804, BIT(2), 0);
336 static SUNXI_CCU_GATE(mbus_tvin_clk, "mbus-tvin", "mbus",
337 0x804, BIT(7), 0);
338 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
339 0x804, BIT(8), 0);
340 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus",
341 0x804, BIT(10), 0);
342
343 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb",
344 0x80c, BIT(0), CLK_IS_CRITICAL);
345
346 /* don't use postdiv for bsp kernel */
347 static const char * const mmc0_mmc1_parents[] = { "dcxo24M", "pll-periph0",
348 "pll-periph0-2x", "pll-audio1-div2" };
349 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,
350 0, 4, /* M */
351 8, 2, /* N->P */
352 24, 3, /* mux */
353 BIT(31), /* gate */
354 CLK_SET_RATE_NO_REPARENT);
355
356 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,
357 0, 4, /* M */
358 8, 2, /* N */
359 24, 3, /* mux */
360 BIT(31), /* gate */
361 CLK_SET_RATE_NO_REPARENT);
362
363 static const char * const mmc2_parents[] = { "dcxo24M", "pll-periph0",
364 "pll-periph0-2x", "pll-periph0-800m",
365 "pll-audio1-div2" };
366 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,
367 0, 4, /* M */
368 8, 2, /* N */
369 24, 3, /* mux */
370 BIT(31), /* gate */
371 CLK_SET_RATE_NO_REPARENT);
372
373 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "psi-ahb", 0x84c, BIT(0), 0);
374 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "psi-ahb", 0x84c, BIT(1), 0);
375 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "psi-ahb", 0x84c, BIT(2), 0);
376
377 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1", 0x90c, BIT(0), 0);
378 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1", 0x90c, BIT(1), 0);
379 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1", 0x90c, BIT(2), 0);
380 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1", 0x90c, BIT(3), 0);
381 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1", 0x90c, BIT(4), 0);
382 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1", 0x90c, BIT(5), 0);
383
384 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1", 0x91c, BIT(0), 0);
385 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1", 0x91c, BIT(1), 0);
386 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1", 0x91c, BIT(2), 0);
387 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1", 0x91c, BIT(3), 0);
388
389 static const char * const spi_parents[] = { "dcxo24M", "pll-periph0",
390 "pll-periph0-2x", "pll-audio1-div2",
391 "pll-audio1-div5" };
392 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940,
393 0, 4, /* M */
394 8, 2, /* N */
395 24, 3, /* mux */
396 BIT(31), /* gate */
397 0);
398
399 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944,
400 0, 4, /* M */
401 8, 2, /* N */
402 24, 3, /* mux */
403 BIT(31), /* gate */
404 0);
405
406 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "psi-ahb", 0x96c, BIT(0), 0);
407 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "psi-ahb", 0x96c, BIT(1), 0);
408
409 static SUNXI_CCU_GATE(emac0_25m_clk, "emac0-25m", "pll-periph0", 0x970,
410 BIT(31) | BIT(30), 0);
411
412 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "psi-ahb", 0x97c, BIT(0), 0);
413
414 static const char * const ir_parents[] = { "dcxo24M", "pll-periph0" };
415 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_parents, 0x9c0,
416 0, 4, /* M */
417 8, 2, /* N */
418 24, 3, /* mux */
419 BIT(31), /* gate */
420 0);
421
422 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb0", 0x9cc, BIT(0), 0);
423
424 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0", 0x9ec, BIT(0), 0);
425
426 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb0", 0x9fc, BIT(0), 0);
427
428 static const char * const i2s_spdif_tx_parents[] = { "pll-audio0", "pll-audio0-4x",
429 "pll-audio1-div2", "pll-audio1-div5" };
430 static SUNXI_CCU_MP_WITH_MUX_GATE(i2s0_clk, "i2s0", i2s_spdif_tx_parents, 0xa10,
431 0, 5, /* M */
432 8, 2, /* N */
433 24, 3, /* mux */
434 BIT(31), /* gate */
435 0);
436
437 static SUNXI_CCU_MP_WITH_MUX_GATE(i2s1_clk, "i2s1", i2s_spdif_tx_parents, 0xa14,
438 0, 5, /* M */
439 8, 2, /* N */
440 24, 3, /* mux */
441 BIT(31), /* gate */
442 0);
443
444 static SUNXI_CCU_MP_WITH_MUX_GATE(i2s2_clk, "i2s2", i2s_spdif_tx_parents, 0xa18,
445 0, 5, /* M */
446 8, 2, /* N */
447 24, 3, /* mux */
448 BIT(31), /* gate */
449 0);
450
451 static const char * const i2s2_asrc_parents[] = { "pll-audio0-4x", "pll-periph0",
452 "pll-audio1-div2", "pll-audio1-div5" };
453
454 static SUNXI_CCU_MP_WITH_MUX_GATE(i2s2_asrc_clk, "i2s2-asrc", i2s2_asrc_parents, 0xa1c,
455 0, 5, /* M */
456 8, 2, /* N */
457 24, 3, /* mux */
458 BIT(31), /* gate */
459 0);
460
461 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa20, BIT(0), 0);
462 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa20, BIT(1), 0);
463 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa20, BIT(2), 0);
464
465 static SUNXI_CCU_MP_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", i2s_spdif_tx_parents, 0xa24,
466 0, 5, /* M */
467 8, 2, /* N */
468 24, 3, /* mux */
469 BIT(31), /* gate */
470 0);
471
472 static const char * const spdif_rx_parents[] = { "pll-periph0", "pll-audio1-div2",
473 "pll-audio1-div5" };
474
475 static SUNXI_CCU_MP_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0xa28,
476 0, 5, /* M */
477 8, 2, /* N */
478 24, 3, /* mux */
479 BIT(31), /* gate */
480 0);
481
482 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0", 0xa2c, BIT(0), 0);
483
484 static const char * const dmic_codec_parents[] = { "pll-audio0", "pll-audio1-div2",
485 "pll-audio1-div5" };
486
487 static SUNXI_CCU_MP_WITH_MUX_GATE(dmic_clk, "dmic", dmic_codec_parents, 0xa40,
488 0, 5, /* M */
489 8, 2, /* N */
490 24, 3, /* mux */
491 BIT(31), /* gate */
492 0);
493
494 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb0", 0xa4c, BIT(0), 0);
495
496 static SUNXI_CCU_MP_WITH_MUX_GATE(audio_codec_dac_clk, "audio-codec-dac", dmic_codec_parents, 0xa50,
497 0, 5, /* M */
498 8, 2, /* N */
499 24, 3, /* mux */
500 BIT(31), /* gate */
501 CLK_SET_RATE_NO_REPARENT);
502
503 static SUNXI_CCU_MP_WITH_MUX_GATE(audio_codec_adc_clk, "audio-codec-adc", dmic_codec_parents, 0xa54,
504 0, 5, /* M */
505 8, 2, /* N */
506 24, 3, /* mux */
507 BIT(31), /* gate */
508 CLK_SET_RATE_NO_REPARENT);
509
510 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb0", 0xa5c, BIT(0), 0);
511
512 /*
513 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
514 * We will force them to 0 (12M divided from 48M).
515 */
516 #define SUN8IW20_USB0_CLK_REG 0xa70
517 #define SUN8IW20_USB1_CLK_REG 0xa74
518
519 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
520
521 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0);
522
523 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "psi-ahb", 0xa8c, BIT(0), 0);
524 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "psi-ahb", 0xa8c, BIT(1), 0);
525 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "psi-ahb", 0xa8c, BIT(4), 0);
526 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "psi-ahb", 0xa8c, BIT(5), 0);
527 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "psi-ahb", 0xa8c, BIT(8), 0);
528
529 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "psi-ahb", 0xa9c, BIT(0), 0);
530
531 static SUNXI_CCU_GATE(bus_dpss_top0_clk, "bus-dpss-top0", "psi-ahb",
532 0xabc, BIT(0), 0);
533
534 static SUNXI_CCU_GATE(hdmi_24m_clk, "hdmi-24m", "dcxo24M", 0xb04, BIT(31), 0);
535
536 static const char * const hdmi_cec_parents[] = { "osc32k", "hdmi-cec-32k" };
537 static SUNXI_CCU_MUX_WITH_GATE(hdmi_cec_clk, "hdmi-cec",
538 hdmi_cec_parents,
539 0xb10,
540 24, 1, /* mux */
541 BIT(31) | BIT(30), /* TODO:gate peri*/
542 0);
543
544 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "psi-ahb", 0xb1c, BIT(0), 0);
545
546 static const char * const mipi_dsi_parents[] = { "dcxo24M", "pll-periph0",
547 "pll-video0-2x", "pll-video1-2x",
548 "pll-audio1-div2" };
549 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi",
550 mipi_dsi_parents,
551 0xb24,
552 0, 4, /* M */
553 24, 3, /* mux */
554 BIT(31), /* gate */
555 0);
556
557 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "psi-ahb",
558 0xb4c, BIT(0), 0);
559
560 static const char * const hdmi_tcon_tve_parents[] = { "pll-video0", "pll-video0-4x",
561 "pll-video1", "pll-video1-4x",
562 "pll-periph0-2x", "pll-audio1-div2" };
563 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0",
564 hdmi_tcon_tve_parents, 0xb60,
565 0, 4, /* M */
566 8, 2, /* N */
567 24, 3, /* mux */
568 BIT(31), /* gate */
569 CLK_SET_RATE_NO_REPARENT);
570
571 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "psi-ahb",
572 0xb7c, BIT(0), 0);
573
574 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv_clk, "tcon-tv",
575 hdmi_tcon_tve_parents, 0xb80,
576 0, 4, /* M */
577 8, 2, /* N */
578 24, 3, /* mux */
579 BIT(31), /* gate */
580 CLK_SET_RATE_NO_REPARENT);
581
582 static SUNXI_CCU_GATE(bus_tcon_tv_clk, "bus-tcon-tv", "psi-ahb",
583 0xb9c, BIT(0), 0);
584
585 static SUNXI_CCU_MP_WITH_MUX_GATE(tve_clk, "tve",
586 hdmi_tcon_tve_parents, 0xbb0,
587 0, 4, /* M */
588 8, 2, /* N */
589 24, 3, /* mux */
590 BIT(31), /* gate */
591 0);
592
593 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "psi-ahb",
594 0xbbc, BIT(0), 0);
595 static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "psi-ahb",
596 0xbbc, BIT(1), 0);
597
598 static const char * const tvd_parents[] = { "dcxo24M", "pll-video0",
599 "pll-video1", "pll-periph0" };
600 static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd",
601 tvd_parents,
602 0xbc0,
603 0, 5, /* M */
604 24, 3, /* mux */
605 BIT(31), /* gate */
606 0);
607
608 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "psi-ahb",
609 0xbdc, BIT(0), 0);
610 static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "psi-ahb",
611 0xbdc, BIT(1), 0);
612
613 static const char * const ledc_parents[] = { "dcxo24M", "pll-periph0" };
614 static SUNXI_CCU_MP_WITH_MUX_GATE(ledc_clk, "ledc",
615 ledc_parents, 0xbf0,
616 0, 4,
617 8, 2,
618 24, 1,
619 BIT(31),
620 0);
621
622 static SUNXI_CCU_GATE(bus_ledc_clk, "bus-ledc", "psi-ahb",
623 0xbfc, BIT(0), 0);
624
625 static const char * const csi_top_parents[] = { "pll-periph0-2x", "pll-video0-2x",
626 "pll-video1-2x" };
627 static SUNXI_CCU_M_WITH_MUX_GATE(csi_top_clk, "csi-top",
628 csi_top_parents, 0xc04,
629 0, 4, /* M */
630 24, 3, /* mux */
631 BIT(31), /* gate */
632 0);
633
634 static const char * const csi0_mclk_parents[] = { "dcxo24M", "pll-periph0",
635 "pll-video0", "pll-video1",
636 "pll-audio-div2", "pll-audio-div5" };
637 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk",
638 csi0_mclk_parents, 0xc08,
639 0, 5, /* M */
640 24, 3, /* mux */
641 BIT(31), /* gate */
642 CLK_SET_RATE_NO_REPARENT);
643
644 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "psi-ahb", 0xc1c, BIT(0), 0);
645
646 static const char * const tpadc_parents[] = { "dcxo24M", "pll-audio0" };
647 static SUNXI_CCU_MUX_WITH_GATE(tpadc_clk, "tpadc",
648 tpadc_parents, 0xc50,
649 24, 3, /* mux */
650 BIT(31), /* gate */
651 0);
652
653 static SUNXI_CCU_GATE(bus_tpadc_clk, "bus-tpadc", "apb0", 0xc5c, BIT(0), 0);
654
655 static SUNXI_CCU_GATE(bus_tzma_clk, "bus-tzma", "apb0", 0xc6c, BIT(0), 0);
656
657 static const char * const dsp_parents[] = { "dcxo24M", "osc32k",
658 "iosc", "pll-periph0-2x" };
659 static SUNXI_CCU_M_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70,
660 0, 4,
661 24, 3,
662 BIT(31), 0);
663
664 static SUNXI_CCU_GATE(bus_dsp_cfg_clk, "bus-dsp-cfg", "psi-ahb", 0xc7c, BIT(1), 0);
665
666 static const char * const riscv_parents[] = { "dcxo24M", "osc32k",
667 "iosc", "pll-periph0-800m",
668 "pll-periph0", "pll-cpux",
669 "pll-audio1-div2"};
670 static struct ccu_div riscv_clk = {
671 .div = _SUNXI_CCU_DIV(0, 5),
672 .mux = _SUNXI_CCU_MUX(24, 3),
673 .common = {
674 .reg = 0xd00,
675 .features = CCU_FEATURE_REPEAT_SET_MUX,
676 .hw.init = CLK_HW_INIT_PARENTS("riscv", riscv_parents,
677 &ccu_div_ops,
678 CLK_SET_RATE_PARENT |
679 CLK_SET_RATE_NO_REPARENT),
680 },
681 };
682
683 /* The riscv-axi clk needs to be divided by at least 2 */
684 static struct clk_div_table riscv_axi_table[] = {
685 { .val = 1, .div = 2 },
686 { .val = 2, .div = 3 },
687 { .val = 3, .div = 4 },
688 { /* Sentinel */ },
689 };
690 static SUNXI_CCU_DIV_TABLE(riscv_axi_clk, "riscv-axi",
691 "riscv", 0xd00, 8, 2,
692 riscv_axi_table, 0);
693
694 static SUNXI_CCU_GATE(bus_riscv_cfg_clk, "bus-riscv-cfg", "psi-ahb",
695 0xd0c, BIT(0), 0);
696
697 /* Add the cpu fanout clk */
698 static SUNXI_CCU_GATE(fanout_24m_clk, "fanout-24m",
699 "dcxo24M", 0xf30, BIT(0), 0);
700 static SUNXI_CCU_GATE(fanout_12m_clk, "fanout-12m",
701 "osc12M", 0xf30, BIT(1), 0);
702 static SUNXI_CCU_GATE_WITH_PREDIV(fanout_16m_clk, "fanout-16m",
703 "pll-periph0-2x", 0xf30,
704 75, /* prediv */
705 BIT(2), 0);
706 static SUNXI_CCU_GATE_WITH_PREDIV(fanout_25m_clk, "fanout-25m",
707 "pll-periph0", 0xf30,
708 24, /* prediv */
709 BIT(3), 0);
710 static SUNXI_CCU_GATE_WITH_PREDIV(fanout_32k_clk, "fanout-32k",
711 "pll-periph0-2x", 0xf30,
712 36621, /* prediv */
713 BIT(4), 0);
714
715 static const char * const fanout_27m_parents[] = { "pll-video0", "pll-video1" };
716 static SUNXI_CCU_MP_WITH_MUX_GATE_NO_INDEX(fanout_27m_clk, "fanout-27m",
717 fanout_27m_parents, 0xf34,
718 8, 2,
719 0, 5,
720 24, 2,
721 BIT(31), 0);
722
723 static SUNXI_CCU_M_WITH_GATE(fanout_pclk, "fanout-pclk",
724 "apb0", 0xf38, 0, 5, BIT(31), 0);
725
726 static const char * const fanout_parents[] = { "fanout-32k", "fanout-12m",
727 "fanout-16m", "fanout-24m",
728 "fanout-25m", "fanout-27m",
729 "fanout-pclk"};
730 static SUNXI_CCU_MUX_WITH_GATE(fanout0_out_clk, "fanout0-out-clk",
731 fanout_parents, 0xf3c,
732 0, 3,
733 BIT(21), 0);
734 static SUNXI_CCU_MUX_WITH_GATE(fanout1_out_clk, "fanout1-out-clk",
735 fanout_parents, 0xf3c,
736 3, 3,
737 BIT(22), 0);
738 static SUNXI_CCU_MUX_WITH_GATE(fanout2_out_clk, "fanout2-out-clk",
739 fanout_parents, 0xf3c,
740 6, 3,
741 BIT(23), 0);
742
743 /* Fixed factor clocks */
744 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
745
746 static CLK_FIXED_FACTOR_HW(pll_periph0_clk, "pll-periph0",
747 &pll_periph0_2x_clk.common.hw,
748 2, 1, 0);
749
750 /* For AHBS */
751 static CLK_FIXED_FACTOR_HW(pll_periph0_div3_clk, "pll-periph0-div3",
752 &pll_periph0_2x_clk.common.hw,
753 6, 1, 0);
754
755 static CLK_FIXED_FACTOR_HW(hdmi_cec_32k_clk, "hdmi-cec-32k",
756 &pll_periph0_2x_clk.common.hw,
757 36621, 1, 0);
758
759 static CLK_FIXED_FACTOR_HW(mbus_clk, "mbus",
760 &pll_ddr0_clk.common.hw,
761 4, 1, 0);
762
763 static const struct clk_hw *pll_video0_parents[] = {
764 &pll_video0_clk.common.hw
765 };
766 static CLK_FIXED_FACTOR_HWS(pll_video0_4x_clk, "pll-video0-4x",
767 pll_video0_parents,
768 1, 4, CLK_SET_RATE_PARENT);
769 static CLK_FIXED_FACTOR_HWS(pll_video0_2x_clk, "pll-video0-2x",
770 pll_video0_parents,
771 1, 2, CLK_SET_RATE_PARENT);
772
773 static const struct clk_hw *pll_video1_parents[] = {
774 &pll_video1_clk.common.hw
775 };
776 static CLK_FIXED_FACTOR_HWS(pll_video1_4x_clk, "pll-video1-4x",
777 pll_video1_parents,
778 1, 4, CLK_SET_RATE_PARENT);
779 static CLK_FIXED_FACTOR_HWS(pll_video1_2x_clk, "pll-video1-2x",
780 pll_video1_parents,
781 1, 2, CLK_SET_RATE_PARENT);
782
783 static const struct clk_hw *pll_audio0_parents[] = {
784 &pll_audio0_4x_clk.common.hw
785 };
786 static CLK_FIXED_FACTOR_HWS(pll_audio0_clk, "pll-audio0",
787 pll_audio0_parents,
788 4, 1, CLK_SET_RATE_PARENT);
789 static CLK_FIXED_FACTOR_HWS(pll_audio0_2x_clk, "pll-audio0-2x",
790 pll_audio0_parents,
791 2, 1, CLK_SET_RATE_PARENT);
792 /* ccu_des_end */
793
794 static struct ccu_common *sun8iw20_ccu_clks[] = {
795 &pll_cpux_clk.common,
796 &pll_ddr0_clk.common,
797 &pll_periph0_parent_clk.common,
798 &pll_periph0_2x_clk.common,
799 &pll_periph0_800m_clk.common,
800 &pll_video0_clk.common,
801 &pll_video1_clk.common,
802 &pll_ve_clk.common,
803 &pll_audio0_4x_clk.common,
804 &pll_audio1_clk.common,
805 &pll_audio1_div2_clk.common,
806 &pll_audio1_div5_clk.common,
807 &pll_cpux_div.common,
808 &cpux_clk.common,
809 &axi_clk.common,
810 &apb_clk.common,
811 &psi_ahb_clk.common,
812 &apb0_clk.common,
813 &apb1_clk.common,
814 &de0_clk.common,
815 &bus_de0_clk.common,
816 &di_clk.common,
817 &bus_di_clk.common,
818 &g2d_clk.common,
819 &bus_g2d_clk.common,
820 &ce_clk.common,
821 &bus_ce_clk.common,
822 &ve_clk.common,
823 &bus_ve_clk.common,
824 &bus_dma_clk.common,
825 &bus_msgbox0_clk.common,
826 &bus_msgbox1_clk.common,
827 &bus_msgbox2_clk.common,
828 &bus_spinlock_clk.common,
829 &bus_hstimer_clk.common,
830 &avs_clk.common,
831 &bus_dbg_clk.common,
832 &bus_pwm_clk.common,
833 &bus_iommu_clk.common,
834 &dram_clk.common,
835 &mbus_dma_clk.common,
836 &mbus_ve_clk.common,
837 &mbus_ce_clk.common,
838 &mbus_tvin_clk.common,
839 &mbus_csi_clk.common,
840 &mbus_g2d_clk.common,
841 &bus_dram_clk.common,
842 &mmc0_clk.common,
843 &mmc1_clk.common,
844 &mmc2_clk.common,
845 &bus_mmc0_clk.common,
846 &bus_mmc1_clk.common,
847 &bus_mmc2_clk.common,
848 &bus_uart0_clk.common,
849 &bus_uart1_clk.common,
850 &bus_uart2_clk.common,
851 &bus_uart3_clk.common,
852 &bus_uart4_clk.common,
853 &bus_uart5_clk.common,
854 &bus_i2c0_clk.common,
855 &bus_i2c1_clk.common,
856 &bus_i2c2_clk.common,
857 &bus_i2c3_clk.common,
858 &spi0_clk.common,
859 &spi1_clk.common,
860 &bus_spi0_clk.common,
861 &bus_spi1_clk.common,
862 &emac0_25m_clk.common,
863 &bus_emac0_clk.common,
864 &ir_tx_clk.common,
865 &bus_ir_tx_clk.common,
866 &bus_gpadc_clk.common,
867 &bus_ths_clk.common,
868 &i2s0_clk.common,
869 &i2s1_clk.common,
870 &i2s2_clk.common,
871 &i2s2_asrc_clk.common,
872 &bus_i2s0_clk.common,
873 &bus_i2s1_clk.common,
874 &bus_i2s2_clk.common,
875 &spdif_tx_clk.common,
876 &spdif_rx_clk.common,
877 &bus_spdif_clk.common,
878 &dmic_clk.common,
879 &bus_dmic_clk.common,
880 &audio_codec_dac_clk.common,
881 &audio_codec_adc_clk.common,
882 &bus_audio_codec_clk.common,
883 &usb_ohci0_clk.common,
884 &usb_ohci1_clk.common,
885 &bus_ohci0_clk.common,
886 &bus_ohci1_clk.common,
887 &bus_ehci0_clk.common,
888 &bus_ehci1_clk.common,
889 &bus_otg_clk.common,
890 &bus_lradc_clk.common,
891 &bus_dpss_top0_clk.common,
892 &hdmi_24m_clk.common,
893 &hdmi_cec_clk.common,
894 &bus_hdmi_clk.common,
895 &mipi_dsi_clk.common,
896 &bus_mipi_dsi_clk.common,
897 &tcon_lcd0_clk.common,
898 &bus_tcon_lcd0_clk.common,
899 &tcon_tv_clk.common,
900 &bus_tcon_tv_clk.common,
901 &tve_clk.common,
902 &bus_tve_clk.common,
903 &bus_tve_top_clk.common,
904 &tvd_clk.common,
905 &bus_tvd_clk.common,
906 &ledc_clk.common,
907 &bus_ledc_clk.common,
908 &bus_tvd_top_clk.common,
909 &csi_top_clk.common,
910 &csi0_mclk_clk.common,
911 &bus_csi_clk.common,
912 &tpadc_clk.common,
913 &bus_tpadc_clk.common,
914 &bus_tzma_clk.common,
915 &dsp_clk.common,
916 &bus_dsp_cfg_clk.common,
917 &riscv_clk.common,
918 &riscv_axi_clk.common,
919 &bus_riscv_cfg_clk.common,
920 &fanout_24m_clk.common,
921 &fanout_12m_clk.common,
922 &fanout_16m_clk.common,
923 &fanout_25m_clk.common,
924 &fanout_32k_clk.common,
925 &fanout_27m_clk.common,
926 &fanout_pclk.common,
927 &fanout0_out_clk.common,
928 &fanout1_out_clk.common,
929 &fanout2_out_clk.common,
930 };
931
932 /* ccu_def_start */
933 static struct clk_hw_onecell_data sun8iw20_hw_clks = {
934 .hws = {
935 [CLK_OSC12M] = &osc12M_clk.hw,
936 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
937 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
938 [CLK_PLL_PERIPH0_PARENT] = &pll_periph0_parent_clk.common.hw,
939 [CLK_PLL_PERIPH0] = &pll_periph0_clk.hw,
940 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw,
941 [CLK_PLL_PERIPH0_800M] = &pll_periph0_800m_clk.common.hw,
942 [CLK_PLL_PERIPH0_DIV3] = &pll_periph0_div3_clk.hw,
943 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
944 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
945 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
946 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
947 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
948 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
949 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
950 [CLK_PLL_AUDIO0] = &pll_audio0_clk.hw,
951 [CLK_PLL_AUDIO0_2X] = &pll_audio0_2x_clk.hw,
952 [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
953 [CLK_PLL_AUDIO1] = &pll_audio1_clk.common.hw,
954 [CLK_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.common.hw,
955 [CLK_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.common.hw,
956 [CLK_PLL_CPUX_DIV] = &pll_cpux_div.common.hw,
957 [CLK_CPUX] = &cpux_clk.common.hw,
958 [CLK_AXI] = &axi_clk.common.hw,
959 [CLK_APB] = &apb_clk.common.hw,
960 [CLK_PSI_AHB] = &psi_ahb_clk.common.hw,
961 [CLK_APB0] = &apb0_clk.common.hw,
962 [CLK_APB1] = &apb1_clk.common.hw,
963 [CLK_MBUS] = &mbus_clk.hw,
964 [CLK_DE0] = &de0_clk.common.hw,
965 [CLK_BUS_DE0] = &bus_de0_clk.common.hw,
966 [CLK_DI] = &di_clk.common.hw,
967 [CLK_BUS_DI] = &bus_di_clk.common.hw,
968 [CLK_G2D] = &g2d_clk.common.hw,
969 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
970 [CLK_CE] = &ce_clk.common.hw,
971 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
972 [CLK_VE] = &ve_clk.common.hw,
973 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
974 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
975 [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
976 [CLK_BUS_MSGBOX1] = &bus_msgbox1_clk.common.hw,
977 [CLK_BUS_MSGBOX2] = &bus_msgbox2_clk.common.hw,
978 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
979 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
980 [CLK_AVS] = &avs_clk.common.hw,
981 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
982 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
983 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
984 [CLK_DRAM] = &dram_clk.common.hw,
985 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
986 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
987 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
988 [CLK_MBUS_TVIN] = &mbus_tvin_clk.common.hw,
989 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
990 [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
991 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
992 [CLK_MMC0] = &mmc0_clk.common.hw,
993 [CLK_MMC1] = &mmc1_clk.common.hw,
994 [CLK_MMC2] = &mmc2_clk.common.hw,
995 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
996 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
997 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
998 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
999 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1000 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1001 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1002 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1003 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1004 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1005 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1006 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1007 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1008 [CLK_SPI0] = &spi0_clk.common.hw,
1009 [CLK_SPI1] = &spi1_clk.common.hw,
1010 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1011 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1012 [CLK_EMAC0_25M] = &emac0_25m_clk.common.hw,
1013 [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw,
1014 [CLK_IR_TX] = &ir_tx_clk.common.hw,
1015 [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
1016 [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
1017 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1018 [CLK_I2S0] = &i2s0_clk.common.hw,
1019 [CLK_I2S1] = &i2s1_clk.common.hw,
1020 [CLK_I2S2] = &i2s2_clk.common.hw,
1021 [CLK_I2S2_ASRC] = &i2s2_asrc_clk.common.hw,
1022 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1023 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1024 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1025 [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw,
1026 [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw,
1027 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1028 [CLK_DMIC] = &dmic_clk.common.hw,
1029 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
1030 [CLK_AUDIO_DAC] = &audio_codec_dac_clk.common.hw,
1031 [CLK_AUDIO_ADC] = &audio_codec_adc_clk.common.hw,
1032 [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw,
1033 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1034 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1035 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1036 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1037 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1038 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1039 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1040 [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
1041 [CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw,
1042 [CLK_HDMI_24M] = &hdmi_24m_clk.common.hw,
1043 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
1044 [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.hw,
1045 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
1046 [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1047 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
1048 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1049 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1050 [CLK_TCON_TV] = &tcon_tv_clk.common.hw,
1051 [CLK_BUS_TCON_TV] = &bus_tcon_tv_clk.common.hw,
1052 [CLK_TVE] = &tve_clk.common.hw,
1053 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
1054 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1055 [CLK_TVD] = &tvd_clk.common.hw,
1056 [CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
1057 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
1058 [CLK_LEDC] = &ledc_clk.common.hw,
1059 [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
1060 [CLK_CSI_TOP] = &csi_top_clk.common.hw,
1061 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1062 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
1063 [CLK_TPADC] = &tpadc_clk.common.hw,
1064 [CLK_BUS_TPADC] = &bus_tpadc_clk.common.hw,
1065 [CLK_BUS_TZMA] = &bus_tzma_clk.common.hw,
1066 [CLK_DSP] = &dsp_clk.common.hw,
1067 [CLK_BUS_DSP_CFG] = &bus_dsp_cfg_clk.common.hw,
1068 [CLK_RISCV] = &riscv_clk.common.hw,
1069 [CLK_RISCV_AXI] = &riscv_axi_clk.common.hw,
1070 [CLK_BUS_RISCV_CFG] = &bus_riscv_cfg_clk.common.hw,
1071 [CLK_FANOUT_24M] = &fanout_24m_clk.common.hw,
1072 [CLK_FANOUT_12M] = &fanout_12m_clk.common.hw,
1073 [CLK_FANOUT_16M] = &fanout_16m_clk.common.hw,
1074 [CLK_FANOUT_25M] = &fanout_25m_clk.common.hw,
1075 [CLK_FANOUT_32K] = &fanout_32k_clk.common.hw,
1076 [CLK_FANOUT_27M] = &fanout_27m_clk.common.hw,
1077 [CLK_FANOUT_PCLK] = &fanout_pclk.common.hw,
1078 [CLK_FANOUT0_OUT] = &fanout0_out_clk.common.hw,
1079 [CLK_FANOUT1_OUT] = &fanout1_out_clk.common.hw,
1080 [CLK_FANOUT2_OUT] = &fanout2_out_clk.common.hw,
1081 },
1082 .num = CLK_NUMBER,
1083 };
1084 /* ccu_def_end */
1085
1086 /* rst_def_start */
1087 static struct ccu_reset_map sun8iw20_ccu_resets[] = {
1088 [RST_MBUS] = { 0x540, BIT(30) },
1089
1090 [RST_BUS_DE0] = { 0x60c, BIT(16) },
1091 [RST_BUS_DI] = { 0x62c, BIT(16) },
1092 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1093 [RST_BUS_CE] = { 0x68c, BIT(16) },
1094 [RST_BUS_VE] = { 0x69c, BIT(16) },
1095 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1096 [RST_BUS_MSGBOX0] = { 0x71c, BIT(16) },
1097 [RST_BUS_MSGBOX1] = { 0x71c, BIT(17) },
1098 [RST_BUS_MSGBOX2] = { 0x71c, BIT(18) },
1099 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1100 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1101 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1102 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1103 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1104 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1105 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1106 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1107 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1108 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1109 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1110 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1111 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1112 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1113 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1114 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1115 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1116 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1117 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1118 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1119 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1120 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1121 [RST_BUS_GPADC] = { 0x9ec, BIT(16) },
1122 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1123 [RST_BUS_I2S0] = { 0xa20, BIT(16) },
1124 [RST_BUS_I2S1] = { 0xa20, BIT(17) },
1125 [RST_BUS_I2S2] = { 0xa20, BIT(18) },
1126 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1127 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1128 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) },
1129
1130 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1131 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1132
1133 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1134 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1135 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1136 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1137 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1138
1139 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1140 [RST_BUS_DPSS_TOP0] = { 0xabc, BIT(16) },
1141 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1142 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1143 [RST_BUS_MIPI_DSI] = { 0xb4c, BIT(16) },
1144 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1145 [RST_BUS_TCON_TV] = { 0xb9c, BIT(16) },
1146 [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1147 [RST_BUS_TVE] = { 0xbbc, BIT(17) },
1148 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1149 [RST_BUS_TVD] = { 0xbdc, BIT(17) },
1150 [RST_BUS_TVD_TOP] = { 0xbdc, BIT(16) },
1151 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1152 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1153 [RST_BUS_TPADC] = { 0xc5c, BIT(16) },
1154 [RST_BUS_DSP] = { 0xc7c, BIT(16) },
1155 [RST_BUS_DSP_CFG] = { 0xc7c, BIT(17) },
1156 [RST_BUS_DSP_DBG] = { 0xc7c, BIT(18) },
1157 [RST_BUS_RISCV_CFG] = { 0xd0c, BIT(16) },
1158 /* TODO: RST_RISCV_SOFT */
1159 };
1160 /* rst_def_end */
1161
1162 static const struct sunxi_ccu_desc sun8iw20_ccu_desc = {
1163 .ccu_clks = sun8iw20_ccu_clks,
1164 .num_ccu_clks = ARRAY_SIZE(sun8iw20_ccu_clks),
1165
1166 .hw_clks = &sun8iw20_hw_clks,
1167
1168 .resets = sun8iw20_ccu_resets,
1169 .num_resets = ARRAY_SIZE(sun8iw20_ccu_resets),
1170 };
1171
1172 static const u32 pll_regs[] = {
1173 SUN8IW20_PLL_CPUX_REG,
1174 SUN8IW20_PLL_DDR0_REG,
1175 SUN8IW20_PLL_PERIPH0_REG,
1176 SUN8IW20_PLL_VIDEO0_REG,
1177 SUN8IW20_PLL_VIDEO1_REG,
1178 SUN8IW20_PLL_VE_REG,
1179 SUN8IW20_PLL_AUDIO0_REG,
1180 SUN8IW20_PLL_AUDIO1_REG,
1181 };
1182
1183 static const u32 pll_video_regs[] = {
1184 SUN8IW20_PLL_VIDEO0_REG,
1185 SUN8IW20_PLL_VIDEO1_REG,
1186 };
1187
1188 static const u32 usb2_clk_regs[] = {
1189 SUN8IW20_USB0_CLK_REG,
1190 SUN8IW20_USB1_CLK_REG,
1191 };
1192
1193 static struct ccu_pll_nb sun8iw20_pll_cpu_nb = {
1194 .common = &pll_cpux_clk.common,
1195 /* copy from pll_cpux_clk */
1196 .enable = BIT(27),
1197 .lock = BIT(28),
1198 };
1199
1200 static struct ccu_mux_nb sun8iw20_cpu_nb = {
1201 .common = &cpux_clk.common,
1202 .cm = &cpux_clk.mux,
1203 .delay_us = 1,
1204 .bypass_index = 4, /* index of pll periph0 */
1205 };
1206
1207 static struct ccu_mux_nb sun20iw1_cpu_nb = {
1208 .common = &riscv_clk.common,
1209 .cm = &riscv_clk.mux,
1210 .delay_us = 1,
1211 .bypass_index = 4, /* index of pll periph0 */
1212 };
1213
sun8iw20_ccu_probe(struct platform_device * pdev)1214 static int sun8iw20_ccu_probe(struct platform_device *pdev)
1215 {
1216 void __iomem *reg;
1217 u32 val;
1218 int i, ret;
1219
1220 reg = devm_platform_ioremap_resource(pdev, 0);
1221 if (IS_ERR(reg))
1222 return PTR_ERR(reg);
1223
1224 /* Enable the lock bits on all PLLs */
1225 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1226 val = readl(reg + pll_regs[i]);
1227 val |= BIT(29);
1228 writel(val, reg + pll_regs[i]);
1229 }
1230
1231 /*
1232 * Force the output divider of video PLLs to 0.
1233 *
1234 * See the comment before pll-video0 definition for the reason.
1235 */
1236 for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1237 val = readl(reg + pll_video_regs[i]);
1238 val &= ~BIT(0);
1239 writel(val, reg + pll_video_regs[i]);
1240 }
1241
1242 /* Enforce m1 = 0, m0 = 1 for Audio0 PLL */
1243 val = readl(reg + SUN8IW20_PLL_AUDIO0_REG);
1244 val &= ~BIT(1);
1245 val |= BIT(0);
1246 writel(val, reg + SUN8IW20_PLL_AUDIO0_REG);
1247
1248 /* TODO: config PLL_AUDIO1 here */
1249
1250 /*
1251 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
1252 *
1253 * This clock mux is still mysterious, and the code just enforces
1254 * it to have a valid clock parent.
1255 */
1256 for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
1257 val = readl(reg + usb2_clk_regs[i]);
1258 val &= ~GENMASK(25, 24);
1259 writel(val, reg + usb2_clk_regs[i]);
1260 }
1261
1262 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8iw20_ccu_desc);
1263 if (ret)
1264 return ret;
1265
1266 /* Gate then ungate PLL CPU after any rate changes */
1267 ccu_pll_notifier_register(&sun8iw20_pll_cpu_nb);
1268
1269 /* a7:Reparent CPU during PLL CPU rate changes */
1270 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1271 &sun8iw20_cpu_nb);
1272
1273 /* riscv:Reparent CPU during PLL CPU rate changes */
1274 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1275 &sun20iw1_cpu_nb);
1276
1277 sunxi_ccu_sleep_init(reg, sun8iw20_ccu_clks,
1278 ARRAY_SIZE(sun8iw20_ccu_clks),
1279 NULL, 0);
1280
1281 return 0;
1282 }
1283
1284 static const struct of_device_id sun8iw20_ccu_ids[] = {
1285 { .compatible = "allwinner,sun8iw20-ccu" },
1286 { .compatible = "allwinner,sun20iw1-ccu" },
1287 { }
1288 };
1289
1290 static struct platform_driver sun8iw20_ccu_driver = {
1291 .probe = sun8iw20_ccu_probe,
1292 .driver = {
1293 .name = "sun8iw20-ccu",
1294 .of_match_table = sun8iw20_ccu_ids,
1295 },
1296 };
1297
sunxi_ccu_sun8iw20_init(void)1298 static int __init sunxi_ccu_sun8iw20_init(void)
1299 {
1300 int ret;
1301
1302 ret = platform_driver_register(&sun8iw20_ccu_driver);
1303 if (ret)
1304 pr_err("register ccu sun8iw20 failed\n");
1305
1306 return ret;
1307 }
1308 core_initcall(sunxi_ccu_sun8iw20_init);
1309
sunxi_ccu_sun8iw20_exit(void)1310 static void __exit sunxi_ccu_sun8iw20_exit(void)
1311 {
1312 return platform_driver_unregister(&sun8iw20_ccu_driver);
1313 }
1314 module_exit(sunxi_ccu_sun8iw20_exit);
1315
1316 MODULE_VERSION("0.5.2");
1317