1 /* 2 * Sunxi SD/MMC host driver 3 * 4 * Copyright (C) 2015 AllWinnertech Ltd. 5 * Author: lixiang <lixiang@allwinnertech> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 18 #include <linux/clk.h> 19 #include <linux/reset/sunxi.h> 20 21 #include <pinctrl-sunxi.h> 22 #include <linux/gpio.h> 23 #include <linux/platform_device.h> 24 #include <linux/spinlock.h> 25 #include <linux/scatterlist.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/slab.h> 28 #include <linux/reset.h> 29 30 #include <linux/of_address.h> 31 #include <linux/of_gpio.h> 32 #include <linux/of_platform.h> 33 34 #include <linux/mmc/host.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/mmc/core.h> 39 #include <linux/mmc/card.h> 40 #include <linux/mmc/slot-gpio.h> 41 42 43 #include "../core/core.h" 44 45 #ifndef __SUNXI_MMC_H__ 46 #define __SUNXI_MMC_H__ 47 48 #define DRIVER_NAME "sunxi-mmc" 49 #define DRIVER_RIVISION "v5.04 2022-5-24 09:25" 50 #define DRIVER_VERSION "SD/MMC/SDIO Host Controller Driver(" DRIVER_RIVISION ")" 51 52 #if defined CONFIG_FPGA_V4_PLATFORM || defined CONFIG_FPGA_V7_PLATFORM 53 #define MMC_FPGA 54 #endif 55 56 57 /* register offset definitions */ 58 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 59 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 60 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 61 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 62 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 63 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 64 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 65 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 66 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 67 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 68 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 69 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 70 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 71 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 72 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 73 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 74 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 75 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 76 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 77 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 78 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 79 #define SDXC_REG_A12A (0x58) /*auto cmd12 arg*/ 80 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 81 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 82 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 83 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 84 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 85 #define SDXC_REG_CHDA (0x90) 86 #define SDXC_REG_CBDA (0x94) 87 88 89 #define SDXC_REG_FIFO (0x200) 90 91 #define mmc_readl(host, reg) \ 92 readl((host)->reg_base + SDXC_##reg) 93 #define mmc_writel(host, reg, value) \ 94 writel((value), (host)->reg_base + SDXC_##reg) 95 96 /* global control register bits */ 97 #define SDXC_SOFT_RESET BIT(0) 98 #define SDXC_FIFO_RESET BIT(1) 99 #define SDXC_DMA_RESET BIT(2) 100 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 101 #define SDXC_DMA_ENABLE_BIT BIT(5) 102 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 103 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 104 #define SDXC_DDR_MODE BIT(10) 105 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 106 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 107 #define SDXC_ACCESS_BY_AHB BIT(31) 108 #define SDXC_ACCESS_BY_DMA (0 << 31) 109 #define SDXC_HARDWARE_RESET \ 110 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 111 112 /* clock control bits */ 113 #define SDXC_CARD_CLOCK_ON BIT(16) 114 #define SDXC_LOW_POWER_ON BIT(17) 115 #define SDXC_MASK_DATA0 BIT(31) 116 117 /* bus width */ 118 #define SDXC_WIDTH1 0 119 #define SDXC_WIDTH4 1 120 #define SDXC_WIDTH8 2 121 122 /* smc command bits */ 123 #define SDXC_RESP_EXPECT BIT(6) 124 #define SDXC_LONG_RESPONSE BIT(7) 125 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 126 #define SDXC_DATA_EXPECT BIT(9) 127 #define SDXC_WRITE BIT(10) 128 #define SDXC_SEQUENCE_MODE BIT(11) 129 #define SDXC_SEND_AUTO_STOP BIT(12) 130 #define SDXC_WAIT_PRE_OVER BIT(13) 131 #define SDXC_STOP_ABORT_CMD BIT(14) 132 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 133 #define SDXC_UPCLK_ONLY BIT(21) 134 #define SDXC_READ_CEATA_DEV BIT(22) 135 #define SDXC_CCS_EXPECT BIT(23) 136 #define SDXC_ENABLE_BIT_BOOT BIT(24) 137 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 138 #define SDXC_BOOT_ACK_EXPECT BIT(26) 139 #define SDXC_BOOT_ABORT BIT(27) 140 #define SDXC_VOLTAGE_SWITCH BIT(28) 141 #define SDXC_USE_HOLD_REGISTER BIT(29) 142 #define SDXC_START BIT(31) 143 144 /* interrupt bits */ 145 #define SDXC_RESP_ERROR BIT(1) 146 #define SDXC_COMMAND_DONE BIT(2) 147 #define SDXC_DATA_OVER BIT(3) 148 #define SDXC_TX_DATA_REQUEST BIT(4) 149 #define SDXC_RX_DATA_REQUEST BIT(5) 150 #define SDXC_RESP_CRC_ERROR BIT(6) 151 #define SDXC_DATA_CRC_ERROR BIT(7) 152 #define SDXC_RESP_TIMEOUT BIT(8) 153 #define SDXC_DATA_TIMEOUT BIT(9) 154 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 155 #define SDXC_FIFO_RUN_ERROR BIT(11) 156 #define SDXC_HARD_WARE_LOCKED BIT(12) 157 #define SDXC_START_BIT_ERROR BIT(13) 158 #define SDXC_AUTO_COMMAND_DONE BIT(14) 159 #define SDXC_END_BIT_ERROR BIT(15) 160 #define SDXC_SDIO_INTERRUPT BIT(16) 161 #define SDXC_CARD_INSERT BIT(30) 162 #define SDXC_CARD_REMOVE BIT(31) 163 #define SDXC_INTERRUPT_ERROR_BIT \ 164 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 165 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 166 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 167 #define SDXC_INTERRUPT_CMD_ERROR_BIT \ 168 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_RESP_TIMEOUT) 169 #define SDXC_INTERRUPT_DONE_BIT \ 170 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 171 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 172 #define SDXC_INTERRUPT_DDONE_BIT \ 173 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER) 174 #define SDXC_SWITCH_DDONE_BIT \ 175 (SDXC_VOLTAGE_CHANGE_DONE | SDXC_COMMAND_DONE) 176 177 178 /* status */ 179 #define SDXC_RXWL_FLAG BIT(0) 180 #define SDXC_TXWL_FLAG BIT(1) 181 #define SDXC_FIFO_EMPTY BIT(2) 182 #define SDXC_FIFO_FULL BIT(3) 183 #define SDXC_CARD_PRESENT BIT(8) 184 #define SDXC_CARD_DATA_BUSY BIT(9) 185 #define SDXC_DATA_FSM_BUSY BIT(10) 186 #define SDXC_DMA_REQUEST BIT(31) 187 #define SDXC_FIFO_SIZE 16 188 189 /* Function select */ 190 #define SDXC_CEATA_ON (0xceaa << 16) 191 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 192 #define SDXC_SDIO_READ_WAIT BIT(1) 193 #define SDXC_ABORT_READ_DATA BIT(2) 194 #define SDXC_SEND_CCSD BIT(8) 195 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 196 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 197 198 /* IDMA controller bus mod bit field */ 199 #define SDXC_IDMAC_SOFT_RESET BIT(0) 200 #define SDXC_IDMAC_FIX_BURST BIT(1) 201 #define SDXC_IDMAC_IDMA_ON BIT(7) 202 #define SDXC_IDMAC_REFETCH_DES BIT(31) 203 204 /* IDMA status bit field */ 205 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 206 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 207 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 208 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 209 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 210 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 211 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 212 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 213 #define SDXC_IDMAC_IDLE (0 << 13) 214 #define SDXC_IDMAC_SUSPEND (1 << 13) 215 #define SDXC_IDMAC_DESC_READ (2 << 13) 216 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 217 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 218 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 219 #define SDXC_IDMAC_READ (6 << 13) 220 #define SDXC_IDMAC_WRITE (7 << 13) 221 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 222 223 /* 224 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 225 * Bits 0-12: buf1 size 226 * Bits 13-25: buf2 size 227 * Bits 26-31: not used 228 * Since we only ever set buf1 size, we can simply store it directly. 229 */ 230 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 231 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 232 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 233 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 234 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 235 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 236 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 237 238 void sunxi_dump_reg(struct mmc_host *mmc); 239 240 #if 0 241 #define sunxi_r_op(host, op) (\ 242 {\ 243 int __ret_val = 0;\ 244 struct mmc_host *mmc = host->mmc;\ 245 clk_disable_unprepare(host->clk_mmc);\ 246 dev_dbg(mmc_dev(mmc), "%s, %d\n", __FUNCTION__, __LINE__);\ 247 sunxi_dump_reg(mmc);\ 248 op;\ 249 __ret_val = clk_prepare_enable(host->clk_mmc);\ 250 if (__ret_val) {\ 251 dev_err(mmc_dev(mmc), "Enable mmc clk err %d\n", __ret_val);\ 252 } \ 253 __ret_val;\ 254 } \ 255 ) 256 #else 257 #define sunxi_r_op(__h, __op) (\ 258 {\ 259 int __ret_val = 0;\ 260 struct mmc_host *mmc = (__h)->mmc;\ 261 clk_disable_unprepare((__h)->clk_mmc);\ 262 dev_dbg(mmc_dev(mmc), "%s, %d\n", __FUNCTION__, __LINE__);\ 263 __op;\ 264 __ret_val = clk_prepare_enable((__h)->clk_mmc);\ 265 if (__ret_val) {\ 266 dev_err(mmc_dev(mmc), "Enable mmc clk err %d\n", __ret_val);\ 267 } \ 268 __ret_val;\ 269 } \ 270 ) 271 #endif 272 273 enum sunxi_cookie { 274 COOKIE_UNMAPPED, 275 COOKIE_PRE_MAPPED, /* mapped by sunxi_mmc_pre_req() */ 276 COOKIE_MAPPED, /* mapped by sunxi_mmc_request() or retry*/ 277 }; 278 279 struct sunxi_idma_des { 280 u32 config; 281 u32 buf_size; 282 u32 buf_addr_ptr1; 283 u32 buf_addr_ptr2; 284 }; 285 286 struct sunxi_mmc_ctrl_regs { 287 u32 gctrl; 288 u32 clkc; 289 u32 timeout; 290 u32 buswid; 291 u32 waterlvl; 292 u32 funcsel; 293 u32 debugc; 294 u32 idmacc; 295 u32 dlba; 296 u32 imask; 297 }; 298 299 struct sunxi_mmc_host_perf{ 300 ktime_t start; 301 int64_t rbytes; 302 int64_t wbytes; 303 ktime_t rtime; 304 ktime_t wtime; 305 306 /***use to compute the time no include busy***/ 307 int64_t wbytestran; 308 ktime_t wtimetran; 309 }; 310 311 struct sunxi_mmc_supply { 312 struct regulator *vmmc; /* Card power supply */ 313 struct regulator *vqmmc; /* Optional Vccq supply */ 314 struct regulator *vdmmc; /*Optional card detect pin supply*/ 315 struct regulator *vdmmc33sw; /* SD card PMU control*/ 316 struct regulator *vdmmc18sw; 317 struct regulator *vqmmc33sw; /* SD card PMU control*/ 318 struct regulator *vqmmc18sw; 319 }; 320 321 struct sunxi_mmc_host { 322 struct mmc_host *mmc; 323 struct reset_control *reset; 324 325 /* IO mapping base */ 326 void __iomem *reg_base; 327 328 /* clock management */ 329 struct clk *clk_ahb; 330 struct clk *clk_mmc; 331 struct reset_control *clk_rst; 332 333 int (*sunxi_mmc_clk_set_rate)(struct sunxi_mmc_host *host, 334 struct mmc_ios *ios); 335 int crypt_flag; 336 337 /* irq */ 338 spinlock_t lock; 339 int irq; 340 u32 int_sum; 341 u32 sdio_imask; 342 343 /* dma */ 344 u32 req_page_count; 345 u32 idma_des_size_bits; 346 dma_addr_t sg_dma; 347 void *sg_cpu; 348 bool wait_dma; 349 u32 dma_tl; 350 u64 dma_mask; 351 352 void (*sunxi_mmc_thld_ctl)(struct sunxi_mmc_host *host, 353 struct mmc_ios *ios, 354 struct mmc_data *data); 355 356 struct mmc_request *mrq; 357 struct mmc_request *mrq_busy; 358 struct mmc_request *mrq_retry; 359 struct mmc_request *manual_stop_mrq; 360 int ferror; 361 362 u32 power_on; 363 u32 time_pwroff_ms; 364 365 /* pinctrl handles */ 366 struct pinctrl *pinctrl; 367 struct pinctrl_state *pins_default; 368 struct pinctrl_state *pins_bias_1v8; 369 struct pinctrl_state *pins_sleep; 370 struct pinctrl_state *pins_uart_jtag; 371 372 /*sys node */ 373 struct device_attribute maual_insert; 374 struct device_attribute *dump_register; 375 struct device_attribute dump_clk_dly; 376 struct device_attribute host_sample_dly; 377 struct device_attribute host_ds_dly; 378 struct device_attribute host_send_status; 379 struct device_attribute host_debuglevel; 380 381 void (*sunxi_mmc_dump_dly_table)(struct sunxi_mmc_host *host); 382 383 /* backup register structrue */ 384 struct sunxi_mmc_ctrl_regs bak_regs; 385 void (*sunxi_mmc_save_spec_reg)(struct sunxi_mmc_host *host); 386 void (*sunxi_mmc_restore_spec_reg)(struct sunxi_mmc_host *host); 387 void (*sunxi_mmc_set_acmda)(struct sunxi_mmc_host *host); 388 void (*sunxi_mmc_shutdown)(struct platform_device *pdev); 389 int (*sunxi_mmc_oclk_en)(struct sunxi_mmc_host *host, u32 oclk_en); 390 int (*sunxi_mmc_updata_pha)(struct sunxi_mmc_host *host, 391 struct mmc_command *cmd, struct mmc_data *data); 392 void (*sunxi_mmc_on_off_emce)(struct sunxi_mmc_host *host, 393 u32 en_crypt, u32 ac_mode, u32 en_emce, int data_len, 394 int bypass, int task_load); 395 bool (*sunxi_mmc_hw_busy)(struct sunxi_mmc_host *host); 396 int (*sunxi_mmc_dat0_busy)(struct sunxi_mmc_host *host); 397 398 /*really controller id,no logic id */ 399 int phy_index; 400 401 u32 dat3_imask; 402 403 /*no wait busy if wrtie end, only for customer need */ 404 #define NO_WBUSY_WR_END 0x1 405 #define NO_REINIT_SHUTDOWN 0x2 406 #define CARD_PWR_GPIO_HIGH_ACTIVE 0x4 407 #define SUNXI_SC_EN_RETRY 0x8 408 /**If set this bit,when use sunxi_check_r1_ready_may_sleep, 409 *we will wait 0xFFFFFFFF ms, for debug use 410 *it is no meant on linux4.4 411 */ 412 #define SUNXI_R1B_WAIT_MAX 0x10 413 414 /*#define SUNXI_MANUAL_READ_DATA_TIMEOUT 0x20*/ 415 /* 416 *Disable linux kernel native broken cd function,use host defined. 417 *Host defined cd function only report true when it detect cd pin change. 418 *If not detect cd pin change,it return false. 419 *We use it to deal with some bad card which cannot init at all 420 *But host defined cd function has a disadvantage that it may not detect card 421 *If card is inserted too often. 422 */ 423 #define SUNXI_DIS_KER_NAT_CD 0x40 424 425 /*#define SUNXI_NO_ERASE 0x80*/ 426 #define SUNXI_SC_EN_RETRY_CMD 0x100 427 #define SUNXI_SC_EN_TIMEOUT_DETECT 0x200 428 #define SUNXI_CMD11_TIMEOUT_DETECT 0x400 429 /*control specal function control,for customer need*/ 430 u32 ctl_spec_cap; 431 432 #define MMC_SUNXI_CAP3_DAT3_DET (1 << 0) 433 #define MMC_SUNXI_CAP3_CD_USED_24M (1 << 1) 434 #define MMC_SUNXI_CAP3_HSQ (1 << 2) 435 u32 sunxi_caps3; 436 437 struct sunxi_mmc_supply supply; 438 int card_pwr_gpio; 439 440 u32 retry_cnt; 441 u32 errno_retry; 442 int (*sunxi_mmc_judge_retry)(struct sunxi_mmc_host *host, 443 struct mmc_command *cmd, u32 rcnt, 444 u32 errno, void *other); 445 int sunxi_samp_dl; 446 int sunxi_ds_dl; 447 448 u32 sunxi_ds_dl_cnt; 449 u32 sunxi_samp_dl_cnt; 450 /*only use for MMC_CAP_NEEDS_POLL and SUNXI_DIS_KER_NAT_CD is on*/ 451 u32 present; 452 u32 voltage_switching; 453 454 bool perf_enable; 455 struct device_attribute host_perf; 456 struct sunxi_mmc_host_perf perf; 457 struct device_attribute filter_sector_perf; 458 struct device_attribute filter_speed_perf; 459 unsigned int filter_sector; 460 unsigned int filter_speed; 461 struct device_attribute host_mwr; 462 463 void *version_priv_dat; 464 465 /*auto command 23 operate*/ 466 /*set auto cmd 23 val and enable bit,or get respose*/ 467 bool (*sunxi_mmc_opacmd23)(struct sunxi_mmc_host *host, bool set, u32 arg, u32 *rep); 468 void (*sunxi_mmc_hw_wbusy_wait)(struct sunxi_mmc_host *host, struct mmc_data *data, bool set); 469 470 /*sample fifo contral */ 471 bool sfc_dis; 472 473 /*des phy address shift,use for over 4G phy ddrest*/ 474 size_t des_addr_shift; 475 char name[32]; 476 struct delayed_work sunxi_timerout_work; 477 int debuglevel; 478 }; 479 480 /*the struct as the the kernel version changes,which copy form core/slot-gpio.c*/ 481 struct mmc_gpio { 482 struct gpio_desc *ro_gpio; 483 struct gpio_desc *cd_gpio; 484 bool override_ro_active_level; 485 bool override_cd_active_level; 486 irqreturn_t (*cd_gpio_isr)(int irq, void *dev_id); 487 char *ro_label; 488 char cd_label[0]; 489 }; 490 491 /*use to check ddr mode,not include hs400*/ 492 #define sunxi_mmc_ddr_timing(it) \ 493 (((it) == MMC_TIMING_UHS_DDR50) || ((it) == MMC_TIMING_MMC_DDR52)) 494 495 496 /*Transfer core definition here*/ 497 /*core.h*/ 498 #define MMC_DATA_STREAM BIT(10) 499 /*host.h cap2*/ 500 #define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */ 501 #define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */ 502 #define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */ 503 #define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \ 504 MMC_CAP2_PACKED_WR) 505 #define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ 506 507 void sunxi_mmc_set_a12a(struct sunxi_mmc_host *host); 508 void sunxi_mmc_do_shutdown_com(struct platform_device *pdev); 509 extern int mmc_send_status(struct mmc_card *card, u32 *status); 510 extern void mmc_set_bus_width(struct mmc_host *host, unsigned int width); 511 extern int mmc_flush_cache(struct mmc_card *); 512 extern int sunxi_sel_pio_mode(struct pinctrl *pinctrl, u32 pm_sel); 513 514 #endif 515