1 /* 2 * MSGBUF network driver ioctl/indication encoding 3 * Broadcom 802.11abg Networking Device Driver 4 * 5 * Definitions subject to change without notice. 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: bcmmsgbuf.h 676811 2016-12-24 20:48:46Z $ 31 */ 32 #ifndef _bcmmsgbuf_h_ 33 #define _bcmmsgbuf_h_ 34 35 #include <ethernet.h> 36 #include <wlioctl.h> 37 #include <bcmpcie.h> 38 39 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN 40 41 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */ 42 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1) 43 44 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */ 45 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1) 46 47 #define H2DRING_TXPOST_ITEMSIZE 48 48 #define H2DRING_RXPOST_ITEMSIZE 32 49 #define H2DRING_CTRL_SUB_ITEMSIZE 40 50 51 #define D2HRING_TXCMPLT_ITEMSIZE 24 52 #define D2HRING_RXCMPLT_ITEMSIZE 40 53 54 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16 55 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32 56 57 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24 58 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE 59 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE 60 61 #define H2DRING_TXPOST_MAX_ITEM 512 62 #define H2DRING_RXPOST_MAX_ITEM 512 63 #define H2DRING_CTRL_SUB_MAX_ITEM 64 64 #define D2HRING_TXCMPLT_MAX_ITEM 1024 65 #define D2HRING_RXCMPLT_MAX_ITEM 512 66 67 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32 68 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32 69 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64 70 71 enum { 72 DNGL_TO_HOST_MSGBUF, 73 HOST_TO_DNGL_MSGBUF 74 }; 75 76 enum { 77 HOST_TO_DNGL_TXP_DATA, 78 HOST_TO_DNGL_RXP_DATA, 79 HOST_TO_DNGL_CTRL, 80 DNGL_TO_HOST_DATA, 81 DNGL_TO_HOST_CTRL 82 }; 83 84 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE 85 #define PCIEDEV_FIRMWARE_TSINFO 0x1 86 87 #ifdef PCIE_API_REV1 88 89 #define BCMMSGBUF_DUMMY_REF(a, b) do {BCM_REFERENCE((a));BCM_REFERENCE((b));} while (0) 90 91 #define BCMMSGBUF_API_IFIDX(a) 0 92 #define BCMMSGBUF_API_SEQNUM(a) 0 93 #define BCMMSGBUF_IOCTL_XTID(a) 0 94 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id) 95 96 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b) 97 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b) 98 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b)) 99 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b) 100 101 #else /* PCIE_API_REV1 */ 102 103 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id) 104 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id) 105 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no) 106 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id) 107 108 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b)) 109 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b)) 110 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b)) 111 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b)) 112 113 #endif /* PCIE_API_REV1 */ 114 115 /* utility data structures */ 116 117 union addr64 { 118 struct { 119 uint32 low; 120 uint32 high; 121 }; 122 struct { 123 uint32 low_addr; 124 uint32 high_addr; 125 }; 126 uint64 u64; 127 } DECLSPEC_ALIGN(8); 128 129 typedef union addr64 bcm_addr64_t; 130 131 /* IOCTL req Hdr */ 132 /* cmn Msg Hdr */ 133 typedef struct cmn_msg_hdr { 134 /** message type */ 135 uint8 msg_type; 136 /** interface index this is valid for */ 137 uint8 if_id; 138 /* flags */ 139 uint8 flags; 140 /** sequence number */ 141 uint8 epoch; 142 /** packet Identifier for the associated host buffer */ 143 uint32 request_id; 144 } cmn_msg_hdr_t; 145 146 /** message type */ 147 typedef enum bcmpcie_msgtype { 148 MSG_TYPE_GEN_STATUS = 0x1, 149 MSG_TYPE_RING_STATUS = 0x2, 150 MSG_TYPE_FLOW_RING_CREATE = 0x3, 151 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4, 152 /* Enum value as copied from BISON 7.15: new generic message */ 153 MSG_TYPE_RING_CREATE_CMPLT = 0x4, 154 MSG_TYPE_FLOW_RING_DELETE = 0x5, 155 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6, 156 /* Enum value as copied from BISON 7.15: new generic message */ 157 MSG_TYPE_RING_DELETE_CMPLT = 0x6, 158 MSG_TYPE_FLOW_RING_FLUSH = 0x7, 159 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8, 160 MSG_TYPE_IOCTLPTR_REQ = 0x9, 161 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA, 162 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB, 163 MSG_TYPE_IOCTL_CMPLT = 0xC, 164 MSG_TYPE_EVENT_BUF_POST = 0xD, 165 MSG_TYPE_WL_EVENT = 0xE, 166 MSG_TYPE_TX_POST = 0xF, 167 MSG_TYPE_TX_STATUS = 0x10, 168 MSG_TYPE_RXBUF_POST = 0x11, 169 MSG_TYPE_RX_CMPLT = 0x12, 170 MSG_TYPE_LPBK_DMAXFER = 0x13, 171 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14, 172 MSG_TYPE_FLOW_RING_RESUME = 0x15, 173 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16, 174 MSG_TYPE_FLOW_RING_SUSPEND = 0x17, 175 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18, 176 MSG_TYPE_INFO_BUF_POST = 0x19, 177 MSG_TYPE_INFO_BUF_CMPLT = 0x1A, 178 MSG_TYPE_H2D_RING_CREATE = 0x1B, 179 MSG_TYPE_D2H_RING_CREATE = 0x1C, 180 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D, 181 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E, 182 MSG_TYPE_H2D_RING_CONFIG = 0x1F, 183 MSG_TYPE_D2H_RING_CONFIG = 0x20, 184 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21, 185 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22, 186 MSG_TYPE_H2D_MAILBOX_DATA = 0x23, 187 MSG_TYPE_D2H_MAILBOX_DATA = 0x24, 188 MSG_TYPE_TIMSTAMP_BUFPOST = 0x25, 189 MSG_TYPE_HOSTTIMSTAMP = 0x26, 190 MSG_TYPE_HOSTTIMSTAMP_CMPLT = 0x27, 191 MSG_TYPE_FIRMWARE_TIMESTAMP = 0x28, 192 MSG_TYPE_API_MAX_RSVD = 0x3F 193 } bcmpcie_msg_type_t; 194 195 typedef enum bcmpcie_msgtype_int { 196 MSG_TYPE_INTERNAL_USE_START = 0x40, 197 MSG_TYPE_EVENT_PYLD = 0x41, 198 MSG_TYPE_IOCT_PYLD = 0x42, 199 MSG_TYPE_RX_PYLD = 0x43, 200 MSG_TYPE_HOST_FETCH = 0x44, 201 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45, 202 MSG_TYPE_TXMETADATA_PYLD = 0x46, 203 MSG_TYPE_INDX_UPDATE = 0x47, 204 MSG_TYPE_INFO_PYLD = 0x48, 205 MSG_TYPE_TS_EVENT_PYLD = 0x49 206 } bcmpcie_msgtype_int_t; 207 208 typedef enum bcmpcie_msgtype_u { 209 MSG_TYPE_TX_BATCH_POST = 0x80, 210 MSG_TYPE_IOCTL_REQ = 0x81, 211 MSG_TYPE_HOST_EVNT = 0x82, /* console related */ 212 MSG_TYPE_LOOPBACK = 0x83 213 } bcmpcie_msgtype_u_t; 214 215 /** 216 * D2H ring host wakeup soft doorbell, override the PCIE doorbell. 217 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE 218 * Transl0 to write specified value to host address. 219 * 220 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register 221 * and value is Core/Thread context. Host will ensure routing the 32bit address 222 * offerred to PCIE to the mapped register. 223 * 224 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL 225 */ 226 typedef struct bcmpcie_soft_doorbell { 227 uint32 value; /* host defined value to be written, eg HW threadid */ 228 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */ 229 uint16 items; /* interrupt coalescing: item count before wakeup */ 230 uint16 msecs; /* interrupt coalescing: timeout in millisecs */ 231 } bcmpcie_soft_doorbell_t; 232 233 /** 234 * D2H interrupt using MSI instead of INTX 235 * Host configures MSI vector offset for each D2H interrupt 236 * 237 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL 238 */ 239 typedef enum bcmpcie_msi_intr_idx { 240 MSI_INTR_IDX_CTRL_CMPL_RING, 241 MSI_INTR_IDX_TXP_CMPL_RING, 242 MSI_INTR_IDX_RXP_CMPL_RING, 243 MSI_INTR_IDX_MAILBOX, 244 MSI_INTR_IDX_MAX 245 } bcmpcie_msi_intr_idx_t; 246 247 typedef enum bcmpcie_msi_offset_type { 248 BCMPCIE_D2H_MSI_OFFSET_MB0 = 2, 249 BCMPCIE_D2H_MSI_OFFSET_MB1, 250 BCMPCIE_D2H_MSI_OFFSET_DB0, 251 BCMPCIE_D2H_MSI_OFFSET_DB1, 252 BCMPCIE_D2H_MSI_OFFSET_MAX 253 } bcmpcie_msi_offset_type_t; 254 255 typedef struct bcmpcie_msi_offset { 256 uint16 intr_idx; /* interrupt index */ 257 uint16 msi_offset; /* msi vector offset */ 258 } bcmpcie_msi_offset_t; 259 260 typedef struct bcmpcie_msi_offset_config { 261 uint32 len; 262 bcmpcie_msi_offset_t bcmpcie_msi_offset[MSI_INTR_IDX_MAX]; 263 } bcmpcie_msi_offset_config_t; 264 265 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1 266 267 268 /* if_id */ 269 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5 270 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7 271 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \ 272 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 273 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0 274 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F 275 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \ 276 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 277 278 /* flags */ 279 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1 280 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2 281 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80 282 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80 283 284 /* IOCTL request message */ 285 typedef struct ioctl_req_msg { 286 /** common message header */ 287 cmn_msg_hdr_t cmn_hdr; 288 /** ioctl command type */ 289 uint32 cmd; 290 /** ioctl transaction ID, to pair with a ioctl response */ 291 uint16 trans_id; 292 /** input arguments buffer len */ 293 uint16 input_buf_len; 294 /** expected output len */ 295 uint16 output_buf_len; 296 /** to align the host address on 8 byte boundary */ 297 uint16 rsvd[3]; 298 /** always align on 8 byte boundary */ 299 bcm_addr64_t host_input_buf_addr; 300 /* rsvd */ 301 uint32 rsvd1[2]; 302 } ioctl_req_msg_t; 303 304 /** buffer post messages for device to use to return IOCTL responses, Events */ 305 typedef struct ioctl_resp_evt_buf_post_msg { 306 /** common message header */ 307 cmn_msg_hdr_t cmn_hdr; 308 /** length of the host buffer supplied */ 309 uint16 host_buf_len; 310 /** to align the host address on 8 byte boundary */ 311 uint16 reserved[3]; 312 /** always align on 8 byte boundary */ 313 bcm_addr64_t host_buf_addr; 314 uint32 rsvd[4]; 315 } ioctl_resp_evt_buf_post_msg_t; 316 317 /* buffer post messages for device to use to return dbg buffers */ 318 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t; 319 320 321 /* An infobuf host buffer starts with a 32 bit (LE) version. */ 322 #define PCIE_INFOBUF_V1 1 323 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that 324 * is wrapped previously/also in a WLC_E_TRACE event. See structure 325 * msgrace_hdr_t in msgtrace.h. 326 */ 327 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1 328 329 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that 330 * is wrapped previously/also in a WLC_E_TRACE event. See structure 331 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE 332 * and a LOGTRACE is the "trace type" field.) 333 */ 334 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2 335 336 /* An infobuf version 1 host buffer has a single TLV. The information on the 337 * version 1 types follow this structure definition. (int's LE) 338 */ 339 typedef struct info_buf_payload_hdr_s { 340 uint16 type; 341 uint16 length; 342 } info_buf_payload_hdr_t; 343 344 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0x00000001 345 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 0 346 347 typedef struct pcie_dma_xfer_params { 348 /** common message header */ 349 cmn_msg_hdr_t cmn_hdr; 350 351 /** always align on 8 byte boundary */ 352 bcm_addr64_t host_input_buf_addr; 353 354 /** always align on 8 byte boundary */ 355 bcm_addr64_t host_ouput_buf_addr; 356 357 /** length of transfer */ 358 uint32 xfer_len; 359 /** delay before doing the src txfer */ 360 uint32 srcdelay; 361 /** delay before doing the dest txfer */ 362 uint32 destdelay; 363 uint8 rsvd[3]; 364 uint8 flags; 365 } pcie_dma_xfer_params_t; 366 367 /** Complete msgbuf hdr for flow ring update from host to dongle */ 368 typedef struct tx_flowring_create_request { 369 cmn_msg_hdr_t msg; 370 uint8 da[ETHER_ADDR_LEN]; 371 uint8 sa[ETHER_ADDR_LEN]; 372 uint8 tid; 373 uint8 if_flags; 374 uint16 flow_ring_id; 375 uint8 tc; 376 /* priority_ifrmmask is to define core mask in ifrm mode. 377 * currently it is not used for priority. so uses solely for ifrm mask 378 */ 379 uint8 priority_ifrmmask; 380 uint16 int_vector; 381 uint16 max_items; 382 uint16 len_item; 383 bcm_addr64_t flow_ring_ptr; 384 } tx_flowring_create_request_t; 385 386 typedef struct tx_flowring_delete_request { 387 cmn_msg_hdr_t msg; 388 uint16 flow_ring_id; 389 uint16 reason; 390 uint32 rsvd[7]; 391 } tx_flowring_delete_request_t; 392 393 typedef struct tx_flowring_flush_request { 394 cmn_msg_hdr_t msg; 395 uint16 flow_ring_id; 396 uint16 reason; 397 uint32 rsvd[7]; 398 } tx_flowring_flush_request_t; 399 400 /** Subtypes for ring_config_req control message */ 401 typedef enum ring_config_subtype { 402 /** Default D2H PCIE doorbell override using ring_config_req msg */ 403 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */ 404 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */ 405 } ring_config_subtype_t; 406 407 typedef struct ring_config_req { 408 cmn_msg_hdr_t msg; 409 uint16 subtype; 410 uint16 ring_id; 411 uint32 rsvd; 412 union { 413 uint32 data[6]; 414 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */ 415 bcmpcie_soft_doorbell_t soft_doorbell; 416 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */ 417 bcmpcie_msi_offset_config_t msi_offset; 418 }; 419 } ring_config_req_t; 420 421 /* data structure to use to create on the fly d2h rings */ 422 typedef struct d2h_ring_create_req { 423 cmn_msg_hdr_t msg; 424 uint16 ring_id; 425 uint16 ring_type; 426 uint32 flags; 427 bcm_addr64_t ring_ptr; 428 uint16 max_items; 429 uint16 len_item; 430 uint32 rsvd[3]; 431 } d2h_ring_create_req_t; 432 433 /* data structure to use to create on the fly h2d rings */ 434 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4 435 typedef struct h2d_ring_create_req { 436 cmn_msg_hdr_t msg; 437 uint16 ring_id; 438 uint8 ring_type; 439 uint8 n_completion_ids; 440 uint32 flags; 441 bcm_addr64_t ring_ptr; 442 uint16 max_items; 443 uint16 len_item; 444 uint16 completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED]; 445 uint32 rsvd; 446 } h2d_ring_create_req_t; 447 448 typedef struct d2h_ring_config_req { 449 cmn_msg_hdr_t msg; 450 uint16 d2h_ring_config_subtype; 451 uint16 d2h_ring_id; 452 uint32 d2h_ring_config_data[4]; 453 uint32 rsvd[3]; 454 } d2h_ring_config_req_t; 455 456 typedef struct h2d_ring_config_req { 457 cmn_msg_hdr_t msg; 458 uint16 h2d_ring_config_subtype; 459 uint16 h2d_ring_id; 460 uint32 h2d_ring_config_data; 461 uint32 rsvd[6]; 462 } h2d_ring_config_req_t; 463 464 typedef struct h2d_mailbox_data { 465 cmn_msg_hdr_t msg; 466 uint32 mail_box_data; 467 uint32 rsvd[7]; 468 } h2d_mailbox_data_t; 469 typedef struct host_timestamp_msg { 470 cmn_msg_hdr_t msg; 471 uint16 xt_id; /* transaction ID */ 472 uint16 input_data_len; /* data len at the host_buf_addr, data in TLVs */ 473 uint16 seqnum; /* number of times host captured the timestamp */ 474 uint16 rsvd; 475 /* always align on 8 byte boundary */ 476 bcm_addr64_t host_buf_addr; 477 /* rsvd */ 478 uint32 rsvd1[4]; 479 } host_timestamp_msg_t; 480 481 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */ 482 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t; 483 484 typedef union ctrl_submit_item { 485 ioctl_req_msg_t ioctl_req; 486 ioctl_resp_evt_buf_post_msg_t resp_buf_post; 487 pcie_dma_xfer_params_t dma_xfer; 488 tx_flowring_create_request_t flow_create; 489 tx_flowring_delete_request_t flow_delete; 490 tx_flowring_flush_request_t flow_flush; 491 ring_config_req_t ring_config_req; 492 d2h_ring_create_req_t d2h_create; 493 h2d_ring_create_req_t h2d_create; 494 d2h_ring_config_req_t d2h_config; 495 h2d_ring_config_req_t h2d_config; 496 h2d_mailbox_data_t h2d_mailbox_data; 497 host_timestamp_msg_t host_ts; 498 ts_buf_post_msg_t ts_buf_post; 499 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE]; 500 } ctrl_submit_item_t; 501 502 typedef struct info_ring_submit_item { 503 info_buf_post_msg_t info_buf_post; 504 unsigned char check[H2DRING_INFO_BUFPOST_ITEMSIZE]; 505 } info_sumbit_item_t; 506 507 /** Control Completion messages (20 bytes) */ 508 typedef struct compl_msg_hdr { 509 /** status for the completion */ 510 int16 status; 511 /** submisison flow ring id which generated this status */ 512 union { 513 uint16 ring_id; 514 uint16 flow_ring_id; 515 }; 516 } compl_msg_hdr_t; 517 518 /** XOR checksum or a magic number to audit DMA done */ 519 typedef uint32 dma_done_t; 520 521 #define MAX_CLKSRC_ID 0xF 522 523 typedef struct ts_timestamp_srcid { 524 union { 525 uint32 ts_low; /* time stamp low 32 bits */ 526 uint32 reserved; /* If timestamp not used */ 527 }; 528 union { 529 uint32 ts_high; /* time stamp high 28 bits */ 530 union { 531 uint32 ts_high_ext :28; /* time stamp high 28 bits */ 532 uint32 clk_id_ext :3; /* clock ID source */ 533 uint32 phase :1; /* Phase bit */ 534 dma_done_t marker_ext; 535 }; 536 }; 537 } ts_timestamp_srcid_t; 538 539 typedef ts_timestamp_srcid_t ipc_timestamp_t; 540 541 typedef struct ts_timestamp { 542 uint32 low; 543 uint32 high; 544 } ts_timestamp_t; 545 546 typedef ts_timestamp_t tick_count_64_t; 547 typedef ts_timestamp_t ts_timestamp_ns_64_t; 548 typedef ts_timestamp_t ts_correction_m_t; 549 typedef ts_timestamp_t ts_correction_b_t; 550 551 /* completion header status codes */ 552 #define BCMPCIE_SUCCESS 0 553 #define BCMPCIE_NOTFOUND 1 554 #define BCMPCIE_NOMEM 2 555 #define BCMPCIE_BADOPTION 3 556 #define BCMPCIE_RING_IN_USE 4 557 #define BCMPCIE_RING_ID_INVALID 5 558 #define BCMPCIE_PKT_FLUSH 6 559 #define BCMPCIE_NO_EVENT_BUF 7 560 #define BCMPCIE_NO_RX_BUF 8 561 #define BCMPCIE_NO_IOCTLRESP_BUF 9 562 #define BCMPCIE_MAX_IOCTLRESP_BUF 10 563 #define BCMPCIE_MAX_EVENT_BUF 11 564 #define BCMPCIE_BAD_PHASE 12 565 #define BCMPCIE_INVALID_CPL_RINGID 13 566 #define BCMPCIE_RING_TYPE_INVALID 14 567 #define BCMPCIE_NO_TS_EVENT_BUF 15 568 #define BCMPCIE_MAX_TS_EVENT_BUF 16 569 570 /** IOCTL completion response */ 571 typedef struct ioctl_compl_resp_msg { 572 /** common message header */ 573 cmn_msg_hdr_t cmn_hdr; 574 /** completion message header */ 575 compl_msg_hdr_t compl_hdr; 576 /** response buffer len where a host buffer is involved */ 577 uint16 resp_len; 578 /** transaction id to pair with a request */ 579 uint16 trans_id; 580 /** cmd id */ 581 uint32 cmd; 582 /** XOR checksum or a magic number to audit DMA done */ 583 dma_done_t marker; 584 } ioctl_comp_resp_msg_t; 585 586 /** IOCTL request acknowledgement */ 587 typedef struct ioctl_req_ack_msg { 588 /** common message header */ 589 cmn_msg_hdr_t cmn_hdr; 590 /** completion message header */ 591 compl_msg_hdr_t compl_hdr; 592 /** cmd id */ 593 uint32 cmd; 594 uint32 rsvd; 595 /** XOR checksum or a magic number to audit DMA done */ 596 dma_done_t marker; 597 } ioctl_req_ack_msg_t; 598 599 /** WL event message: send from device to host */ 600 typedef struct wlevent_req_msg { 601 /** common message header */ 602 cmn_msg_hdr_t cmn_hdr; 603 /** completion message header */ 604 compl_msg_hdr_t compl_hdr; 605 /** event data len valid with the event buffer */ 606 uint16 event_data_len; 607 /** sequence number */ 608 uint16 seqnum; 609 /** rsvd */ 610 uint32 rsvd; 611 /** XOR checksum or a magic number to audit DMA done */ 612 dma_done_t marker; 613 } wlevent_req_msg_t; 614 615 /** dma xfer complete message */ 616 typedef struct pcie_dmaxfer_cmplt { 617 /** common message header */ 618 cmn_msg_hdr_t cmn_hdr; 619 /** completion message header */ 620 compl_msg_hdr_t compl_hdr; 621 uint32 rsvd[2]; 622 /** XOR checksum or a magic number to audit DMA done */ 623 dma_done_t marker; 624 } pcie_dmaxfer_cmplt_t; 625 626 /** general status message */ 627 typedef struct pcie_gen_status { 628 /** common message header */ 629 cmn_msg_hdr_t cmn_hdr; 630 /** completion message header */ 631 compl_msg_hdr_t compl_hdr; 632 uint32 rsvd[2]; 633 /** XOR checksum or a magic number to audit DMA done */ 634 dma_done_t marker; 635 } pcie_gen_status_t; 636 637 /** ring status message */ 638 typedef struct pcie_ring_status { 639 /** common message header */ 640 cmn_msg_hdr_t cmn_hdr; 641 /** completion message header */ 642 compl_msg_hdr_t compl_hdr; 643 /** message which firmware couldn't decode */ 644 uint16 write_idx; 645 uint16 rsvd[3]; 646 /** XOR checksum or a magic number to audit DMA done */ 647 dma_done_t marker; 648 } pcie_ring_status_t; 649 650 typedef struct ring_create_response { 651 cmn_msg_hdr_t cmn_hdr; 652 compl_msg_hdr_t cmplt; 653 uint32 rsvd[2]; 654 /** XOR checksum or a magic number to audit DMA done */ 655 dma_done_t marker; 656 } ring_create_response_t; 657 658 typedef ring_create_response_t tx_flowring_create_response_t; 659 typedef ring_create_response_t h2d_ring_create_response_t; 660 typedef ring_create_response_t d2h_ring_create_response_t; 661 662 typedef struct tx_flowring_delete_response { 663 cmn_msg_hdr_t msg; 664 compl_msg_hdr_t cmplt; 665 uint32 rsvd[2]; 666 /** XOR checksum or a magic number to audit DMA done */ 667 dma_done_t marker; 668 } tx_flowring_delete_response_t; 669 670 typedef struct tx_flowring_flush_response { 671 cmn_msg_hdr_t msg; 672 compl_msg_hdr_t cmplt; 673 uint32 rsvd[2]; 674 /** XOR checksum or a magic number to audit DMA done */ 675 dma_done_t marker; 676 } tx_flowring_flush_response_t; 677 678 /** Common layout of all d2h control messages */ 679 typedef struct ctrl_compl_msg { 680 /** common message header */ 681 cmn_msg_hdr_t cmn_hdr; 682 /** completion message header */ 683 compl_msg_hdr_t compl_hdr; 684 uint32 rsvd[2]; 685 /** XOR checksum or a magic number to audit DMA done */ 686 dma_done_t marker; 687 } ctrl_compl_msg_t; 688 689 typedef struct ring_config_resp { 690 /** common message header */ 691 cmn_msg_hdr_t cmn_hdr; 692 /** completion message header */ 693 compl_msg_hdr_t compl_hdr; 694 uint32 rsvd[2]; 695 /** XOR checksum or a magic number to audit DMA done */ 696 dma_done_t marker; 697 } ring_config_resp_t; 698 699 typedef struct d2h_mailbox_data { 700 cmn_msg_hdr_t msg; 701 compl_msg_hdr_t cmplt; 702 uint32 d2h_mailbox_data; 703 uint32 rsvd[1]; 704 /* XOR checksum or a magic number to audit DMA done */ 705 dma_done_t marker; 706 } d2h_mailbox_data_t; 707 708 /* dbg buf completion msg: send from device to host */ 709 typedef struct info_buf_resp { 710 /* common message header */ 711 cmn_msg_hdr_t cmn_hdr; 712 /* completion message header */ 713 compl_msg_hdr_t compl_hdr; 714 /* event data len valid with the event buffer */ 715 uint16 info_data_len; 716 /* sequence number */ 717 uint16 seqnum; 718 /* rsvd */ 719 uint32 rsvd; 720 /* XOR checksum or a magic number to audit DMA done */ 721 dma_done_t marker; 722 } info_buf_resp_t; 723 724 typedef struct info_ring_cpl_item { 725 info_buf_resp_t info_buf_post; 726 unsigned char check[D2HRING_INFO_BUFCMPLT_ITEMSIZE]; 727 } info_cpl_item_t; 728 729 typedef struct host_timestamp_msg_cpl { 730 cmn_msg_hdr_t msg; 731 compl_msg_hdr_t cmplt; 732 uint16 xt_id; /* transaction ID */ 733 uint16 rsvd; 734 uint32 rsvd1; 735 /* XOR checksum or a magic number to audit DMA done */ 736 dma_done_t marker; 737 } host_timestamp_msg_cpl_t; 738 739 typedef struct fw_timestamp_event_msg { 740 cmn_msg_hdr_t msg; 741 compl_msg_hdr_t cmplt; 742 /* fw captures time stamp info and passed that to host in TLVs */ 743 uint16 buf_len; /* length of the time stamp data copied in host buf */ 744 uint16 seqnum; /* number of times fw captured time stamp */ 745 uint32 rsvd; 746 /* XOR checksum or a magic number to audit DMA done */ 747 dma_done_t marker; 748 } fw_timestamp_event_msg_t; 749 750 typedef union ctrl_completion_item { 751 ioctl_comp_resp_msg_t ioctl_resp; 752 wlevent_req_msg_t event; 753 ioctl_req_ack_msg_t ioct_ack; 754 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt; 755 pcie_gen_status_t pcie_gen_status; 756 pcie_ring_status_t pcie_ring_status; 757 tx_flowring_create_response_t txfl_create_resp; 758 tx_flowring_delete_response_t txfl_delete_resp; 759 tx_flowring_flush_response_t txfl_flush_resp; 760 ctrl_compl_msg_t ctrl_compl; 761 ring_config_resp_t ring_config_resp; 762 d2h_mailbox_data_t d2h_mailbox_data; 763 info_buf_resp_t dbg_resp; 764 h2d_ring_create_response_t h2d_ring_create_resp; 765 d2h_ring_create_response_t d2h_ring_create_resp; 766 host_timestamp_msg_cpl_t host_ts_cpl; 767 fw_timestamp_event_msg_t fw_ts_event; 768 unsigned char ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE]; 769 } ctrl_completion_item_t; 770 771 /** H2D Rxpost ring work items */ 772 typedef struct host_rxbuf_post { 773 /** common message header */ 774 cmn_msg_hdr_t cmn_hdr; 775 /** provided meta data buffer len */ 776 uint16 metadata_buf_len; 777 /** provided data buffer len to receive data */ 778 uint16 data_buf_len; 779 /** alignment to make the host buffers start on 8 byte boundary */ 780 uint32 rsvd; 781 /** provided meta data buffer */ 782 bcm_addr64_t metadata_buf_addr; 783 /** provided data buffer to receive data */ 784 bcm_addr64_t data_buf_addr; 785 } host_rxbuf_post_t; 786 787 typedef union rxbuf_submit_item { 788 host_rxbuf_post_t rxpost; 789 unsigned char check[H2DRING_RXPOST_ITEMSIZE]; 790 } rxbuf_submit_item_t; 791 792 /* D2H Rxcompletion ring work items for IPC rev7 */ 793 typedef struct host_rxbuf_cmpl { 794 /** common message header */ 795 cmn_msg_hdr_t cmn_hdr; 796 /** completion message header */ 797 compl_msg_hdr_t compl_hdr; 798 /** filled up meta data len */ 799 uint16 metadata_len; 800 /** filled up buffer len to receive data */ 801 uint16 data_len; 802 /** offset in the host rx buffer where the data starts */ 803 uint16 data_offset; 804 /** offset in the host rx buffer where the data starts */ 805 uint16 flags; 806 /** rx status */ 807 uint32 rx_status_0; 808 uint32 rx_status_1; 809 /** XOR checksum or a magic number to audit DMA done */ 810 /* This is for rev6 only. For IPC rev7, this is a reserved field */ 811 dma_done_t marker; 812 /* timestamp */ 813 ipc_timestamp_t ts; 814 } host_rxbuf_cmpl_t; 815 816 typedef union rxbuf_complete_item { 817 host_rxbuf_cmpl_t rxcmpl; 818 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE]; 819 } rxbuf_complete_item_t; 820 821 822 typedef struct host_txbuf_post { 823 /** common message header */ 824 cmn_msg_hdr_t cmn_hdr; 825 /** eth header */ 826 uint8 txhdr[ETHER_HDR_LEN]; 827 /** flags */ 828 uint8 flags; 829 /** number of segments */ 830 uint8 seg_cnt; 831 832 /** provided meta data buffer for txstatus */ 833 bcm_addr64_t metadata_buf_addr; 834 /** provided data buffer to receive data */ 835 bcm_addr64_t data_buf_addr; 836 /** provided meta data buffer len */ 837 uint16 metadata_buf_len; 838 /** provided data buffer len to receive data */ 839 uint16 data_len; 840 /** XOR checksum or a magic number to audit DMA done */ 841 dma_done_t marker; 842 } host_txbuf_post_t; 843 844 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01 845 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02 846 847 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */ 848 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT 0x02 /* needs to be shifted past other bits */ 849 850 851 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5 852 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT) 853 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00 854 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01 855 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02 856 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03 857 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8 858 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT) 859 860 /* These are added to fix up compile issues */ 861 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3 862 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11 863 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT 864 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK 865 866 867 /* H2D Txpost ring work items */ 868 typedef union txbuf_submit_item { 869 host_txbuf_post_t txpost; 870 unsigned char check[H2DRING_TXPOST_ITEMSIZE]; 871 } txbuf_submit_item_t; 872 873 /* D2H Txcompletion ring work items - extended for IOC rev7 */ 874 typedef struct host_txbuf_cmpl { 875 /** common message header */ 876 cmn_msg_hdr_t cmn_hdr; 877 /** completion message header */ 878 compl_msg_hdr_t compl_hdr; 879 union { 880 struct { 881 /** provided meta data len */ 882 uint16 metadata_len; 883 /** WLAN side txstatus */ 884 uint16 tx_status; 885 }; 886 /** XOR checksum or a magic number to audit DMA done */ 887 /* This is for rev6 only. For IPC rev7, this is not used */ 888 dma_done_t marker; 889 }; 890 /* timestamp */ 891 ipc_timestamp_t ts; 892 } host_txbuf_cmpl_t; 893 894 typedef union txbuf_complete_item { 895 host_txbuf_cmpl_t txcmpl; 896 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE]; 897 } txbuf_complete_item_t; 898 899 #define BCMPCIE_D2H_METADATA_HDRLEN 4 900 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4) 901 902 /** ret buf struct */ 903 typedef struct ret_buf_ptr { 904 uint32 low_addr; 905 uint32 high_addr; 906 } ret_buf_t; 907 908 909 #ifdef PCIE_API_REV1 910 911 /* ioctl specific hdr */ 912 typedef struct ioctl_hdr { 913 uint16 cmd; 914 uint16 retbuf_len; 915 uint32 cmd_id; 916 } ioctl_hdr_t; 917 918 typedef struct ioctlptr_hdr { 919 uint16 cmd; 920 uint16 retbuf_len; 921 uint16 buflen; 922 uint16 rsvd; 923 uint32 cmd_id; 924 } ioctlptr_hdr_t; 925 926 #else /* PCIE_API_REV1 */ 927 928 typedef struct ioctl_req_hdr { 929 uint32 pkt_id; /**< Packet ID */ 930 uint32 cmd; /**< IOCTL ID */ 931 uint16 retbuf_len; 932 uint16 buflen; 933 uint16 xt_id; /**< transaction ID */ 934 uint16 rsvd[1]; 935 } ioctl_req_hdr_t; 936 937 #endif /* PCIE_API_REV1 */ 938 939 940 /** Complete msgbuf hdr for ioctl from host to dongle */ 941 typedef struct ioct_reqst_hdr { 942 cmn_msg_hdr_t msg; 943 #ifdef PCIE_API_REV1 944 ioctl_hdr_t ioct_hdr; 945 #else 946 ioctl_req_hdr_t ioct_hdr; 947 #endif 948 ret_buf_t ret_buf; 949 } ioct_reqst_hdr_t; 950 951 typedef struct ioctptr_reqst_hdr { 952 cmn_msg_hdr_t msg; 953 #ifdef PCIE_API_REV1 954 ioctlptr_hdr_t ioct_hdr; 955 #else 956 ioctl_req_hdr_t ioct_hdr; 957 #endif 958 ret_buf_t ret_buf; 959 ret_buf_t ioct_buf; 960 } ioctptr_reqst_hdr_t; 961 962 /** ioctl response header */ 963 typedef struct ioct_resp_hdr { 964 cmn_msg_hdr_t msg; 965 #ifdef PCIE_API_REV1 966 uint32 cmd_id; 967 #else 968 uint32 pkt_id; 969 #endif 970 uint32 status; 971 uint32 ret_len; 972 uint32 inline_data; 973 #ifdef PCIE_API_REV1 974 #else 975 uint16 xt_id; /**< transaction ID */ 976 uint16 rsvd[1]; 977 #endif 978 } ioct_resp_hdr_t; 979 980 /* ioct resp header used in dongle */ 981 /* ret buf hdr will be stripped off inside dongle itself */ 982 typedef struct msgbuf_ioctl_resp { 983 ioct_resp_hdr_t ioct_hdr; 984 ret_buf_t ret_buf; /**< ret buf pointers */ 985 } msgbuf_ioct_resp_t; 986 987 /** WL event hdr info */ 988 typedef struct wl_event_hdr { 989 cmn_msg_hdr_t msg; 990 uint16 event; 991 uint8 flags; 992 uint8 rsvd; 993 uint16 retbuf_len; 994 uint16 rsvd1; 995 uint32 rxbufid; 996 } wl_event_hdr_t; 997 998 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF 999 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE 1000 1001 typedef struct txbatch_lenptr_tup { 1002 uint32 pktid; 1003 uint16 pktlen; 1004 uint16 rsvd; 1005 ret_buf_t ret_buf; /**< ret buf pointers */ 1006 } txbatch_lenptr_tup_t; 1007 1008 typedef struct txbatch_cmn_msghdr { 1009 cmn_msg_hdr_t msg; 1010 uint8 priority; 1011 uint8 hdrlen; 1012 uint8 pktcnt; 1013 uint8 flowid; 1014 uint8 txhdr[ETHER_HDR_LEN]; 1015 uint16 rsvd; 1016 } txbatch_cmn_msghdr_t; 1017 1018 typedef struct txbatch_msghdr { 1019 txbatch_cmn_msghdr_t txcmn; 1020 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */ 1021 } txbatch_msghdr_t; 1022 1023 /* TX desc posting header */ 1024 typedef struct tx_lenptr_tup { 1025 uint16 pktlen; 1026 uint16 rsvd; 1027 ret_buf_t ret_buf; /**< ret buf pointers */ 1028 } tx_lenptr_tup_t; 1029 1030 typedef struct txdescr_cmn_msghdr { 1031 cmn_msg_hdr_t msg; 1032 uint8 priority; 1033 uint8 hdrlen; 1034 uint8 descrcnt; 1035 uint8 flowid; 1036 uint32 pktid; 1037 } txdescr_cmn_msghdr_t; 1038 1039 typedef struct txdescr_msghdr { 1040 txdescr_cmn_msghdr_t txcmn; 1041 uint8 txhdr[ETHER_HDR_LEN]; 1042 uint16 rsvd; 1043 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */ 1044 } txdescr_msghdr_t; 1045 1046 /** Tx status header info */ 1047 typedef struct txstatus_hdr { 1048 cmn_msg_hdr_t msg; 1049 uint32 pktid; 1050 } txstatus_hdr_t; 1051 1052 /** RX bufid-len-ptr tuple */ 1053 typedef struct rx_lenptr_tup { 1054 uint32 rxbufid; 1055 uint16 len; 1056 uint16 rsvd2; 1057 ret_buf_t ret_buf; /**< ret buf pointers */ 1058 } rx_lenptr_tup_t; 1059 1060 /** Rx descr Post hdr info */ 1061 typedef struct rxdesc_msghdr { 1062 cmn_msg_hdr_t msg; 1063 uint16 rsvd0; 1064 uint8 rsvd1; 1065 uint8 descnt; 1066 rx_lenptr_tup_t rx_tup[0]; 1067 } rxdesc_msghdr_t; 1068 1069 /** RX complete tuples */ 1070 typedef struct rxcmplt_tup { 1071 uint16 retbuf_len; 1072 uint16 data_offset; 1073 uint32 rxstatus0; 1074 uint32 rxstatus1; 1075 uint32 rxbufid; 1076 } rxcmplt_tup_t; 1077 1078 /** RX complete messge hdr */ 1079 typedef struct rxcmplt_hdr { 1080 cmn_msg_hdr_t msg; 1081 uint16 rsvd0; 1082 uint16 rxcmpltcnt; 1083 rxcmplt_tup_t rx_tup[0]; 1084 } rxcmplt_hdr_t; 1085 1086 typedef struct hostevent_hdr { 1087 cmn_msg_hdr_t msg; 1088 uint32 evnt_pyld; 1089 } hostevent_hdr_t; 1090 1091 typedef struct dma_xfer_params { 1092 uint32 src_physaddr_hi; 1093 uint32 src_physaddr_lo; 1094 uint32 dest_physaddr_hi; 1095 uint32 dest_physaddr_lo; 1096 uint32 len; 1097 uint32 srcdelay; 1098 uint32 destdelay; 1099 } dma_xfer_params_t; 1100 1101 enum { 1102 HOST_EVENT_CONS_CMD = 1 1103 }; 1104 1105 /* defines for flags */ 1106 #define MSGBUF_IOC_ACTION_MASK 0x1 1107 1108 #define MAX_SUSPEND_REQ 15 1109 1110 typedef struct tx_idle_flowring_suspend_request { 1111 cmn_msg_hdr_t msg; 1112 uint16 ring_id[MAX_SUSPEND_REQ]; /* ring Id's */ 1113 uint16 num; /* number of flowid's to suspend */ 1114 } tx_idle_flowring_suspend_request_t; 1115 1116 typedef struct tx_idle_flowring_suspend_response { 1117 cmn_msg_hdr_t msg; 1118 compl_msg_hdr_t cmplt; 1119 uint32 rsvd[2]; 1120 dma_done_t marker; 1121 } tx_idle_flowring_suspend_response_t; 1122 1123 typedef struct tx_idle_flowring_resume_request { 1124 cmn_msg_hdr_t msg; 1125 uint16 flow_ring_id; 1126 uint16 reason; 1127 uint32 rsvd[7]; 1128 } tx_idle_flowring_resume_request_t; 1129 1130 typedef struct tx_idle_flowring_resume_response { 1131 cmn_msg_hdr_t msg; 1132 compl_msg_hdr_t cmplt; 1133 uint32 rsvd[2]; 1134 dma_done_t marker; 1135 } tx_idle_flowring_resume_response_t; 1136 1137 /* timesync related additions */ 1138 1139 typedef struct _bcm_xtlv { 1140 uint16 id; /* TLV idenitifier */ 1141 uint16 len; /* TLV length in bytes */ 1142 } _bcm_xtlv_t; 1143 1144 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0 1145 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1 1146 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2 1147 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3 1148 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4 1149 #define BCMMSGBUF_MAX_TSYNC_TAG 5 1150 1151 /* Flags in fw clock info TLV */ 1152 #define CAP_DEVICE_TS (1 << 0) 1153 #define CAP_CORRECTED_TS (1 << 1) 1154 #define TS_CLK_ACTIVE (1 << 2) 1155 1156 typedef struct ts_fw_clock_info { 1157 _bcm_xtlv_t xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */ 1158 ts_timestamp_srcid_t ts; /* tick count */ 1159 uchar clk_src[4]; /* clock source acronym ILP/AVB/TSF */ 1160 uint32 nominal_clock_freq; 1161 uint32 reset_cnt; 1162 uint8 flags; 1163 uint8 rsvd[3]; 1164 } ts_fw_clock_info_t; 1165 1166 typedef struct ts_host_clock_info { 1167 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1168 tick_count_64_t ticks; /* 64 bit host tick counter */ 1169 ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */ 1170 } ts_host_clock_info_t; 1171 1172 typedef struct ts_host_clock_sel { 1173 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */ 1174 uint32 seqnum; /* number of times GPIO time sync toggled */ 1175 uint8 min_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1176 uint8 max_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1177 uint16 rsvd[1]; 1178 } ts_host_clock_sel_t; 1179 1180 typedef struct ts_d2h_clock_correction { 1181 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1182 uint8 clk_id; /* clock source in the device */ 1183 uint8 rsvd[3]; 1184 ts_correction_m_t m; /* y = 'm' x + b */ 1185 ts_correction_b_t b; /* y = 'm' x + 'c' */ 1186 } ts_d2h_clock_correction_t; 1187 1188 typedef struct ts_host_timestamping_config { 1189 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */ 1190 /* time period to capture the device time stamp and toggle WLAN_TIME_SYNC_GPIO */ 1191 uint16 period_ms; 1192 uint8 flags; 1193 uint8 rsvd; 1194 uint32 reset_cnt; 1195 } ts_host_timestamping_config_t; 1196 1197 /* Flags in host timestamping config TLV */ 1198 #define FLAG_HOST_RESET (1 << 0) 1199 1200 #endif /* _bcmmsgbuf_h_ */ 1201