1 /* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Copyright (C) 1999-2017, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: siutils_priv.h 625739 2016-03-17 12:28:03Z $ 28 */ 29 30 #ifndef _siutils_priv_h_ 31 #define _siutils_priv_h_ 32 33 #if defined(SI_ERROR_ENFORCE) 34 #define SI_ERROR(args) printf args 35 #else 36 #define SI_ERROR(args) printf args 37 #endif 38 39 #if defined(ENABLE_CORECAPTURE) 40 41 #define SI_PRINT(args) osl_wificc_logDebug args 42 43 #else 44 45 #define SI_PRINT(args) printf args 46 47 #endif /* ENABLE_CORECAPTURE */ 48 49 50 #define SI_MSG(args) 51 52 #ifdef BCMDBG_SI 53 #define SI_VMSG(args) printf args 54 #else 55 #define SI_VMSG(args) 56 #endif 57 58 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 59 60 typedef uint32 (*si_intrsoff_t)(void *intr_arg); 61 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 62 typedef bool (*si_intrsenabled_t)(void *intr_arg); 63 64 65 #define SI_GPIO_MAX 16 66 67 typedef struct gci_gpio_item { 68 void *arg; 69 uint8 gci_gpio; 70 uint8 status; 71 gci_gpio_handler_t handler; 72 struct gci_gpio_item *next; 73 } gci_gpio_item_t; 74 75 #define AI_SLAVE_WRAPPER 0 76 #define AI_MASTER_WRAPPER 1 77 78 typedef struct axi_wrapper { 79 uint32 mfg; 80 uint32 cid; 81 uint32 rev; 82 uint32 wrapper_type; 83 uint32 wrapper_addr; 84 uint32 wrapper_size; 85 } axi_wrapper_t; 86 87 #define SI_MAX_AXI_WRAPPERS 32 88 #define AI_REG_READ_TIMEOUT 300 /* in msec */ 89 90 /* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */ 91 /* register at 0x19C doesn't exist, so error is logged at the slave wrapper */ 92 #define BT_CC_SPROM_BADREG_LO 0x18000190 93 #define BT_CC_SPROM_BADREG_HI 0 94 #define BCM4350_BT_AXI_ID 6 95 #define BCM4345_BT_AXI_ID 6 96 97 typedef struct si_cores_info { 98 volatile void *regs[SI_MAXCORES]; /* other regs va */ 99 100 uint coreid[SI_MAXCORES]; /**< id of each core */ 101 uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */ 102 void *regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */ 103 uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set (usbh20) */ 104 uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */ 105 uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */ 106 107 void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */ 108 uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */ 109 110 void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */ 111 uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */ 112 113 uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */ 114 uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */ 115 } si_cores_info_t; 116 117 /** misc si info needed by some of the routines */ 118 typedef struct si_info { 119 struct si_pub pub; /**< back plane public state (must be first field) */ 120 121 void *osh; /**< osl os handle */ 122 void *sdh; /**< bcmsdh handle */ 123 124 uint dev_coreid; /**< the core provides driver functions */ 125 void *intr_arg; /**< interrupt callback function arg */ 126 si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */ 127 si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */ 128 si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */ 129 130 void *pch; /**< PCI/E core handle */ 131 132 bool memseg; /**< flag to toggle MEM_SEG register */ 133 134 char *vars; 135 uint varsz; 136 137 volatile void *curmap; /* current regs va */ 138 139 uint curidx; /**< current core index */ 140 uint numcores; /**< # discovered cores */ 141 142 void *curwrap; /**< current wrapper va */ 143 144 uint32 oob_router; /**< oob router registers for axi */ 145 146 si_cores_info_t *cores_info; 147 gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */ 148 uint chipnew; /**< new chip number */ 149 uint second_bar0win; /**< Backplane region */ 150 uint num_br; /**< # discovered bridges */ 151 uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */ 152 uint32 xtalfreq; 153 uint32 macclk_mul_fact; /* Multiplication factor necessary to adjust MAC Clock 154 * during ULB Mode operation. One instance where this is used is configuring TSF L-frac 155 * register 156 */ 157 bool device_removed; 158 uint axi_num_wrappers; 159 axi_wrapper_t * axi_wrapper; 160 } si_info_t; 161 162 163 #define SI_INFO(sih) ((si_info_t *)(uintptr)sih) 164 165 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 166 ISALIGNED((x), SI_CORE_SIZE)) 167 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 168 #define BADCOREADDR 0 169 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 170 #define NOREV -1 /**< Invalid rev */ 171 172 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 173 ((si)->pub.buscoretype == PCI_CORE_ID)) 174 175 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 176 ((si)->pub.buscoretype == PCIE_CORE_ID)) 177 178 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 179 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 180 181 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 182 183 #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 184 185 /** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */ 186 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 187 188 #define CCREGS_FAST(si) \ 189 (((si)->curmap == NULL) ? NULL : \ 190 ((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 191 #define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 192 193 /* 194 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 195 * after core switching to avoid invalid register accesss inside ISR. 196 */ 197 #define INTR_OFF(si, intr_val) \ 198 if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 199 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 200 #define INTR_RESTORE(si, intr_val) \ 201 if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \ 202 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 203 204 /* dynamic clock control defines */ 205 #define LPOMINFREQ 25000 /**< low power oscillator min */ 206 #define LPOMAXFREQ 43000 /**< low power oscillator max */ 207 #define XTALMINFREQ 19800000 /**< 20 MHz - 1% */ 208 #define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */ 209 #define PCIMINFREQ 25000000 /**< 25 MHz */ 210 #define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */ 211 212 #define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */ 213 #define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */ 214 215 /* GPIO Based LED powersave defines */ 216 #define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */ 217 #define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */ 218 219 #ifndef DEFAULT_GPIOTIMERVAL 220 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 221 #endif 222 223 /* Silicon Backplane externs */ 224 extern void sb_scan(si_t *sih, volatile void *regs, uint devid); 225 extern uint sb_coreid(si_t *sih); 226 extern uint sb_intflag(si_t *sih); 227 extern uint sb_flag(si_t *sih); 228 extern void sb_setint(si_t *sih, int siflag); 229 extern uint sb_corevendor(si_t *sih); 230 extern uint sb_corerev(si_t *sih); 231 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 232 extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff); 233 extern bool sb_iscoreup(si_t *sih); 234 extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx); 235 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 236 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 237 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 238 extern void sb_commit(si_t *sih); 239 extern uint32 sb_base(uint32 admatch); 240 extern uint32 sb_size(uint32 admatch); 241 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 242 extern void sb_core_disable(si_t *sih, uint32 bits); 243 extern uint32 sb_addrspace(si_t *sih, uint asidx); 244 extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 245 extern int sb_numaddrspaces(si_t *sih); 246 247 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 248 249 extern bool sb_taclear(si_t *sih, bool details); 250 251 #if defined(BCMDBG_PHYDUMP) 252 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 253 #endif 254 255 /* Wake-on-wireless-LAN (WOWL) */ 256 extern bool sb_pci_pmecap(si_t *sih); 257 struct osl_info; 258 extern bool sb_pci_fastpmecap(struct osl_info *osh); 259 extern bool sb_pci_pmeclr(si_t *sih); 260 extern void sb_pci_pmeen(si_t *sih); 261 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 262 263 /* AMBA Interconnect exported externs */ 264 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 265 void *sdh, char **vars, uint *varsz); 266 extern si_t *ai_kattach(osl_t *osh); 267 extern void ai_scan(si_t *sih, void *regs, uint devid); 268 269 extern uint ai_flag(si_t *sih); 270 extern uint ai_flag_alt(si_t *sih); 271 extern void ai_setint(si_t *sih, int siflag); 272 extern uint ai_coreidx(si_t *sih); 273 extern uint ai_corevendor(si_t *sih); 274 extern uint ai_corerev(si_t *sih); 275 extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff); 276 extern bool ai_iscoreup(si_t *sih); 277 extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx); 278 extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx); 279 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 280 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 281 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 282 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 283 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 284 extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits, 285 uint32 resetbits, void *p, void *s); 286 extern void ai_core_disable(si_t *sih, uint32 bits); 287 extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits, 288 aidmp_t *pmacai, aidmp_t *smacai); 289 extern int ai_numaddrspaces(si_t *sih); 290 extern uint32 ai_addrspace(si_t *sih, uint asidx); 291 extern uint32 ai_addrspacesize(si_t *sih, uint asidx); 292 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 293 extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 294 extern void ai_enable_backplane_timeouts(si_t *sih); 295 extern uint32 ai_clear_backplane_to(si_t *sih); 296 extern uint ai_num_slaveports(si_t *sih, uint coreidx); 297 298 #ifdef BCM_BACKPLANE_TIMEOUT 299 uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr); 300 #endif /* BCM_BACKPLANE_TIMEOUT */ 301 302 #if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT) 303 extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap); 304 #endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */ 305 306 #if defined(BCMDBG_PHYDUMP) 307 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 308 #endif 309 310 extern uint32 ai_wrapper_dump_buf_size(si_t *sih); 311 extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p); 312 313 #define ub_scan(a, b, c) do {} while (0) 314 #define ub_flag(a) (0) 315 #define ub_setint(a, b) do {} while (0) 316 #define ub_coreidx(a) (0) 317 #define ub_corevendor(a) (0) 318 #define ub_corerev(a) (0) 319 #define ub_iscoreup(a) (0) 320 #define ub_setcoreidx(a, b) (0) 321 #define ub_core_cflags(a, b, c) (0) 322 #define ub_core_cflags_wo(a, b, c) do {} while (0) 323 #define ub_core_sflags(a, b, c) (0) 324 #define ub_corereg(a, b, c, d, e) (0) 325 #define ub_core_reset(a, b, c) do {} while (0) 326 #define ub_core_disable(a, b) do {} while (0) 327 #define ub_numaddrspaces(a) (0) 328 #define ub_addrspace(a, b) (0) 329 #define ub_addrspacesize(a, b) (0) 330 #define ub_view(a, b) do {} while (0) 331 #define ub_dumpregs(a, b) do {} while (0) 332 333 #endif /* _siutils_priv_h_ */ 334