1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 /*
3 * Copyright(c) 2012-2016 Allwinnertech Co., Ltd.
4 * Author: huangshuosheng <huangshuosheng@allwinnertech.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/pinctrl/pinctrl.h>
12
13 #include "pinctrl-sunxi.h"
14
15 static const struct sunxi_desc_pin sun50iw10p1_pins[] = {
16 //Register Name: PB_CFG0
17 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
18 SUNXI_FUNCTION(0x0, "gpio_in"),
19 SUNXI_FUNCTION(0x1, "gpio_out"),
20 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
21 SUNXI_FUNCTION(0x3, "spi2"), /* CS */
22 SUNXI_FUNCTION(0x4, "jtag"), /* MS */
23 SUNXI_FUNCTION(0x5, "test"), /* For Test */
24 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0),
25 SUNXI_FUNCTION(0x7, "io_disabled")),
26 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
27 SUNXI_FUNCTION(0x0, "gpio_in"),
28 SUNXI_FUNCTION(0x1, "gpio_out"),
29 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
30 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
31 SUNXI_FUNCTION(0x4, "jtag"), /* CK */
32 SUNXI_FUNCTION(0x5, "test"), /* For Test */
33 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1),
34 SUNXI_FUNCTION(0x7, "io_disabled")),
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
39 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
40 SUNXI_FUNCTION(0x4, "jtag"), /* DO */
41 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2),
42 SUNXI_FUNCTION(0x7, "io_disabled")),
43 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
47 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
48 SUNXI_FUNCTION(0x4, "jtag"), /* DI */
49 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3),
50 SUNXI_FUNCTION(0x7, "io_disabled")),
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
52 SUNXI_FUNCTION(0x0, "gpio_in"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
54 SUNXI_FUNCTION(0x2, "twi1"), /* SCK */
55 SUNXI_FUNCTION(0x3, "h_i2s0"), /* MCLK */
56 SUNXI_FUNCTION(0x4, "jtag"), /* MS_GPU */
57 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4),
58 SUNXI_FUNCTION(0x7, "io_disabled")),
59 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
60 SUNXI_FUNCTION(0x0, "gpio_in"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
62 SUNXI_FUNCTION(0x2, "twi1"), /* SDA */
63 SUNXI_FUNCTION(0x3, "h_i2s0"), /* BCLK */
64 SUNXI_FUNCTION(0x4, "jtag"), /* CK_GPU */
65 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5),
66 SUNXI_FUNCTION(0x7, "io_disabled")),
67 /* for spdif */
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "spdif"),
72 SUNXI_FUNCTION(0x3, "h_i2s0"), /* LRCK */
73 SUNXI_FUNCTION(0x4, "jtag"), /* DO_GPU */
74 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6),
75 SUNXI_FUNCTION(0x7, "io_disabled")),
76 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), /* spdif */
77 SUNXI_FUNCTION(0x0, "gpio_in"),
78 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x2, "spdif"), /* DIN */
80 SUNXI_FUNCTION(0x3, "h_i2s0"), /* DOUT0 */
81 SUNXI_FUNCTION(0x4, "h_i2s0"), /* DIN1 */
82 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7),
83 SUNXI_FUNCTION(0x7, "io_disabled")),
84 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
85 SUNXI_FUNCTION(0x0, "gpio_in"),
86 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x2, "spdif"), /* DOUT */
88 SUNXI_FUNCTION(0x3, "h_i2s0"), /* DIN0 */
89 SUNXI_FUNCTION(0x4, "h_i2s0"), /* DOUT1 */
90 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8),
91 SUNXI_FUNCTION(0x7, "io_disabled")),
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
96 SUNXI_FUNCTION(0x3, "twi0"), /* SCK */
97 SUNXI_FUNCTION(0x4, "jtag"), /* DI_GPU */
98 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9),
99 SUNXI_FUNCTION(0x7, "io_disabled")),
100 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
101 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out"),
103 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
104 SUNXI_FUNCTION(0x3, "twi0"), /* SDA */
105 SUNXI_FUNCTION(0x4, "pwm1"),
106 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10),
107 SUNXI_FUNCTION(0x7, "io_disabled")),
108 /* HOLE */
109 //Register Name: PC_CFG0
110 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
111 SUNXI_FUNCTION(0x0, "gpio_in"),
112 SUNXI_FUNCTION(0x1, "gpio_out"),
113 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
114 SUNXI_FUNCTION(0x3, "sdc2"), /* DS */
115 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0), /* PC_EINT0 */
116 SUNXI_FUNCTION(0x7, "io_disabled")),
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
121 SUNXI_FUNCTION(0x3, "sdc2"), /* RST */
122 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1), /* PC_EINT1 */
123 SUNXI_FUNCTION(0x7, "io_disabled")),
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
128 SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
129 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2), /* PC_EINT2 */
130 SUNXI_FUNCTION(0x7, "io_disabled")),
131 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
132 SUNXI_FUNCTION(0x0, "gpio_in"),
133 SUNXI_FUNCTION(0x1, "gpio_out"),
134 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
135 SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
136 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3), /* PC_EINT3 */
137 SUNXI_FUNCTION(0x7, "io_disabled")),
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
142 SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
143 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4), /* PC_EINT4 */
144 SUNXI_FUNCTION(0x7, "io_disabled")),
145 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
149 SUNXI_FUNCTION(0x3, "sdc2"), /* CLK */
150 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5), /* PC_EINT5 */
151 SUNXI_FUNCTION(0x7, "io_disabled")),
152 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
153 SUNXI_FUNCTION(0x0, "gpio_in"),
154 SUNXI_FUNCTION(0x1, "gpio_out"),
155 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
156 SUNXI_FUNCTION(0x3, "sdc2"), /* CMD */
157 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6), /* PC_EINT6 */
158 SUNXI_FUNCTION(0x7, "io_disabled")),
159 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
160 SUNXI_FUNCTION(0x0, "gpio_in"),
161 SUNXI_FUNCTION(0x1, "gpio_out"),
162 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
163 SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
164 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7), /* PC_EINT7 */
165 SUNXI_FUNCTION(0x7, "io_disabled")),
166 //Register Name: PC_CFG1
167 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
171 SUNXI_FUNCTION(0x3, "sdc2"), /* D3 */
172 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8), /* PC_EINT8 */
173 SUNXI_FUNCTION(0x7, "io_disabled")),
174 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
175 SUNXI_FUNCTION(0x0, "gpio_in"),
176 SUNXI_FUNCTION(0x1, "gpio_out"),
177 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
178 SUNXI_FUNCTION(0x3, "sdc2"), /* D4 */
179 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9), /* PC_EINT9 */
180 SUNXI_FUNCTION(0x7, "io_disabled")),
181 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
182 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out"),
184 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
185 SUNXI_FUNCTION(0x3, "sdc2"), /* D0 */
186 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10), /* PC_EINT10 */
187 SUNXI_FUNCTION(0x7, "io_disabled")),
188 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
189 SUNXI_FUNCTION(0x0, "gpio_in"),
190 SUNXI_FUNCTION(0x1, "gpio_out"),
191 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
192 SUNXI_FUNCTION(0x3, "sdc2"), /* D5 */
193 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11), /* PC_EINT11 */
194 SUNXI_FUNCTION(0x7, "io_disabled")),
195 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
199 SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
200 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12), /* PC_EINT12 */
201 SUNXI_FUNCTION(0x7, "io_disabled")),
202 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
203 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out"),
205 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
206 SUNXI_FUNCTION(0x3, "sdc2"), /* D1 */
207 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13), /* PC_EINT13 */
208 SUNXI_FUNCTION(0x7, "io_disabled")),
209 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
210 SUNXI_FUNCTION(0x0, "gpio_in"),
211 SUNXI_FUNCTION(0x1, "gpio_out"),
212 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
213 SUNXI_FUNCTION(0x3, "sdc2"), /* D6 */
214 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14), /* PC_EINT14 */
215 SUNXI_FUNCTION(0x7, "io_disabled")),
216 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
217 SUNXI_FUNCTION(0x0, "gpio_in"),
218 SUNXI_FUNCTION(0x1, "gpio_out"),
219 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
220 SUNXI_FUNCTION(0x3, "sdc2"), /* D2 */
221 SUNXI_FUNCTION(0x4, "spi0"), /* WP */
222 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15), /* PC_EINT15 */
223 SUNXI_FUNCTION(0x7, "io_disabled")),
224 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
225 SUNXI_FUNCTION(0x0, "gpio_in"),
226 SUNXI_FUNCTION(0x1, "gpio_out"),
227 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
228 SUNXI_FUNCTION(0x3, "sdc2"), /* D7 */
229 SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
230 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16), /* PC_EINT16 */
231 SUNXI_FUNCTION(0x7, "io_disabled")),
232
233 /* HOLE */
234 //Register Name: PD_CFG0
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
239 SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
240 SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */
241 SUNXI_FUNCTION(0x5, "eink"), /* D0 */
242 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0), /* PD_EINT0 */
243 SUNXI_FUNCTION(0x7, "io_disabled")),
244 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
245 SUNXI_FUNCTION(0x0, "gpio_in"),
246 SUNXI_FUNCTION(0x1, "gpio_out"),
247 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
248 SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
249 SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */
250 SUNXI_FUNCTION(0x5, "eink"), /* D1 */
251 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1), /* PD_EINT1 */
252 SUNXI_FUNCTION(0x7, "io_disabled")),
253 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
254 SUNXI_FUNCTION(0x0, "gpio_in"),
255 SUNXI_FUNCTION(0x1, "gpio_out"),
256 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
257 SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
258 SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */
259 SUNXI_FUNCTION(0x5, "eink"), /* D2 */
260 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2), /* PD_EINT2 */
261 SUNXI_FUNCTION(0x7, "io_disabled")),
262 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
266 SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
267 SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */
268 SUNXI_FUNCTION(0x5, "eink"), /* D3 */
269 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3), /* PD_EINT3 */
270 SUNXI_FUNCTION(0x7, "io_disabled")),
271 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
272 SUNXI_FUNCTION(0x0, "gpio_in"),
273 SUNXI_FUNCTION(0x1, "gpio_out"),
274 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
275 SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
276 SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */
277 SUNXI_FUNCTION(0x5, "eink"), /* D4 */
278 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4), /* PD_EINT4 */
279 SUNXI_FUNCTION(0x7, "io_disabled")),
280 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
284 SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
285 SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */
286 SUNXI_FUNCTION(0x5, "eink"), /* D5 */
287 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5), /* PD_EINT5 */
288 SUNXI_FUNCTION(0x7, "io_disabled")),
289 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
293 SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
294 SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */
295 SUNXI_FUNCTION(0x5, "eink"), /* D6 */
296 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6), /* PD_EINT6 */
297 SUNXI_FUNCTION(0x7, "io_disabled")),
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
302 SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
303 SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */
304 SUNXI_FUNCTION(0x5, "eink"), /* D7 */
305 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7), /* PD_EINT7 */
306 SUNXI_FUNCTION(0x7, "io_disabled")),
307 //Register Name: PD_CFG1
308 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
309 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out"),
311 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
312 SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
313 SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
314 SUNXI_FUNCTION(0x5, "eink"), /* D8 */
315 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8), /* PD_EINT8 */
316 SUNXI_FUNCTION(0x7, "io_disabled")),
317 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
318 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
321 SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
322 SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
323 SUNXI_FUNCTION(0x5, "eink"), /* D9 */
324 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9), /* PD_EINT9 */
325 SUNXI_FUNCTION(0x7, "io_disabled")),
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
330 SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */
331 SUNXI_FUNCTION(0x4, "spi1"), /* CS */
332 SUNXI_FUNCTION(0x5, "eink"), /* D10 */
333 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10), /* PD_EINT10 */
334 SUNXI_FUNCTION(0x7, "io_disabled")),
335 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
336 SUNXI_FUNCTION(0x0, "gpio_in"),
337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
339 SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */
340 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
341 SUNXI_FUNCTION(0x5, "eink"), /* D11 */
342 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11), /* PD_EINT11 */
343 SUNXI_FUNCTION(0x7, "io_disabled")),
344 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
345 SUNXI_FUNCTION(0x0, "gpio_in"),
346 SUNXI_FUNCTION(0x1, "gpio_out"),
347 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
348 SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */
349 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
350 SUNXI_FUNCTION(0x5, "eink"), /* D12 */
351 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12), /* PD_EINT12 */
352 SUNXI_FUNCTION(0x7, "io_disabled")),
353 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
354 SUNXI_FUNCTION(0x0, "gpio_in"),
355 SUNXI_FUNCTION(0x1, "gpio_out"),
356 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
357 SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */
358 SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
359 SUNXI_FUNCTION(0x5, "eink"), /* D13 */
360 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13), /* PD_EINT13 */
361 SUNXI_FUNCTION(0x7, "io_disabled")),
362 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
363 SUNXI_FUNCTION(0x0, "gpio_in"),
364 SUNXI_FUNCTION(0x1, "gpio_out"),
365 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
366 SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */
367 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
368 SUNXI_FUNCTION(0x5, "eink"), /* D14 */
369 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14), /* PD_EINT14 */
370 SUNXI_FUNCTION(0x7, "io_disabled")),
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
375 SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */
376 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
377 SUNXI_FUNCTION(0x5, "eink"), /* D15 */
378 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15), /* PD_EINT15 */
379 SUNXI_FUNCTION(0x7, "io_disabled")),
380 //Register Name: PD_CFG2
381 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
385 SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */
386 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
387 SUNXI_FUNCTION(0x5, "eink"), /* OEH */
388 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16), /* PD_EINT16 */
389 SUNXI_FUNCTION(0x7, "io_disabled")),
390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
394 SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */
395 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
396 SUNXI_FUNCTION(0x5, "eink"), /* LEH */
397 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17), /* PD_EINT17 */
398 SUNXI_FUNCTION(0x7, "io_disabled")),
399 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
400 SUNXI_FUNCTION(0x0, "gpio_in"),
401 SUNXI_FUNCTION(0x1, "gpio_out"),
402 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
403 SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */
404 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
405 SUNXI_FUNCTION(0x5, "eink"), /* CKH */
406 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18), /* PD_EINT18 */
407 SUNXI_FUNCTION(0x7, "io_disabled")),
408 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
409 SUNXI_FUNCTION(0x0, "gpio_in"),
410 SUNXI_FUNCTION(0x1, "gpio_out"),
411 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
412 SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */
413 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
414 SUNXI_FUNCTION(0x5, "eink"), /* CKH */
415 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19), /* PD_EINT19 */
416 SUNXI_FUNCTION(0x7, "io_disabled")),
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
421 SUNXI_FUNCTION(0x3, "pwm2"), /* PWM */
422 SUNXI_FUNCTION(0x4, "uart4"), /* RTS */
423 SUNXI_FUNCTION(0x5, "eink"), /* CKV */
424 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20), /* PD_EINT20 */
425 SUNXI_FUNCTION(0x7, "io_disabled")),
426 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
427 SUNXI_FUNCTION(0x0, "gpio_in"),
428 SUNXI_FUNCTION(0x1, "gpio_out"),
429 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
430 SUNXI_FUNCTION(0x3, "pwm3"), /* PWM */
431 SUNXI_FUNCTION(0x4, "uart4"), /* CTS */
432 SUNXI_FUNCTION(0x5, "eink"), /* MODE */
433 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21), /* PD_EINT21 */
434 SUNXI_FUNCTION(0x7, "io_disabled")),
435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "pwm1"), /* PWM */
439 SUNXI_FUNCTION(0x4, "twi0"), /* SCK */
440 SUNXI_FUNCTION(0x5, "eink"), /* STV */
441 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22), /* PD_EINT22 */
442 SUNXI_FUNCTION(0x7, "io_disabled")),
443 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
444 SUNXI_FUNCTION(0x0, "gpio_in"),
445 SUNXI_FUNCTION(0x1, "gpio_out"),
446 SUNXI_FUNCTION(0x2, "pwm0"), /* PWM */
447 SUNXI_FUNCTION(0x4, "twi0"), /* SDA */
448 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23), /* PD_EINT23 */
449 SUNXI_FUNCTION(0x7, "io_disabled")),
450
451 /* HOLE */
452 //Register Name: PE_CFG0
453 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
454 SUNXI_FUNCTION(0x0, "gpio_in"),
455 SUNXI_FUNCTION(0x1, "gpio_out"),
456 SUNXI_FUNCTION(0x2, "csi_mclk0"), /* MCLK */
457 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0), /* PE_EINT0 */
458 SUNXI_FUNCTION(0x7, "io_disabled")),
459 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
460 SUNXI_FUNCTION(0x0, "gpio_in"),
461 SUNXI_FUNCTION(0x1, "gpio_out"),
462 SUNXI_FUNCTION(0x2, "twi2"), /* SCK */
463 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1), /* PE_EINT1 */
464 SUNXI_FUNCTION(0x7, "io_disabled")),
465 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "twi2"), /* SDA */
469 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2), /* PE_EINT2 */
470 SUNXI_FUNCTION(0x7, "io_disabled")),
471 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
472 SUNXI_FUNCTION(0x0, "gpio_in"),
473 SUNXI_FUNCTION(0x1, "gpio_out"),
474 SUNXI_FUNCTION(0x2, "twi3"), /* SCK */
475 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3), /* PE_EINT3 */
476 SUNXI_FUNCTION(0x7, "io_disabled")),
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "twi3"), /* SDA */
481 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4), /* PE_EINT4 */
482 SUNXI_FUNCTION(0x7, "io_disabled")),
483 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
484 SUNXI_FUNCTION(0x0, "gpio_in"),
485 SUNXI_FUNCTION(0x1, "gpio_out"),
486 SUNXI_FUNCTION(0x2, "csi_mclk1"), /* MCLK */
487 SUNXI_FUNCTION(0x3, "pll0"), /* LOCK_DBG */
488 SUNXI_FUNCTION(0x4, "h_i2s2"), /* MCLK */
489 SUNXI_FUNCTION(0x5, "ledc"), /* LEDC */
490 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5), /* PE_EINT5 */
491 SUNXI_FUNCTION(0x7, "io_disabled")),
492 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
493 SUNXI_FUNCTION(0x0, "gpio_in"),
494 SUNXI_FUNCTION(0x1, "gpio_out"),
495 SUNXI_FUNCTION(0x3, "bist0"), /* RESULT0 */
496 SUNXI_FUNCTION(0x4, "h_i2s2"), /* BCLK */
497 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6), /* PE_EINT6 */
498 SUNXI_FUNCTION(0x7, "io_disabled")),
499 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
500 SUNXI_FUNCTION(0x0, "gpio_in"),
501 SUNXI_FUNCTION(0x1, "gpio_out"),
502 SUNXI_FUNCTION(0x2, "csi1"), /* SM_VS */
503 SUNXI_FUNCTION(0x3, "bist0"), /* RESULT1 */
504 SUNXI_FUNCTION(0x4, "h_i2s2"), /* LRCK */
505 SUNXI_FUNCTION(0x5, "tcon0"), /* TRIG */
506 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7), /* PE_EINT7 */
507 SUNXI_FUNCTION(0x7, "io_disabled")),
508 //Register Name: PE_CFG1
509 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
510 SUNXI_FUNCTION(0x0, "gpio_in"),
511 SUNXI_FUNCTION(0x1, "gpio_out"),
512 SUNXI_FUNCTION(0x3, "bist0"), /* RESULT2 */
513 SUNXI_FUNCTION(0x4, "h_i2s2"), /* DOUT0 */
514 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8), /* PE_EINT8 */
515 SUNXI_FUNCTION(0x7, "io_disabled")),
516 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x3, "bist0"), /* RESULT3 */
520 SUNXI_FUNCTION(0x4, "h_i2s2"), /* DIN0 */
521 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9), /* PE_EINT9 */
522 SUNXI_FUNCTION(0x7, "io_disabled")),
523
524 /* HOLE */
525 //Register Name: PF_CFG0
526 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
527 SUNXI_FUNCTION(0x0, "gpio_in"),
528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "sdc0"), /* D1 */
530 SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */
531 SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */
532 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0), /* PF_EINT0 */
533 SUNXI_FUNCTION(0x7, "io_disabled")),
534 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
535 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out"),
537 SUNXI_FUNCTION(0x2, "sdc0"), /* D0 */
538 SUNXI_FUNCTION(0x3, "jtag"), /* DI1 */
539 SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */
540 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1), /* PF_EINT1 */
541 SUNXI_FUNCTION(0x7, "io_disabled")),
542 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
543 SUNXI_FUNCTION(0x0, "gpio_in"),
544 SUNXI_FUNCTION(0x1, "gpio_out"),
545 SUNXI_FUNCTION(0x2, "sdc0"), /* CLK */
546 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
547 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2), /* PF_EINT2 */
548 SUNXI_FUNCTION(0x7, "io_disabled")),
549 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
550 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out"),
552 SUNXI_FUNCTION(0x2, "sdc0"), /* CMD */
553 SUNXI_FUNCTION(0x3, "jtag"), /* DO1 */
554 SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */
555 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3), /* PF_EINT3 */
556 SUNXI_FUNCTION(0x7, "io_disabled")),
557 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "sdc0"), /* D3 */
561 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
562 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4), /* PF_EINT4 */
563 SUNXI_FUNCTION(0x7, "io_disabled")),
564 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
565 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out"),
567 SUNXI_FUNCTION(0x2, "sdc0"), /* D2 */
568 SUNXI_FUNCTION(0x3, "jtag"), /* CK1 */
569 SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */
570 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5), /* PF_EINT5 */
571 SUNXI_FUNCTION(0x7, "io_disabled")),
572 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
573 SUNXI_FUNCTION(0x0, "gpio_in"),
574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6), /* PF_EINT6 */
576 SUNXI_FUNCTION(0x7, "io_disabled")),
577 /* HOLE */
578 //Register Name: PG_CFG0
579 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
580 SUNXI_FUNCTION(0x0, "gpio_in"),
581 SUNXI_FUNCTION(0x1, "gpio_out"),
582 SUNXI_FUNCTION(0x2, "sdc1"), /* CLK */
583 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0), /* PG_EINT0 */
584 SUNXI_FUNCTION(0x7, "io_disabled")),
585 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
586 SUNXI_FUNCTION(0x0, "gpio_in"),
587 SUNXI_FUNCTION(0x1, "gpio_out"),
588 SUNXI_FUNCTION(0x2, "sdc1"), /* CMD */
589 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1), /* PG_EINT1 */
590 SUNXI_FUNCTION(0x7, "io_disabled")),
591 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
592 SUNXI_FUNCTION(0x0, "gpio_in"),
593 SUNXI_FUNCTION(0x1, "gpio_out"),
594 SUNXI_FUNCTION(0x2, "sdc1"), /* D0 */
595 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2), /* PG_EINT2 */
596 SUNXI_FUNCTION(0x7, "io_disabled")),
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "sdc1"), /* D1 */
601 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3), /* PG_EINT3 */
602 SUNXI_FUNCTION(0x7, "io_disabled")),
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */
607 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4), /* PG_EINT4 */
608 SUNXI_FUNCTION(0x7, "io_disabled")),
609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */
613 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5), /* PG_EINT5 */
614 SUNXI_FUNCTION(0x7, "io_disabled")),
615 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
616 SUNXI_FUNCTION(0x0, "gpio_in"),
617 SUNXI_FUNCTION(0x1, "gpio_out"),
618 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
619 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6), /* PG_EINT6 */
620 SUNXI_FUNCTION(0x7, "io_disabled")),
621 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
625 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7), /* PG_EINT7 */
626 SUNXI_FUNCTION(0x7, "io_disabled")),
627 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
628 SUNXI_FUNCTION(0x0, "gpio_in"),
629 SUNXI_FUNCTION(0x1, "gpio_out"),
630 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
631 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8), /* PG_EINT8 */
632 SUNXI_FUNCTION(0x7, "io_disabled")),
633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
634 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
637 SUNXI_FUNCTION(0x3, "h_i2s1"), /* MCLK */
638 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9), /* PG_EINT9 */
639 SUNXI_FUNCTION(0x7, "io_disabled")),
640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x3, "h_i2s1"), /* BCLK */
644 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10), /* PG_EINT10 */
645 SUNXI_FUNCTION(0x7, "io_disabled")),
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x3, "h_i2s1"), /* LRCK */
650 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11), /* PG_EINT11 */
651 SUNXI_FUNCTION(0x7, "io_disabled")),
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x3, "h_i2s1"), /* DOUT0 */
656 SUNXI_FUNCTION(0x4, "h_i2s1"), /* DIN1 */
657 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12), /* PG_EINT12 */
658 SUNXI_FUNCTION(0x7, "io_disabled")),
659 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
660 SUNXI_FUNCTION(0x0, "gpio_in"),
661 SUNXI_FUNCTION(0x1, "gpio_out"),
662 SUNXI_FUNCTION(0x3, "h_i2s1"), /* DIN0 */
663 SUNXI_FUNCTION(0x4, "h_i2s1"), /* DOUT1 */
664 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13), /* PG_EINT13 */
665 SUNXI_FUNCTION(0x7, "io_disabled")),
666
667 /* HOLE */
668 //Register Name: PH_CFG0
669 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
670 SUNXI_FUNCTION(0x0, "gpio_in"),
671 SUNXI_FUNCTION(0x1, "gpio_out"),
672 SUNXI_FUNCTION(0x2, "twi0"), /* SCK */
673 SUNXI_FUNCTION(0x5, "gmac0"), /* RXD1 */
674 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0),
675 SUNXI_FUNCTION(0x7, "io_disabled")),
676 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
677 SUNXI_FUNCTION(0x0, "gpio_in"),
678 SUNXI_FUNCTION(0x1, "gpio_out"),
679 SUNXI_FUNCTION(0x2, "twi0"), /* SDA */
680 SUNXI_FUNCTION(0x5, "gmac0"), /* RXD0 */
681 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1),
682 SUNXI_FUNCTION(0x7, "io_disabled")),
683 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
684 SUNXI_FUNCTION(0x0, "gpio_in"),
685 SUNXI_FUNCTION(0x1, "gpio_out"),
686 SUNXI_FUNCTION(0x2, "twi1"), /* SCK */
687 SUNXI_FUNCTION(0x3, "cpu"), /* CUR_W */
688 SUNXI_FUNCTION(0x5, "gmac0"), /* RXCTL */
689 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2),
690 SUNXI_FUNCTION(0x7, "io_disabled")),
691 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
692 SUNXI_FUNCTION(0x0, "gpio_in"),
693 SUNXI_FUNCTION(0x1, "gpio_out"),
694 SUNXI_FUNCTION(0x2, "twi1"), /* SDA */
695 SUNXI_FUNCTION(0x3, "ir0"), /* OUT */
696 SUNXI_FUNCTION(0x5, "gmac0"), /* CLKIN */
697 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3),
698 SUNXI_FUNCTION(0x7, "io_disabled")),
699 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
700 SUNXI_FUNCTION(0x0, "gpio_in"),
701 SUNXI_FUNCTION(0x1, "gpio_out"),
702 SUNXI_FUNCTION(0x2, "uart3"), /* TX */
703 SUNXI_FUNCTION(0x3, "spi1"), /* CS */
704 SUNXI_FUNCTION(0x4, "cpu"), /* CUR_W */
705 SUNXI_FUNCTION(0x5, "gmac0"), /* TXD1 */
706 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4),
707 SUNXI_FUNCTION(0x7, "io_disabled")),
708 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
709 SUNXI_FUNCTION(0x0, "gpio_in"),
710 SUNXI_FUNCTION(0x1, "gpio_out"),
711 SUNXI_FUNCTION(0x2, "uart3"), /* RX */
712 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
713 SUNXI_FUNCTION(0x4, "ledc"),
714 SUNXI_FUNCTION(0x5, "gmac0"), /* TXD0 */
715 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5),
716 SUNXI_FUNCTION(0x7, "io_disabled")),
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "uart3"), /* RTS */
721 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
722 SUNXI_FUNCTION(0x4, "spdif"), /* IN */
723 SUNXI_FUNCTION(0x5, "gmac0"), /* TXCK */
724 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6),
725 SUNXI_FUNCTION(0x7, "io_disabled")),
726 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
727 SUNXI_FUNCTION(0x0, "gpio_in"),
728 SUNXI_FUNCTION(0x1, "gpio_out"),
729 SUNXI_FUNCTION(0x2, "uart3"), /* CTS */
730 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
731 SUNXI_FUNCTION(0x4, "spdif"), /* OUT */
732 SUNXI_FUNCTION(0x5, "gmac0"), /* TXCTL */
733 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7),
734 SUNXI_FUNCTION(0x7, "io_disabled")),
735 //Register Name: PH_CFG1
736 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
737 SUNXI_FUNCTION(0x0, "gpio_in"),
738 SUNXI_FUNCTION(0x1, "gpio_out"),
739 SUNXI_FUNCTION(0x2, "dmic"), /* CLK */
740 SUNXI_FUNCTION(0x3, "spi2"), /* CS */
741 SUNXI_FUNCTION(0x4, "h_i2s2"), /* MCLK */
742 SUNXI_FUNCTION(0x5, "h_i2s2"), /* DIN2 */
743 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8),
744 SUNXI_FUNCTION(0x7, "io_disabled")),
745 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
746 SUNXI_FUNCTION(0x0, "gpio_in"),
747 SUNXI_FUNCTION(0x1, "gpio_out"),
748 SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */
749 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
750 SUNXI_FUNCTION(0x4, "h_i2s2"), /* BCLK */
751 SUNXI_FUNCTION(0x5, "gmac0"),
752 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9),
753 SUNXI_FUNCTION(0x7, "io_disabled")),
754 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
755 SUNXI_FUNCTION(0x0, "gpio_in"),
756 SUNXI_FUNCTION(0x1, "gpio_out"),
757 SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */
758 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
759 SUNXI_FUNCTION(0x4, "h_i2s2"), /* LRCK */
760 SUNXI_FUNCTION(0x5, "gmac0"),
761 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10),
762 SUNXI_FUNCTION(0x7, "io_disabled")),
763 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
764 SUNXI_FUNCTION(0x0, "gpio_in"),
765 SUNXI_FUNCTION(0x1, "gpio_out"),
766 SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */
767 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
768 SUNXI_FUNCTION(0x4, "h_i2s2"), /* DOUT0 */
769 SUNXI_FUNCTION(0x5, "h_i2s2"),
770 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11),
771 SUNXI_FUNCTION(0x7, "io_disabled")),
772 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
773 SUNXI_FUNCTION(0x0, "gpio_in"),
774 SUNXI_FUNCTION(0x1, "gpio_out"),
775 SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */
776 SUNXI_FUNCTION(0x3, "twi3"), /* SCK */
777 SUNXI_FUNCTION(0x4, "h_i2s2"), /* DIN0 */
778 SUNXI_FUNCTION(0x5, "h_i2s2"), /* DOUT1 */
779 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12),
780 SUNXI_FUNCTION(0x7, "io_disabled")),
781 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
782 SUNXI_FUNCTION(0x0, "gpio_in"),
783 SUNXI_FUNCTION(0x1, "gpio_out"),
784 SUNXI_FUNCTION(0x3, "twi3"), /* SCK */
785 SUNXI_FUNCTION(0x4, "h_i2s3"), /* MCLK */
786 SUNXI_FUNCTION(0x5, "gmac0"), /* 25 */
787 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13),
788 SUNXI_FUNCTION(0x7, "io_disabled")),
789 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
790 SUNXI_FUNCTION(0x0, "gpio_in"),
791 SUNXI_FUNCTION(0x1, "gpio_out"),
792 SUNXI_FUNCTION(0x4, "h_i2s3"), /* BCLK */
793 SUNXI_FUNCTION(0x5, "gmac0"), /* RXD3 */
794 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14),
795 SUNXI_FUNCTION(0x7, "io_disabled")),
796 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
797 SUNXI_FUNCTION(0x0, "gpio_in"),
798 SUNXI_FUNCTION(0x1, "gpio_out"),
799 SUNXI_FUNCTION(0x4, "h_i2s3"), /* LRCK */
800 SUNXI_FUNCTION(0x5, "gmac0"), /* RXD2 */
801 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15),
802 SUNXI_FUNCTION(0x7, "io_disabled")),
803 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
804 SUNXI_FUNCTION(0x0, "gpio_in"),
805 SUNXI_FUNCTION(0x1, "gpio_out"),
806 SUNXI_FUNCTION(0x3, "h_i2s3"), /* DOUT0 */
807 SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN1 */
808 SUNXI_FUNCTION(0x5, "gmac0"), /* RXCK */
809 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16),
810 SUNXI_FUNCTION(0x7, "io_disabled")),
811 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x3, "h_i2s3"), /* DOUT1 */
815 SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN0 */
816 SUNXI_FUNCTION(0x5, "gmac0"), /* TXD3 */
817 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17),
818 SUNXI_FUNCTION(0x7, "io_disabled")),
819 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
820 SUNXI_FUNCTION(0x0, "gpio_in"),
821 SUNXI_FUNCTION(0x1, "gpio_out"),
822 SUNXI_FUNCTION(0x2, "cir"), /* OUT */
823 SUNXI_FUNCTION(0x3, "h_i2s3"), /* DOUT2 */
824 SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN2 */
825 SUNXI_FUNCTION(0x5, "gmac0"), /* TXD2 */
826 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18),
827 SUNXI_FUNCTION(0x7, "io_disabled")),
828 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
829 SUNXI_FUNCTION(0x0, "gpio_in"),
830 SUNXI_FUNCTION(0x1, "gpio_out"),
831 SUNXI_FUNCTION(0x2, "cir"), /* IN */
832 SUNXI_FUNCTION(0x3, "h_i2s3"), /* DOUT3 */
833 SUNXI_FUNCTION(0x4, "h_i2s3"), /* DIN3 */
834 SUNXI_FUNCTION(0x5, "ledc"),
835 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19),
836 SUNXI_FUNCTION(0x7, "io_disabled")),
837
838 /* HOLE */
839 //Register Name: PI_CFG0
840 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
841 SUNXI_FUNCTION(0x0, "gpio_in"),
842 SUNXI_FUNCTION(0x1, "gpio_out"),
843 SUNXI_FUNCTION(0x2, "twi4"), /* SCK */
844 SUNXI_FUNCTION(0x3, "uart4"), /* TX */
845 SUNXI_FUNCTION(0x4, "pwm1"),
846 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0),
847 SUNXI_FUNCTION(0x7, "io_disabled")),
848 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
849 SUNXI_FUNCTION(0x0, "gpio_in"),
850 SUNXI_FUNCTION(0x1, "gpio_out"),
851 SUNXI_FUNCTION(0x2, "twi4"), /* SDA */
852 SUNXI_FUNCTION(0x3, "uart4"), /* RX */
853 SUNXI_FUNCTION(0x4, "pwm2"),
854 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1),
855 SUNXI_FUNCTION(0x7, "io_disabled")),
856 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
857 SUNXI_FUNCTION(0x0, "gpio_in"),
858 SUNXI_FUNCTION(0x1, "gpio_out"),
859 SUNXI_FUNCTION(0x2, "uart5"), /* TX */
860 SUNXI_FUNCTION(0x3, "spi1"), /* CS */
861 SUNXI_FUNCTION(0x4, "pwm3"),
862 SUNXI_FUNCTION(0x5, "h_i2s2"), /* BCLK */
863 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2),
864 SUNXI_FUNCTION(0x7, "io_disabled")),
865 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
866 SUNXI_FUNCTION(0x0, "gpio_in"),
867 SUNXI_FUNCTION(0x1, "gpio_out"),
868 SUNXI_FUNCTION(0x2, "uart5"), /* RX */
869 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
870 SUNXI_FUNCTION(0x4, "pwm4"),
871 SUNXI_FUNCTION(0x5, "h_i2s2"), /* LRCK */
872 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3),
873 SUNXI_FUNCTION(0x7, "io_disabled")),
874 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
875 SUNXI_FUNCTION(0x0, "gpio_in"),
876 SUNXI_FUNCTION(0x1, "gpio_out"),
877 SUNXI_FUNCTION(0x2, "uart5"), /* RTS */
878 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
879 SUNXI_FUNCTION(0x4, "pwm5"),
880 SUNXI_FUNCTION(0x5, "h_i2s2"), /* DOUT0 */
881 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4),
882 SUNXI_FUNCTION(0x7, "io_disabled")),
883 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
884 SUNXI_FUNCTION(0x0, "gpio_in"),
885 SUNXI_FUNCTION(0x1, "gpio_out"),
886 SUNXI_FUNCTION(0x2, "uart5"), /* CTS */
887 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
888 SUNXI_FUNCTION(0x4, "pwm6"),
889 SUNXI_FUNCTION(0x5, "h_i2s2"), /* DIN0 */
890 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5),
891 SUNXI_FUNCTION(0x7, "io_disabled")),
892 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
893 SUNXI_FUNCTION(0x0, "gpio_in"),
894 SUNXI_FUNCTION(0x1, "gpio_out"),
895 SUNXI_FUNCTION(0x2, "uart6"), /* TX */
896 SUNXI_FUNCTION(0x4, "pwm7"),
897 SUNXI_FUNCTION(0x5, "spi2"), /* CS */
898 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6),
899 SUNXI_FUNCTION(0x7, "io_disabled")),
900 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out"),
903 SUNXI_FUNCTION(0x2, "uart6"), /* RX */
904 SUNXI_FUNCTION(0x4, "pwm8"),
905 SUNXI_FUNCTION(0x5, "spi2"), /* CLK */
906 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7),
907 SUNXI_FUNCTION(0x7, "io_disabled")),
908 //Register Name: PI_CFG1
909 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
910 SUNXI_FUNCTION(0x0, "gpio_in"),
911 SUNXI_FUNCTION(0x1, "gpio_out"),
912 SUNXI_FUNCTION(0x2, "twi5"), /* SCK */
913 SUNXI_FUNCTION(0x3, "cir"), /* IN */
914 SUNXI_FUNCTION(0x4, "pwm9"),
915 SUNXI_FUNCTION(0x5, "spi2"), /* MOSI */
916 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8),
917 SUNXI_FUNCTION(0x7, "io_disabled")),
918 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
919 SUNXI_FUNCTION(0x0, "gpio_in"),
920 SUNXI_FUNCTION(0x1, "gpio_out"),
921 SUNXI_FUNCTION(0x2, "twi5"), /* SDA */
922 SUNXI_FUNCTION(0x3, "sdc3"), /* CLK */
923 SUNXI_FUNCTION(0x4, "pwm10"),
924 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9),
925 SUNXI_FUNCTION(0x7, "io_disabled")),
926 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
927 SUNXI_FUNCTION(0x0, "gpio_in"),
928 SUNXI_FUNCTION(0x1, "gpio_out"),
929 SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
930 SUNXI_FUNCTION(0x3, "sdc3"), /* CMD */
931 SUNXI_FUNCTION(0x4, "pwm11"),
932 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10),
933 SUNXI_FUNCTION(0x7, "io_disabled")),
934 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
935 SUNXI_FUNCTION(0x0, "gpio_in"),
936 SUNXI_FUNCTION(0x1, "gpio_out"),
937 SUNXI_FUNCTION(0x2, "uart3"), /* TX */
938 SUNXI_FUNCTION(0x3, "sdc3"), /* DO */
939 SUNXI_FUNCTION(0x4, "pwm12"),
940 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11),
941 SUNXI_FUNCTION(0x7, "io_disabled")),
942 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
943 SUNXI_FUNCTION(0x0, "gpio_in"),
944 SUNXI_FUNCTION(0x1, "gpio_out"),
945 SUNXI_FUNCTION(0x2, "uart3"), /* RX */
946 SUNXI_FUNCTION(0x3, "sdc3"), /* D1 */
947 SUNXI_FUNCTION(0x4, "pwm13"),
948 SUNXI_FUNCTION(0x5, "spi2"), /* MISO */
949 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12),
950 SUNXI_FUNCTION(0x7, "io_disabled")),
951 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
952 SUNXI_FUNCTION(0x0, "gpio_in"),
953 SUNXI_FUNCTION(0x1, "gpio_out"),
954 SUNXI_FUNCTION(0x2, "uart6"), /* CTS */
955 SUNXI_FUNCTION(0x3, "sdc3"), /* D2 */
956 SUNXI_FUNCTION(0x4, "pwm14"),
957 SUNXI_FUNCTION(0x5, "h_i2s2"), /* MCLK */
958 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13),
959 SUNXI_FUNCTION(0x7, "io_disabled")),
960 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
961 SUNXI_FUNCTION(0x0, "gpio_in"),
962 SUNXI_FUNCTION(0x1, "gpio_out"),
963 SUNXI_FUNCTION(0x2, "uart6"), /* RTS */
964 SUNXI_FUNCTION(0x3, "sdc3"), /* D3 */
965 SUNXI_FUNCTION(0x4, "pwm15"),
966 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14),
967 SUNXI_FUNCTION(0x7, "io_disabled")),
968
969 /* HOLE */
970 //Register Name: PJ_CFG0
971 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 0),
972 SUNXI_FUNCTION(0x0, "gpio_in"),
973 SUNXI_FUNCTION(0x1, "gpio_out"),
974 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
975 SUNXI_FUNCTION(0x3, "lvds2"), /* DOP */
976 SUNXI_FUNCTION(0x4, "eink1"), /* D0 */
977 SUNXI_FUNCTION(0x5, "gmac1"), /* RXD1 */
978 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 0),
979 SUNXI_FUNCTION(0x7, "io_disabled")),
980 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 1),
981 SUNXI_FUNCTION(0x0, "gpio_in"),
982 SUNXI_FUNCTION(0x1, "gpio_out"),
983 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
984 SUNXI_FUNCTION(0x3, "lvds2"), /* DON */
985 SUNXI_FUNCTION(0x4, "eink1"), /* D1 */
986 SUNXI_FUNCTION(0x5, "gmac1"), /* RXD0 */
987 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 1),
988 SUNXI_FUNCTION(0x7, "io_disabled")),
989 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 2),
990 SUNXI_FUNCTION(0x0, "gpio_in"),
991 SUNXI_FUNCTION(0x1, "gpio_out"),
992 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
993 SUNXI_FUNCTION(0x3, "lvds2"), /* DIP */
994 SUNXI_FUNCTION(0x4, "eink1"), /* D2 */
995 SUNXI_FUNCTION(0x5, "gmac1"), /* RXCTL */
996 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 2),
997 SUNXI_FUNCTION(0x7, "io_disabled")),
998 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 3),
999 SUNXI_FUNCTION(0x0, "gpio_in"),
1000 SUNXI_FUNCTION(0x1, "gpio_out"),
1001 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
1002 SUNXI_FUNCTION(0x3, "lvds2"), /* D1N */
1003 SUNXI_FUNCTION(0x4, "eink1"), /* D3 */
1004 SUNXI_FUNCTION(0x5, "gmac1"), /* CLKIN */
1005 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 3),
1006 SUNXI_FUNCTION(0x7, "io_disabled")),
1007 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 4),
1008 SUNXI_FUNCTION(0x0, "gpio_in"),
1009 SUNXI_FUNCTION(0x1, "gpio_out"),
1010 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
1011 SUNXI_FUNCTION(0x3, "lvds2"), /* D2P */
1012 SUNXI_FUNCTION(0x4, "eink1"), /* D4 */
1013 SUNXI_FUNCTION(0x5, "gmac1"), /* TXD1 */
1014 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 4),
1015 SUNXI_FUNCTION(0x7, "io_disabled")),
1016 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 5),
1017 SUNXI_FUNCTION(0x0, "gpio_in"),
1018 SUNXI_FUNCTION(0x1, "gpio_out"),
1019 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
1020 SUNXI_FUNCTION(0x3, "lvds2"), /* D2N */
1021 SUNXI_FUNCTION(0x4, "eink1"), /* D5 */
1022 SUNXI_FUNCTION(0x5, "gmac1"), /* TXD0 */
1023 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 5),
1024 SUNXI_FUNCTION(0x7, "io_disabled")),
1025 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 6),
1026 SUNXI_FUNCTION(0x0, "gpio_in"),
1027 SUNXI_FUNCTION(0x1, "gpio_out"),
1028 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
1029 SUNXI_FUNCTION(0x3, "lvds2"), /* CKP */
1030 SUNXI_FUNCTION(0x4, "eink1"), /* D6 */
1031 SUNXI_FUNCTION(0x5, "gmac1"), /* TXCK */
1032 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 6),
1033 SUNXI_FUNCTION(0x7, "io_disabled")),
1034 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 7),
1035 SUNXI_FUNCTION(0x0, "gpio_in"),
1036 SUNXI_FUNCTION(0x1, "gpio_out"),
1037 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
1038 SUNXI_FUNCTION(0x3, "lvds2"), /* CKN */
1039 SUNXI_FUNCTION(0x4, "eink1"), /* D7 */
1040 SUNXI_FUNCTION(0x5, "gmac1"), /* TXCTL */
1041 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 7),
1042 SUNXI_FUNCTION(0x7, "io_disabled")),
1043 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 8),
1044 SUNXI_FUNCTION(0x0, "gpio_in"),
1045 SUNXI_FUNCTION(0x1, "gpio_out"),
1046 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
1047 SUNXI_FUNCTION(0x3, "lvds2"), /* D3P */
1048 SUNXI_FUNCTION(0x4, "eink1"), /* D8 */
1049 SUNXI_FUNCTION(0x5, "gmac1"),
1050 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 8),
1051 SUNXI_FUNCTION(0x7, "io_disabled")),
1052 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 9),
1053 SUNXI_FUNCTION(0x0, "gpio_in"),
1054 SUNXI_FUNCTION(0x1, "gpio_out"),
1055 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
1056 SUNXI_FUNCTION(0x3, "lvds2"), /* D3N */
1057 SUNXI_FUNCTION(0x4, "eink1"), /* D9 */
1058 SUNXI_FUNCTION(0x5, "gmac1"),
1059 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 9),
1060 SUNXI_FUNCTION(0x7, "io_disabled")),
1061 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 10),
1062 SUNXI_FUNCTION(0x0, "gpio_in"),
1063 SUNXI_FUNCTION(0x1, "gpio_out"),
1064 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
1065 SUNXI_FUNCTION(0x3, "lvds3"), /* D0P */
1066 SUNXI_FUNCTION(0x4, "eink1"), /* D10 */
1067 SUNXI_FUNCTION(0x5, "gmac1"),
1068 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 10),
1069 SUNXI_FUNCTION(0x7, "io_disabled")),
1070 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 11),
1071 SUNXI_FUNCTION(0x0, "gpio_in"),
1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
1074 SUNXI_FUNCTION(0x3, "lvds3"), /* D0N */
1075 SUNXI_FUNCTION(0x4, "eink1"), /* D11 */
1076 SUNXI_FUNCTION(0x5, "gmac1"), /* RXD3 */
1077 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 10),
1078 SUNXI_FUNCTION(0x7, "io_disabled")),
1079 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 12),
1080 SUNXI_FUNCTION(0x0, "gpio_in"),
1081 SUNXI_FUNCTION(0x1, "gpio_out"),
1082 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
1083 SUNXI_FUNCTION(0x3, "lvds3"), /* D1P */
1084 SUNXI_FUNCTION(0x4, "eink1"), /* D12 */
1085 SUNXI_FUNCTION(0x5, "gmac1"), /* RXD2 */
1086 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 12),
1087 SUNXI_FUNCTION(0x7, "io_disabled")),
1088 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 13),
1089 SUNXI_FUNCTION(0x0, "gpio_in"),
1090 SUNXI_FUNCTION(0x1, "gpio_out"),
1091 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
1092 SUNXI_FUNCTION(0x3, "lvds3"), /* D1N */
1093 SUNXI_FUNCTION(0x4, "eink1"), /* D13 */
1094 SUNXI_FUNCTION(0x5, "gmac1"), /* RXCK */
1095 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 13),
1096 SUNXI_FUNCTION(0x7, "io_disabled")),
1097 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 14),
1098 SUNXI_FUNCTION(0x0, "gpio_in"),
1099 SUNXI_FUNCTION(0x1, "gpio_out"),
1100 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
1101 SUNXI_FUNCTION(0x3, "lvds3"), /* D2P */
1102 SUNXI_FUNCTION(0x4, "eink1"), /* D14 */
1103 SUNXI_FUNCTION(0x5, "gmac1"), /* TXD3 */
1104 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 14),
1105 SUNXI_FUNCTION(0x7, "io_disabled")),
1106 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 15),
1107 SUNXI_FUNCTION(0x0, "gpio_in"),
1108 SUNXI_FUNCTION(0x1, "gpio_out"),
1109 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
1110 SUNXI_FUNCTION(0x3, "lvds3"), /* D2N */
1111 SUNXI_FUNCTION(0x4, "eink1"), /* D15 */
1112 SUNXI_FUNCTION(0x5, "gmac1"), /* TXD2 */
1113 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 15),
1114 SUNXI_FUNCTION(0x7, "io_disabled")),
1115 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 16),
1116 SUNXI_FUNCTION(0x0, "gpio_in"),
1117 SUNXI_FUNCTION(0x1, "gpio_out"),
1118 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
1119 SUNXI_FUNCTION(0x3, "lvds3"), /* CKP */
1120 SUNXI_FUNCTION(0x4, "spi1"), /* CS */
1121 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 16),
1122 SUNXI_FUNCTION(0x7, "io_disabled")),
1123 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 17),
1124 SUNXI_FUNCTION(0x0, "gpio_in"),
1125 SUNXI_FUNCTION(0x1, "gpio_out"),
1126 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
1127 SUNXI_FUNCTION(0x3, "lvds3"), /* CKN */
1128 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
1129 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 17),
1130 SUNXI_FUNCTION(0x7, "io_disabled")),
1131 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 18),
1132 SUNXI_FUNCTION(0x0, "gpio_in"),
1133 SUNXI_FUNCTION(0x1, "gpio_out"),
1134 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
1135 SUNXI_FUNCTION(0x3, "lvds3"), /* D3P */
1136 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
1137 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 18),
1138 SUNXI_FUNCTION(0x7, "io_disabled")),
1139 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 19),
1140 SUNXI_FUNCTION(0x0, "gpio_in"),
1141 SUNXI_FUNCTION(0x1, "gpio_out"),
1142 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
1143 SUNXI_FUNCTION(0x3, "lvds3"), /* D3N */
1144 SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
1145 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 19),
1146 SUNXI_FUNCTION(0x7, "io_disabled")),
1147 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 20),
1148 SUNXI_FUNCTION(0x0, "gpio_in"),
1149 SUNXI_FUNCTION(0x1, "gpio_out"),
1150 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
1151 SUNXI_FUNCTION(0x3, "spi2"), /* CS */
1152 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
1153 SUNXI_FUNCTION(0x5, "uart2"), /* TX */
1154 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 20),
1155 SUNXI_FUNCTION(0x7, "io_disabled")),
1156 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 21),
1157 SUNXI_FUNCTION(0x0, "gpio_in"),
1158 SUNXI_FUNCTION(0x1, "gpio_out"),
1159 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
1160 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
1161 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
1162 SUNXI_FUNCTION(0x5, "uart2"), /* RX */
1163 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 21),
1164 SUNXI_FUNCTION(0x7, "io_disabled")),
1165 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 22),
1166 SUNXI_FUNCTION(0x0, "gpio_in"),
1167 SUNXI_FUNCTION(0x1, "gpio_out"),
1168 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
1169 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
1170 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
1171 SUNXI_FUNCTION(0x5, "uart2"), /* RTS */
1172 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 22),
1173 SUNXI_FUNCTION(0x7, "io_disabled")),
1174 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 23),
1175 SUNXI_FUNCTION(0x0, "gpio_in"),
1176 SUNXI_FUNCTION(0x1, "gpio_out"),
1177 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
1178 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
1179 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
1180 SUNXI_FUNCTION(0x5, "uart2"), /* CTS */
1181 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 23),
1182 SUNXI_FUNCTION(0x7, "io_disabled")),
1183 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 24),
1184 SUNXI_FUNCTION(0x0, "gpio_in"),
1185 SUNXI_FUNCTION(0x1, "gpio_out"),
1186 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
1187 SUNXI_FUNCTION(0x3, "twi4"), /* SCK */
1188 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
1189 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 24),
1190 SUNXI_FUNCTION(0x7, "io_disabled")),
1191 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 25),
1192 SUNXI_FUNCTION(0x0, "gpio_in"),
1193 SUNXI_FUNCTION(0x1, "gpio_out"),
1194 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
1195 SUNXI_FUNCTION(0x3, "twi4"), /* SDA */
1196 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
1197 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 25),
1198 SUNXI_FUNCTION(0x7, "io_disabled")),
1199 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 26),
1200 SUNXI_FUNCTION(0x0, "gpio_in"),
1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
1203 SUNXI_FUNCTION(0x3, "twi5"), /* SCK */
1204 SUNXI_FUNCTION(0x4, "uart4"), /* RTS */
1205 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 26),
1206 SUNXI_FUNCTION(0x7, "io_disabled")),
1207 SUNXI_PIN(SUNXI_PINCTRL_PIN(J, 27),
1208 SUNXI_FUNCTION(0x0, "gpio_in"),
1209 SUNXI_FUNCTION(0x1, "gpio_out"),
1210 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
1211 SUNXI_FUNCTION(0x3, "twi5"), /* SDA */
1212 SUNXI_FUNCTION(0x4, "uart4"), /* CTS */
1213 SUNXI_FUNCTION_IRQ_BANK(0x6, 8, 27),
1214 SUNXI_FUNCTION(0x7, "io_disabled")),
1215 };
1216
1217 static const unsigned int sun50iw10p1_irq_bank_map[] = {
1218 SUNXI_BANK_OFFSET('B', 'A'),
1219 SUNXI_BANK_OFFSET('C', 'A'),
1220 SUNXI_BANK_OFFSET('D', 'A'),
1221 SUNXI_BANK_OFFSET('E', 'A'),
1222 SUNXI_BANK_OFFSET('F', 'A'),
1223 SUNXI_BANK_OFFSET('G', 'A'),
1224 SUNXI_BANK_OFFSET('H', 'A'),
1225 SUNXI_BANK_OFFSET('I', 'A'),
1226 SUNXI_BANK_OFFSET('J', 'A'),
1227 };
1228
1229 static const struct sunxi_pinctrl_desc sun50iw10p1_pinctrl_data = {
1230 .pins = sun50iw10p1_pins,
1231 .npins = ARRAY_SIZE(sun50iw10p1_pins),
1232 .irq_banks = ARRAY_SIZE(sun50iw10p1_irq_bank_map),
1233 .irq_bank_map = sun50iw10p1_irq_bank_map,
1234 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
1235 .pf_power_source_switch = true,
1236 .hw_type = SUNXI_PCTL_HW_TYPE_0,
1237 };
1238
1239 static void *mem;
1240 static int mem_size;
1241
sun50iw10p1_pinctrl_probe(struct platform_device * pdev)1242 static int sun50iw10p1_pinctrl_probe(struct platform_device *pdev)
1243 {
1244 struct resource *res;
1245
1246 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1247 if (!res)
1248 return -EINVAL;
1249 mem_size = resource_size(res);
1250
1251 mem = devm_kzalloc(&pdev->dev, mem_size, GFP_KERNEL);
1252 if (!mem)
1253 return -ENOMEM;
1254
1255 #if IS_ENABLED(CONFIG_PINCTRL_SUNXI_DEBUGFS)
1256 dev_set_name(&pdev->dev, "pio");
1257 #endif
1258
1259 return sunxi_bsp_pinctrl_init(pdev, &sun50iw10p1_pinctrl_data);
1260 }
1261
sun50iw10p1_pinctrl_suspend_noirq(struct device * dev)1262 static int __maybe_unused sun50iw10p1_pinctrl_suspend_noirq(struct device *dev)
1263 {
1264 struct sunxi_pinctrl *pctl = dev_get_drvdata(dev);
1265 unsigned long flags;
1266
1267 raw_spin_lock_irqsave(&pctl->lock, flags);
1268 memcpy(mem, pctl->membase, mem_size);
1269 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1270
1271 return 0;
1272 }
1273
sun50iw10p1_pinctrl_resume_noirq(struct device * dev)1274 static int __maybe_unused sun50iw10p1_pinctrl_resume_noirq(struct device *dev)
1275 {
1276 struct sunxi_pinctrl *pctl = dev_get_drvdata(dev);
1277 unsigned long flags;
1278
1279 raw_spin_lock_irqsave(&pctl->lock, flags);
1280 memcpy(pctl->membase, mem, mem_size);
1281 raw_spin_unlock_irqrestore(&pctl->lock, flags);
1282
1283 return 0;
1284 }
1285
1286 static struct of_device_id sun50iw10p1_pinctrl_match[] = {
1287 { .compatible = "allwinner,sun50iw10p1-pinctrl", },
1288 {}
1289 };
1290 MODULE_DEVICE_TABLE(of, sun50iw10p1_pinctrl_match);
1291
1292 static const struct dev_pm_ops sun50iw10p1_pinctrl_pm_ops = {
1293 .suspend_noirq = sun50iw10p1_pinctrl_suspend_noirq,
1294 .resume_noirq = sun50iw10p1_pinctrl_resume_noirq,
1295 };
1296
1297 static struct platform_driver sun50iw10p1_pinctrl_driver = {
1298 .probe = sun50iw10p1_pinctrl_probe,
1299 .driver = {
1300 .name = "sun50iw10p1-pinctrl",
1301 .pm = &sun50iw10p1_pinctrl_pm_ops,
1302 .of_match_table = sun50iw10p1_pinctrl_match,
1303 },
1304 };
1305
sun50iw10p1_pio_init(void)1306 static int __init sun50iw10p1_pio_init(void)
1307 {
1308 return platform_driver_register(&sun50iw10p1_pinctrl_driver);
1309 }
1310 postcore_initcall(sun50iw10p1_pio_init);
1311
1312 MODULE_AUTHOR("Huangshuosheng<huangshuosheng@allwinnertech.com>");
1313 MODULE_DESCRIPTION("Allwinner sun50iw10p1 pio pinctrl driver");
1314 MODULE_LICENSE("GPL");
1315 MODULE_VERSION("1.0.0");
1316