1 /*
2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-vipp/vipp_reg.c
3 *
4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
5 *
6 * Authors: Zhao Wei <zhaowei@allwinnertech.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19 #include <linux/kernel.h>
20 #include "vipp_reg_i.h"
21 #include "vipp_reg.h"
22
23 #include "../utility/vin_io.h"
24 #include "../platform/platform_cfg.h"
25
26 /*#define VIPP_SCALER_DIRECTLY_WRITE_REG*/
27 #define VIPP_ADDR_BIT_R_SHIFT 2
28
29 volatile void __iomem *vipp_base[VIN_MAX_SCALER];
30
31 struct vipp_reg {
32 VIPP_MODULE_EN_REG_t *vipp_module_en;
33 VIPP_SCALER_CFG_REG_t *vipp_scaler_cfg;
34 VIPP_SCALER_OUTPUT_SIZE_REG_t *vipp_scaler_output_size;
35 VIPP_OUTPUT_FMT_REG_t *vipp_output_fmt;
36 VIPP_OSD_CFG_REG_t *vipp_osd_cfg;
37 VIPP_OSD_RGB2YUV_GAIN0_REG_t *vipp_osd_rgb2yuv_gain0;
38 VIPP_OSD_RGB2YUV_GAIN1_REG_t *vipp_osd_rgb2yuv_gain1;
39 VIPP_OSD_RGB2YUV_GAIN2_REG_t *vipp_osd_rgb2yuv_gain2;
40 VIPP_OSD_RGB2YUV_GAIN3_REG_t *vipp_osd_rgb2yuv_gain3;
41 VIPP_OSD_RGB2YUV_GAIN4_REG_t *vipp_osd_rgb2yuv_gain4;
42 VIPP_OSD_RGB2YUV_OFFSET_REG_t *vipp_osd_rgb2yuv_offset;
43 VIPP_CROP_START_POSITION_REG_t *vipp_crop_start;
44 VIPP_CROP_SIZE_REG_t *vipp_crop_size;
45 #if defined CONFIG_ARCH_SUN8IW16P1 || defined CONFIG_ARCH_SUN8IW19P1
46 VIPP_OSD_REGION_REG_t *vipp_osd_ov_region;
47 VIPP_OSD_OV_ALPHA_CFG0_REG_t *vipp_osd_ov_alpha_cfg0;
48 VIPP_OSD_OV_ALPHA_CFG1_REG_t *vipp_osd_ov_alpha_cfg1;
49 VIPP_OSD_REGION_REG_t *vipp_osd_cv_region;
50 VIPP_OSD_CV_REGION_YUV_REG_t *vipp_osd_cv_region_yuv;
51 VIPP_OSD_INV_W_REG_t *vipp_osd_inv_w;
52 VIPP_OSD_INV_H_REG_t *vipp_osd_inv_h;
53 VIPP_ORL_CONTROL_REG_t *vipp_orl_control;
54 VIPP_ORL_START_REG_t *vipp_orl_start;
55 VIPP_ORL_END_REG_t *vipp_orl_end;
56 VIPP_ORL_YUV_REG_t *vipp_orl_yuv;
57 #endif
58 };
59 struct vipp_reg vipp_reg_load_addr[VIN_MAX_SCALER];
60
61 #if defined CONFIG_ARCH_SUN8IW12P1
62 struct vipp_osd_para {
63 VIPP_OSD_OVERLAY_CFG_REG_t *vipp_osd_overlay_cfg;
64 VIPP_OSD_COVER_CFG_REG_t *vipp_osd_cover_cfg;
65 VIPP_OSD_COVER_DATA_REG_t *vipp_osd_cover_data;
66 };
67 struct vipp_osd_para vipp_osd_para_load_addr[VIN_MAX_SCALER];
68 #endif
69
vipp_set_base_addr(unsigned int id,unsigned long addr)70 int vipp_set_base_addr(unsigned int id, unsigned long addr)
71 {
72 if (id > VIN_MAX_SCALER - 1)
73 return -1;
74 vipp_base[id] = (volatile void __iomem *)addr;
75
76 return 0;
77 }
78
79 /* open module */
80
vipp_top_clk_en(unsigned int id,unsigned int en)81 void vipp_top_clk_en(unsigned int id, unsigned int en)
82 {
83 vin_reg_clr_set(vipp_base[id] + VIPP_TOP_EN_REG_OFF,
84 VIPP_CLK_GATING_EN_MASK, en << VIPP_CLK_GATING_EN);
85 }
86
vipp_enable(unsigned int id)87 void vipp_enable(unsigned int id)
88 {
89 vin_reg_clr_set(vipp_base[id] + VIPP_EN_REG_OFF,
90 VIPP_EN_MASK, 1 << VIPP_EN);
91 }
92
vipp_disable(unsigned int id)93 void vipp_disable(unsigned int id)
94 {
95 vin_reg_clr_set(vipp_base[id] + VIPP_EN_REG_OFF,
96 VIPP_EN_MASK, 0 << VIPP_EN);
97 }
98
vipp_ver_en(unsigned int id,unsigned int en)99 void vipp_ver_en(unsigned int id, unsigned int en)
100 {
101 vin_reg_clr_set(vipp_base[id] + VIPP_EN_REG_OFF,
102 VIPP_VER_EN_MASK, en << VIPP_VER_EN);
103 }
104
vipp_version_get(unsigned int id,struct vipp_version * v)105 void vipp_version_get(unsigned int id, struct vipp_version *v)
106 {
107 unsigned int reg_val = vin_reg_readl(vipp_base[id] + VIPP_VER_REG_OFF);
108
109 v->ver_small = (reg_val & VIPP_SMALL_VER_MASK) >> VIPP_SMALL_VER;
110 v->ver_big = (reg_val & VIPP_BIG_VER_MASK) >> VIPP_BIG_VER;
111 }
112
vipp_feature_list_get(unsigned int id,struct vipp_feature_list * fl)113 void vipp_feature_list_get(unsigned int id, struct vipp_feature_list *fl)
114 {
115 unsigned int reg_val = vin_reg_readl(vipp_base[id] + VIPP_FEATURE_REG_OFF);
116
117 fl->osd_exit = (reg_val & VIPP_OSD_EXIST_MASK) >> VIPP_OSD_EXIST;
118 fl->yuv422to420 = (reg_val & VIPP_YUV422TO420_MASK) >> VIPP_YUV422TO420;
119 }
120
vipp_set_para_ready(unsigned int id,enum vipp_ready_flag flag)121 void vipp_set_para_ready(unsigned int id, enum vipp_ready_flag flag)
122 {
123 #ifndef VIPP_SCALER_DIRECTLY_WRITE_REG
124 vin_reg_clr_set(vipp_base[id] + VIPP_CTRL_REG_OFF,
125 VIPP_PARA_READY_MASK, flag << VIPP_PARA_READY);
126 #endif
127 }
128
vipp_set_osd_ov_update(unsigned int id,enum vipp_update_flag flag)129 void vipp_set_osd_ov_update(unsigned int id, enum vipp_update_flag flag)
130 {
131 if (id > MAX_OSD_NUM - 1)
132 return;
133
134 vin_reg_clr_set(vipp_base[id] + VIPP_CTRL_REG_OFF,
135 VIPP_OSD_OV_UPDATE_MASK, flag << VIPP_OSD_OV_UPDATE);
136 }
137
vipp_set_osd_cv_update(unsigned int id,enum vipp_update_flag flag)138 void vipp_set_osd_cv_update(unsigned int id, enum vipp_update_flag flag)
139 {
140 #if defined CONFIG_ARCH_SUN8IW12P1
141 vin_reg_clr_set(vipp_base[id] + VIPP_CTRL_REG_OFF,
142 VIPP_OSD_CV_UPDATE_MASK, flag << VIPP_OSD_CV_UPDATE);
143 #endif
144 }
145
vipp_set_osd_para_load_addr(unsigned int id,unsigned long dma_addr)146 void vipp_set_osd_para_load_addr(unsigned int id, unsigned long dma_addr)
147 {
148 #if defined CONFIG_ARCH_SUN8IW12P1
149 vin_reg_writel(vipp_base[id] + VIPP_OSD_LOAD_ADDR_REG_OFF, dma_addr >> VIPP_ADDR_BIT_R_SHIFT);
150 #endif
151 }
152
vipp_map_osd_para_load_addr(unsigned int id,unsigned long vaddr)153 int vipp_map_osd_para_load_addr(unsigned int id, unsigned long vaddr)
154 {
155 #if defined CONFIG_ARCH_SUN8IW12P1
156 if (id > VIN_MAX_SCALER - 1)
157 return -1;
158
159 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg = (VIPP_OSD_OVERLAY_CFG_REG_t *)vaddr;
160 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg = (VIPP_OSD_COVER_CFG_REG_t *)(vaddr + MAX_OVERLAY_NUM * 8);
161 vipp_osd_para_load_addr[id].vipp_osd_cover_data = (VIPP_OSD_COVER_DATA_REG_t *)(vaddr + MAX_OVERLAY_NUM * 8 + MAX_COVER_NUM * 8);
162 #endif
163 return 0;
164 }
165
vipp_set_osd_stat_load_addr(unsigned int id,unsigned long dma_addr)166 void vipp_set_osd_stat_load_addr(unsigned int id, unsigned long dma_addr)
167 {
168 vin_reg_writel(vipp_base[id] + VIPP_OSD_STAT_ADDR_REG_OFF, dma_addr >> VIPP_ADDR_BIT_R_SHIFT);
169 }
170
vipp_set_osd_bm_load_addr(unsigned int id,unsigned long dma_addr)171 void vipp_set_osd_bm_load_addr(unsigned int id, unsigned long dma_addr)
172 {
173 vin_reg_writel(vipp_base[id] + VIPP_OSD_BM_ADDR_REG_OFF, dma_addr >> VIPP_ADDR_BIT_R_SHIFT);
174 }
175
vipp_set_reg_load_addr(unsigned int id,unsigned long dma_addr)176 void vipp_set_reg_load_addr(unsigned int id, unsigned long dma_addr)
177 {
178 vin_reg_writel(vipp_base[id] + VIPP_REG_LOAD_ADDR_REG_OFF, dma_addr >> VIPP_ADDR_BIT_R_SHIFT);
179 }
180
vipp_map_reg_load_addr(unsigned int id,unsigned long vaddr)181 int vipp_map_reg_load_addr(unsigned int id, unsigned long vaddr)
182 {
183 if (id > VIN_MAX_SCALER - 1)
184 return -1;
185
186 vipp_reg_load_addr[id].vipp_module_en = (VIPP_MODULE_EN_REG_t *)(vaddr + VIPP_MODULE_EN_REG_OFF);
187 vipp_reg_load_addr[id].vipp_scaler_cfg = (VIPP_SCALER_CFG_REG_t *)(vaddr + VIPP_SC_CFG_REG_OFF);
188 vipp_reg_load_addr[id].vipp_scaler_output_size = (VIPP_SCALER_OUTPUT_SIZE_REG_t *)(vaddr + VIPP_SC_SIZE_REG_OFF);
189 vipp_reg_load_addr[id].vipp_output_fmt = (VIPP_OUTPUT_FMT_REG_t *)(vaddr + VIPP_MODE_REG_OFF);
190 vipp_reg_load_addr[id].vipp_osd_cfg = (VIPP_OSD_CFG_REG_t *)(vaddr + VIPP_OSD_CFG_REG_OFF);
191 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain0 = (VIPP_OSD_RGB2YUV_GAIN0_REG_t *)(vaddr + VIPP_OSD_GAIN0_REG_OFF);
192 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain1 = (VIPP_OSD_RGB2YUV_GAIN1_REG_t *)(vaddr + VIPP_OSD_GAIN1_REG_OFF);
193 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain2 = (VIPP_OSD_RGB2YUV_GAIN2_REG_t *)(vaddr + VIPP_OSD_GAIN2_REG_OFF);
194 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain3 = (VIPP_OSD_RGB2YUV_GAIN3_REG_t *)(vaddr + VIPP_OSD_GAIN3_REG_OFF);
195 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain4 = (VIPP_OSD_RGB2YUV_GAIN4_REG_t *)(vaddr + VIPP_OSD_GAIN4_REG_OFF);
196 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_offset = (VIPP_OSD_RGB2YUV_OFFSET_REG_t *)(vaddr + VIPP_OSD_OFFSET_REG_OFF);
197 vipp_reg_load_addr[id].vipp_crop_start = (VIPP_CROP_START_POSITION_REG_t *)(vaddr + VIPP_CROP_START_REG_OFF);
198 vipp_reg_load_addr[id].vipp_crop_size = (VIPP_CROP_SIZE_REG_t *)(vaddr + VIPP_CROP_SIZE_REG_OFF);
199 #if defined CONFIG_ARCH_SUN8IW16P1 || defined CONFIG_ARCH_SUN8IW19P1
200 vipp_reg_load_addr[id].vipp_osd_ov_region = (VIPP_OSD_REGION_REG_t *)(vaddr + VIPP_OSD_OV0_ST_REG_OFF);
201 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg0 = (VIPP_OSD_OV_ALPHA_CFG0_REG_t *)(vaddr + VIPP_OSD_OV_ALPHA_CFG0_REG_OFF);
202 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg1 = (VIPP_OSD_OV_ALPHA_CFG1_REG_t *)(vaddr + VIPP_OSD_OV_ALPHA_CFG1_REG_OFF);
203 vipp_reg_load_addr[id].vipp_osd_cv_region = (VIPP_OSD_REGION_REG_t *)(vaddr + VIPP_OSD_CV0_ST_REG_OFF);
204 vipp_reg_load_addr[id].vipp_osd_cv_region_yuv = (VIPP_OSD_CV_REGION_YUV_REG_t *)(vaddr + VIPP_OSD_CV0_YUV_REG_OFF);
205 vipp_reg_load_addr[id].vipp_osd_inv_w = (VIPP_OSD_INV_W_REG_t *)(vaddr + VIPP_OSD_INV_WIDTH_REG_OFF);
206 vipp_reg_load_addr[id].vipp_osd_inv_h = (VIPP_OSD_INV_H_REG_t *)(vaddr + VIPP_OSD_INV_HEIGHT_REG_OFF);
207 vipp_reg_load_addr[id].vipp_orl_control = (VIPP_ORL_CONTROL_REG_t *)(vaddr + VIPP_ORL_CONTROL_REG_OFF);
208 vipp_reg_load_addr[id].vipp_orl_start = (VIPP_ORL_START_REG_t *)(vaddr + VIPP_ORL_START0_REG_OFF);
209 vipp_reg_load_addr[id].vipp_orl_end = (VIPP_ORL_END_REG_t *)(vaddr + VIPP_ORL_END0_REG_OFF);
210 vipp_reg_load_addr[id].vipp_orl_yuv = (VIPP_ORL_YUV_REG_t *)(vaddr + VIPP_ORL_YUV0_REG_OFF);
211 #endif
212 return 0;
213 }
214
vipp_get_status(unsigned int id,struct vipp_status * status)215 void vipp_get_status(unsigned int id, struct vipp_status *status)
216 {
217 unsigned int reg_val = vin_reg_readl(vipp_base[id] + VIPP_STA_REG_OFF);
218
219 status->reg_load_pd = (reg_val & VIPP_REG_LOAD_PD_MASK) >> VIPP_REG_LOAD_PD;
220 status->bm_error_pd = (reg_val & VIPP_BM_ERROR_PD_MASK) >> VIPP_BM_ERROR_PD;
221 }
222
vipp_clr_status(unsigned int id,enum vipp_status_sel sel)223 void vipp_clr_status(unsigned int id, enum vipp_status_sel sel)
224 {
225 vin_reg_writel(vipp_base[id] + VIPP_STA_REG_OFF, sel);
226 }
227
vipp_scaler_en(unsigned int id,unsigned int en)228 void vipp_scaler_en(unsigned int id, unsigned int en)
229 {
230 #ifndef VIPP_SCALER_DIRECTLY_WRITE_REG
231 vipp_reg_load_addr[id].vipp_module_en->bits.sc_en = en;
232 #else
233 VIPP_MODULE_EN_REG_t vipp_module_en;
234
235 vipp_module_en.dwval = 0;
236 vipp_module_en.bits.sc_en = en;
237 vin_reg_writel(vipp_base[id] + VIPP_MODULE_EN_REG_OFF, vipp_module_en.dwval);
238 #endif
239 }
240
vipp_osd_en(unsigned int id,unsigned int en)241 void vipp_osd_en(unsigned int id, unsigned int en)
242 {
243 if (id > MAX_OSD_NUM - 1)
244 return;
245
246 vipp_reg_load_addr[id].vipp_module_en->bits.osd_en = en;
247 }
248
vipp_chroma_ds_en(unsigned int id,unsigned int en)249 void vipp_chroma_ds_en(unsigned int id, unsigned int en)
250 {
251 if (id > MAX_OSD_NUM - 1)
252 return;
253
254 vipp_reg_load_addr[id].vipp_module_en->bits.chroma_ds_en = en;
255 }
256
vipp_scaler_cfg(unsigned int id,struct vipp_scaler_config * cfg)257 void vipp_scaler_cfg(unsigned int id, struct vipp_scaler_config *cfg)
258 {
259 #ifndef VIPP_SCALER_DIRECTLY_WRITE_REG
260 #if !defined CONFIG_ARCH_SUN8IW19P1 && !defined CONFIG_ARCH_SUN50IW10
261 vipp_reg_load_addr[id].vipp_scaler_cfg->bits.sc_out_fmt = cfg->sc_out_fmt;
262 #else
263 vipp_reg_load_addr[id].vipp_output_fmt->bits.sc_out_fmt = cfg->sc_out_fmt;
264 #endif
265 vipp_reg_load_addr[id].vipp_scaler_cfg->bits.sc_xratio = cfg->sc_x_ratio;
266 vipp_reg_load_addr[id].vipp_scaler_cfg->bits.sc_yratio = cfg->sc_y_ratio;
267 vipp_reg_load_addr[id].vipp_scaler_cfg->bits.sc_weight_shift = cfg->sc_w_shift;
268 #else
269 VIPP_SCALER_CFG_REG_t vipp_scaler_cfg;
270
271 vipp_scaler_cfg.dwval = 0;
272 vipp_scaler_cfg.bits.sc_out_fmt = cfg->sc_out_fmt;
273 vipp_scaler_cfg.bits.sc_xratio = cfg->sc_x_ratio;
274 vipp_scaler_cfg.bits.sc_yratio = cfg->sc_y_ratio;
275 vipp_scaler_cfg.bits.sc_weight_shift = cfg->sc_w_shift;
276 vin_reg_writel(vipp_base[id] + VIPP_SC_CFG_REG_OFF, vipp_scaler_cfg.dwval);
277
278 #endif
279 }
280
vipp_scaler_output_fmt(unsigned int id,enum vipp_format fmt)281 void vipp_scaler_output_fmt(unsigned int id, enum vipp_format fmt)
282 {
283 #ifndef VIPP_SCALER_DIRECTLY_WRITE_REG
284 #if !defined CONFIG_ARCH_SUN8IW19P1 && !defined CONFIG_ARCH_SUN50IW10
285 vipp_reg_load_addr[id].vipp_scaler_cfg->bits.sc_out_fmt = fmt;
286 #else
287 vipp_reg_load_addr[id].vipp_output_fmt->bits.sc_out_fmt = fmt;
288 #endif
289 #else
290 vin_reg_clr_set(vipp_base[id] + VIPP_SC_CFG_REG_OFF, 0x1, fmt);
291 #endif
292 }
293
vipp_scaler_output_size(unsigned int id,struct vipp_scaler_size * size)294 void vipp_scaler_output_size(unsigned int id, struct vipp_scaler_size *size)
295 {
296 #ifndef VIPP_SCALER_DIRECTLY_WRITE_REG
297 vipp_reg_load_addr[id].vipp_scaler_output_size->bits.sc_width = size->sc_width;
298 vipp_reg_load_addr[id].vipp_scaler_output_size->bits.sc_height = size->sc_height;
299 #else
300 VIPP_SCALER_OUTPUT_SIZE_REG_t vipp_scaler_output_size;
301
302 vipp_scaler_output_size.dwval = 0;
303 vipp_scaler_output_size.bits.sc_width = size->sc_width;
304 vipp_scaler_output_size.bits.sc_height = size->sc_height;
305 vin_reg_writel(vipp_base[id] + VIPP_SC_SIZE_REG_OFF, vipp_scaler_output_size.dwval);
306 #endif
307 }
308
vipp_output_fmt_cfg(unsigned int id,enum vipp_format fmt)309 void vipp_output_fmt_cfg(unsigned int id, enum vipp_format fmt)
310 {
311 #ifndef VIPP_SCALER_DIRECTLY_WRITE_REG
312 vipp_reg_load_addr[id].vipp_output_fmt->bits.vipp_out_fmt = fmt;
313 vipp_reg_load_addr[id].vipp_output_fmt->bits.vipp_in_fmt = 1;
314
315 #else
316 VIPP_OUTPUT_FMT_REG_t vipp_output_fmt;
317
318 vipp_output_fmt.dwval = 0;
319 vipp_output_fmt.bits.vipp_out_fmt = fmt;
320 vipp_output_fmt.bits.vipp_in_fmt = 1;
321 vin_reg_writel(vipp_base[id] + VIPP_MODE_REG_OFF, vipp_output_fmt.dwval);
322 #endif
323 }
324
vipp_osd_cfg(unsigned int id,struct vipp_osd_config * cfg)325 void vipp_osd_cfg(unsigned int id, struct vipp_osd_config *cfg)
326 {
327 #if defined CONFIG_ARCH_SUN8IW12P1
328 vipp_reg_load_addr[id].vipp_osd_cfg->bits.osd_ov_en = cfg->osd_ov_en;
329 vipp_reg_load_addr[id].vipp_osd_cfg->bits.osd_cv_en = cfg->osd_cv_en;
330 vipp_reg_load_addr[id].vipp_osd_cfg->bits.osd_argb_mode = cfg->osd_argb_mode;
331 vipp_reg_load_addr[id].vipp_osd_cfg->bits.osd_stat_en = cfg->osd_stat_en;
332 vipp_reg_load_addr[id].vipp_osd_cfg->bits.osd_ov_num = cfg->osd_ov_num;
333 vipp_reg_load_addr[id].vipp_osd_cfg->bits.osd_cv_num = cfg->osd_cv_num;
334 #elif defined CONFIG_ARCH_SUN8IW16P1 || defined CONFIG_ARCH_SUN8IW19P1
335 vipp_reg_load_addr[id].vipp_osd_cfg->bits.argb_mode = cfg->osd_argb_mode;
336 vipp_reg_load_addr[id].vipp_osd_cfg->bits.stat_en = 1;
337 vipp_reg_load_addr[id].vipp_osd_cfg->bits.ov_num = cfg->osd_ov_num + 1;
338 vipp_reg_load_addr[id].vipp_osd_cfg->bits.cv_num = cfg->osd_cv_num + 1;
339 vipp_reg_load_addr[id].vipp_orl_control->bits.orl_num = cfg->osd_orl_num + 1;
340 vipp_reg_load_addr[id].vipp_orl_control->bits.orl_width = cfg->osd_orl_width;
341 #endif
342 }
343
vipp_osd_rgb2yuv(unsigned int id,struct vipp_rgb2yuv_factor * factor)344 void vipp_osd_rgb2yuv(unsigned int id, struct vipp_rgb2yuv_factor *factor)
345 {
346 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain0->bits.jc0 = factor->jc0;
347 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain0->bits.jc1 = factor->jc1;
348 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain1->bits.jc2 = factor->jc2;
349 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain1->bits.jc3 = factor->jc3;
350 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain2->bits.jc4 = factor->jc4;
351 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain2->bits.jc5 = factor->jc5;
352 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain3->bits.jc6 = factor->jc6;
353 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain3->bits.jc7 = factor->jc7;
354 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_gain4->bits.jc8 = factor->jc8;
355 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_offset->bits.jc9 = factor->jc9;
356 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_offset->bits.jc10 = factor->jc10;
357 vipp_reg_load_addr[id].vipp_osd_rgb2yuv_offset->bits.jc11 = factor->jc11;
358 }
359
vipp_set_crop(unsigned int id,struct vipp_crop * crop)360 void vipp_set_crop(unsigned int id, struct vipp_crop *crop)
361 {
362 vipp_reg_load_addr[id].vipp_crop_start->bits.crop_hor_st = crop->hor;
363 vipp_reg_load_addr[id].vipp_crop_start->bits.crop_ver_st = crop->ver;
364 vipp_reg_load_addr[id].vipp_crop_size->bits.crop_width = crop->width;
365 vipp_reg_load_addr[id].vipp_crop_size->bits.crop_height = crop->height;
366 }
367
vipp_osd_hvflip(unsigned int id,int hflip,int vflip)368 void vipp_osd_hvflip(unsigned int id, int hflip, int vflip)
369 {
370 #if defined CONFIG_ARCH_SUN8IW16P1 || defined CONFIG_ARCH_SUN8IW19P1
371 vipp_reg_load_addr[id].vipp_osd_cfg->bits.hflip = hflip;
372 vipp_reg_load_addr[id].vipp_osd_cfg->bits.vflip = vflip;
373 #endif
374 }
375
vipp_osd_inverse(unsigned int id,int * inverse,int cnt)376 void vipp_osd_inverse(unsigned int id, int *inverse, int cnt)
377 {
378 #if defined CONFIG_ARCH_SUN8IW12P1
379 int i;
380
381 for (i = 0; i < cnt; i++)
382 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.inverse_en = inverse[i];
383 #endif
384 }
385
vipp_osd_para_cfg(unsigned int id,struct vipp_osd_para_config * para,struct vipp_osd_config * cfg)386 void vipp_osd_para_cfg(unsigned int id, struct vipp_osd_para_config *para,
387 struct vipp_osd_config *cfg)
388 {
389 #if defined CONFIG_ARCH_SUN8IW12P1
390 int i;
391
392 for (i = 0; i < cfg->osd_ov_num + 1; i++) {
393 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.h_start = para->overlay_cfg[i].h_start;
394 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.h_end = para->overlay_cfg[i].h_end;
395 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.v_start = para->overlay_cfg[i].v_start;
396 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.v_end = para->overlay_cfg[i].v_end;
397 vipp_osd_para_load_addr[id].vipp_osd_overlay_cfg[i].bits.alpha = para->overlay_cfg[i].alpha;
398 }
399
400 for (i = 0; i < cfg->osd_cv_num + 1; i++) {
401 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.h_start = para->cover_cfg[i].h_start;
402 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.h_end = para->cover_cfg[i].h_end;
403 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.v_start = para->cover_cfg[i].v_start;
404 vipp_osd_para_load_addr[id].vipp_osd_cover_cfg[i].bits.v_end = para->cover_cfg[i].v_end;
405 vipp_osd_para_load_addr[id].vipp_osd_cover_data[i].bits.y = para->cover_data[i].y;
406 vipp_osd_para_load_addr[id].vipp_osd_cover_data[i].bits.u = para->cover_data[i].u;
407 vipp_osd_para_load_addr[id].vipp_osd_cover_data[i].bits.v = para->cover_data[i].v;
408 }
409 #elif defined CONFIG_ARCH_SUN8IW16P1
410 int i;
411
412 for (i = 0; i < cfg->osd_ov_num + 1; i++) {
413 vipp_reg_load_addr[id].vipp_osd_ov_region[i].bits.h_start = para->overlay_cfg[i].h_start;
414 vipp_reg_load_addr[id].vipp_osd_ov_region[i].bits.h_end = para->overlay_cfg[i].h_end;
415 vipp_reg_load_addr[id].vipp_osd_ov_region[i].bits.v_start = para->overlay_cfg[i].v_start;
416 vipp_reg_load_addr[id].vipp_osd_ov_region[i].bits.v_end = para->overlay_cfg[i].v_end;
417 }
418 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg0->bits.ov_alpha_rgn0 = para->overlay_cfg[0].alpha;
419 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg0->bits.ov_alpha_rgn1 = para->overlay_cfg[1].alpha;
420 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg0->bits.ov_alpha_rgn2 = para->overlay_cfg[2].alpha;
421 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg0->bits.ov_alpha_rgn3 = para->overlay_cfg[3].alpha;
422 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg1->bits.ov_alpha_rgn4 = para->overlay_cfg[4].alpha;
423 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg1->bits.ov_alpha_rgn5 = para->overlay_cfg[5].alpha;
424 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg1->bits.ov_alpha_rgn6 = para->overlay_cfg[6].alpha;
425 vipp_reg_load_addr[id].vipp_osd_ov_alpha_cfg1->bits.ov_alpha_rgn7 = para->overlay_cfg[7].alpha;
426
427 for (i = 0; i < cfg->osd_cv_num + 1; i++) {
428 vipp_reg_load_addr[id].vipp_osd_cv_region[i].bits.h_start = para->cover_cfg[i].h_start;
429 vipp_reg_load_addr[id].vipp_osd_cv_region[i].bits.h_end = para->cover_cfg[i].h_end;
430 vipp_reg_load_addr[id].vipp_osd_cv_region[i].bits.v_start = para->cover_cfg[i].v_start;
431 vipp_reg_load_addr[id].vipp_osd_cv_region[i].bits.v_end = para->cover_cfg[i].v_end;
432 vipp_reg_load_addr[id].vipp_osd_cv_region_yuv[i].bits.cv_y = para->cover_data[i].y;
433 vipp_reg_load_addr[id].vipp_osd_cv_region_yuv[i].bits.cv_u = para->cover_data[i].u;
434 vipp_reg_load_addr[id].vipp_osd_cv_region_yuv[i].bits.cv_v = para->cover_data[i].v;
435 }
436
437 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn0 = para->overlay_cfg[0].inv_w_rgn;
438 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn1 = para->overlay_cfg[1].inv_w_rgn;
439 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn2 = para->overlay_cfg[2].inv_w_rgn;
440 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn3 = para->overlay_cfg[3].inv_w_rgn;
441 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn4 = para->overlay_cfg[4].inv_w_rgn;
442 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn5 = para->overlay_cfg[5].inv_w_rgn;
443 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn6 = para->overlay_cfg[6].inv_w_rgn;
444 vipp_reg_load_addr[id].vipp_osd_inv_w->bits.inv_w_rgn7 = para->overlay_cfg[7].inv_w_rgn;
445
446 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn0 = para->overlay_cfg[0].inv_h_rgn;
447 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn1 = para->overlay_cfg[1].inv_h_rgn;
448 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn2 = para->overlay_cfg[2].inv_h_rgn;
449 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn3 = para->overlay_cfg[3].inv_h_rgn;
450 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn4 = para->overlay_cfg[4].inv_h_rgn;
451 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn5 = para->overlay_cfg[5].inv_h_rgn;
452 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn6 = para->overlay_cfg[6].inv_h_rgn;
453 vipp_reg_load_addr[id].vipp_osd_inv_h->bits.inv_h_rgn7 = para->overlay_cfg[7].inv_h_rgn;
454
455 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en0 = para->overlay_cfg[0].inv_en;
456 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en1 = para->overlay_cfg[1].inv_en;
457 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en2 = para->overlay_cfg[2].inv_en;
458 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en3 = para->overlay_cfg[3].inv_en;
459 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en4 = para->overlay_cfg[4].inv_en;
460 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en5 = para->overlay_cfg[5].inv_en;
461 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en6 = para->overlay_cfg[6].inv_en;
462 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_en7 = para->overlay_cfg[7].inv_en;
463
464 vipp_reg_load_addr[id].vipp_osd_cfg->bits.inv_th = para->overlay_cfg[0].inv_th;
465
466 #elif defined CONFIG_ARCH_SUN8IW19P1
467 int i;
468
469 for (i = 0; i < cfg->osd_orl_num + 1; i++) {
470 vipp_reg_load_addr[id].vipp_orl_start[i].bits.orl_ys = para->orl_cfg[i].v_start;
471 vipp_reg_load_addr[id].vipp_orl_start[i].bits.orl_xs = para->orl_cfg[i].h_start;
472 vipp_reg_load_addr[id].vipp_orl_end[i].bits.orl_ye = para->orl_cfg[i].v_end;
473 vipp_reg_load_addr[id].vipp_orl_end[i].bits.orl_xe = para->orl_cfg[i].h_end;
474 vipp_reg_load_addr[id].vipp_orl_yuv[i].bits.orl_y = para->orl_data[i].y;
475 vipp_reg_load_addr[id].vipp_orl_yuv[i].bits.orl_u = para->orl_data[i].u;
476 vipp_reg_load_addr[id].vipp_orl_yuv[i].bits.orl_v = para->orl_data[i].v;
477 }
478 #endif
479 }
480