1 /* 2 * drivers/media/platform/sunxi-vin/vin_test/sunxi_display2.h -- Ctrl IDs definitions for sunxi-vin 3 * 4 * Copyright (C) 2014 Allwinnertech Co., Ltd. 5 * Copyright (C) 2015 Yang Feng 6 * 7 * Author: Yang Feng <yangfeng@allwinnertech.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 */ 19 #ifndef __SUNXI_DISPLAY2_H__ 20 #define __SUNXI_DISPLAY2_H__ 21 22 #include <sys/ioctl.h> 23 #include <linux/types.h> 24 #define __int64 long long 25 #define bool unsigned char 26 struct disp_manager; 27 struct disp_device; 28 struct disp_smbl; 29 struct disp_enhance; 30 struct disp_capture; 31 typedef __u32 u32; 32 typedef __u16 u16; 33 typedef __u64 u64; 34 35 struct disp_color { 36 unsigned char alpha; 37 unsigned char red; 38 unsigned char green; 39 unsigned char blue; 40 }; 41 42 typedef struct disp_color disp_color; 43 44 struct disp_rect { 45 int x; 46 int y; 47 unsigned int width; 48 unsigned int height; 49 }; 50 typedef struct disp_rect disp_rect; 51 52 struct disp_rectsz { 53 unsigned int width; 54 unsigned int height; 55 }; 56 typedef struct disp_rectsz disp_rectsz; 57 58 struct disp_position { 59 int x; 60 int y; 61 }; 62 typedef struct disp_position disp_position; 63 64 enum disp_pixel_format { 65 DISP_FORMAT_ARGB_8888 = 0x00,/* MSB A-R-G-B LSB */ 66 DISP_FORMAT_ABGR_8888 = 0x01, 67 DISP_FORMAT_RGBA_8888 = 0x02, 68 DISP_FORMAT_BGRA_8888 = 0x03, 69 DISP_FORMAT_XRGB_8888 = 0x04, 70 DISP_FORMAT_XBGR_8888 = 0x05, 71 DISP_FORMAT_RGBX_8888 = 0x06, 72 DISP_FORMAT_BGRX_8888 = 0x07, 73 DISP_FORMAT_RGB_888 = 0x08, 74 DISP_FORMAT_BGR_888 = 0x09, 75 DISP_FORMAT_RGB_565 = 0x0a, 76 DISP_FORMAT_BGR_565 = 0x0b, 77 DISP_FORMAT_ARGB_4444 = 0x0c, 78 DISP_FORMAT_ABGR_4444 = 0x0d, 79 DISP_FORMAT_RGBA_4444 = 0x0e, 80 DISP_FORMAT_BGRA_4444 = 0x0f, 81 DISP_FORMAT_ARGB_1555 = 0x10, 82 DISP_FORMAT_ABGR_1555 = 0x11, 83 DISP_FORMAT_RGBA_5551 = 0x12, 84 DISP_FORMAT_BGRA_5551 = 0x13, 85 DISP_FORMAT_A2R10G10B10 = 0x14, 86 DISP_FORMAT_A2B10G10R10 = 0x15, 87 DISP_FORMAT_R10G10B10A2 = 0x16, 88 DISP_FORMAT_B10G10R10A2 = 0x17, 89 90 /* SP: semi-planar, P:planar, I:interleaved 91 * UVUV: U in the LSBs; VUVU: V in the LSBs */ 92 DISP_FORMAT_YUV444_I_AYUV = 0x40, /* MSB A-Y-U-V LSB, reserved */ 93 DISP_FORMAT_YUV444_I_VUYA = 0x41, /* MSB V-U-Y-A LSB */ 94 DISP_FORMAT_YUV422_I_YVYU = 0x42, /* MSB Y-V-Y-U LSB */ 95 DISP_FORMAT_YUV422_I_YUYV = 0x43, /* MSB Y-U-Y-V LSB */ 96 DISP_FORMAT_YUV422_I_UYVY = 0x44, /* MSB U-Y-V-Y LSB */ 97 DISP_FORMAT_YUV422_I_VYUY = 0x45, /* MSB V-Y-U-Y LSB */ 98 DISP_FORMAT_YUV444_P = 0x46, /* MSB P3-2-1-0 LSB, YYYY UUUU VVVV, reserved */ 99 DISP_FORMAT_YUV422_P = 0x47, /* MSB P3-2-1-0 LSB YYYY UU VV */ 100 /* MSB P3-2-1-0 LSB YYYY V U */ 101 DISP_FORMAT_YUV420_P = 0x48, 102 DISP_FORMAT_YUV411_P = 0x49, /* MSB P3-2-1-0 LSB YYYY U V */ 103 DISP_FORMAT_YUV422_SP_UVUV = 0x4a, /* MSB V-U-V-U LSB */ 104 DISP_FORMAT_YUV422_SP_VUVU = 0x4b, /* MSB U-V-U-V LSB */ 105 DISP_FORMAT_YUV420_SP_UVUV = 0x4c, 106 DISP_FORMAT_YUV420_SP_VUVU = 0x4d, 107 DISP_FORMAT_YUV411_SP_UVUV = 0x4e, 108 DISP_FORMAT_YUV411_SP_VUVU = 0x4f, 109 DISP_FORMAT_8BIT_GRAY = 0x50, 110 DISP_FORMAT_YUV444_I_AYUV_10BIT = 0x51, 111 DISP_FORMAT_YUV444_I_VUYA_10BIT = 0x52, 112 DISP_FORMAT_YUV422_I_YVYU_10BIT = 0x53, 113 DISP_FORMAT_YUV422_I_YUYV_10BIT = 0x54, 114 DISP_FORMAT_YUV422_I_UYVY_10BIT = 0x55, 115 DISP_FORMAT_YUV422_I_VYUY_10BIT = 0x56, 116 DISP_FORMAT_YUV444_P_10BIT = 0x57, 117 DISP_FORMAT_YUV422_P_10BIT = 0x58, 118 DISP_FORMAT_YUV420_P_10BIT = 0x59, 119 DISP_FORMAT_YUV411_P_10BIT = 0x5a, 120 DISP_FORMAT_YUV422_SP_UVUV_10BIT = 0x5b, 121 DISP_FORMAT_YUV422_SP_VUVU_10BIT = 0x5c, 122 DISP_FORMAT_YUV420_SP_UVUV_10BIT = 0x5d, 123 DISP_FORMAT_YUV420_SP_VUVU_10BIT = 0x5e, 124 DISP_FORMAT_YUV411_SP_UVUV_10BIT = 0x5f, 125 DISP_FORMAT_YUV411_SP_VUVU_10BIT = 0x60, 126 DISP_FORMAT_MAX, 127 }; 128 129 typedef enum disp_pixel_format disp_pixel_format; 130 131 enum disp_3d_out_mode { 132 DISP_3D_OUT_MODE_CI_1 = 0x5, /* column interlaved 1 */ 133 DISP_3D_OUT_MODE_CI_2 = 0x6, /* column interlaved 2 */ 134 DISP_3D_OUT_MODE_CI_3 = 0x7, /* column interlaved 3 */ 135 DISP_3D_OUT_MODE_CI_4 = 0x8, /* column interlaved 4 */ 136 DISP_3D_OUT_MODE_LIRGB = 0x9, /* line interleaved rgb */ 137 138 DISP_3D_OUT_MODE_TB = 0x0, /* top bottom */ 139 DISP_3D_OUT_MODE_FP = 0x1, /* frame packing */ 140 DISP_3D_OUT_MODE_SSF = 0x2, /* side by side full */ 141 DISP_3D_OUT_MODE_SSH = 0x3, /* side by side half */ 142 DISP_3D_OUT_MODE_LI = 0x4, /* line interleaved */ 143 DISP_3D_OUT_MODE_FA = 0xa, /* field alternative */ 144 }; 145 146 typedef enum disp_3d_out_mode disp_3d_out_mode; 147 148 enum disp_color_space { 149 DISP_UNDEF = 0x00, 150 DISP_UNDEF_F = 0x01, 151 DISP_GBR = 0x100, 152 DISP_BT709 = 0x101, 153 DISP_FCC = 0x102, 154 DISP_BT470BG = 0x103, 155 DISP_BT601 = 0x104, 156 DISP_SMPTE240M = 0x105, 157 DISP_YCGCO = 0x106, 158 DISP_BT2020NC = 0x107, 159 DISP_BT2020C = 0x108, 160 DISP_GBR_F = 0x200, 161 DISP_BT709_F = 0x201, 162 DISP_FCC_F = 0x202, 163 DISP_BT470BG_F = 0x203, 164 DISP_BT601_F = 0x204, 165 DISP_SMPTE240M_F = 0x205, 166 DISP_YCGCO_F = 0x206, 167 DISP_BT2020NC_F = 0x207, 168 DISP_BT2020C_F = 0x208, 169 DISP_RESERVED = 0x300, 170 DISP_RESERVED_F = 0x301, 171 }; 172 173 typedef enum disp_color_space disp_color_space; 174 175 enum disp_csc_type { 176 DISP_CSC_TYPE_RGB = 0, 177 DISP_CSC_TYPE_YUV444 = 1, 178 DISP_CSC_TYPE_YUV422 = 2, 179 DISP_CSC_TYPE_YUV420 = 3, 180 }; 181 182 typedef enum disp_csc_type disp_csc_type; 183 184 enum disp_data_bits { 185 DISP_DATA_8BITS = 0, 186 DISP_DATA_10BITS = 1, 187 DISP_DATA_12BITS = 2, 188 DISP_DATA_16BITS = 3, 189 }; 190 typedef enum disp_data_bits disp_data_bits; 191 192 enum disp_dvi_hdmi { 193 DISP_DVI_HDMI_UNDEFINED = 0, 194 DISP_DVI = 1, 195 DISP_HDMI = 2, 196 }; 197 typedef enum disp_dvi_hdmi disp_dvi_hdmi; 198 199 enum disp_scan_info { 200 DISP_SCANINFO_NO_DATA = 0, 201 OVERSCAN = 1, 202 UNDERSCAN = 2, 203 }; 204 typedef enum disp_scan_info disp_scan_info; 205 206 enum disp_color_range { 207 DISP_COLOR_RANGE_DEFAULT = 0, /*default*/ 208 DISP_COLOR_RANGE_0_255 = 1, /*full*/ 209 DISP_COLOR_RANGE_16_235 = 2, /*limited*/ 210 }; 211 typedef enum disp_color_range disp_color_range; 212 213 enum disp_output_type { 214 DISP_OUTPUT_TYPE_NONE = 0, 215 DISP_OUTPUT_TYPE_LCD = 1, 216 DISP_OUTPUT_TYPE_TV = 2, 217 DISP_OUTPUT_TYPE_HDMI = 4, 218 DISP_OUTPUT_TYPE_VGA = 8, 219 DISP_OUTPUT_TYPE_EDP = 32, /*16 for vdpo*/ 220 }; 221 typedef enum disp_output_type disp_output_type; 222 223 enum disp_tv_mode { 224 DISP_TV_MOD_480I = 0, 225 DISP_TV_MOD_576I = 1, 226 DISP_TV_MOD_480P = 2, 227 DISP_TV_MOD_576P = 3, 228 DISP_TV_MOD_720P_50HZ = 4, 229 DISP_TV_MOD_720P_60HZ = 5, 230 DISP_TV_MOD_1080I_50HZ = 6, 231 DISP_TV_MOD_1080I_60HZ = 7, 232 DISP_TV_MOD_1080P_24HZ = 8, 233 DISP_TV_MOD_1080P_50HZ = 9, 234 DISP_TV_MOD_1080P_60HZ = 0xa, 235 DISP_TV_MOD_1080P_24HZ_3D_FP = 0x17, 236 DISP_TV_MOD_720P_50HZ_3D_FP = 0x18, 237 DISP_TV_MOD_720P_60HZ_3D_FP = 0x19, 238 DISP_TV_MOD_1080P_25HZ = 0x1a, 239 DISP_TV_MOD_1080P_30HZ = 0x1b, 240 DISP_TV_MOD_PAL = 0xb, 241 DISP_TV_MOD_PAL_SVIDEO = 0xc, 242 DISP_TV_MOD_NTSC = 0xe, 243 DISP_TV_MOD_NTSC_SVIDEO = 0xf, 244 DISP_TV_MOD_PAL_M = 0x11, 245 DISP_TV_MOD_PAL_M_SVIDEO = 0x12, 246 DISP_TV_MOD_PAL_NC = 0x14, 247 DISP_TV_MOD_PAL_NC_SVIDEO = 0x15, 248 DISP_TV_MOD_3840_2160P_30HZ = 0x1c, 249 DISP_TV_MOD_3840_2160P_25HZ = 0x1d, 250 DISP_TV_MOD_3840_2160P_24HZ = 0x1e, 251 DISP_TV_MOD_4096_2160P_24HZ = 0x1f, 252 DISP_TV_MOD_4096_2160P_25HZ = 0x20, 253 DISP_TV_MOD_4096_2160P_30HZ = 0x21, 254 DISP_TV_MOD_3840_2160P_60HZ = 0x22, 255 DISP_TV_MOD_4096_2160P_60HZ = 0x23, 256 DISP_TV_MOD_3840_2160P_50HZ = 0x24, 257 DISP_TV_MOD_4096_2160P_50HZ = 0x25, 258 DISP_TV_MOD_1280_1024P_60HZ = 0x41, 259 DISP_TV_MOD_1024_768P_60HZ = 0x42, 260 DISP_TV_MOD_900_540P_60HZ = 0x43, 261 DISP_TV_MOD_1920_720P_60HZ = 0x44, 262 /* 263 * vga 264 * NOTE:macro'value of new solution must between 265 * DISP_VGA_MOD_640_480P_60 and DISP_VGA_MOD_MAX_NUM 266 * or you have to modify is_vag_mode function in drv_tv.h 267 */ 268 DISP_VGA_MOD_640_480P_60 = 0x50, 269 DISP_VGA_MOD_800_600P_60 = 0x51, 270 DISP_VGA_MOD_1024_768P_60 = 0x52, 271 DISP_VGA_MOD_1280_768P_60 = 0x53, 272 DISP_VGA_MOD_1280_800P_60 = 0x54, 273 DISP_VGA_MOD_1366_768P_60 = 0x55, 274 DISP_VGA_MOD_1440_900P_60 = 0x56, 275 DISP_VGA_MOD_1920_1080P_60 = 0x57, 276 DISP_VGA_MOD_1280_720P_60 = 0x58, 277 DISP_VGA_MOD_1920_1200P_60 = 0x5a, 278 DISP_VGA_MOD_MAX_NUM = 0x5b, 279 DISP_TV_MODE_NUM = 0x5c, 280 }; 281 typedef enum disp_tv_mode disp_tv_mode; 282 283 /* FIXME:still need? */ 284 enum disp_exit_mode { 285 DISP_EXIT_MODE_CLEAN_ALL = 0, 286 DISP_EXIT_MODE_CLEAN_PARTLY = 1, /* only clean interrupt temply */ 287 }; 288 typedef enum disp_exit_mode disp_exit_mode; 289 290 enum disp_buffer_flags { 291 DISP_BF_NORMAL = 0, /* non-stereo */ 292 DISP_BF_STEREO_TB = 1 << 0, /* stereo top-bottom */ 293 DISP_BF_STEREO_FP = 1 << 1, /* stereo frame packing */ 294 DISP_BF_STEREO_SSH = 1 << 2, /* stereo side by side half */ 295 DISP_BF_STEREO_SSF = 1 << 3, /* stereo side by side full */ 296 DISP_BF_STEREO_LI = 1 << 4, /* stereo line interlace */ 297 /* 298 * 2d plus depth to convert into 3d, 299 * left and right image using the same frame buffer 300 */ 301 DISP_BF_STEREO_2D_DEPTH = 1 << 5, 302 }; 303 typedef enum disp_buffer_flags disp_buffer_flags; 304 305 enum disp_layer_mode { 306 LAYER_MODE_BUFFER = 0, 307 LAYER_MODE_COLOR = 1, 308 }; 309 typedef enum disp_layer_mode disp_layer_mode; 310 311 enum disp_scan_flags { 312 DISP_SCAN_PROGRESSIVE = 0, /* non interlace */ 313 DISP_SCAN_INTERLACED_ODD_FLD_FIRST = 1 << 0, /* interlace ,odd field first */ 314 DISP_SCAN_INTERLACED_EVEN_FLD_FIRST = 1 << 1, /* interlace,even field first */ 315 }; 316 typedef enum disp_scan_flags disp_scan_flags; 317 318 enum disp_eotf { 319 DISP_EOTF_RESERVED = 0x000, 320 DISP_EOTF_BT709 = 0x001, 321 DISP_EOTF_UNDEF = 0x002, 322 DISP_EOTF_GAMMA22 = 0x004, /* SDR */ 323 DISP_EOTF_GAMMA28 = 0x005, 324 DISP_EOTF_BT601 = 0x006, 325 DISP_EOTF_SMPTE240M = 0x007, 326 DISP_EOTF_LINEAR = 0x008, 327 DISP_EOTF_LOG100 = 0x009, 328 DISP_EOTF_LOG100S10 = 0x00a, 329 DISP_EOTF_IEC61966_2_4 = 0x00b, 330 DISP_EOTF_BT1361 = 0x00c, 331 DISP_EOTF_IEC61966_2_1 = 0X00d, 332 DISP_EOTF_BT2020_0 = 0x00e, 333 DISP_EOTF_BT2020_1 = 0x00f, 334 DISP_EOTF_SMPTE2084 = 0x010, /* HDR10 */ 335 DISP_EOTF_SMPTE428_1 = 0x011, 336 DISP_EOTF_ARIB_STD_B67 = 0x012, /* HLG */ 337 }; 338 typedef enum disp_eotf disp_eotf; 339 340 /* disp_atw_mode - mode for asynchronous time warp 341 * 342 * @NORMAL_MODE: dual buffer, left eye and right eye buffer is individual 343 * @LEFT_RIGHT_MODE: single buffer, the left half of each line buffer 344 * is for left eye, the right half is for the right eye 345 * @UP_DOWN_MODE: single buffer, the first half of the total buffer 346 * is for the left eye, the second half is for the right eye 347 */ 348 enum disp_atw_mode { 349 NORMAL_MODE, 350 LEFT_RIGHT_MODE, 351 UP_DOWN_MODE, 352 }; 353 typedef enum disp_atw_mode disp_atw_mode; 354 355 struct disp_output { 356 unsigned int type; 357 unsigned int mode; 358 }; 359 typedef struct disp_output disp_output; 360 361 struct disp_rect64 { 362 long long x; 363 long long y; 364 long long width; 365 long long height; 366 }; 367 typedef struct disp_rect64 disp_rect64; 368 369 struct disp_fb_info { 370 unsigned long long addr[3]; /* address of frame buffer, single addr for interleaved fomart, 371 double addr for semi-planar fomart triple addr for planar format */ 372 struct disp_rectsz size[3]; /* size for 3 component,unit: pixels */ 373 unsigned int align[3]; /* align for 3 comonent,unit: bytes(align=2^n,i.e. 1/2/4/8/16/32..) */ 374 enum disp_pixel_format format; 375 enum disp_color_space color_space; /* color space */ 376 unsigned int trd_right_addr[3]; /* right address of 3d fb, used when in frame packing 3d mode */ 377 bool pre_multiply; /* true: pre-multiply fb */ 378 struct disp_rect64 crop; /* crop rectangle boundaries */ 379 enum disp_buffer_flags flags; /* indicate stereo or non-stereo buffer */ 380 enum disp_scan_flags scan; /* scan type & scan order */ 381 }; 382 typedef struct disp_fb_info disp_fb_info; 383 384 struct disp_layer_info { 385 enum disp_layer_mode mode; 386 unsigned char zorder; /*specifies the front-to-back ordering of the layers on the screen, the top layer having the highest Z value 387 can't set zorder, but can get */ 388 unsigned char alpha_mode; /* 0: pixel alpha; 1: global alpha; 2: global pixel alpha */ 389 unsigned char alpha_value; /* global alpha value */ 390 struct disp_rect screen_win; /* display window on the screen */ 391 bool b_trd_out; /* 3d display */ 392 enum disp_3d_out_mode out_trd_mode; /*3d display mode */ 393 union { 394 unsigned int color; /* valid when LAYER_MODE_COLOR */ 395 struct disp_fb_info fb; /* framebuffer, valid when LAYER_MODE_BUFFER */ 396 }; 397 unsigned int id; /* frame id, can get the id of frame display currently by DISP_LAYER_GET_FRAME_ID */ 398 }; 399 typedef struct disp_layer_info disp_layer_info; 400 401 struct disp_layer_config { 402 struct disp_layer_info info; 403 bool enable; 404 unsigned int channel; 405 unsigned int layer_id; 406 }; 407 typedef struct disp_layer_config disp_layer_config; 408 409 /* disp_atw_info - asynchronous time wrap infomation 410 * 411 * @used: indicate if the atw funtion is used 412 * @mode: atw mode 413 * @b_row: the row number of the micro block 414 * @b_col: the column number of the micro block 415 * @cof_fd: dma_buf fd for the buffer contaied coefficient for atw 416 */ 417 struct disp_atw_info { 418 bool used; 419 enum disp_atw_mode mode; 420 unsigned int b_row; 421 unsigned int b_col; 422 int cof_fd; 423 }; 424 typedef struct disp_atw_info disp_atw_info; 425 426 /* disp_fb_info2 - image buffer info v2 427 * 428 * @fd: dma_buf fd for frame buffer 429 * @size: size<width,height> for each buffer, unit:pixels 430 * @align: align for each buffer, unit:bytes 431 * @format: pixel format 432 * @color_space: color space 433 * @trd_right_fd: dma_buf fd for the right-eye frame buffer, 434 * valid when frame-packing 3d buffer input 435 * @pre_multiply: indicate the pixel use premultiplied alpha 436 * @crop: crop rectangle for buffer to be display 437 * @flag: indicate stereo/non-stereo buffer 438 * @scan: indicate interleave/progressive scan type, and the scan order 439 * @depth: depth perception for stereo image, only valid when stereo image input 440 * unit: pixel 441 * @fbd_en: indicate if enable fbd function 442 * @metadata_fd: dma_buf fd for the buffer contained metadata for fbc/hdr 443 * @metadata_size: the size of metadata buffer, unit:bytes 444 * @metadata_flag: the flag to indicate the type of metadata buffer 445 * 0 : no metadata 446 * 1 << 0: hdr static metadata 447 * 1 << 1: hdr dynamic metadata 448 * 1 << 4: frame buffer compress(fbc) metadata 449 * x : all type could be "or" together 450 */ 451 struct disp_fb_info2 { 452 int fd; 453 struct disp_rectsz size[3]; 454 unsigned int align[3]; 455 enum disp_pixel_format format; 456 enum disp_color_space color_space; 457 int trd_right_fd; 458 bool pre_multiply; 459 struct disp_rect64 crop; 460 enum disp_buffer_flags flags; 461 enum disp_scan_flags scan; 462 enum disp_eotf eotf; 463 int depth; 464 unsigned int fbd_en; 465 int metadata_fd; 466 unsigned int metadata_size; 467 unsigned int metadata_flag; 468 }; 469 typedef struct disp_fb_info2 disp_fb_info2; 470 471 /* disp_layer_info2 - layer info v2 472 * 473 * @mode: buffer/clolor mode, when in color mode, the layer is widthout buffer 474 * @zorder: the zorder of layer, 0~max-layer-number 475 * @alpha_mode: 476 * 0: pixel alpha; 477 * 1: global alpha 478 * 2: mixed alpha, compositing width pixel alpha before global alpha 479 * @alpha_value: global alpha value, valid when alpha_mode is not pixel alpha 480 * @screen_win: the rectangle on the screen for fb to be display 481 * @b_trd_out: indicate if 3d display output 482 * @out_trd_mode: 3d output mode, valid when b_trd_out is true 483 * @color: the color value to be display, valid when layer is in color mode 484 * @fb: the framebuffer info related width the layer, valid when in buffer mode 485 * @id: frame id, the user could get the frame-id display currently by 486 * DISP_LAYER_GET_FRAME_ID ioctl 487 * @atw: asynchronous time wrap information 488 */ 489 struct disp_layer_info2 { 490 enum disp_layer_mode mode; 491 unsigned char zorder; 492 unsigned char alpha_mode; 493 unsigned char alpha_value; 494 struct disp_rect screen_win; 495 bool b_trd_out; 496 enum disp_3d_out_mode out_trd_mode; 497 union { 498 unsigned int color; 499 struct disp_fb_info2 fb; 500 }; 501 unsigned int id; 502 struct disp_atw_info atw; 503 }; 504 505 typedef struct disp_layer_info2 disp_layer_info2; 506 507 /* disp_layer_config2 - layer config v2 508 * 509 * @info: layer info 510 * @enable: indicate to enable/disable the layer 511 * @channel: the channel index of the layer, 0~max-channel-number 512 * @layer_id: the layer index of the layer widthin it's channel 513 */ 514 struct disp_layer_config2 { 515 struct disp_layer_info2 info; 516 bool enable; 517 unsigned int channel; 518 unsigned int layer_id; 519 }; 520 typedef struct disp_layer_config2 disp_layer_config2; 521 522 struct disp_colorkey { 523 struct disp_color ck_max; 524 struct disp_color ck_min; 525 unsigned int red_match_rule; /*0/1:always match; 2:match if min<=color<=max; 3:match if color>max or color<min */ 526 unsigned int green_match_rule; /* 0/1:always match; 2:match if min<=color<=max; 3:match if color>max or color<min */ 527 unsigned int blue_match_rule; /* 0/1:always match; 2:match if min<=color<=max; 3:match if color>max or color<min */ 528 }; 529 typedef struct disp_colorkey disp_colorkey; 530 531 struct disp_s_frame { 532 enum disp_pixel_format format; 533 struct disp_rectsz size[3]; 534 struct disp_rect crop; 535 unsigned long long addr[3]; 536 }; 537 typedef struct disp_s_frame disp_s_frame; 538 539 struct disp_capture_info { 540 struct disp_rect window; /* capture window, rectangle of screen to be captured */ 541 /*capture the whole screen if window eq ZERO */ 542 struct disp_s_frame out_frame; 543 }; 544 typedef struct disp_capture_info disp_capture_info; 545 546 /* disp_s_frame2 - display simple frame buffer 547 * 548 * @format: pixel format of fb 549 * @size: size for each plane 550 * @crop: crop zone to be fill image data 551 * @fd: dma_buf fd 552 */ 553 struct disp_s_frame2 { 554 enum disp_pixel_format format; 555 struct disp_rectsz size[3]; 556 struct disp_rect crop; 557 int fd; 558 }; 559 typedef struct disp_s_frame2 disp_s_frame2; 560 561 /* disp_capture_info2 - display capture information 562 * 563 * @window: the rectange on the screen to be capture 564 * @out_frame: the framebuffer to be restore capture image data 565 */ 566 struct disp_capture_info2 { 567 struct disp_rect window; 568 struct disp_s_frame2 out_frame; 569 }; 570 typedef struct disp_capture_info2 disp_capture_info2; 571 572 struct disp_capture_fmt { 573 enum disp_pixel_format format; /* write-back ouput format, doson't support YUV ouput yet */ 574 struct disp_rect window; /* source crop */ 575 struct disp_rect crop; /* output crop */ 576 }; 577 typedef struct disp_capture_fmt disp_capture_fmt; 578 579 struct disp_capture_buffer { 580 int handle; /* Unique integer id represent this buffer */ 581 enum disp_pixel_format format; /* write-back ouput format */ 582 struct disp_rect window; /* source crop */ 583 struct disp_rect crop; /* output crop */ 584 struct disp_rectsz size[3]; 585 586 int fd; 587 int width; /* buffer width in pixels */ 588 int height; /* buffer height in pixels */ 589 }; 590 typedef struct disp_capture_buffer disp_capture_buffer; 591 592 struct disp_capture_handle { 593 int handle; /* unique integer id represent a capture buffer */ 594 int fencefd; /* fence fd for this buffer */ 595 }; 596 typedef struct disp_capture_handle disp_capture_handle; 597 598 enum disp_capture_extend_cmd { 599 DISP_CAPTURE_E_SET_FMT, 600 DISP_CAPTURE_E_BUFFER_LIST_INIT, 601 DISP_CAPTURE_E_BUFFER_LIST_CLEAR, 602 DISP_CAPTURE_E_ACQUIRE_BUFFER, 603 DISP_CAPTURE_E_RELEASE_BUFFER, 604 DISP_CAPTURE_E_CTRL, 605 }; 606 typedef enum disp_capture_extend_cmd disp_capture_extend_cmd; 607 608 /* disp_device_config - display deivce config 609 * 610 * @type: output type 611 * @mode: output mode 612 * @format: data format 613 * @bits: data bits 614 * @eotf: electro-optical transfer function 615 * SDR : DISP_EOTF_GAMMA22 616 * HDR10: DISP_EOTF_SMPTE2084 617 * HLG : DISP_EOTF_ARIB_STD_B67 618 * @cs: color space type 619 * DISP_BT601: SDR for SD resolution(< 720P) 620 * DISP_BT709: SDR for HD resolution(>= 720P) 621 * DISP_BT2020NC: HDR10 or HLG or wide-color-gamut 622 * @dvi_hdmi: output mode 623 * DVI: DISP_DVI 624 * HDMI: DISP_HDMI 625 * @range: RGB/YUV quantization range 626 * DEFUALT: limited range when sending a CE video format 627 * full range when sending an IT video format 628 * LIMITED: color limited range from 16 to 235 629 * FULL: color full range from 0 to 255 630 * @scan info: 631 * DISP_SCANINFO_NO_DATA: overscan if it is a CE format, 632 * underscan if it is an IT format 633 * OVERSCAN: composed for overscan display 634 * UNDERSCAN: composed for underscan display 635 * @aspect_ratio: active format aspect ratio 636 */ 637 struct disp_device_config { 638 enum disp_output_type type; 639 enum disp_tv_mode mode; 640 enum disp_csc_type format; 641 enum disp_data_bits bits; 642 enum disp_eotf eotf; 643 enum disp_color_space cs; 644 enum disp_dvi_hdmi dvi_hdmi; 645 enum disp_color_range range; 646 enum disp_scan_info scan; 647 unsigned int aspect_ratio; 648 unsigned int reserve1; 649 }; 650 typedef struct disp_device_config disp_device_config; 651 652 /* disp_device_dynamic_config - display deivce dynamic config 653 * 654 * @metadata_fd: dma_buf fd for the buffer contained metadata for fbc/hdr 655 * @metadata_size: the size of metadata buffer, unit:bytes 656 * @metadata_flag: the flag to indicate the type of metadata buffer 657 * 0 : no metadata 658 * 1 << 0: hdr static metadata 659 * 1 << 1: hdr dynamic metadata 660 * 1 << 4: frame buffer compress(fbc) metadata 661 * x : all type could be "or" together 662 * @vmap:vmap a block contigous phys memory into virtual space 663 * @vunmap: release virtual mapping obtained by vmap() 664 */ 665 struct disp_device_dynamic_config { 666 int metadata_fd; 667 unsigned int metadata_size; 668 unsigned int metadata_flag; 669 void *(*vmap)(unsigned long phys_addr, unsigned long size); 670 void (*vunmap)(const void *vaddr); 671 }; 672 typedef struct disp_device_dynamic_config disp_device_dynamic_config; 673 674 struct disp_video_timings { 675 unsigned int vic; /* video infomation code */ 676 unsigned int tv_mode; 677 unsigned int pixel_clk; 678 unsigned int pixel_repeat; /* pixel repeat (pixel_repeat+1) times */ 679 unsigned int x_res; 680 unsigned int y_res; 681 unsigned int hor_total_time; 682 unsigned int hor_back_porch; 683 unsigned int hor_front_porch; 684 unsigned int hor_sync_time; 685 unsigned int ver_total_time; /* lines of a frame */ 686 unsigned int ver_back_porch; 687 unsigned int ver_front_porch; 688 unsigned int ver_sync_time; 689 unsigned int hor_sync_polarity; /* 0: negative, 1: positive */ 690 unsigned int ver_sync_polarity; /* 0: negative, 1: positive */ 691 bool b_interlace; 692 unsigned int vactive_space; 693 unsigned int trd_mode; 694 695 unsigned long dclk_rate_set; /*unit: hz */ 696 unsigned long long frame_period; /* unit: ns */ 697 int start_delay; /* unit: line */ 698 }; 699 typedef struct disp_video_timings disp_video_timings; 700 701 enum disp_fb_mode { 702 FB_MODE_SCREEN0 = 0, 703 FB_MODE_SCREEN1 = 1, 704 FB_MODE_SCREEN2 = 2, 705 FB_MODE_DUAL_SAME_SCREEN_TB = 3, /* two screen, top buffer for screen0, bottom buffer for screen1 */ 706 FB_MODE_DUAL_DIFF_SCREEN_SAME_CONTENTS = 4, /* two screen, they have same contents; */ 707 }; 708 typedef enum disp_fb_mode disp_fb_mode; 709 710 struct disp_fb_create_info { 711 enum disp_fb_mode fb_mode; 712 enum disp_layer_mode mode; 713 unsigned int buffer_num; 714 unsigned int width; 715 unsigned int height; 716 717 unsigned int output_width; /* used when scaler mode */ 718 unsigned int output_height; /* used when scaler mode */ 719 }; 720 typedef struct disp_fb_create_info disp_fb_create_info; 721 722 enum disp_init_mode { 723 DISP_INIT_MODE_SCREEN0 = 0, /* fb0 for screen0 */ 724 DISP_INIT_MODE_SCREEN1 = 1, /* fb0 for screen1 */ 725 DISP_INIT_MODE_SCREEN2 = 2, /* fb0 for screen1 */ 726 DISP_INIT_MODE_TWO_DIFF_SCREEN = 3, /* fb0 for screen0 and fb1 for screen1 */ 727 DISP_INIT_MODE_TWO_SAME_SCREEN = 4, /* fb0(up buffer for screen0, down buffer for screen1) */ 728 DISP_INIT_MODE_TWO_DIFF_SCREEN_SAME_CONTENTS = 5, /* fb0 for two different screen(screen0 layer is normal layer, screen1 layer is scaler layer); */ 729 }; 730 typedef enum disp_init_mode disp_init_mode; 731 732 struct disp_tv_func { 733 int (*tv_enable)(u32 sel); 734 int (*tv_disable)(u32 sel); 735 int (*tv_suspend)(u32 sel); 736 int (*tv_resume)(u32 sel); 737 int (*tv_get_mode)(u32 sel); 738 int (*tv_set_mode)(u32 sel, enum disp_tv_mode tv_mod); 739 int (*tv_get_input_csc) (u32 sel); 740 int (*tv_get_video_timing_info) (u32 sel, struct disp_video_timings **video_info); 741 int (*tv_mode_support) (u32 sel, enum disp_tv_mode mode); 742 int (*tv_hot_plugging_detect)(u32 state); 743 int (*tv_set_enhance_mode)(u32 sel, u32 mode); 744 int (*tv_irq_enable)(u32 sel, u32 irq_id, u32 en); 745 int (*tv_irq_query)(u32 sel); 746 int (*tv_get_startdelay)(u32 sel); 747 int (*tv_get_cur_line)(u32 sel); 748 }; 749 typedef struct disp_tv_func disp_tv_func; 750 751 /* disp_vdevice_interface_para - vdevice interaface parameter 752 * 753 * @intf:interface 754 * 0:hv, 1:cpu, 3:lvds, 4:dsi 755 * @sub_intf: sub interface 756 * rgb interface: 0:parallel hv, 8:serial hv, 10:dummy rgb, 11: rgb dummy, 12: ccir656 757 * cpu interface: 0:18 pin, 10:9pin, 12:6pin, 8:16pin, 14:8pin 758 * lvds interface:0:single link, 1:dual link 759 * dsi inerafce: 0:video mode, 1:command mode, 2: video burst mode 760 * @sequence:output sequence 761 * rgb output: 0:rgb rgb, 1:rgb brg, 2:rgb gbr, 4:brg rgb, 5:brg brg, 6:brg gbr 762 * 8:grb rgb, 9:grb brg, 10:grb gbr 763 * yuv output:0:yuyv, 1: yvyu, 2:uyvy, 3:vyuy 764 * @fdelay:yuv eav/sav F line delay 765 * 0: F toggle right after active video line 766 * 1: delay 2 line(CCIR NTSC) 767 * 2: delay 3 line(CCIR PAL) 768 * @clk_phase:clk phase 769 * 0: 0 degree, 1:90 degree, 2: 180 degree, 3:270 degree 770 * @sync_polarity:sync signals polarity 771 * 0: vsync active low,hsync active low 772 * 1: vsync active high,hsync active low 773 * 2: vsync active low,hsync active high 774 * 3: vsync active high,hsync active high 775 * @ccir_clk_div:the divide number of tcon_lcd's clk freq 776 * @input_csc:colorspace type of video source 777 */ 778 struct disp_vdevice_interface_para { 779 unsigned int intf; 780 unsigned int sub_intf; 781 unsigned int sequence; 782 unsigned int fdelay; 783 unsigned int clk_phase; 784 unsigned int sync_polarity; 785 unsigned int ccir_clk_div; 786 unsigned int input_csc; 787 }; 788 typedef struct disp_vdevice_interface_para disp_vdevice_interface_para; 789 790 struct disp_vdevice_source_ops { 791 int (*tcon_enable)(struct disp_device *dispdev); 792 int (*tcon_disable)(struct disp_device *dispdev); 793 int (*tcon_simple_enable)(struct disp_device *dispdev); 794 int (*tcon_simple_disable)(struct disp_device *dispdev); 795 }; 796 typedef struct disp_vdevice_source_ops disp_vdevice_source_ops; 797 798 struct disp_device_func { 799 int (*enable)(void); 800 int (*disable)(void); 801 int (*set_mode)(u32 mode); 802 int (*mode_support)(u32 mode); 803 int (*get_HPD_status)(void); 804 int (*get_input_csc)(void); 805 int (*get_video_timing_info)(struct disp_video_timings **video_info); 806 int (*suspend)(void); 807 int (*resume)(void); 808 int (*early_suspend)(void); 809 int (*late_resume)(void); 810 int (*get_interface_para)(void *para); 811 int (*set_static_config)(struct disp_device_config *config); 812 int (*get_static_config)(struct disp_device_config *config); 813 int (*set_dynamic_config)(struct disp_device_dynamic_config *config); 814 int (*get_dynamic_config)(struct disp_device_dynamic_config *config); 815 }; 816 typedef struct disp_device_func disp_device_func; 817 818 struct disp_vdevice_init_data { 819 char name[32]; 820 u32 disp; 821 u32 fix_timing; 822 enum disp_output_type type; 823 struct disp_device_func func; 824 }; 825 typedef struct disp_vdevice_init_data disp_vdevice_init_data; 826 827 enum disp_tv_dac_source { 828 DISP_TV_DAC_SRC_COMPOSITE = 0, 829 DISP_TV_DAC_SRC_LUMA = 1, 830 DISP_TV_DAC_SRC_CHROMA = 2, 831 DISP_TV_DAC_SRC_Y = 4, 832 DISP_TV_DAC_SRC_PB = 5, 833 DISP_TV_DAC_SRC_PR = 6, 834 DISP_TV_DAC_SRC_NONE = 7, 835 }; 836 typedef enum disp_tv_dac_source disp_tv_dac_source; 837 838 enum disp_tv_output { 839 DISP_TV_NONE = 0, 840 DISP_TV_CVBS = 1, 841 DISP_TV_YPBPR = 2, 842 DISP_TV_SVIDEO = 4, 843 DISP_VGA = 5, 844 }; 845 typedef enum disp_tv_output disp_tv_output; 846 847 enum tag_DISP_CMD { 848 /* ----disp global---- */ 849 DISP_RESERVE0 = 0x00, 850 DISP_RESERVE1 = 0x01, 851 DISP_SET_BKCOLOR = 0x03, 852 DISP_GET_BKCOLOR = 0x04, 853 DISP_SET_COLORKEY = 0x05, 854 DISP_GET_COLORKEY = 0x06, 855 DISP_GET_SCN_WIDTH = 0x07, 856 DISP_GET_SCN_HEIGHT = 0x08, 857 DISP_GET_OUTPUT_TYPE = 0x09, 858 DISP_SET_EXIT_MODE = 0x0A, 859 DISP_VSYNC_EVENT_EN = 0x0B, 860 DISP_BLANK = 0x0C, 861 DISP_SHADOW_PROTECT = 0x0D, 862 DISP_HWC_COMMIT = 0x0E, 863 DISP_DEVICE_SWITCH = 0x0F, 864 DISP_GET_OUTPUT = 0x10, 865 DISP_SET_COLOR_RANGE = 0x11, 866 DISP_GET_COLOR_RANGE = 0x12, 867 DISP_HWC_CUSTOM = 0x13, 868 DISP_DEVICE_SET_CONFIG = 0x14, 869 DISP_DEVICE_GET_CONFIG = 0x15, 870 871 /* ----layer---- */ 872 DISP_LAYER_ENABLE = 0x40, 873 DISP_LAYER_DISABLE = 0x41, 874 DISP_LAYER_SET_INFO = 0x42, 875 DISP_LAYER_GET_INFO = 0x43, 876 DISP_LAYER_TOP = 0x44, 877 DISP_LAYER_BOTTOM = 0x45, 878 DISP_LAYER_GET_FRAME_ID = 0x46, 879 DISP_LAYER_SET_CONFIG = 0x47, 880 DISP_LAYER_GET_CONFIG = 0x48, 881 /* 882 * LAYER_S(G)ET_CONFIG2 takes disp_layer_config2, 883 * it will support more featuras 884 */ 885 DISP_LAYER_SET_CONFIG2 = 0x49, 886 DISP_LAYER_GET_CONFIG2 = 0x4a, 887 888 /* ----hdmi---- */ 889 DISP_HDMI_SUPPORT_MODE = 0xc4, 890 DISP_SET_TV_HPD = 0xc5, 891 DISP_HDMI_GET_EDID = 0xc6, 892 893 /* ----lcd---- */ 894 DISP_LCD_ENABLE = 0x100, 895 DISP_LCD_DISABLE = 0x101, 896 DISP_LCD_SET_BRIGHTNESS = 0x102, 897 DISP_LCD_GET_BRIGHTNESS = 0x103, 898 DISP_LCD_BACKLIGHT_ENABLE = 0x104, 899 DISP_LCD_BACKLIGHT_DISABLE = 0x105, 900 DISP_LCD_SET_SRC = 0x106, 901 DISP_LCD_SET_FPS = 0x107, 902 DISP_LCD_GET_FPS = 0x108, 903 DISP_LCD_GET_SIZE = 0x109, 904 DISP_LCD_GET_MODEL_NAME = 0x10a, 905 DISP_LCD_SET_GAMMA_TABLE = 0x10b, 906 DISP_LCD_GAMMA_CORRECTION_ENABLE = 0x10c, 907 DISP_LCD_GAMMA_CORRECTION_DISABLE = 0x10d, 908 DISP_LCD_USER_DEFINED_FUNC = 0x10e, 909 DISP_LCD_CHECK_OPEN_FINISH = 0x10f, 910 DISP_LCD_CHECK_CLOSE_FINISH = 0x110, 911 912 /* tv */ 913 DISP_TV_SET_GAMMA_TABLE = 0x111, 914 915 /* ---- capture --- */ 916 DISP_CAPTURE_START = 0x140,//caputre screen and scaler to dram 917 DISP_CAPTURE_STOP = 0x141, 918 DISP_CAPTURE_COMMIT = 0x142, 919 DISP_CAPTURE_COMMIT2 = 0x143, 920 DISP_CAPTURE_QUERY = 0x144, 921 DISP_CAPTURE_EXTEND = 0x145, 922 923 //---enhance --- 924 DISP_ENHANCE_ENABLE = 0x180, 925 DISP_ENHANCE_DISABLE = 0x181, 926 DISP_ENHANCE_GET_EN = 0x182, 927 DISP_ENHANCE_SET_WINDOW = 0x183, 928 DISP_ENHANCE_GET_WINDOW = 0x184, 929 DISP_ENHANCE_SET_MODE = 0x185, 930 DISP_ENHANCE_GET_MODE = 0x186, 931 DISP_ENHANCE_DEMO_ENABLE = 0x187, 932 DISP_ENHANCE_DEMO_DISABLE = 0x188, 933 934 /* ---smart backlight --- */ 935 DISP_SMBL_ENABLE = 0x200, 936 DISP_SMBL_DISABLE = 0x201, 937 DISP_SMBL_GET_EN = 0x202, 938 DISP_SMBL_SET_WINDOW = 0x203, 939 DISP_SMBL_GET_WINDOW = 0x204, 940 941 /* ---- for test */ 942 DISP_FB_REQUEST = 0x280, 943 DISP_FB_RELEASE = 0x281, 944 945 DISP_MEM_REQUEST = 0x2c0, 946 DISP_MEM_RELEASE = 0x2c1, 947 DISP_MEM_GETADR = 0x2c2, 948 949 DISP_EINK_UPDATE = 0x402, 950 DISP_EINK_SET_TEMP = 0x403, 951 DISP_EINK_GET_TEMP = 0x404, 952 DISP_EINK_OVERLAP_SKIP = 0x405, 953 }; 954 typedef enum tag_DISP_CMD tag_DISP_CMD; 955 956 #define FBIOGET_LAYER_HDL_0 0x4700 957 #define FBIOGET_LAYER_HDL_1 0x4701 958 959 #endif 960 961