1 // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 /* 3 * Copyright (C) 2020 frank@allwinnertech.com 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_SUN50IW9_H_ 7 #define _DT_BINDINGS_CLK_SUN50IW9_H_ 8 9 #define CLK_OSC12M 0 10 #define CLK_PLL_CPUX 1 11 #define CLK_PLL_DDR0 2 12 #define CLK_PLL_DDR1 3 13 #define CLK_PLL_PERIPH0 4 14 #define CLK_PLL_PERIPH0_2X 5 15 #define CLK_PLL_PERIPH1 6 16 #define CLK_PLL_PERIPH1_2X 7 17 #define CLK_PLL_GPU 8 18 #define CLK_PLL_VIDEO0 9 19 #define CLK_PLL_VIDEO0_4X 10 20 #define CLK_PLL_VIDEO1 11 21 #define CLK_PLL_VIDEO1_4X 12 22 #define CLK_PLL_VIDEO2 13 23 #define CLK_PLL_VIDEO2_4X 14 24 #define CLK_PLL_VE 15 25 #define CLK_PLL_DE 16 26 #define CLK_PLL_AUDIO 17 27 #define CLK_PLL_AUDIO_2X 18 28 #define CLK_PLL_AUDIO_4X 19 29 #define CLK_PLL_CSI 20 30 #define CLK_CPUX 21 31 #define CLK_AXI 22 32 #define CLK_CPUX_APB 23 33 #define CLK_PSI_AHB1_AHB2 24 34 #define CLK_AHB3 25 35 #define CLK_APB1 26 36 #define CLK_APB2 27 37 #define CLK_MBUS 28 38 #define CLK_DE 29 39 #define CLK_BUS_DE 30 40 #define CLK_DI 31 41 #define CLK_BUS_DI 32 42 #define CLK_G2D 33 43 #define CLK_BUS_G2D 34 44 #define CLK_GPU0 35 45 #define CLK_GPU1 36 46 #define CLK_BUS_GPU 37 47 #define CLK_CE 38 48 #define CLK_BUS_CE 39 49 #define CLK_VE 40 50 #define CLK_BUS_VE 41 51 #define CLK_BUS_DMA 42 52 #define CLK_BUS_HSTIMER 43 53 #define CLK_AVS 44 54 #define CLK_BUS_DBG 45 55 #define CLK_BUS_PSI 46 56 #define CLK_BUS_PWM 47 57 #define CLK_BUS_IOMMU 48 58 #define CLK_DRAM 49 59 #define CLK_MBUS_DMA 50 60 #define CLK_MBUS_VE 51 61 #define CLK_MBUS_CE 52 62 #define CLK_MBUS_TS 53 63 #define CLK_MBUS_NAND 54 64 #define CLK_MBUS_CSI 55 65 #define CLK_MBUS_G2D 56 66 #define CLK_BUS_DRAM 57 67 #define CLK_NAND0 58 68 #define CLK_NAND1 59 69 #define CLK_BUS_NAND 60 70 #define CLK_MMC0 61 71 #define CLK_MMC1 62 72 #define CLK_MMC2 63 73 #define CLK_BUS_MMC0 64 74 #define CLK_BUS_MMC1 65 75 #define CLK_BUS_MMC2 66 76 #define CLK_BUS_UART0 67 77 #define CLK_BUS_UART1 68 78 #define CLK_BUS_UART2 69 79 #define CLK_BUS_UART3 70 80 #define CLK_BUS_UART4 71 81 #define CLK_BUS_UART5 72 82 #define CLK_BUS_I2C0 73 83 #define CLK_BUS_I2C1 74 84 #define CLK_BUS_I2C2 75 85 #define CLK_BUS_I2C3 76 86 #define CLK_BUS_I2C4 77 87 #define CLK_BUS_SCR 78 88 #define CLK_SPI0 79 89 #define CLK_SPI1 80 90 #define CLK_BUS_SPI0 81 91 #define CLK_BUS_SPI1 82 92 #define CLK_EMAC_25M 83 93 #define CLK_BUS_EMAC0 84 94 #define CLK_BUS_EMAC1 85 95 #define CLK_TS 86 96 #define CLK_BUS_TS 87 97 #define CLK_BUS_GPADC 88 98 #define CLK_BUS_THS 89 99 #define CLK_SPDIF 90 100 #define CLK_BUS_SPDIF 91 101 #define CLK_DMIC 92 102 #define CLK_BUS_DMIC 93 103 #define CLK_AUDIO 94 104 #define CLK_AUDIO_4X 95 105 #define CLK_BUS_AUDIO_CODEC 96 106 #define CLK_AUDIO_HUB 97 107 #define CLK_BUS_AUDIO_HUB 98 108 #define CLK_USB_OHCI0 99 109 #define CLK_USB_PHY0 100 110 #define CLK_USB_OHCI1 101 111 #define CLK_USB_PHY1 102 112 #define CLK_USB_OHCI2 103 113 #define CLK_USB_PHY2 104 114 #define CLK_USB_OHCI3 105 115 #define CLK_USB_PHY3 106 116 #define CLK_BUS_OHCI0 107 117 #define CLK_BUS_OHCI1 108 118 #define CLK_BUS_OHCI2 109 119 #define CLK_BUS_OHCI3 110 120 #define CLK_BUS_EHCI0 111 121 #define CLK_BUS_EHCI1 112 122 #define CLK_BUS_EHCI2 113 123 #define CLK_BUS_EHCI3 114 124 #define CLK_BUS_OTG 115 125 #define CLK_BUS_LRADC 116 126 #define CLK_HDMI 117 127 #define CLK_HDMI_SLOW 118 128 #define CLK_PLL_PERIPH0_2X_DIV 119 129 #define CLK_HDMI_CEC 120 130 #define CLK_BUS_HDMI 121 131 #define CLK_BUS_DISPLAY_IF_TOP 122 132 #define CLK_TCON_LCD0 123 133 #define CLK_TCON_LCD1 124 134 #define CLK_BUS_TCON_LCD0 125 135 #define CLK_BUS_TCON_LCD1 126 136 #define CLK_TCON_TV0 127 137 #define CLK_TCON_TV1 128 138 #define CLK_BUS_TCON_TV0 129 139 #define CLK_BUS_TCON_TV1 130 140 #define CLK_TVE 131 141 #define CLK_BUS_TVE 132 142 #define CLK_BUS_TVE_TOP 133 143 #define CLK_CSI_TOP 134 144 #define CLK_CSI0_MCLK 135 145 #define CLK_CSI1_MCLK 136 146 #define CLK_BUS_CSI 137 147 #define CLK_HDMI_HDCP 138 148 #define CLK_BUS_HDMI_HDCP 139 149 150 #endif /* _DT_BINDINGS_CLK_SUN50IW9_H_ */ 151