1 // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 /* 3 * Copyright (C) 2020 huangzhenwei@allwinnertech.com 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_SUN8IW20_H_ 7 #define _DT_BINDINGS_CLK_SUN8IW20_H_ 8 9 #define CLK_OSC12M 0 10 #define CLK_PLL_CPUX 1 11 #define CLK_PLL_DDR0 2 12 #define CLK_PLL_PERIPH0_PARENT 3 13 #define CLK_PLL_PERIPH0 4 14 #define CLK_PLL_PERIPH0_2X 5 15 #define CLK_PLL_PERIPH0_800M 6 16 #define CLK_PLL_PERIPH0_DIV3 7 17 #define CLK_PLL_VIDEO0 8 18 #define CLK_PLL_VIDEO0_2X 9 19 #define CLK_PLL_VIDEO0_4X 10 20 #define CLK_PLL_VIDEO1 11 21 #define CLK_PLL_VIDEO1_2X 12 22 #define CLK_PLL_VIDEO1_4X 13 23 #define CLK_PLL_VE 14 24 #define CLK_PLL_AUDIO0 15 25 #define CLK_PLL_AUDIO0_2X 16 26 #define CLK_PLL_AUDIO0_4X 17 27 #define CLK_PLL_AUDIO1 18 28 #define CLK_PLL_AUDIO1_DIV2 19 29 #define CLK_PLL_AUDIO1_DIV5 20 30 #define CLK_PLL_CPUX_DIV 21 31 #define CLK_CPUX 22 32 #define CLK_AXI 23 33 #define CLK_APB 24 34 #define CLK_PSI_AHB 25 35 #define CLK_APB0 26 36 #define CLK_APB1 27 37 #define CLK_MBUS 28 38 #define CLK_DE0 29 39 #define CLK_BUS_DE0 30 40 #define CLK_DI 31 41 #define CLK_BUS_DI 32 42 #define CLK_G2D 33 43 #define CLK_BUS_G2D 34 44 #define CLK_CE 35 45 #define CLK_BUS_CE 36 46 #define CLK_VE 37 47 #define CLK_BUS_VE 38 48 #define CLK_BUS_DMA 39 49 #define CLK_BUS_MSGBOX0 40 50 #define CLK_BUS_MSGBOX1 41 51 #define CLK_BUS_MSGBOX2 42 52 #define CLK_BUS_SPINLOCK 43 53 #define CLK_BUS_HSTIMER 44 54 #define CLK_AVS 45 55 #define CLK_BUS_DBG 46 56 #define CLK_BUS_PWM 47 57 #define CLK_BUS_IOMMU 48 58 #define CLK_DRAM 49 59 #define CLK_MBUS_DMA 50 60 #define CLK_MBUS_VE 51 61 #define CLK_MBUS_CE 52 62 #define CLK_MBUS_TVIN 53 63 #define CLK_MBUS_CSI 54 64 #define CLK_MBUS_G2D 55 65 #define CLK_BUS_DRAM 56 66 #define CLK_MMC0 57 67 #define CLK_MMC1 58 68 #define CLK_MMC2 59 69 #define CLK_BUS_MMC0 60 70 #define CLK_BUS_MMC1 61 71 #define CLK_BUS_MMC2 62 72 #define CLK_BUS_UART0 63 73 #define CLK_BUS_UART1 64 74 #define CLK_BUS_UART2 65 75 #define CLK_BUS_UART3 66 76 #define CLK_BUS_UART4 67 77 #define CLK_BUS_UART5 68 78 #define CLK_BUS_I2C0 69 79 #define CLK_BUS_I2C1 70 80 #define CLK_BUS_I2C2 71 81 #define CLK_BUS_I2C3 72 82 #define CLK_SPI0 75 83 #define CLK_SPI1 76 84 #define CLK_BUS_SPI0 77 85 #define CLK_BUS_SPI1 78 86 #define CLK_EMAC0_25M 79 87 #define CLK_BUS_EMAC0 80 88 #define CLK_IR_TX 81 89 #define CLK_BUS_IR_TX 82 90 #define CLK_BUS_GPADC 83 91 #define CLK_BUS_THS 84 92 #define CLK_I2S0 85 93 #define CLK_I2S1 86 94 #define CLK_I2S2 87 95 #define CLK_I2S2_ASRC 88 96 #define CLK_BUS_I2S0 89 97 #define CLK_BUS_I2S1 90 98 #define CLK_BUS_I2S2 91 99 #define CLK_SPDIF_TX 92 100 #define CLK_SPDIF_RX 93 101 #define CLK_BUS_SPDIF 94 102 #define CLK_DMIC 95 103 #define CLK_BUS_DMIC 96 104 #define CLK_AUDIO_DAC 97 105 #define CLK_AUDIO_ADC 98 106 #define CLK_BUS_AUDIO_CODEC 99 107 #define CLK_USB_OHCI0 100 108 #define CLK_USB_OHCI1 101 109 #define CLK_BUS_OHCI0 102 110 #define CLK_BUS_OHCI1 103 111 #define CLK_BUS_EHCI0 104 112 #define CLK_BUS_EHCI1 105 113 #define CLK_BUS_OTG 106 114 #define CLK_BUS_LRADC 107 115 #define CLK_BUS_DPSS_TOP0 108 116 #define CLK_HDMI_24M 109 117 #define CLK_HDMI_CEC 110 118 #define CLK_HDMI_CEC_32K 111 119 #define CLK_BUS_HDMI 112 120 #define CLK_MIPI_DSI 113 121 #define CLK_BUS_MIPI_DSI 114 122 #define CLK_TCON_LCD0 115 123 #define CLK_BUS_TCON_LCD0 116 124 #define CLK_TCON_TV 117 125 #define CLK_BUS_TCON_TV 118 126 #define CLK_TVE 119 127 #define CLK_BUS_TVE 120 128 #define CLK_BUS_TVE_TOP 121 129 #define CLK_TVD 122 130 #define CLK_BUS_TVD 123 131 #define CLK_BUS_TVD_TOP 124 132 #define CLK_LEDC 125 133 #define CLK_BUS_LEDC 126 134 #define CLK_CSI_TOP 127 135 #define CLK_CSI0_MCLK 128 136 #define CLK_BUS_CSI 129 137 #define CLK_TPADC 130 138 #define CLK_BUS_TPADC 131 139 #define CLK_BUS_TZMA 132 140 #define CLK_DSP 133 141 #define CLK_BUS_DSP_CFG 134 142 #define CLK_RISCV 135 143 #define CLK_RISCV_AXI 136 144 #define CLK_BUS_RISCV_CFG 137 145 #define CLK_FANOUT_24M 138 146 #define CLK_FANOUT_12M 139 147 #define CLK_FANOUT_16M 140 148 #define CLK_FANOUT_25M 141 149 #define CLK_FANOUT_32K 142 150 #define CLK_FANOUT_27M 143 151 #define CLK_FANOUT_PCLK 144 152 #define CLK_FANOUT0_OUT 145 153 #define CLK_FANOUT1_OUT 146 154 #define CLK_FANOUT2_OUT 147 155 156 #define CLK_MAX_NO CLK_FANOUT2_OUT 157 158 #endif /* _DT_BINDINGS_CLK_SUN8IW20_H_ */ 159