1 // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 /* 3 * Copyright (C) 2020 frank@allwinnertech.com 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_SUN50IW12_H_ 7 #define _DT_BINDINGS_RESET_SUN50IW12_H_ 8 9 #define RST_MBUS 0 10 #define RST_BUS_MIPS 1 11 #define RST_BUS_MIPS_COLD 2 12 #define RST_BUS_MIPS_SOFT 3 13 #define RST_BUS_GPU 4 14 #define RST_BUS_CE 5 15 #define RST_BUS_CE_SYS 6 16 #define RST_BUS_VE 7 17 #define RST_BUS_AV1 8 18 #define RST_BUS_VE3 9 19 #define RST_BUS_DMA 10 20 #define RST_BUS_MSGBOX 11 21 #define RST_BUS_SPINLOCK 12 22 #define RST_BUS_TIMER0 13 23 #define RST_BUS_DBGSYS 14 24 #define RST_BUS_PWM 15 25 #define RST_BUS_DRAM_MODULE 16 26 #define RST_BUS_DRAM 17 27 #define RST_BUS_NAND 18 28 #define RST_BUS_MMC0 19 29 #define RST_BUS_MMC1 20 30 #define RST_BUS_MMC2 21 31 #define RST_BUS_UART0 22 32 #define RST_BUS_UART1 23 33 #define RST_BUS_UART2 24 34 #define RST_BUS_UART3 25 35 #define RST_BUS_UART4 26 36 #define RST_BUS_I2C0 27 37 #define RST_BUS_I2C1 28 38 #define RST_BUS_I2C2 29 39 #define RST_BUS_I2C3 30 40 #define RST_BUS_SPI0 31 41 #define RST_BUS_SPI1 32 42 #define RST_BUS_EMAC 33 43 #define RST_BUS_GPADC 34 44 #define RST_BUS_THS 35 45 #define RST_BUS_I2S0 36 46 #define RST_BUS_I2S1 37 47 #define RST_BUS_I2S2 38 48 #define RST_BUS_SPDIF0 39 49 #define RST_BUS_SPDIF1 40 50 #define RST_BUS_AUDIO_HUB 41 51 #define RST_BUS_AUDIO_CODEC 42 52 #define RST_USB_PHY0 43 53 #define RST_USB_PHY1 44 54 #define RST_USB_PHY2 45 55 #define RST_BUS_OHCI0 46 56 #define RST_BUS_OHCI1 47 57 #define RST_BUS_OHCI2 48 58 #define RST_BUS_EHCI0 49 59 #define RST_BUS_EHCI1 50 60 #define RST_BUS_EHCI2 51 61 #define RST_BUS_OTG 52 62 #define RST_BUS_LRADC 53 63 #define RST_BUS_LVDS 54 64 #define RST_BUS_DEMOD 55 65 #define RST_BUS_TVCAP 56 66 #define RST_BUS_DISP 57 67 68 #endif /* _DT_BINDINGS_RESET_SUN50IW12_H_ */ 69