1/dts-v1/; 2 3/ { 4 compatible = "rockchip,rk3566-evb2-lp4x-v10\0rockchip,rk3566"; 5 interrupt-parent = <0x01>; 6 #address-cells = <0x02>; 7 #size-cells = <0x02>; 8 model = "Rockchip RK3566 EVB2 LP4X V10 Board"; 9 10 ddr_timing { 11 compatible = "rockchip,ddr-timing"; 12 ddr2_speed_bin = <0x00>; 13 ddr3_speed_bin = <0x15>; 14 ddr4_speed_bin = <0x0c>; 15 pd_idle = <0x0d>; 16 sr_idle = <0x5d>; 17 sr_mc_gate_idle = <0x00>; 18 srpd_lite_idle = <0x00>; 19 standby_idle = <0x00>; 20 auto_pd_dis_freq = <0x42a>; 21 auto_sr_dis_freq = <0x320>; 22 ddr2_dll_dis_freq = <0x12c>; 23 ddr3_dll_dis_freq = <0x12c>; 24 ddr4_dll_dis_freq = <0x271>; 25 phy_dll_dis_freq = <0x190>; 26 ddr2_odt_dis_freq = <0x64>; 27 phy_ddr2_odt_dis_freq = <0x64>; 28 ddr2_drv = <0x02>; 29 ddr2_odt = <0x40>; 30 phy_ddr2_ca_drv = <0x00>; 31 phy_ddr2_ck_drv = <0x00>; 32 phy_ddr2_dq_drv = <0x00>; 33 phy_ddr2_odt = <0x00>; 34 ddr3_odt_dis_freq = <0x14d>; 35 phy_ddr3_odt_dis_freq = <0x14d>; 36 ddr3_drv = <0x02>; 37 ddr3_odt = <0x40>; 38 phy_ddr3_ca_drv = <0x00>; 39 phy_ddr3_ck_drv = <0x00>; 40 phy_ddr3_dq_drv = <0x00>; 41 phy_ddr3_odt = <0x00>; 42 phy_lpddr2_odt_dis_freq = <0x14d>; 43 lpddr2_drv = <0x02>; 44 phy_lpddr2_ca_drv = <0x00>; 45 phy_lpddr2_ck_drv = <0x00>; 46 phy_lpddr2_dq_drv = <0x00>; 47 phy_lpddr2_odt = <0x00>; 48 lpddr3_odt_dis_freq = <0x14d>; 49 phy_lpddr3_odt_dis_freq = <0x14d>; 50 lpddr3_drv = <0x01>; 51 lpddr3_odt = <0x02>; 52 phy_lpddr3_ca_drv = <0x00>; 53 phy_lpddr3_ck_drv = <0x00>; 54 phy_lpddr3_dq_drv = <0x00>; 55 phy_lpddr3_odt = <0x00>; 56 lpddr4_odt_dis_freq = <0x14d>; 57 phy_lpddr4_odt_dis_freq = <0x14d>; 58 lpddr4_drv = <0x30>; 59 lpddr4_dq_odt = <0x01>; 60 lpddr4_ca_odt = <0x00>; 61 phy_lpddr4_ca_drv = <0x00>; 62 phy_lpddr4_ck_cs_drv = <0x00>; 63 phy_lpddr4_dq_drv = <0x00>; 64 phy_lpddr4_odt = <0x00>; 65 ddr4_odt_dis_freq = <0x271>; 66 phy_ddr4_odt_dis_freq = <0x271>; 67 ddr4_drv = <0x00>; 68 ddr4_odt = <0x200>; 69 phy_ddr4_ca_drv = <0x00>; 70 phy_ddr4_ck_drv = <0x00>; 71 phy_ddr4_dq_drv = <0x00>; 72 phy_ddr4_odt = <0x00>; 73 phandle = <0xa8>; 74 }; 75 76 aliases { 77 csi2dphy0 = "/csi2-dphy0"; 78 csi2dphy1 = "/csi2-dphy1"; 79 csi2dphy2 = "/csi2-dphy2"; 80 dsi0 = "/dsi@fe060000"; 81 dsi1 = "/dsi@fe070000"; 82 ethernet0 = "/ethernet@fe2a0000"; 83 ethernet1 = "/ethernet@fe010000"; 84 gpio0 = "/pinctrl/gpio0@fdd60000"; 85 gpio1 = "/pinctrl/gpio1@fe740000"; 86 gpio2 = "/pinctrl/gpio2@fe750000"; 87 gpio3 = "/pinctrl/gpio3@fe760000"; 88 gpio4 = "/pinctrl/gpio4@fe770000"; 89 i2c0 = "/i2c@fdd40000"; 90 i2c1 = "/i2c@fe5a0000"; 91 i2c2 = "/i2c@fe5b0000"; 92 i2c3 = "/i2c@fe5c0000"; 93 i2c4 = "/i2c@fe5d0000"; 94 i2c5 = "/i2c@fe5e0000"; 95 mmc0 = "/sdhci@fe310000"; 96 mmc1 = "/dwmmc@fe2b0000"; 97 mmc2 = "/dwmmc@fe2c0000"; 98 mmc3 = "/dwmmc@fe000000"; 99 serial0 = "/serial@fdd50000"; 100 serial1 = "/serial@fe650000"; 101 serial2 = "/serial@fe660000"; 102 serial3 = "/serial@fe670000"; 103 serial4 = "/serial@fe680000"; 104 serial5 = "/serial@fe690000"; 105 serial6 = "/serial@fe6a0000"; 106 serial7 = "/serial@fe6b0000"; 107 serial8 = "/serial@fe6c0000"; 108 serial9 = "/serial@fe6d0000"; 109 spi0 = "/spi@fe610000"; 110 spi1 = "/spi@fe620000"; 111 spi2 = "/spi@fe630000"; 112 spi3 = "/spi@fe640000"; 113 }; 114 115 cpus { 116 #address-cells = <0x02>; 117 #size-cells = <0x00>; 118 119 cpu@0 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a55"; 122 reg = <0x00 0x00>; 123 enable-method = "psci"; 124 clocks = <0x02 0x00>; 125 operating-points-v2 = <0x03>; 126 cpu-idle-states = <0x04>; 127 #cooling-cells = <0x02>; 128 dynamic-power-coefficient = <0xbb>; 129 cpu-supply = <0x05>; 130 phandle = <0x09>; 131 }; 132 133 cpu@100 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x00 0x100>; 137 enable-method = "psci"; 138 clocks = <0x02 0x00>; 139 operating-points-v2 = <0x03>; 140 cpu-idle-states = <0x04>; 141 phandle = <0x0a>; 142 }; 143 144 cpu@200 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a55"; 147 reg = <0x00 0x200>; 148 enable-method = "psci"; 149 clocks = <0x02 0x00>; 150 operating-points-v2 = <0x03>; 151 cpu-idle-states = <0x04>; 152 phandle = <0x0b>; 153 }; 154 155 cpu@300 { 156 device_type = "cpu"; 157 compatible = "arm,cortex-a55"; 158 reg = <0x00 0x300>; 159 enable-method = "psci"; 160 clocks = <0x02 0x00>; 161 operating-points-v2 = <0x03>; 162 cpu-idle-states = <0x04>; 163 phandle = <0x0c>; 164 }; 165 166 idle-states { 167 entry-method = "psci"; 168 169 cpu-sleep { 170 compatible = "arm,idle-state"; 171 local-timer-stop; 172 arm,psci-suspend-param = <0x10000>; 173 entry-latency-us = <0x64>; 174 exit-latency-us = <0x78>; 175 min-residency-us = <0x3e8>; 176 phandle = <0x04>; 177 }; 178 }; 179 }; 180 181 cpu0-opp-table { 182 compatible = "operating-points-v2"; 183 opp-shared; 184 mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; 185 nvmem-cells = <0x06 0x07 0x08>; 186 nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; 187 rockchip,pvtm-voltage-sel = <0x00 0x14050 0x00 0x14051 0x16b48 0x01 0x16b49 0x186a0 0x02>; 188 rockchip,pvtm-freq = <0x639c0>; 189 rockchip,pvtm-volt = <0xdbba0>; 190 rockchip,pvtm-ch = <0x00 0x05>; 191 rockchip,pvtm-sample-time = <0x3e8>; 192 rockchip,pvtm-number = <0x0a>; 193 rockchip,pvtm-error = <0x3e8>; 194 rockchip,pvtm-ref-temp = <0x28>; 195 rockchip,pvtm-temp-prop = <0x1a 0x1a>; 196 rockchip,thermal-zone = "soc-thermal"; 197 rockchip,temp-hysteresis = <0x1388>; 198 rockchip,low-temp = <0x00>; 199 rockchip,low-temp-adjust-volt = <0x00 0x648 0x124f8>; 200 phandle = <0x03>; 201 202 opp-408000000 { 203 opp-hz = <0x00 0x18519600>; 204 opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; 205 clock-latency-ns = <0x9c40>; 206 }; 207 208 opp-600000000 { 209 opp-hz = <0x00 0x23c34600>; 210 opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; 211 clock-latency-ns = <0x9c40>; 212 }; 213 214 opp-816000000 { 215 opp-hz = <0x00 0x30a32c00>; 216 opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; 217 clock-latency-ns = <0x9c40>; 218 opp-suspend; 219 }; 220 221 opp-1104000000 { 222 opp-hz = <0x00 0x41cdb400>; 223 opp-microvolt = <0xc96a8 0xc96a8 0x118c30>; 224 clock-latency-ns = <0x9c40>; 225 }; 226 227 opp-1416000000 { 228 opp-hz = <0x00 0x54667200>; 229 opp-microvolt = <0xe1d48 0xe1d48 0x118c30>; 230 clock-latency-ns = <0x9c40>; 231 }; 232 233 opp-1608000000 { 234 opp-hz = <0x00 0x5fd82200>; 235 opp-microvolt = <0xf4240 0xf4240 0x118c30>; 236 clock-latency-ns = <0x9c40>; 237 }; 238 239 opp-1800000000 { 240 opp-hz = <0x00 0x6b49d200>; 241 opp-microvolt = <0x100590 0x100590 0x118c30>; 242 clock-latency-ns = <0x9c40>; 243 }; 244 245 opp-1992000000 { 246 opp-hz = <0x00 0x76bb8200>; 247 opp-microvolt = <0x118c30 0x118c30 0x118c30>; 248 clock-latency-ns = <0x9c40>; 249 }; 250 }; 251 252 arm-pmu { 253 compatible = "arm,cortex-a55-pmu\0arm,armv8-pmuv3"; 254 interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>; 255 interrupt-affinity = <0x09 0x0a 0x0b 0x0c>; 256 }; 257 258 cpuinfo { 259 compatible = "rockchip,cpuinfo"; 260 nvmem-cells = <0x0d 0x0e 0x0f>; 261 nvmem-cell-names = "id\0cpu-version\0cpu-code"; 262 }; 263 264 display-subsystem { 265 compatible = "rockchip,display-subsystem"; 266 memory-region = <0x10 0x11>; 267 memory-region-names = "drm-logo\0drm-cubic-lut"; 268 ports = <0x12>; 269 devfreq = <0x13>; 270 271 route { 272 273 route-dsi0 { 274 status = "okay"; 275 logo,uboot = "logo.bmp"; 276 logo,kernel = "logo_kernel.bmp"; 277 logo,mode = "center"; 278 charge_logo,mode = "center"; 279 connect = <0x14>; 280 }; 281 282 route-dsi1 { 283 status = "disabled"; 284 logo,uboot = "logo.bmp"; 285 logo,kernel = "logo_kernel.bmp"; 286 logo,mode = "center"; 287 charge_logo,mode = "center"; 288 connect = <0x15>; 289 }; 290 291 route-edp { 292 status = "disabled"; 293 logo,uboot = "logo.bmp"; 294 logo,kernel = "logo_kernel.bmp"; 295 logo,mode = "center"; 296 charge_logo,mode = "center"; 297 connect = <0x16>; 298 }; 299 300 route-hdmi { 301 status = "okay"; 302 logo,uboot = "logo.bmp"; 303 logo,kernel = "logo_kernel.bmp"; 304 logo,mode = "center"; 305 charge_logo,mode = "center"; 306 connect = <0x17>; 307 }; 308 309 route-lvds { 310 status = "disabled"; 311 logo,uboot = "logo.bmp"; 312 logo,kernel = "logo_kernel.bmp"; 313 logo,mode = "center"; 314 charge_logo,mode = "center"; 315 connect = <0x18>; 316 }; 317 318 route-rgb { 319 status = "disabled"; 320 logo,uboot = "logo.bmp"; 321 logo,kernel = "logo_kernel.bmp"; 322 logo,mode = "center"; 323 charge_logo,mode = "center"; 324 connect = <0x19>; 325 }; 326 }; 327 }; 328 329 firmware { 330 331 optee { 332 compatible = "linaro,optee-tz"; 333 method = "smc"; 334 }; 335 336 scmi { 337 compatible = "arm,scmi-smc"; 338 shmem = <0x1a>; 339 arm,smc-id = <0x82000010>; 340 #address-cells = <0x01>; 341 #size-cells = <0x00>; 342 343 protocol@14 { 344 reg = <0x14>; 345 #clock-cells = <0x01>; 346 rockchip,clk-init = "Tfr"; 347 phandle = <0x02>; 348 }; 349 }; 350 351 sdei { 352 compatible = "arm,sdei-1.0"; 353 method = "smc"; 354 }; 355 }; 356 357 mpp-srv { 358 compatible = "rockchip,mpp-service"; 359 rockchip,taskqueue-count = <0x06>; 360 rockchip,resetgroup-count = <0x06>; 361 status = "okay"; 362 phandle = <0x6a>; 363 }; 364 365 psci { 366 compatible = "arm,psci-1.0"; 367 method = "smc"; 368 }; 369 370 reserved-memory { 371 #address-cells = <0x02>; 372 #size-cells = <0x02>; 373 ranges; 374 375 drm-logo@00000000 { 376 compatible = "rockchip,drm-logo"; 377 reg = <0x00 0x00 0x00 0x00>; 378 phandle = <0x10>; 379 }; 380 381 drm-cubic-lut@00000000 { 382 compatible = "rockchip,drm-cubic-lut"; 383 reg = <0x00 0x00 0x00 0x00>; 384 phandle = <0x11>; 385 }; 386 387 ramoops@110000 { 388 compatible = "ramoops"; 389 reg = <0x00 0x110000 0x00 0xf0000>; 390 record-size = <0x20000>; 391 console-size = <0x80000>; 392 ftrace-size = <0x00>; 393 pmsg-size = <0x50000>; 394 }; 395 }; 396 397 rockchip-suspend { 398 compatible = "rockchip,pm-rk3568"; 399 status = "okay"; 400 rockchip,sleep-debug-en = <0x01>; 401 rockchip,sleep-mode-config = <0x5ec>; 402 rockchip,wakeup-config = <0x10>; 403 }; 404 405 rockchip-system-monitor { 406 compatible = "rockchip,system-monitor"; 407 rockchip,thermal-zone = "soc-thermal"; 408 }; 409 410 thermal-zones { 411 412 soc-thermal { 413 polling-delay-passive = <0x14>; 414 polling-delay = <0x3e8>; 415 sustainable-power = <0x389>; 416 thermal-sensors = <0x1b 0x00>; 417 418 trips { 419 420 trip-point-0 { 421 temperature = <0x124f8>; 422 hysteresis = <0x7d0>; 423 type = "passive"; 424 }; 425 426 trip-point-1 { 427 temperature = <0x14c08>; 428 hysteresis = <0x7d0>; 429 type = "passive"; 430 phandle = <0x1c>; 431 }; 432 433 soc-crit { 434 temperature = <0x1c138>; 435 hysteresis = <0x7d0>; 436 type = "critical"; 437 }; 438 }; 439 440 cooling-maps { 441 442 map0 { 443 trip = <0x1c>; 444 cooling-device = <0x09 0xffffffff 0xffffffff>; 445 contribution = <0x400>; 446 }; 447 448 map1 { 449 trip = <0x1c>; 450 cooling-device = <0x1d 0xffffffff 0xffffffff>; 451 contribution = <0x400>; 452 }; 453 }; 454 }; 455 456 gpu-thermal { 457 polling-delay-passive = <0x14>; 458 polling-delay = <0x3e8>; 459 thermal-sensors = <0x1b 0x01>; 460 }; 461 }; 462 463 timer { 464 compatible = "arm,armv8-timer"; 465 interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; 466 arm,no-tick-in-suspend; 467 }; 468 469 external-gmac0-clock { 470 compatible = "fixed-clock"; 471 clock-frequency = <0x7735940>; 472 clock-output-names = "gmac0_clkin"; 473 #clock-cells = <0x00>; 474 }; 475 476 external-gmac1-clock { 477 compatible = "fixed-clock"; 478 clock-frequency = <0x7735940>; 479 clock-output-names = "gmac1_clkin"; 480 #clock-cells = <0x00>; 481 phandle = <0x7e>; 482 }; 483 484 xpcs-gmac0-clock { 485 compatible = "fixed-clock"; 486 clock-frequency = <0x7735940>; 487 clock-output-names = "clk_gmac0_xpcs_mii"; 488 #clock-cells = <0x00>; 489 }; 490 491 xpcs-gmac1-clock { 492 compatible = "fixed-clock"; 493 clock-frequency = <0x7735940>; 494 clock-output-names = "clk_gmac1_xpcs_mii"; 495 #clock-cells = <0x00>; 496 }; 497 498 i2s1-mclkin-rx { 499 compatible = "fixed-clock"; 500 #clock-cells = <0x00>; 501 clock-frequency = <0xbb8000>; 502 clock-output-names = "i2s1_mclkin_rx"; 503 }; 504 505 i2s1-mclkin-tx { 506 compatible = "fixed-clock"; 507 #clock-cells = <0x00>; 508 clock-frequency = <0xbb8000>; 509 clock-output-names = "i2s1_mclkin_tx"; 510 }; 511 512 i2s2-mclkin { 513 compatible = "fixed-clock"; 514 #clock-cells = <0x00>; 515 clock-frequency = <0xbb8000>; 516 clock-output-names = "i2s2_mclkin"; 517 }; 518 519 i2s3-mclkin { 520 compatible = "fixed-clock"; 521 #clock-cells = <0x00>; 522 clock-frequency = <0xbb8000>; 523 clock-output-names = "i2s3_mclkin"; 524 }; 525 526 mpll { 527 compatible = "fixed-clock"; 528 #clock-cells = <0x00>; 529 clock-frequency = <0x2faf0800>; 530 clock-output-names = "mpll"; 531 }; 532 533 xin24m { 534 compatible = "fixed-clock"; 535 #clock-cells = <0x00>; 536 clock-frequency = <0x16e3600>; 537 clock-output-names = "xin24m"; 538 }; 539 540 xin32k { 541 compatible = "fixed-clock"; 542 clock-frequency = <0x8000>; 543 clock-output-names = "xin32k"; 544 #clock-cells = <0x00>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <0x1e>; 547 }; 548 549 scmi-shmem@10f000 { 550 compatible = "arm,scmi-shmem"; 551 reg = <0x00 0x10f000 0x00 0x100>; 552 phandle = <0x1a>; 553 }; 554 555 sata@fc000000 { 556 compatible = "snps,dwc-ahci"; 557 reg = <0x00 0xfc000000 0x00 0x1000>; 558 clocks = <0x1f 0x96 0x1f 0x97 0x1f 0x98>; 559 clock-names = "sata\0pmalive\0rxoob"; 560 interrupts = <0x00 0x5e 0x04>; 561 interrupt-names = "hostc"; 562 phys = <0x20 0x01>; 563 phy-names = "sata-phy"; 564 ports-implemented = <0x01>; 565 power-domains = <0x21 0x0f>; 566 status = "disabled"; 567 }; 568 569 sata@fc400000 { 570 compatible = "snps,dwc-ahci"; 571 reg = <0x00 0xfc400000 0x00 0x1000>; 572 clocks = <0x1f 0x9b 0x1f 0x9c 0x1f 0x9d>; 573 clock-names = "sata\0pmalive\0rxoob"; 574 interrupts = <0x00 0x5f 0x04>; 575 interrupt-names = "hostc"; 576 phys = <0x22 0x01>; 577 phy-names = "sata-phy"; 578 ports-implemented = <0x01>; 579 power-domains = <0x21 0x0f>; 580 status = "disabled"; 581 }; 582 583 sata@fc800000 { 584 compatible = "snps,dwc-ahci"; 585 reg = <0x00 0xfc800000 0x00 0x1000>; 586 clocks = <0x1f 0xa0 0x1f 0xa1 0x1f 0xa2>; 587 clock-names = "sata\0pmalive\0rxoob"; 588 interrupts = <0x00 0x60 0x04>; 589 interrupt-names = "hostc"; 590 phys = <0x23 0x01>; 591 phy-names = "sata-phy"; 592 ports-implemented = <0x01>; 593 power-domains = <0x21 0x0f>; 594 status = "disabled"; 595 }; 596 597 usbdrd { 598 compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3"; 599 clocks = <0x1f 0xa6 0x1f 0xa7 0x1f 0xa5 0x1f 0x7f>; 600 clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk"; 601 #address-cells = <0x02>; 602 #size-cells = <0x02>; 603 ranges; 604 status = "okay"; 605 606 dwc3@fcc00000 { 607 compatible = "snps,dwc3"; 608 reg = <0x00 0xfcc00000 0x00 0x400000>; 609 interrupts = <0x00 0xa9 0x04>; 610 dr_mode = "otg"; 611 phys = <0x24 0x20 0x04>; 612 phy-names = "usb2-phy\0usb3-phy"; 613 phy_type = "utmi_wide"; 614 power-domains = <0x21 0x0f>; 615 resets = <0x1f 0x94>; 616 reset-names = "usb3-otg"; 617 snps,dis_enblslpm_quirk; 618 snps,dis-u2-freeclk-exists-quirk; 619 snps,dis-del-phy-power-chg-quirk; 620 snps,dis-tx-ipgap-linecheck-quirk; 621 snps,xhci-trb-ent-quirk; 622 status = "okay"; 623 extcon = <0x25>; 624 }; 625 }; 626 627 usbhost { 628 compatible = "rockchip,rk3568-dwc3\0rockchip,rk3399-dwc3"; 629 clocks = <0x1f 0xa9 0x1f 0xaa 0x1f 0xa8 0x1f 0x7f>; 630 clock-names = "ref_clk\0suspend_clk\0bus_clk\0pipe_clk"; 631 #address-cells = <0x02>; 632 #size-cells = <0x02>; 633 ranges; 634 status = "okay"; 635 636 dwc3@fd000000 { 637 compatible = "snps,dwc3"; 638 reg = <0x00 0xfd000000 0x00 0x400000>; 639 interrupts = <0x00 0xaa 0x04>; 640 dr_mode = "host"; 641 phys = <0x26 0x22 0x04>; 642 phy-names = "usb2-phy\0usb3-phy"; 643 phy_type = "utmi_wide"; 644 power-domains = <0x21 0x0f>; 645 resets = <0x1f 0x95>; 646 reset-names = "usb3-host"; 647 snps,dis_enblslpm_quirk; 648 snps,dis-u2-freeclk-exists-quirk; 649 snps,dis-del-phy-power-chg-quirk; 650 snps,dis-tx-ipgap-linecheck-quirk; 651 snps,xhci-trb-ent-quirk; 652 status = "okay"; 653 }; 654 }; 655 656 interrupt-controller@fd400000 { 657 compatible = "arm,gic-v3"; 658 #interrupt-cells = <0x03>; 659 #address-cells = <0x02>; 660 #size-cells = <0x02>; 661 ranges; 662 interrupt-controller; 663 reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; 664 interrupts = <0x01 0x09 0x04>; 665 phandle = <0x01>; 666 667 interrupt-controller@fd440000 { 668 compatible = "arm,gic-v3-its"; 669 msi-controller; 670 #msi-cells = <0x01>; 671 reg = <0x00 0xfd440000 0x00 0x20000>; 672 phandle = <0xab>; 673 }; 674 }; 675 676 usb@fd800000 { 677 compatible = "generic-ehci"; 678 reg = <0x00 0xfd800000 0x00 0x40000>; 679 interrupts = <0x00 0x82 0x04>; 680 clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x27>; 681 clock-names = "usbhost\0arbiter\0pclk\0utmi"; 682 phys = <0x28>; 683 phy-names = "usb2-phy"; 684 status = "okay"; 685 }; 686 687 usb@fd840000 { 688 compatible = "generic-ohci"; 689 reg = <0x00 0xfd840000 0x00 0x40000>; 690 interrupts = <0x00 0x83 0x04>; 691 clocks = <0x1f 0xbd 0x1f 0xbe 0x1f 0xbc 0x27>; 692 clock-names = "usbhost\0arbiter\0pclk\0utmi"; 693 phys = <0x28>; 694 phy-names = "usb2-phy"; 695 status = "okay"; 696 }; 697 698 usb@fd880000 { 699 compatible = "generic-ehci"; 700 reg = <0x00 0xfd880000 0x00 0x40000>; 701 interrupts = <0x00 0x85 0x04>; 702 clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x27>; 703 clock-names = "usbhost\0arbiter\0pclk\0utmi"; 704 phys = <0x29>; 705 phy-names = "usb2-phy"; 706 status = "okay"; 707 }; 708 709 usb@fd8c0000 { 710 compatible = "generic-ohci"; 711 reg = <0x00 0xfd8c0000 0x00 0x40000>; 712 interrupts = <0x00 0x86 0x04>; 713 clocks = <0x1f 0xbf 0x1f 0xc0 0x1f 0xbc 0x27>; 714 clock-names = "usbhost\0arbiter\0pclk\0utmi"; 715 phys = <0x29>; 716 phy-names = "usb2-phy"; 717 status = "okay"; 718 }; 719 720 syscon@fda00000 { 721 compatible = "rockchip,rk3568-xpcs\0syscon"; 722 reg = <0x00 0xfda00000 0x00 0x200000>; 723 status = "disabled"; 724 }; 725 726 syscon@fdc20000 { 727 compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; 728 reg = <0x00 0xfdc20000 0x00 0x10000>; 729 phandle = <0x34>; 730 731 io-domains { 732 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 733 status = "okay"; 734 pmuio1-supply = <0x2a>; 735 pmuio2-supply = <0x2a>; 736 vccio1-supply = <0x2b>; 737 vccio3-supply = <0x2c>; 738 vccio4-supply = <0x2d>; 739 vccio5-supply = <0x2d>; 740 vccio6-supply = <0x2e>; 741 vccio7-supply = <0x2d>; 742 }; 743 744 reboot-mode { 745 compatible = "syscon-reboot-mode"; 746 offset = <0x200>; 747 mode-bootloader = <0x5242c301>; 748 mode-charge = <0x5242c30b>; 749 mode-fastboot = <0x5242c309>; 750 mode-loader = <0x5242c301>; 751 mode-normal = <0x5242c300>; 752 mode-recovery = <0x5242c303>; 753 mode-ums = <0x5242c30c>; 754 mode-panic = <0x5242c307>; 755 mode-watchdog = <0x5242c308>; 756 }; 757 }; 758 759 syscon@fdc50000 { 760 compatible = "rockchip,rk3568-pipegrf\0syscon"; 761 reg = <0x00 0xfdc50000 0x00 0x1000>; 762 phandle = <0x105>; 763 }; 764 765 syscon@fdc60000 { 766 compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; 767 reg = <0x00 0xfdc60000 0x00 0x10000>; 768 phandle = <0x33>; 769 770 io-domains { 771 compatible = "rockchip,rk3568-io-voltage-domain"; 772 status = "disabled"; 773 }; 774 775 lvds { 776 compatible = "rockchip,rk3568-lvds"; 777 phys = <0x2f>; 778 phy-names = "phy"; 779 status = "disabled"; 780 781 ports { 782 #address-cells = <0x01>; 783 #size-cells = <0x00>; 784 785 port@0 { 786 reg = <0x00>; 787 #address-cells = <0x01>; 788 #size-cells = <0x00>; 789 790 endpoint@1 { 791 reg = <0x01>; 792 remote-endpoint = <0x18>; 793 status = "disabled"; 794 phandle = <0x90>; 795 }; 796 797 endpoint@2 { 798 reg = <0x02>; 799 remote-endpoint = <0x30>; 800 status = "disabled"; 801 phandle = <0x91>; 802 }; 803 }; 804 }; 805 }; 806 807 rgb { 808 compatible = "rockchip,rk3568-rgb"; 809 pinctrl-names = "default"; 810 pinctrl-0 = <0x31>; 811 status = "disabled"; 812 813 ports { 814 #address-cells = <0x01>; 815 #size-cells = <0x00>; 816 817 port@0 { 818 reg = <0x00>; 819 #address-cells = <0x01>; 820 #size-cells = <0x00>; 821 822 endpoint@2 { 823 reg = <0x02>; 824 remote-endpoint = <0x19>; 825 status = "disabled"; 826 phandle = <0x92>; 827 }; 828 }; 829 }; 830 }; 831 }; 832 833 syscon@fdc70000 { 834 compatible = "rockchip,pipe-phy-grf\0syscon"; 835 reg = <0x00 0xfdc70000 0x00 0x1000>; 836 phandle = <0x106>; 837 }; 838 839 syscon@fdc80000 { 840 compatible = "rockchip,pipe-phy-grf\0syscon"; 841 reg = <0x00 0xfdc80000 0x00 0x1000>; 842 phandle = <0x107>; 843 }; 844 845 syscon@fdc90000 { 846 compatible = "rockchip,pipe-phy-grf\0syscon"; 847 reg = <0x00 0xfdc90000 0x00 0x1000>; 848 phandle = <0x108>; 849 }; 850 851 syscon@fdca0000 { 852 compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; 853 reg = <0x00 0xfdca0000 0x00 0x8000>; 854 phandle = <0x10c>; 855 }; 856 857 syscon@fdca8000 { 858 compatible = "rockchip,rk3568-usb2phy-grf\0syscon"; 859 reg = <0x00 0xfdca8000 0x00 0x8000>; 860 phandle = <0x10f>; 861 }; 862 863 edp-phy@fdcb0000 { 864 compatible = "rockchip,rk3568-edp-phy"; 865 reg = <0x00 0xfdcb0000 0x00 0x8000>; 866 clocks = <0x32 0x29 0x1f 0x192>; 867 clock-names = "refclk\0pclk"; 868 resets = <0x1f 0x1d6>; 869 reset-names = "apb"; 870 #phy-cells = <0x00>; 871 status = "disabled"; 872 phandle = <0xa0>; 873 }; 874 875 syscon@fdcb8000 { 876 compatible = "rockchip,pcie30-phy-grf\0syscon"; 877 reg = <0x00 0xfdcb8000 0x00 0x10000>; 878 phandle = <0x110>; 879 }; 880 881 sram@fdcc0000 { 882 compatible = "mmio-sram"; 883 reg = <0x00 0xfdcc0000 0x00 0xb000>; 884 #address-cells = <0x01>; 885 #size-cells = <0x01>; 886 ranges = <0x00 0x00 0xfdcc0000 0xb000>; 887 888 rkvdec-sram@0 { 889 reg = <0x00 0xb000>; 890 phandle = <0x72>; 891 }; 892 }; 893 894 clock-controller@fdd00000 { 895 compatible = "rockchip,rk3568-pmucru"; 896 reg = <0x00 0xfdd00000 0x00 0x1000>; 897 rockchip,grf = <0x33>; 898 rockchip,pmugrf = <0x34>; 899 #clock-cells = <0x01>; 900 #reset-cells = <0x01>; 901 assigned-clocks = <0x32 0x32>; 902 assigned-clock-parents = <0x32 0x05>; 903 phandle = <0x32>; 904 }; 905 906 clock-controller@fdd20000 { 907 compatible = "rockchip,rk3568-cru"; 908 reg = <0x00 0xfdd20000 0x00 0x1000>; 909 rockchip,grf = <0x33>; 910 #clock-cells = <0x01>; 911 #reset-cells = <0x01>; 912 assigned-clocks = <0x32 0x05 0x1f 0x106 0x1f 0x10b 0x32 0x01 0x32 0x2b 0x1f 0x03 0x1f 0x19b 0x1f 0x09 0x1f 0x19c 0x1f 0x19d 0x1f 0x1a1 0x1f 0x19e 0x1f 0x19f 0x1f 0x1a0 0x1f 0x04 0x1f 0x10d 0x1f 0x10e 0x1f 0x173 0x1f 0x174 0x1f 0x175 0x1f 0x176 0x1f 0xc9 0x1f 0xca 0x1f 0x06 0x1f 0x7e 0x1f 0x7f 0x1f 0x3d 0x1f 0x41 0x1f 0x45 0x1f 0x49 0x1f 0x4d 0x1f 0x4d 0x1f 0x55 0x1f 0x51 0x1f 0x5d 0x1f 0xdd>; 913 assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; 914 assigned-clock-parents = <0x32 0x08 0x1f 0x04 0x1f 0x04>; 915 phandle = <0x1f>; 916 }; 917 918 i2c@fdd40000 { 919 compatible = "rockchip,rk3399-i2c"; 920 reg = <0x00 0xfdd40000 0x00 0x1000>; 921 clocks = <0x32 0x07 0x32 0x2d>; 922 clock-names = "i2c\0pclk"; 923 interrupts = <0x00 0x2e 0x04>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <0x35>; 926 #address-cells = <0x01>; 927 #size-cells = <0x00>; 928 status = "okay"; 929 930 tcs4525@1c { 931 compatible = "tcs,tcs452x"; 932 reg = <0x1c>; 933 vin-supply = <0x36>; 934 regulator-compatible = "fan53555-reg"; 935 regulator-name = "vdd_cpu"; 936 regulator-min-microvolt = <0xadf34>; 937 regulator-max-microvolt = <0x1535b0>; 938 regulator-init-microvolt = <0xdbba0>; 939 regulator-ramp-delay = <0x8fc>; 940 fcs,suspend-voltage-selector = <0x01>; 941 regulator-boot-on; 942 regulator-always-on; 943 phandle = <0x05>; 944 945 regulator-state-mem { 946 regulator-off-in-suspend; 947 }; 948 }; 949 950 pmic@20 { 951 compatible = "rockchip,rk809"; 952 reg = <0x20>; 953 interrupt-parent = <0x37>; 954 interrupts = <0x03 0x08>; 955 pinctrl-names = "default\0pmic-sleep\0pmic-power-off\0pmic-reset"; 956 pinctrl-0 = <0x38>; 957 pinctrl-1 = <0x39 0x3a>; 958 pinctrl-2 = <0x3b 0x3c>; 959 pinctrl-3 = <0x3b 0x3d>; 960 rockchip,system-power-controller; 961 wakeup-source; 962 #clock-cells = <0x01>; 963 clock-output-names = "rk808-clkout1\0rk808-clkout2"; 964 pmic-reset-func = <0x00>; 965 not-save-power-en = <0x01>; 966 vcc1-supply = <0x3e>; 967 vcc2-supply = <0x3e>; 968 vcc3-supply = <0x3e>; 969 vcc4-supply = <0x3e>; 970 vcc5-supply = <0x3e>; 971 vcc6-supply = <0x3e>; 972 vcc7-supply = <0x3e>; 973 vcc8-supply = <0x3e>; 974 vcc9-supply = <0x3e>; 975 phandle = <0x12b>; 976 977 pwrkey { 978 status = "okay"; 979 }; 980 981 pinctrl_rk8xx { 982 gpio-controller; 983 #gpio-cells = <0x02>; 984 985 rk817_slppin_null { 986 pins = "gpio_slp"; 987 function = "pin_fun0"; 988 }; 989 990 rk817_slppin_slp { 991 pins = "gpio_slp"; 992 function = "pin_fun1"; 993 phandle = <0x3a>; 994 }; 995 996 rk817_slppin_pwrdn { 997 pins = "gpio_slp"; 998 function = "pin_fun2"; 999 phandle = <0x3c>; 1000 }; 1001 1002 rk817_slppin_rst { 1003 pins = "gpio_slp"; 1004 function = "pin_fun3"; 1005 phandle = <0x3d>; 1006 }; 1007 }; 1008 1009 regulators { 1010 1011 DCDC_REG1 { 1012 regulator-always-on; 1013 regulator-boot-on; 1014 regulator-min-microvolt = <0x7a120>; 1015 regulator-max-microvolt = <0x149970>; 1016 regulator-init-microvolt = <0xdbba0>; 1017 regulator-ramp-delay = <0x1771>; 1018 regulator-initial-mode = <0x02>; 1019 regulator-name = "vdd_logic"; 1020 phandle = <0x65>; 1021 1022 regulator-state-mem { 1023 regulator-off-in-suspend; 1024 }; 1025 }; 1026 1027 DCDC_REG2 { 1028 regulator-always-on; 1029 regulator-boot-on; 1030 regulator-min-microvolt = <0x7a120>; 1031 regulator-max-microvolt = <0x149970>; 1032 regulator-init-microvolt = <0xdbba0>; 1033 regulator-ramp-delay = <0x1771>; 1034 regulator-initial-mode = <0x02>; 1035 regulator-name = "vdd_gpu"; 1036 phandle = <0x67>; 1037 1038 regulator-state-mem { 1039 regulator-off-in-suspend; 1040 }; 1041 }; 1042 1043 DCDC_REG3 { 1044 regulator-always-on; 1045 regulator-boot-on; 1046 regulator-initial-mode = <0x02>; 1047 regulator-name = "vcc_ddr"; 1048 1049 regulator-state-mem { 1050 regulator-on-in-suspend; 1051 }; 1052 }; 1053 1054 DCDC_REG4 { 1055 regulator-always-on; 1056 regulator-boot-on; 1057 regulator-min-microvolt = <0x7a120>; 1058 regulator-max-microvolt = <0x149970>; 1059 regulator-init-microvolt = <0xdbba0>; 1060 regulator-ramp-delay = <0x1771>; 1061 regulator-initial-mode = <0x02>; 1062 regulator-name = "vdd_npu"; 1063 phandle = <0x62>; 1064 1065 regulator-state-mem { 1066 regulator-off-in-suspend; 1067 }; 1068 }; 1069 1070 LDO_REG1 { 1071 regulator-boot-on; 1072 regulator-always-on; 1073 regulator-min-microvolt = <0xdbba0>; 1074 regulator-max-microvolt = <0xdbba0>; 1075 regulator-name = "vdda0v9_image"; 1076 1077 regulator-state-mem { 1078 regulator-off-in-suspend; 1079 }; 1080 }; 1081 1082 LDO_REG2 { 1083 regulator-always-on; 1084 regulator-boot-on; 1085 regulator-min-microvolt = <0xdbba0>; 1086 regulator-max-microvolt = <0xdbba0>; 1087 regulator-name = "vdda_0v9"; 1088 1089 regulator-state-mem { 1090 regulator-off-in-suspend; 1091 }; 1092 }; 1093 1094 LDO_REG3 { 1095 regulator-always-on; 1096 regulator-boot-on; 1097 regulator-min-microvolt = <0xdbba0>; 1098 regulator-max-microvolt = <0xdbba0>; 1099 regulator-name = "vdda0v9_pmu"; 1100 1101 regulator-state-mem { 1102 regulator-on-in-suspend; 1103 regulator-suspend-microvolt = <0xdbba0>; 1104 }; 1105 }; 1106 1107 LDO_REG4 { 1108 regulator-always-on; 1109 regulator-boot-on; 1110 regulator-min-microvolt = <0x325aa0>; 1111 regulator-max-microvolt = <0x325aa0>; 1112 regulator-name = "vccio_acodec"; 1113 phandle = <0x2b>; 1114 1115 regulator-state-mem { 1116 regulator-off-in-suspend; 1117 }; 1118 }; 1119 1120 LDO_REG5 { 1121 regulator-always-on; 1122 regulator-boot-on; 1123 regulator-min-microvolt = <0x1b7740>; 1124 regulator-max-microvolt = <0x325aa0>; 1125 regulator-name = "vccio_sd"; 1126 phandle = <0x2c>; 1127 1128 regulator-state-mem { 1129 regulator-off-in-suspend; 1130 }; 1131 }; 1132 1133 LDO_REG6 { 1134 regulator-always-on; 1135 regulator-boot-on; 1136 regulator-min-microvolt = <0x325aa0>; 1137 regulator-max-microvolt = <0x325aa0>; 1138 regulator-name = "vcc3v3_pmu"; 1139 phandle = <0x2a>; 1140 1141 regulator-state-mem { 1142 regulator-on-in-suspend; 1143 regulator-suspend-microvolt = <0x325aa0>; 1144 }; 1145 }; 1146 1147 LDO_REG7 { 1148 regulator-always-on; 1149 regulator-boot-on; 1150 regulator-min-microvolt = <0x1b7740>; 1151 regulator-max-microvolt = <0x1b7740>; 1152 regulator-name = "vcca_1v8"; 1153 phandle = <0x104>; 1154 1155 regulator-state-mem { 1156 regulator-off-in-suspend; 1157 }; 1158 }; 1159 1160 LDO_REG8 { 1161 regulator-always-on; 1162 regulator-boot-on; 1163 regulator-min-microvolt = <0x1b7740>; 1164 regulator-max-microvolt = <0x1b7740>; 1165 regulator-name = "vcca1v8_pmu"; 1166 1167 regulator-state-mem { 1168 regulator-on-in-suspend; 1169 regulator-suspend-microvolt = <0x1b7740>; 1170 }; 1171 }; 1172 1173 LDO_REG9 { 1174 regulator-always-on; 1175 regulator-boot-on; 1176 regulator-min-microvolt = <0x1b7740>; 1177 regulator-max-microvolt = <0x1b7740>; 1178 regulator-name = "vcca1v8_image"; 1179 1180 regulator-state-mem { 1181 regulator-off-in-suspend; 1182 }; 1183 }; 1184 1185 DCDC_REG5 { 1186 regulator-always-on; 1187 regulator-boot-on; 1188 regulator-min-microvolt = <0x1b7740>; 1189 regulator-max-microvolt = <0x1b7740>; 1190 regulator-name = "vcc_1v8"; 1191 phandle = <0x2e>; 1192 1193 regulator-state-mem { 1194 regulator-off-in-suspend; 1195 }; 1196 }; 1197 1198 SWITCH_REG1 { 1199 regulator-always-on; 1200 regulator-boot-on; 1201 regulator-name = "vcc_3v3"; 1202 phandle = <0x2d>; 1203 1204 regulator-state-mem { 1205 regulator-off-in-suspend; 1206 }; 1207 }; 1208 1209 SWITCH_REG2 { 1210 regulator-always-on; 1211 regulator-boot-on; 1212 regulator-name = "vcc3v3_sd"; 1213 phandle = <0xb4>; 1214 1215 regulator-state-mem { 1216 regulator-off-in-suspend; 1217 }; 1218 }; 1219 }; 1220 1221 codec { 1222 #sound-dai-cells = <0x00>; 1223 compatible = "rockchip,rk809-codec\0rockchip,rk817-codec"; 1224 clocks = <0x1f 0x1a3>; 1225 clock-names = "mclk"; 1226 assigned-clocks = <0x1f 0x1a3 0x1f 0x1a6>; 1227 assigned-clock-rates = <0xbb8000>; 1228 assigned-clock-parents = <0x1f 0x48 0x1f 0x48>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <0x3f>; 1231 hp-volume = <0x14>; 1232 spk-volume = <0x03>; 1233 mic-in-differential; 1234 status = "okay"; 1235 phandle = <0x123>; 1236 }; 1237 }; 1238 }; 1239 1240 serial@fdd50000 { 1241 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 1242 reg = <0x00 0xfdd50000 0x00 0x100>; 1243 interrupts = <0x00 0x74 0x04>; 1244 clocks = <0x32 0x0b 0x32 0x2c>; 1245 clock-names = "baudclk\0apb_pclk"; 1246 reg-shift = <0x02>; 1247 reg-io-width = <0x04>; 1248 dmas = <0x40 0x00 0x40 0x01>; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <0x41>; 1251 status = "disabled"; 1252 }; 1253 1254 pwm@fdd70000 { 1255 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 1256 reg = <0x00 0xfdd70000 0x00 0x10>; 1257 #pwm-cells = <0x03>; 1258 pinctrl-names = "active"; 1259 pinctrl-0 = <0x42>; 1260 clocks = <0x32 0x0d 0x32 0x30>; 1261 clock-names = "pwm\0pclk"; 1262 status = "okay"; 1263 }; 1264 1265 pwm@fdd70010 { 1266 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 1267 reg = <0x00 0xfdd70010 0x00 0x10>; 1268 #pwm-cells = <0x03>; 1269 pinctrl-names = "active"; 1270 pinctrl-0 = <0x43>; 1271 clocks = <0x32 0x0d 0x32 0x30>; 1272 clock-names = "pwm\0pclk"; 1273 status = "disabled"; 1274 }; 1275 1276 pwm@fdd70020 { 1277 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 1278 reg = <0x00 0xfdd70020 0x00 0x10>; 1279 #pwm-cells = <0x03>; 1280 pinctrl-names = "active"; 1281 pinctrl-0 = <0x44>; 1282 clocks = <0x32 0x0d 0x32 0x30>; 1283 clock-names = "pwm\0pclk"; 1284 status = "disabled"; 1285 }; 1286 1287 pwm@fdd70030 { 1288 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 1289 reg = <0x00 0xfdd70030 0x00 0x10>; 1290 interrupts = <0x00 0x52 0x04 0x00 0x56 0x04>; 1291 #pwm-cells = <0x03>; 1292 pinctrl-names = "active"; 1293 pinctrl-0 = <0x45>; 1294 clocks = <0x32 0x0d 0x32 0x30>; 1295 clock-names = "pwm\0pclk"; 1296 status = "disabled"; 1297 }; 1298 1299 power-management@fdd90000 { 1300 compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd"; 1301 reg = <0x00 0xfdd90000 0x00 0x1000>; 1302 1303 power-controller { 1304 compatible = "rockchip,rk3568-power-controller"; 1305 #power-domain-cells = <0x01>; 1306 #address-cells = <0x01>; 1307 #size-cells = <0x00>; 1308 status = "okay"; 1309 phandle = <0x21>; 1310 1311 pd_gpu@7 { 1312 reg = <0x07>; 1313 clocks = <0x1f 0x19 0x1f 0x1a>; 1314 pm_qos = <0x46>; 1315 }; 1316 1317 pd_vi@8 { 1318 reg = <0x08>; 1319 clocks = <0x1f 0xcc 0x1f 0xcd>; 1320 pm_qos = <0x47 0x48 0x49>; 1321 }; 1322 1323 pd_vo@9 { 1324 reg = <0x09>; 1325 clocks = <0x1f 0xda 0x1f 0xdb 0x1f 0xdc>; 1326 pm_qos = <0x4a 0x4b 0x4c>; 1327 }; 1328 1329 pd_rga@10 { 1330 reg = <0x0a>; 1331 clocks = <0x1f 0xf1 0x1f 0xf2>; 1332 pm_qos = <0x4d 0x4e 0x4f 0x50 0x51 0x52>; 1333 }; 1334 1335 pd_vpu@11 { 1336 reg = <0x0b>; 1337 clocks = <0x1f 0xed>; 1338 pm_qos = <0x53>; 1339 }; 1340 1341 pd_rkvdec@13 { 1342 clocks = <0x1f 0x107>; 1343 reg = <0x0d>; 1344 pm_qos = <0x54>; 1345 }; 1346 1347 pd_rkvenc@14 { 1348 reg = <0x0e>; 1349 clocks = <0x1f 0x102>; 1350 pm_qos = <0x55 0x56 0x57>; 1351 }; 1352 1353 pd_pipe@15 { 1354 reg = <0x0f>; 1355 clocks = <0x1f 0x7f>; 1356 pm_qos = <0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f>; 1357 }; 1358 }; 1359 }; 1360 1361 pvtm@fde00000 { 1362 compatible = "rockchip,rk3568-core-pvtm"; 1363 reg = <0x00 0xfde00000 0x00 0x100>; 1364 #address-cells = <0x01>; 1365 #size-cells = <0x00>; 1366 1367 pvtm@0 { 1368 reg = <0x00>; 1369 clocks = <0x1f 0x13 0x1f 0x1c2>; 1370 clock-names = "clk\0pclk"; 1371 resets = <0x1f 0x1a 0x1f 0x19>; 1372 reset-names = "rts\0rst-p"; 1373 thermal-zone = "soc-thermal"; 1374 }; 1375 }; 1376 1377 npu@fde40000 { 1378 compatible = "rockchip,rk3568-rknpu\0rockchip,rknpu"; 1379 reg = <0x00 0xfde40000 0x00 0x10000>; 1380 interrupts = <0x00 0x97 0x04>; 1381 clocks = <0x02 0x02 0x1f 0x23 0x1f 0x28 0x1f 0x29>; 1382 clock-names = "scmi_clk\0clk\0aclk\0hclk"; 1383 assigned-clocks = <0x1f 0x23>; 1384 assigned-clock-rates = <0x23c34600>; 1385 resets = <0x1f 0x2b 0x1f 0x2c>; 1386 reset-names = "srst_a\0srst_h"; 1387 power-domains = <0x21 0x06>; 1388 operating-points-v2 = <0x60>; 1389 iommus = <0x61>; 1390 status = "okay"; 1391 rknpu-supply = <0x62>; 1392 }; 1393 1394 npu-opp-table { 1395 compatible = "operating-points-v2"; 1396 mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; 1397 nvmem-cells = <0x63 0x07 0x08>; 1398 nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; 1399 rockchip,temp-hysteresis = <0x1388>; 1400 rockchip,low-temp = <0x00>; 1401 rockchip,low-temp-adjust-volt = <0x00 0x2bc 0xc350>; 1402 phandle = <0x60>; 1403 1404 opp-200000000 { 1405 opp-hz = <0x00 0xbebc200>; 1406 opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; 1407 }; 1408 1409 opp-300000000 { 1410 opp-hz = <0x00 0x11b3dc40>; 1411 opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; 1412 }; 1413 1414 opp-400000000 { 1415 opp-hz = <0x00 0x17d78400>; 1416 opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; 1417 }; 1418 1419 opp-600000000 { 1420 opp-hz = <0x00 0x23c34600>; 1421 opp-microvolt = <0xc96a8 0xc96a8 0xf4240>; 1422 }; 1423 1424 opp-700000000 { 1425 opp-hz = <0x00 0x29b92700>; 1426 opp-microvolt = <0xcf850 0xcf850 0xf4240>; 1427 }; 1428 1429 opp-800000000 { 1430 opp-hz = <0x00 0x2faf0800>; 1431 opp-microvolt = <0xd59f8 0xd59f8 0xf4240>; 1432 }; 1433 1434 opp-900000000 { 1435 opp-hz = <0x00 0x35a4e900>; 1436 opp-microvolt = <0xe1d48 0xe1d48 0xf4240>; 1437 }; 1438 1439 opp-1000000000 { 1440 opp-hz = <0x00 0x3b9aca00>; 1441 opp-microvolt = <0xf4240 0xf4240 0xf4240>; 1442 status = "disabled"; 1443 }; 1444 }; 1445 1446 bus-npu { 1447 compatible = "rockchip,rk3568-bus"; 1448 rockchip,busfreq-policy = "clkfreq"; 1449 clocks = <0x02 0x02>; 1450 clock-names = "bus"; 1451 operating-points-v2 = <0x64>; 1452 status = "okay"; 1453 bus-supply = <0x65>; 1454 pvtm-supply = <0x05>; 1455 }; 1456 1457 bus-npu-opp-table { 1458 compatible = "operating-points-v2"; 1459 opp-shared; 1460 nvmem-cells = <0x07>; 1461 nvmem-cell-names = "pvtm"; 1462 rockchip,pvtm-voltage-sel = <0x00 0x14050 0x00 0x14051 0x16b48 0x01 0x16b49 0x186a0 0x02>; 1463 rockchip,pvtm-ch = <0x00 0x05>; 1464 phandle = <0x64>; 1465 1466 opp-1000000000 { 1467 opp-hz = <0x00 0x3b9aca00>; 1468 opp-microvolt = <0xe7ef0>; 1469 opp-microvolt-L0 = <0xe7ef0>; 1470 opp-microvolt-L1 = <0xe1d48>; 1471 opp-microvolt-L2 = <0x00>; 1472 }; 1473 1474 opp-900000000 { 1475 opp-hz = <0x00 0x35a4e900>; 1476 opp-microvolt = <0x00>; 1477 }; 1478 }; 1479 1480 iommu@fde4b000 { 1481 compatible = "rockchip,iommu-v2"; 1482 reg = <0x00 0xfde4b000 0x00 0x40>; 1483 interrupts = <0x00 0x97 0x04>; 1484 interrupt-names = "rknpu_mmu"; 1485 clocks = <0x1f 0x28 0x1f 0x29>; 1486 clock-names = "aclk\0iface"; 1487 power-domains = <0x21 0x06>; 1488 #iommu-cells = <0x00>; 1489 status = "okay"; 1490 phandle = <0x61>; 1491 }; 1492 1493 gpu@fde60000 { 1494 compatible = "arm,mali-bifrost"; 1495 reg = <0x00 0xfde60000 0x00 0x4000>; 1496 interrupts = <0x00 0x27 0x04 0x00 0x29 0x04 0x00 0x28 0x04>; 1497 interrupt-names = "GPU\0MMU\0JOB"; 1498 upthreshold = <0x28>; 1499 downdifferential = <0x0a>; 1500 clocks = <0x02 0x01 0x1f 0x1b>; 1501 clock-names = "clk_mali\0clk_gpu"; 1502 power-domains = <0x21 0x07>; 1503 #cooling-cells = <0x02>; 1504 operating-points-v2 = <0x66>; 1505 status = "okay"; 1506 mali-supply = <0x67>; 1507 phandle = <0x1d>; 1508 1509 power-model { 1510 compatible = "simple-power-model"; 1511 leakage-range = <0x05 0x0f>; 1512 ls = <0xffffa23e 0x5927 0x00>; 1513 static-coefficient = <0x186a0>; 1514 dynamic-coefficient = <0x3b9>; 1515 ts = <0xfffe56a6 0xf87a 0xfffffab5 0x14>; 1516 thermal-zone = "gpu-thermal"; 1517 }; 1518 }; 1519 1520 opp-table2 { 1521 compatible = "operating-points-v2"; 1522 mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; 1523 nvmem-cells = <0x68 0x07 0x08>; 1524 nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; 1525 phandle = <0x66>; 1526 1527 opp-200000000 { 1528 opp-hz = <0x00 0xbebc200>; 1529 opp-microvolt = <0xc96a8>; 1530 }; 1531 1532 opp-300000000 { 1533 opp-hz = <0x00 0x11e1a300>; 1534 opp-microvolt = <0xc96a8>; 1535 }; 1536 1537 opp-400000000 { 1538 opp-hz = <0x00 0x17d78400>; 1539 opp-microvolt = <0xc96a8>; 1540 }; 1541 1542 opp-600000000 { 1543 opp-hz = <0x00 0x23c34600>; 1544 opp-microvolt = <0xc96a8>; 1545 }; 1546 1547 opp-700000000 { 1548 opp-hz = <0x00 0x29b92700>; 1549 opp-microvolt = <0xdbba0>; 1550 }; 1551 1552 opp-800000000 { 1553 opp-hz = <0x00 0x2faf0800>; 1554 opp-microvolt = <0xe7ef0>; 1555 }; 1556 }; 1557 1558 pvtm@fde80000 { 1559 compatible = "rockchip,rk3568-gpu-pvtm"; 1560 reg = <0x00 0xfde80000 0x00 0x100>; 1561 #address-cells = <0x01>; 1562 #size-cells = <0x00>; 1563 1564 pvtm@1 { 1565 reg = <0x01>; 1566 clocks = <0x1f 0x1e 0x1f 0x1d>; 1567 clock-names = "clk\0pclk"; 1568 resets = <0x1f 0x24 0x1f 0x23>; 1569 reset-names = "rts\0rst-p"; 1570 thermal-zone = "gpu-thermal"; 1571 }; 1572 }; 1573 1574 pvtm@fde90000 { 1575 compatible = "rockchip,rk3568-npu-pvtm"; 1576 reg = <0x00 0xfde90000 0x00 0x100>; 1577 #address-cells = <0x01>; 1578 #size-cells = <0x00>; 1579 1580 pvtm@2 { 1581 reg = <0x02>; 1582 clocks = <0x1f 0x2b 0x1f 0x2a 0x1f 0x25>; 1583 clock-names = "clk\0pclk\0hclk"; 1584 resets = <0x1f 0x2e 0x1f 0x2d>; 1585 reset-names = "rts\0rst-p"; 1586 thermal-zone = "soc-thermal"; 1587 }; 1588 }; 1589 1590 vdpu@fdea0400 { 1591 compatible = "rockchip,vpu-decoder-v2"; 1592 reg = <0x00 0xfdea0400 0x00 0x400>; 1593 interrupts = <0x00 0x8b 0x04>; 1594 interrupt-names = "irq_dec"; 1595 clocks = <0x1f 0xee 0x1f 0xef>; 1596 clock-names = "aclk_vcodec\0hclk_vcodec"; 1597 resets = <0x1f 0x11a 0x1f 0x11b>; 1598 reset-names = "video_a\0video_h"; 1599 iommus = <0x69>; 1600 power-domains = <0x21 0x0b>; 1601 rockchip,srv = <0x6a>; 1602 rockchip,taskqueue-node = <0x00>; 1603 rockchip,resetgroup-node = <0x00>; 1604 status = "okay"; 1605 }; 1606 1607 iommu@fdea0800 { 1608 compatible = "rockchip,iommu-v2"; 1609 reg = <0x00 0xfdea0800 0x00 0x40>; 1610 interrupts = <0x00 0x8a 0x04>; 1611 interrupt-names = "vdpu_mmu"; 1612 clock-names = "aclk\0iface"; 1613 clocks = <0x1f 0xee 0x1f 0xef>; 1614 power-domains = <0x21 0x0b>; 1615 #iommu-cells = <0x00>; 1616 status = "okay"; 1617 phandle = <0x69>; 1618 }; 1619 1620 rk_rga@fdeb0000 { 1621 compatible = "rockchip,rga2"; 1622 reg = <0x00 0xfdeb0000 0x00 0x1000>; 1623 interrupts = <0x00 0x5a 0x04>; 1624 clocks = <0x1f 0xf3 0x1f 0xf4 0x1f 0xf5>; 1625 clock-names = "aclk_rga\0hclk_rga\0clk_rga"; 1626 power-domains = <0x21 0x0a>; 1627 status = "okay"; 1628 }; 1629 1630 ebc@fdec0000 { 1631 compatible = "rockchip,rk3568-ebc-tcon"; 1632 reg = <0x00 0xfdec0000 0x00 0x5000>; 1633 interrupts = <0x00 0x11 0x04>; 1634 clocks = <0x1f 0xf9 0x1f 0xfa>; 1635 clock-names = "hclk\0dclk"; 1636 power-domains = <0x21 0x0a>; 1637 rockchip,grf = <0x33>; 1638 pinctrl-names = "default"; 1639 pinctrl-0 = <0x6b>; 1640 status = "disabled"; 1641 }; 1642 1643 jpegd@fded0000 { 1644 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1645 reg = <0x00 0xfded0000 0x00 0x400>; 1646 interrupts = <0x00 0x3e 0x04>; 1647 clocks = <0x1f 0xfb 0x1f 0xfc>; 1648 clock-names = "aclk_vcodec\0hclk_vcodec"; 1649 rockchip,disable-auto-freq; 1650 resets = <0x1f 0x12c 0x1f 0x12d>; 1651 reset-names = "video_a\0video_h"; 1652 iommus = <0x6c>; 1653 rockchip,srv = <0x6a>; 1654 rockchip,taskqueue-node = <0x01>; 1655 rockchip,resetgroup-node = <0x01>; 1656 power-domains = <0x21 0x0a>; 1657 status = "okay"; 1658 }; 1659 1660 iommu@fded0480 { 1661 compatible = "rockchip,iommu-v2"; 1662 reg = <0x00 0xfded0480 0x00 0x40>; 1663 interrupts = <0x00 0x3d 0x04>; 1664 interrupt-names = "jpegd_mmu"; 1665 clock-names = "aclk\0iface"; 1666 clocks = <0x1f 0xfb 0x1f 0xfc>; 1667 power-domains = <0x21 0x0a>; 1668 #iommu-cells = <0x00>; 1669 status = "okay"; 1670 phandle = <0x6c>; 1671 }; 1672 1673 vepu@fdee0000 { 1674 compatible = "rockchip,vpu-encoder-v2"; 1675 reg = <0x00 0xfdee0000 0x00 0x400>; 1676 interrupts = <0x00 0x40 0x04>; 1677 clocks = <0x1f 0xfd 0x1f 0xfe>; 1678 clock-names = "aclk_vcodec\0hclk_vcodec"; 1679 rockchip,disable-auto-freq; 1680 resets = <0x1f 0x12e 0x1f 0x12f>; 1681 reset-names = "video_a\0video_h"; 1682 iommus = <0x6d>; 1683 rockchip,srv = <0x6a>; 1684 rockchip,taskqueue-node = <0x02>; 1685 rockchip,resetgroup-node = <0x02>; 1686 power-domains = <0x21 0x0a>; 1687 status = "okay"; 1688 }; 1689 1690 iommu@fdee0800 { 1691 compatible = "rockchip,iommu-v2"; 1692 reg = <0x00 0xfdee0800 0x00 0x40>; 1693 interrupts = <0x00 0x3f 0x04>; 1694 interrupt-names = "vepu_mmu"; 1695 clock-names = "aclk\0iface"; 1696 clocks = <0x1f 0xfd 0x1f 0xfe>; 1697 power-domains = <0x21 0x0a>; 1698 #iommu-cells = <0x00>; 1699 status = "okay"; 1700 phandle = <0x6d>; 1701 }; 1702 1703 iep@fdef0000 { 1704 compatible = "rockchip,iep-v2"; 1705 reg = <0x00 0xfdef0000 0x00 0x500>; 1706 interrupts = <0x00 0x38 0x04>; 1707 clocks = <0x1f 0xf6 0x1f 0xf7 0x1f 0xf8>; 1708 clock-names = "aclk\0hclk\0sclk"; 1709 resets = <0x1f 0x127 0x1f 0x128 0x1f 0x129>; 1710 reset-names = "rst_a\0rst_h\0rst_s"; 1711 power-domains = <0x21 0x0a>; 1712 rockchip,srv = <0x6a>; 1713 rockchip,taskqueue-node = <0x05>; 1714 rockchip,resetgroup-node = <0x05>; 1715 iommus = <0x6e>; 1716 status = "okay"; 1717 }; 1718 1719 iommu@fdef0800 { 1720 compatible = "rockchip,iommu-v2"; 1721 reg = <0x00 0xfdef0800 0x00 0x100>; 1722 interrupts = <0x00 0x38 0x04>; 1723 interrupt-names = "iep_mmu"; 1724 clocks = <0x1f 0xf6 0x1f 0xf7>; 1725 clock-names = "aclk\0iface"; 1726 #iommu-cells = <0x00>; 1727 power-domains = <0x21 0x0a>; 1728 status = "okay"; 1729 phandle = <0x6e>; 1730 }; 1731 1732 eink@fdf00000 { 1733 compatible = "rockchip,rk3568-eink-tcon"; 1734 reg = <0x00 0xfdf00000 0x00 0x74>; 1735 interrupts = <0x00 0xb2 0x04>; 1736 clocks = <0x1f 0xff 0x1f 0x100>; 1737 clock-names = "pclk\0hclk"; 1738 status = "disabled"; 1739 }; 1740 1741 rkvenc@fdf40000 { 1742 compatible = "rockchip,rkv-encoder-v1"; 1743 reg = <0x00 0xfdf40000 0x00 0x400>; 1744 interrupts = <0x00 0x8c 0x04>; 1745 interrupt-names = "irq_enc"; 1746 clocks = <0x1f 0x103 0x1f 0x104 0x1f 0x105>; 1747 clock-names = "aclk_vcodec\0hclk_vcodec\0clk_core"; 1748 rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40>; 1749 resets = <0x1f 0x133 0x1f 0x134 0x1f 0x135>; 1750 reset-names = "video_a\0video_h\0video_core"; 1751 assigned-clocks = <0x1f 0x103 0x1f 0x105>; 1752 assigned-clock-rates = <0x11b3dc40 0x11b3dc40>; 1753 iommus = <0x6f>; 1754 node-name = "rkvenc"; 1755 rockchip,srv = <0x6a>; 1756 rockchip,taskqueue-node = <0x03>; 1757 rockchip,resetgroup-node = <0x03>; 1758 power-domains = <0x21 0x0e>; 1759 operating-points-v2 = <0x70>; 1760 status = "okay"; 1761 venc-supply = <0x65>; 1762 }; 1763 1764 rkvenc-opp-table { 1765 compatible = "operating-points-v2"; 1766 nvmem-cells = <0x07>; 1767 nvmem-cell-names = "pvtm"; 1768 rockchip,pvtm-voltage-sel = <0x00 0x14050 0x00 0x14051 0x16b48 0x01 0x16b49 0x186a0 0x02>; 1769 rockchip,pvtm-ch = <0x00 0x05>; 1770 phandle = <0x70>; 1771 1772 opp-297000000 { 1773 opp-hz = <0x00 0x11b3dc40>; 1774 opp-microvolt = <0x00>; 1775 }; 1776 1777 opp-400000000 { 1778 opp-hz = <0x00 0x17d78400>; 1779 opp-microvolt = <0xe7ef0>; 1780 opp-microvolt-L0 = <0xe7ef0>; 1781 opp-microvolt-L1 = <0xe1d48>; 1782 opp-microvolt-L2 = <0x00>; 1783 }; 1784 }; 1785 1786 iommu@fdf40f00 { 1787 compatible = "rockchip,iommu-v2"; 1788 reg = <0x00 0xfdf40f00 0x00 0x40 0x00 0xfdf40f40 0x00 0x40>; 1789 interrupts = <0x00 0x8d 0x04 0x00 0x8e 0x04>; 1790 interrupt-names = "rkvenc_mmu0\0rkvenc_mmu1"; 1791 clocks = <0x1f 0x103 0x1f 0x104>; 1792 clock-names = "aclk\0iface"; 1793 rockchip,disable-mmu-reset; 1794 rockchip,enable-cmd-retry; 1795 #iommu-cells = <0x00>; 1796 power-domains = <0x21 0x0e>; 1797 status = "okay"; 1798 phandle = <0x6f>; 1799 }; 1800 1801 rkvdec@fdf80200 { 1802 compatible = "rockchip,rkv-decoder-rk3568\0rockchip,rkv-decoder-v2"; 1803 reg = <0x00 0xfdf80200 0x00 0x400>; 1804 interrupts = <0x00 0x5b 0x04>; 1805 interrupt-names = "irq_dec"; 1806 clocks = <0x1f 0x108 0x1f 0x109 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>; 1807 clock-names = "aclk_vcodec\0hclk_vcodec\0clk_cabac\0clk_core\0clk_hevc_cabac"; 1808 rockchip,normal-rates = <0x11b3dc40 0x00 0x11b3dc40 0x11b3dc40 0x23c34600>; 1809 rockchip,advanced-rates = <0x179a7b00 0x00 0x179a7b00 0x179a7b00 0x23c34600>; 1810 rockchip,default-max-load = <0x1fe000>; 1811 resets = <0x1f 0x142 0x1f 0x143 0x1f 0x144 0x1f 0x145 0x1f 0x146>; 1812 assigned-clocks = <0x1f 0x108 0x1f 0x10a 0x1f 0x10b 0x1f 0x10c>; 1813 assigned-clock-rates = <0x11b3dc40 0x11b3dc40 0x11b3dc40 0x11b3dc40>; 1814 reset-names = "video_a\0video_h\0video_cabac\0video_core\0video_hevc_cabac"; 1815 power-domains = <0x21 0x0d>; 1816 iommus = <0x71>; 1817 rockchip,srv = <0x6a>; 1818 rockchip,taskqueue-node = <0x04>; 1819 rockchip,resetgroup-node = <0x04>; 1820 rockchip,sram = <0x72>; 1821 rockchip,rcb-iova = <0x10000000 0x10000>; 1822 rockchip,rcb-min-width = <0x200>; 1823 status = "okay"; 1824 }; 1825 1826 iommu@fdf80800 { 1827 compatible = "rockchip,iommu-v2"; 1828 reg = <0x00 0xfdf80800 0x00 0x40 0x00 0xfdf80840 0x00 0x40>; 1829 interrupts = <0x00 0x5c 0x04>; 1830 interrupt-names = "rkvdec_mmu"; 1831 clocks = <0x1f 0x108 0x1f 0x109>; 1832 clock-names = "aclk\0iface"; 1833 power-domains = <0x21 0x0d>; 1834 #iommu-cells = <0x00>; 1835 status = "okay"; 1836 phandle = <0x71>; 1837 }; 1838 1839 mipi-csi2@fdfb0000 { 1840 compatible = "rockchip,rk3568-mipi-csi2"; 1841 reg = <0x00 0xfdfb0000 0x00 0x10000>; 1842 reg-names = "csihost_regs"; 1843 interrupts = <0x00 0x08 0x04 0x00 0x09 0x04>; 1844 interrupt-names = "csi-intr1\0csi-intr2"; 1845 clocks = <0x1f 0xd5>; 1846 clock-names = "pclk_csi2host"; 1847 resets = <0x1f 0xff>; 1848 reset-names = "srst_csihost_p"; 1849 status = "disabled"; 1850 }; 1851 1852 rkcif@fdfe0000 { 1853 compatible = "rockchip,rk3568-cif"; 1854 reg = <0x00 0xfdfe0000 0x00 0x8000>; 1855 reg-names = "cif_regs"; 1856 interrupts = <0x00 0x92 0x04>; 1857 interrupt-names = "cif-intr"; 1858 clocks = <0x1f 0xce 0x1f 0xcf 0x1f 0xd0 0x1f 0xd1>; 1859 clock-names = "aclk_cif\0hclk_cif\0dclk_cif\0iclk_cif_g"; 1860 resets = <0x1f 0xf7 0x1f 0xf8 0x1f 0xf9 0x1f 0xfb 0x1f 0xfa>; 1861 reset-names = "rst_cif_a\0rst_cif_h\0rst_cif_d\0rst_cif_p\0rst_cif_i"; 1862 assigned-clocks = <0x1f 0xd0>; 1863 assigned-clock-rates = <0x11e1a300>; 1864 power-domains = <0x21 0x08>; 1865 rockchip,grf = <0x33>; 1866 iommus = <0x73>; 1867 status = "okay"; 1868 phandle = <0x74>; 1869 }; 1870 1871 iommu@fdfe0800 { 1872 compatible = "rockchip,iommu-v2"; 1873 reg = <0x00 0xfdfe0800 0x00 0x100>; 1874 interrupts = <0x00 0x92 0x04>; 1875 interrupt-names = "cif_mmu"; 1876 clocks = <0x1f 0xce 0x1f 0xcf>; 1877 clock-names = "aclk\0iface"; 1878 power-domains = <0x21 0x08>; 1879 rockchip,disable-mmu-reset; 1880 #iommu-cells = <0x00>; 1881 status = "okay"; 1882 phandle = <0x73>; 1883 }; 1884 1885 rkcif_dvp { 1886 compatible = "rockchip,rkcif-dvp"; 1887 rockchip,hw = <0x74>; 1888 status = "disabled"; 1889 phandle = <0x75>; 1890 }; 1891 1892 rkcif_dvp_sditf { 1893 compatible = "rockchip,rkcif-sditf"; 1894 rockchip,cif = <0x75>; 1895 status = "disabled"; 1896 }; 1897 1898 rkcif_mipi_lvds { 1899 compatible = "rockchip,rkcif-mipi-lvds"; 1900 rockchip,hw = <0x74>; 1901 status = "disabled"; 1902 phandle = <0x76>; 1903 }; 1904 1905 rkcif_mipi_lvds_sditf { 1906 compatible = "rockchip,rkcif-sditf"; 1907 rockchip,cif = <0x76>; 1908 status = "disabled"; 1909 }; 1910 1911 rkisp@fdff0000 { 1912 compatible = "rockchip,rk3568-rkisp"; 1913 reg = <0x00 0xfdff0000 0x00 0x10000>; 1914 interrupts = <0x00 0x39 0x04 0x00 0x3a 0x04 0x00 0x3c 0x04>; 1915 interrupt-names = "mipi_irq\0mi_irq\0isp_irq"; 1916 clocks = <0x1f 0xd2 0x1f 0xd3 0x1f 0xd4>; 1917 clock-names = "aclk_isp\0hclk_isp\0clk_isp"; 1918 resets = <0x1f 0xfd 0x1f 0xfc>; 1919 reset-names = "isp\0isp-h"; 1920 rockchip,grf = <0x33>; 1921 power-domains = <0x21 0x08>; 1922 iommus = <0x77>; 1923 rockchip,iq-feature = <0x3fb 0xfffe67ff>; 1924 status = "okay"; 1925 phandle = <0x78>; 1926 }; 1927 1928 iommu@fdff1a00 { 1929 compatible = "rockchip,iommu-v2"; 1930 reg = <0x00 0xfdff1a00 0x00 0x100>; 1931 interrupts = <0x00 0x3b 0x04>; 1932 interrupt-names = "isp_mmu"; 1933 clocks = <0x1f 0xd2 0x1f 0xd3>; 1934 clock-names = "aclk\0iface"; 1935 power-domains = <0x21 0x08>; 1936 #iommu-cells = <0x00>; 1937 rockchip,disable-mmu-reset; 1938 status = "okay"; 1939 phandle = <0x77>; 1940 }; 1941 1942 rkisp-vir0 { 1943 compatible = "rockchip,rkisp-vir"; 1944 rockchip,hw = <0x78>; 1945 status = "okay"; 1946 1947 port { 1948 #address-cells = <0x01>; 1949 #size-cells = <0x00>; 1950 1951 endpoint@0 { 1952 reg = <0x00>; 1953 remote-endpoint = <0x79>; 1954 phandle = <0x10b>; 1955 }; 1956 }; 1957 }; 1958 1959 rkisp-vir1 { 1960 compatible = "rockchip,rkisp-vir"; 1961 rockchip,hw = <0x78>; 1962 status = "disabled"; 1963 }; 1964 1965 ethernet@fe010000 { 1966 compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; 1967 reg = <0x00 0xfe010000 0x00 0x10000>; 1968 interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>; 1969 interrupt-names = "macirq\0eth_wake_irq"; 1970 rockchip,grf = <0x33>; 1971 clocks = <0x1f 0x186 0x1f 0x189 0x1f 0x189 0x1f 0xc7 0x1f 0xc3 0x1f 0xc4 0x1f 0x189 0x1f 0xc8 0x1f 0xac>; 1972 clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs"; 1973 resets = <0x1f 0xec>; 1974 reset-names = "stmmaceth"; 1975 snps,mixed-burst; 1976 snps,tso; 1977 snps,axi-config = <0x7a>; 1978 snps,mtl-rx-config = <0x7b>; 1979 snps,mtl-tx-config = <0x7c>; 1980 status = "okay"; 1981 phy-mode = "rgmii"; 1982 clock_in_out = "input"; 1983 snps,reset-gpio = <0x7d 0x0c 0x01>; 1984 snps,reset-active-low; 1985 snps,reset-delays-us = <0x00 0x4e20 0x186a0>; 1986 assigned-clocks = <0x1f 0x189 0x1f 0x186 0x1f 0xc6>; 1987 assigned-clock-parents = <0x1f 0x187 0x7e>; 1988 assigned-clock-rates = <0x00 0x7735940 0x17d7840>; 1989 pinctrl-names = "default"; 1990 pinctrl-0 = <0x7f 0x80 0x81 0x82 0x83 0x84 0x85>; 1991 tx_delay = <0x3a>; 1992 rx_delay = <0x2a>; 1993 phy-handle = <0x86>; 1994 1995 mdio { 1996 compatible = "snps,dwmac-mdio"; 1997 #address-cells = <0x01>; 1998 #size-cells = <0x00>; 1999 2000 phy@0 { 2001 compatible = "ethernet-phy-ieee802.3-c22"; 2002 reg = <0x00>; 2003 clocks = <0x1f 0xc6>; 2004 phandle = <0x86>; 2005 }; 2006 }; 2007 2008 stmmac-axi-config { 2009 snps,wr_osr_lmt = <0x04>; 2010 snps,rd_osr_lmt = <0x08>; 2011 snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; 2012 phandle = <0x7a>; 2013 }; 2014 2015 rx-queues-config { 2016 snps,rx-queues-to-use = <0x01>; 2017 phandle = <0x7b>; 2018 2019 queue0 { 2020 }; 2021 }; 2022 2023 tx-queues-config { 2024 snps,tx-queues-to-use = <0x01>; 2025 phandle = <0x7c>; 2026 2027 queue0 { 2028 }; 2029 }; 2030 }; 2031 2032 vop@fe040000 { 2033 compatible = "rockchip,rk3568-vop"; 2034 reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>; 2035 reg-names = "regs\0gamma_lut"; 2036 rockchip,grf = <0x33>; 2037 interrupts = <0x00 0x94 0x04>; 2038 clocks = <0x1f 0xdd 0x1f 0xde 0x1f 0xdf 0x1f 0xe0 0x1f 0xe1>; 2039 clock-names = "aclk_vop\0hclk_vop\0dclk_vp0\0dclk_vp1\0dclk_vp2"; 2040 iommus = <0x87>; 2041 power-domains = <0x21 0x09>; 2042 status = "okay"; 2043 assigned-clocks = <0x1f 0xdf 0x1f 0xe0>; 2044 assigned-clock-parents = <0x32 0x02 0x1f 0x05>; 2045 2046 ports { 2047 #address-cells = <0x01>; 2048 #size-cells = <0x00>; 2049 phandle = <0x12>; 2050 2051 port@0 { 2052 #address-cells = <0x01>; 2053 #size-cells = <0x00>; 2054 reg = <0x00>; 2055 2056 endpoint@0 { 2057 reg = <0x00>; 2058 remote-endpoint = <0x88>; 2059 phandle = <0x14>; 2060 }; 2061 2062 endpoint@1 { 2063 reg = <0x01>; 2064 remote-endpoint = <0x89>; 2065 phandle = <0x15>; 2066 }; 2067 2068 endpoint@2 { 2069 reg = <0x02>; 2070 remote-endpoint = <0x8a>; 2071 phandle = <0x16>; 2072 }; 2073 2074 endpoint@3 { 2075 reg = <0x03>; 2076 remote-endpoint = <0x8b>; 2077 phandle = <0x17>; 2078 }; 2079 }; 2080 2081 port@1 { 2082 #address-cells = <0x01>; 2083 #size-cells = <0x00>; 2084 reg = <0x01>; 2085 2086 endpoint@0 { 2087 reg = <0x00>; 2088 remote-endpoint = <0x8c>; 2089 phandle = <0x93>; 2090 }; 2091 2092 endpoint@1 { 2093 reg = <0x01>; 2094 remote-endpoint = <0x8d>; 2095 phandle = <0x9b>; 2096 }; 2097 2098 endpoint@2 { 2099 reg = <0x02>; 2100 remote-endpoint = <0x8e>; 2101 phandle = <0xa1>; 2102 }; 2103 2104 endpoint@3 { 2105 reg = <0x03>; 2106 remote-endpoint = <0x8f>; 2107 phandle = <0x9f>; 2108 }; 2109 2110 endpoint@4 { 2111 reg = <0x04>; 2112 remote-endpoint = <0x90>; 2113 phandle = <0x18>; 2114 }; 2115 }; 2116 2117 port@2 { 2118 #address-cells = <0x01>; 2119 #size-cells = <0x00>; 2120 reg = <0x02>; 2121 2122 endpoint@0 { 2123 reg = <0x00>; 2124 remote-endpoint = <0x91>; 2125 phandle = <0x30>; 2126 }; 2127 2128 endpoint@1 { 2129 reg = <0x01>; 2130 remote-endpoint = <0x92>; 2131 phandle = <0x19>; 2132 }; 2133 }; 2134 }; 2135 }; 2136 2137 iommu@fe043e00 { 2138 compatible = "rockchip,iommu-v2"; 2139 reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>; 2140 interrupts = <0x00 0x94 0x04>; 2141 interrupt-names = "vop_mmu"; 2142 clocks = <0x1f 0xdd 0x1f 0xde>; 2143 clock-names = "aclk\0iface"; 2144 #iommu-cells = <0x00>; 2145 rockchip,disable-device-link-resume; 2146 status = "okay"; 2147 phandle = <0x87>; 2148 }; 2149 2150 dsi@fe060000 { 2151 compatible = "rockchip,rk3568-mipi-dsi"; 2152 reg = <0x00 0xfe060000 0x00 0x10000>; 2153 interrupts = <0x00 0x44 0x04>; 2154 clocks = <0x1f 0xe8 0x1f 0xda>; 2155 clock-names = "pclk\0hclk"; 2156 resets = <0x1f 0x110>; 2157 reset-names = "apb"; 2158 phys = <0x2f>; 2159 phy-names = "dphy"; 2160 power-domains = <0x21 0x09>; 2161 rockchip,grf = <0x33>; 2162 #address-cells = <0x01>; 2163 #size-cells = <0x00>; 2164 status = "okay"; 2165 2166 ports { 2167 #address-cells = <0x01>; 2168 #size-cells = <0x00>; 2169 2170 port@0 { 2171 reg = <0x00>; 2172 #address-cells = <0x01>; 2173 #size-cells = <0x00>; 2174 2175 endpoint@0 { 2176 reg = <0x00>; 2177 remote-endpoint = <0x14>; 2178 status = "okay"; 2179 phandle = <0x88>; 2180 }; 2181 2182 endpoint@1 { 2183 reg = <0x01>; 2184 remote-endpoint = <0x93>; 2185 status = "disabled"; 2186 phandle = <0x8c>; 2187 }; 2188 }; 2189 2190 port@1 { 2191 reg = <0x01>; 2192 2193 endpoint { 2194 remote-endpoint = <0x94>; 2195 phandle = <0x99>; 2196 }; 2197 }; 2198 }; 2199 2200 panel@0 { 2201 status = "okay"; 2202 compatible = "simple-panel-dsi"; 2203 reg = <0x00>; 2204 backlight = <0x95>; 2205 reset-delay-ms = <0x78>; 2206 init-delay-ms = <0x78>; 2207 enable-delay-ms = <0x78>; 2208 prepare-delay-ms = <0x78>; 2209 dsi,flags = <0xa03>; 2210 dsi,format = <0x00>; 2211 dsi,lanes = <0x04>; 2212 panel-init-sequence = <0x5780111 0x5050129>; 2213 panel-exit-sequence = <0x5000128 0x5780110>; 2214 power-supply = <0x96>; 2215 reset-gpios = <0x37 0x0f 0x01>; 2216 pinctrl-names = "default"; 2217 pinctrl-0 = <0x97>; 2218 2219 display-timings { 2220 native-mode = <0x98>; 2221 2222 timing0 { 2223 clock-frequency = "\bX;"; 2224 hactive = <0x780>; 2225 vactive = <0x4b0>; 2226 hback-porch = <0x3c>; 2227 hfront-porch = <0x10>; 2228 vback-porch = <0x17>; 2229 vfront-porch = <0x0c>; 2230 hsync-len = <0x14>; 2231 vsync-len = <0x03>; 2232 hsync-active = <0x00>; 2233 vsync-active = <0x00>; 2234 de-active = <0x00>; 2235 pixelclk-active = <0x00>; 2236 phandle = <0x98>; 2237 }; 2238 }; 2239 2240 ports { 2241 #address-cells = <0x01>; 2242 #size-cells = <0x00>; 2243 2244 port@0 { 2245 reg = <0x00>; 2246 2247 endpoint { 2248 remote-endpoint = <0x99>; 2249 phandle = <0x94>; 2250 }; 2251 }; 2252 }; 2253 }; 2254 }; 2255 2256 dsi@fe070000 { 2257 compatible = "rockchip,rk3568-mipi-dsi"; 2258 reg = <0x00 0xfe070000 0x00 0x10000>; 2259 interrupts = <0x00 0x45 0x04>; 2260 clocks = <0x1f 0xe9 0x1f 0xda>; 2261 clock-names = "pclk\0hclk"; 2262 resets = <0x1f 0x111>; 2263 reset-names = "apb"; 2264 phys = <0x9a>; 2265 phy-names = "dphy"; 2266 power-domains = <0x21 0x09>; 2267 rockchip,grf = <0x33>; 2268 #address-cells = <0x01>; 2269 #size-cells = <0x00>; 2270 status = "disabled"; 2271 2272 ports { 2273 #address-cells = <0x01>; 2274 #size-cells = <0x00>; 2275 2276 port@0 { 2277 reg = <0x00>; 2278 #address-cells = <0x01>; 2279 #size-cells = <0x00>; 2280 2281 endpoint@0 { 2282 reg = <0x00>; 2283 remote-endpoint = <0x15>; 2284 status = "disabled"; 2285 phandle = <0x89>; 2286 }; 2287 2288 endpoint@1 { 2289 reg = <0x01>; 2290 remote-endpoint = <0x9b>; 2291 status = "disabled"; 2292 phandle = <0x8d>; 2293 }; 2294 }; 2295 }; 2296 }; 2297 2298 hdmi@fe0a0000 { 2299 compatible = "rockchip,rk3568-dw-hdmi"; 2300 reg = <0x00 0xfe0a0000 0x00 0x20000>; 2301 interrupts = <0x00 0x2d 0x04>; 2302 clocks = <0x1f 0xe6 0x1f 0xe7 0x1f 0x193 0x32 0x02 0x1f 0xde>; 2303 clock-names = "iahb\0isfr\0cec\0ref\0hclk"; 2304 power-domains = <0x21 0x09>; 2305 reg-io-width = <0x04>; 2306 rockchip,grf = <0x33>; 2307 #sound-dai-cells = <0x00>; 2308 pinctrl-names = "default"; 2309 pinctrl-0 = <0x9c 0x9d 0x9e>; 2310 status = "okay"; 2311 rockchip,phy-table = <0x58834d4 0x8009 0x00 0x270 0x9d5b340 0x800b 0x00 0x26d 0xb1069a8 0x800b 0x00 0x1ed 0x11b3dc40 0x800b 0x00 0x1ad 0x2367b880 0x8029 0x00 0x88 0x00 0x00 0x00 0x00>; 2312 phandle = <0x120>; 2313 2314 ports { 2315 #address-cells = <0x01>; 2316 #size-cells = <0x00>; 2317 2318 port { 2319 reg = <0x00>; 2320 #address-cells = <0x01>; 2321 #size-cells = <0x00>; 2322 2323 endpoint@0 { 2324 reg = <0x00>; 2325 remote-endpoint = <0x17>; 2326 status = "okay"; 2327 phandle = <0x8b>; 2328 }; 2329 2330 endpoint@1 { 2331 reg = <0x01>; 2332 remote-endpoint = <0x9f>; 2333 status = "disabled"; 2334 phandle = <0x8f>; 2335 }; 2336 }; 2337 }; 2338 }; 2339 2340 edp@fe0c0000 { 2341 compatible = "rockchip,rk3568-edp"; 2342 reg = <0x00 0xfe0c0000 0x00 0x10000>; 2343 interrupts = <0x00 0x12 0x04>; 2344 clocks = <0x32 0x29 0x1f 0xea 0x1f 0xeb 0x1f 0xda>; 2345 clock-names = "dp\0pclk\0spdif\0hclk"; 2346 resets = <0x1f 0x113 0x1f 0x112>; 2347 reset-names = "dp\0apb"; 2348 phys = <0xa0>; 2349 phy-names = "dp"; 2350 power-domains = <0x21 0x09>; 2351 status = "disabled"; 2352 2353 ports { 2354 #address-cells = <0x01>; 2355 #size-cells = <0x00>; 2356 2357 port@0 { 2358 reg = <0x00>; 2359 #address-cells = <0x01>; 2360 #size-cells = <0x00>; 2361 2362 endpoint@0 { 2363 reg = <0x00>; 2364 remote-endpoint = <0x16>; 2365 status = "disabled"; 2366 phandle = <0x8a>; 2367 }; 2368 2369 endpoint@1 { 2370 reg = <0x01>; 2371 remote-endpoint = <0xa1>; 2372 status = "disabled"; 2373 phandle = <0x8e>; 2374 }; 2375 }; 2376 }; 2377 }; 2378 2379 qos@fe128000 { 2380 compatible = "syscon"; 2381 reg = <0x00 0xfe128000 0x00 0x20>; 2382 phandle = <0x46>; 2383 }; 2384 2385 qos@fe138080 { 2386 compatible = "syscon"; 2387 reg = <0x00 0xfe138080 0x00 0x20>; 2388 phandle = <0x55>; 2389 }; 2390 2391 qos@fe138100 { 2392 compatible = "syscon"; 2393 reg = <0x00 0xfe138100 0x00 0x20>; 2394 phandle = <0x56>; 2395 }; 2396 2397 qos@fe138180 { 2398 compatible = "syscon"; 2399 reg = <0x00 0xfe138180 0x00 0x20>; 2400 phandle = <0x57>; 2401 }; 2402 2403 qos@fe148000 { 2404 compatible = "syscon"; 2405 reg = <0x00 0xfe148000 0x00 0x20>; 2406 phandle = <0x47>; 2407 }; 2408 2409 qos@fe148080 { 2410 compatible = "syscon"; 2411 reg = <0x00 0xfe148080 0x00 0x20>; 2412 phandle = <0x48>; 2413 }; 2414 2415 qos@fe148100 { 2416 compatible = "syscon"; 2417 reg = <0x00 0xfe148100 0x00 0x20>; 2418 phandle = <0x49>; 2419 }; 2420 2421 qos@fe150000 { 2422 compatible = "syscon"; 2423 reg = <0x00 0xfe150000 0x00 0x20>; 2424 phandle = <0x53>; 2425 }; 2426 2427 qos@fe158000 { 2428 compatible = "syscon"; 2429 reg = <0x00 0xfe158000 0x00 0x20>; 2430 phandle = <0x4d>; 2431 }; 2432 2433 qos@fe158100 { 2434 compatible = "syscon"; 2435 reg = <0x00 0xfe158100 0x00 0x20>; 2436 phandle = <0x4e>; 2437 }; 2438 2439 qos@fe158180 { 2440 compatible = "syscon"; 2441 reg = <0x00 0xfe158180 0x00 0x20>; 2442 phandle = <0x4f>; 2443 }; 2444 2445 qos@fe158200 { 2446 compatible = "syscon"; 2447 reg = <0x00 0xfe158200 0x00 0x20>; 2448 phandle = <0x50>; 2449 }; 2450 2451 qos@fe158280 { 2452 compatible = "syscon"; 2453 reg = <0x00 0xfe158280 0x00 0x20>; 2454 phandle = <0x51>; 2455 }; 2456 2457 qos@fe158300 { 2458 compatible = "syscon"; 2459 reg = <0x00 0xfe158300 0x00 0x20>; 2460 phandle = <0x52>; 2461 }; 2462 2463 qos@fe180000 { 2464 compatible = "syscon"; 2465 reg = <0x00 0xfe180000 0x00 0x20>; 2466 }; 2467 2468 qos@fe190000 { 2469 compatible = "syscon"; 2470 reg = <0x00 0xfe190000 0x00 0x20>; 2471 phandle = <0x58>; 2472 }; 2473 2474 qos@fe190080 { 2475 compatible = "syscon"; 2476 reg = <0x00 0xfe190080 0x00 0x20>; 2477 phandle = <0x59>; 2478 }; 2479 2480 qos@fe190100 { 2481 compatible = "syscon"; 2482 reg = <0x00 0xfe190100 0x00 0x20>; 2483 phandle = <0x5a>; 2484 }; 2485 2486 qos@fe190200 { 2487 compatible = "syscon"; 2488 reg = <0x00 0xfe190200 0x00 0x20>; 2489 phandle = <0x5b>; 2490 }; 2491 2492 qos@fe190280 { 2493 compatible = "syscon"; 2494 reg = <0x00 0xfe190280 0x00 0x20>; 2495 phandle = <0x5c>; 2496 }; 2497 2498 qos@fe190300 { 2499 compatible = "syscon"; 2500 reg = <0x00 0xfe190300 0x00 0x20>; 2501 phandle = <0x5d>; 2502 }; 2503 2504 qos@fe190380 { 2505 compatible = "syscon"; 2506 reg = <0x00 0xfe190380 0x00 0x20>; 2507 phandle = <0x5e>; 2508 }; 2509 2510 qos@fe190400 { 2511 compatible = "syscon"; 2512 reg = <0x00 0xfe190400 0x00 0x20>; 2513 phandle = <0x5f>; 2514 }; 2515 2516 qos@fe198000 { 2517 compatible = "syscon"; 2518 reg = <0x00 0xfe198000 0x00 0x20>; 2519 phandle = <0x54>; 2520 }; 2521 2522 qos@fe1a8000 { 2523 compatible = "syscon"; 2524 reg = <0x00 0xfe1a8000 0x00 0x20>; 2525 phandle = <0x4a>; 2526 }; 2527 2528 qos@fe1a8080 { 2529 compatible = "syscon"; 2530 reg = <0x00 0xfe1a8080 0x00 0x20>; 2531 phandle = <0x4b>; 2532 }; 2533 2534 qos@fe1a8100 { 2535 compatible = "syscon"; 2536 reg = <0x00 0xfe1a8100 0x00 0x20>; 2537 phandle = <0x4c>; 2538 }; 2539 2540 dwmmc@fe000000 { 2541 compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; 2542 reg = <0x00 0xfe000000 0x00 0x4000>; 2543 interrupts = <0x00 0x64 0x04>; 2544 max-frequency = <0x5f5e100>; 2545 clocks = <0x1f 0xc1 0x1f 0xc2 0x1f 0x18e 0x1f 0x18f>; 2546 clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; 2547 fifo-depth = <0x100>; 2548 resets = <0x1f 0xeb>; 2549 reset-names = "reset"; 2550 status = "okay"; 2551 supports-sdio; 2552 bus-width = <0x04>; 2553 disable-wp; 2554 cap-sd-highspeed; 2555 cap-sdio-irq; 2556 keep-power-in-suspend; 2557 mmc-pwrseq = <0xa2>; 2558 non-removable; 2559 pinctrl-names = "default"; 2560 pinctrl-0 = <0xa3 0xa4 0xa5>; 2561 sd-uhs-sdr104; 2562 }; 2563 2564 dfi@fe230000 { 2565 reg = <0x00 0xfe230000 0x00 0x400>; 2566 compatible = "rockchip,rk3568-dfi"; 2567 rockchip,pmugrf = <0x34>; 2568 status = "okay"; 2569 phandle = <0xa6>; 2570 }; 2571 2572 dmc { 2573 compatible = "rockchip,rk3568-dmc"; 2574 interrupts = <0x00 0x0a 0x04>; 2575 interrupt-names = "complete"; 2576 devfreq-events = <0xa6>; 2577 clocks = <0x02 0x03>; 2578 clock-names = "dmc_clk"; 2579 operating-points-v2 = <0xa7>; 2580 ddr_timing = <0xa8>; 2581 vop-bw-dmc-freq = <0x00 0x1f9 0x4f1a0 0x1fa 0x1869f 0x80e80>; 2582 upthreshold = <0x28>; 2583 downdifferential = <0x14>; 2584 system-status-level = <0x01 0x04 0x08 0x08 0x02 0x01 0x10 0x04 0x10000 0x04 0x1000 0x08 0x4000 0x08 0x2000 0x08 0xc00 0x08>; 2585 auto-min-freq = <0x4f1a0>; 2586 auto-freq-en = <0x01>; 2587 #cooling-cells = <0x02>; 2588 status = "okay"; 2589 center-supply = <0x65>; 2590 phandle = <0x13>; 2591 }; 2592 2593 dmc-opp-table { 2594 compatible = "operating-points-v2"; 2595 mbist-vmin = <0xc96a8 0xdbba0 0xe7ef0>; 2596 nvmem-cells = <0xa9 0x07 0x08>; 2597 nvmem-cell-names = "leakage\0pvtm\0mbist-vmin"; 2598 rockchip,temp-hysteresis = <0x1388>; 2599 rockchip,low-temp = <0x00>; 2600 rockchip,low-temp-adjust-volt = <0x00 0x618 0x61a8>; 2601 rockchip,leakage-voltage-sel = <0x01 0x50 0x00 0x51 0xfe 0x01>; 2602 phandle = <0xa7>; 2603 2604 opp-1560000000 { 2605 opp-hz = <0x00 0x5cfbb600>; 2606 opp-microvolt = <0xdbba0>; 2607 opp-microvolt-L0 = <0xdbba0>; 2608 opp-microvolt-L1 = <0xcf850>; 2609 }; 2610 }; 2611 2612 pcie@fe260000 { 2613 compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; 2614 #address-cells = <0x03>; 2615 #size-cells = <0x02>; 2616 bus-range = <0x00 0x0f>; 2617 clocks = <0x1f 0x81 0x1f 0x82 0x1f 0x83 0x1f 0x84 0x1f 0x85>; 2618 clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; 2619 device_type = "pci"; 2620 interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>; 2621 interrupt-names = "sys\0pmc\0msg\0legacy\0err"; 2622 #interrupt-cells = <0x01>; 2623 interrupt-map-mask = <0x00 0x00 0x00 0x07>; 2624 interrupt-map = <0x00 0x00 0x00 0x01 0xaa 0x00 0x00 0x00 0x00 0x02 0xaa 0x01 0x00 0x00 0x00 0x03 0xaa 0x02 0x00 0x00 0x00 0x04 0xaa 0x03>; 2625 linux,pci-domain = <0x00>; 2626 num-ib-windows = <0x06>; 2627 num-ob-windows = <0x02>; 2628 max-link-speed = <0x02>; 2629 msi-map = <0x00 0xab 0x00 0x1000>; 2630 num-lanes = <0x01>; 2631 phys = <0x23 0x02>; 2632 phy-names = "pcie-phy"; 2633 power-domains = <0x21 0x0f>; 2634 ranges = <0x800 0x00 0x00 0x03 0x00 0x00 0x800000 0x81000000 0x00 0x800000 0x03 0x800000 0x00 0x100000 0x83000000 0x00 0x900000 0x03 0x900000 0x00 0x3f700000>; 2635 reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000>; 2636 reg-names = "pcie-dbi\0pcie-apb"; 2637 resets = <0x1f 0xa1>; 2638 reset-names = "pipe"; 2639 status = "okay"; 2640 reset-gpios = <0xac 0x0a 0x00>; 2641 vpcie3v3-supply = <0xad>; 2642 2643 legacy-interrupt-controller { 2644 interrupt-controller; 2645 #address-cells = <0x00>; 2646 #interrupt-cells = <0x01>; 2647 interrupt-parent = <0x01>; 2648 interrupts = <0x00 0x48 0x01>; 2649 phandle = <0xaa>; 2650 }; 2651 }; 2652 2653 pcie@fe270000 { 2654 compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; 2655 #address-cells = <0x03>; 2656 #size-cells = <0x02>; 2657 bus-range = <0x10 0x1f>; 2658 clocks = <0x1f 0x88 0x1f 0x89 0x1f 0x8a 0x1f 0x8b 0x1f 0x8c>; 2659 clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; 2660 device_type = "pci"; 2661 interrupts = <0x00 0xa0 0x04 0x00 0x9f 0x04 0x00 0x9e 0x04 0x00 0x9d 0x04 0x00 0x9c 0x04>; 2662 interrupt-names = "sys\0pmc\0msg\0legacy\0err"; 2663 #interrupt-cells = <0x01>; 2664 interrupt-map-mask = <0x00 0x00 0x00 0x07>; 2665 interrupt-map = <0x00 0x00 0x00 0x01 0xae 0x00 0x00 0x00 0x00 0x02 0xae 0x01 0x00 0x00 0x00 0x03 0xae 0x02 0x00 0x00 0x00 0x04 0xae 0x03>; 2666 linux,pci-domain = <0x01>; 2667 num-ib-windows = <0x06>; 2668 num-ob-windows = <0x02>; 2669 max-link-speed = <0x03>; 2670 msi-map = <0x1000 0xab 0x1000 0x1000>; 2671 num-lanes = <0x01>; 2672 phys = <0xaf>; 2673 phy-names = "pcie-phy"; 2674 power-domains = <0x21 0x0f>; 2675 ranges = <0x800 0x00 0x40000000 0x03 0x40000000 0x00 0x800000 0x81000000 0x00 0x40800000 0x03 0x40800000 0x00 0x100000 0x83000000 0x00 0x40900000 0x03 0x40900000 0x00 0x3f700000>; 2676 reg = <0x03 0xc0400000 0x00 0x400000 0x00 0xfe270000 0x00 0x10000>; 2677 reg-names = "pcie-dbi\0pcie-apb"; 2678 resets = <0x1f 0xb1>; 2679 reset-names = "pipe"; 2680 status = "disabled"; 2681 2682 legacy-interrupt-controller { 2683 interrupt-controller; 2684 #address-cells = <0x00>; 2685 #interrupt-cells = <0x01>; 2686 interrupt-parent = <0x01>; 2687 interrupts = <0x00 0x9d 0x01>; 2688 phandle = <0xae>; 2689 }; 2690 }; 2691 2692 pcie@fe280000 { 2693 compatible = "rockchip,rk3568-pcie\0snps,dw-pcie"; 2694 #address-cells = <0x03>; 2695 #size-cells = <0x02>; 2696 bus-range = <0x20 0x2f>; 2697 clocks = <0x1f 0x8f 0x1f 0x90 0x1f 0x91 0x1f 0x92 0x1f 0x93>; 2698 clock-names = "aclk_mst\0aclk_slv\0aclk_dbi\0pclk\0aux"; 2699 device_type = "pci"; 2700 interrupts = <0x00 0xa5 0x04 0x00 0xa4 0x04 0x00 0xa3 0x04 0x00 0xa2 0x04 0x00 0xa1 0x04>; 2701 interrupt-names = "sys\0pmc\0msg\0legacy\0err"; 2702 #interrupt-cells = <0x01>; 2703 interrupt-map-mask = <0x00 0x00 0x00 0x07>; 2704 interrupt-map = <0x00 0x00 0x00 0x01 0xb0 0x00 0x00 0x00 0x00 0x02 0xb0 0x01 0x00 0x00 0x00 0x03 0xb0 0x02 0x00 0x00 0x00 0x04 0xb0 0x03>; 2705 linux,pci-domain = <0x02>; 2706 num-ib-windows = <0x06>; 2707 num-ob-windows = <0x02>; 2708 max-link-speed = <0x03>; 2709 msi-map = <0x2000 0xab 0x2000 0x1000>; 2710 num-lanes = <0x02>; 2711 phys = <0xaf>; 2712 phy-names = "pcie-phy"; 2713 power-domains = <0x21 0x0f>; 2714 ranges = <0x800 0x00 0x80000000 0x03 0x80000000 0x00 0x800000 0x81000000 0x00 0x80800000 0x03 0x80800000 0x00 0x100000 0x83000000 0x00 0x80900000 0x03 0x80900000 0x00 0x3f700000>; 2715 reg = <0x03 0xc0800000 0x00 0x400000 0x00 0xfe280000 0x00 0x10000>; 2716 reg-names = "pcie-dbi\0pcie-apb"; 2717 resets = <0x1f 0xc1>; 2718 reset-names = "pipe"; 2719 status = "disabled"; 2720 2721 legacy-interrupt-controller { 2722 interrupt-controller; 2723 #address-cells = <0x00>; 2724 #interrupt-cells = <0x01>; 2725 interrupt-parent = <0x01>; 2726 interrupts = <0x00 0xa2 0x01>; 2727 phandle = <0xb0>; 2728 }; 2729 }; 2730 2731 ethernet@fe2a0000 { 2732 compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a"; 2733 reg = <0x00 0xfe2a0000 0x00 0x10000>; 2734 interrupts = <0x00 0x1b 0x04 0x00 0x18 0x04>; 2735 interrupt-names = "macirq\0eth_wake_irq"; 2736 rockchip,grf = <0x33>; 2737 clocks = <0x1f 0x182 0x1f 0x185 0x1f 0x185 0x1f 0xb8 0x1f 0xb4 0x1f 0xb5 0x1f 0x185 0x1f 0xb9 0x1f 0xac>; 2738 clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref\0pclk_xpcs"; 2739 resets = <0x1f 0xd7>; 2740 reset-names = "stmmaceth"; 2741 snps,mixed-burst; 2742 snps,tso; 2743 snps,axi-config = <0xb1>; 2744 snps,mtl-rx-config = <0xb2>; 2745 snps,mtl-tx-config = <0xb3>; 2746 status = "disabled"; 2747 2748 mdio { 2749 compatible = "snps,dwmac-mdio"; 2750 #address-cells = <0x01>; 2751 #size-cells = <0x00>; 2752 }; 2753 2754 stmmac-axi-config { 2755 snps,wr_osr_lmt = <0x04>; 2756 snps,rd_osr_lmt = <0x08>; 2757 snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>; 2758 phandle = <0xb1>; 2759 }; 2760 2761 rx-queues-config { 2762 snps,rx-queues-to-use = <0x01>; 2763 phandle = <0xb2>; 2764 2765 queue0 { 2766 }; 2767 }; 2768 2769 tx-queues-config { 2770 snps,tx-queues-to-use = <0x01>; 2771 phandle = <0xb3>; 2772 2773 queue0 { 2774 }; 2775 }; 2776 }; 2777 2778 dwmmc@fe2b0000 { 2779 compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; 2780 reg = <0x00 0xfe2b0000 0x00 0x4000>; 2781 interrupts = <0x00 0x62 0x04>; 2782 max-frequency = <0x8f0d180>; 2783 clocks = <0x1f 0xb0 0x1f 0xb1 0x1f 0x18a 0x1f 0x18b>; 2784 clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; 2785 fifo-depth = <0x100>; 2786 resets = <0x1f 0xd4>; 2787 reset-names = "reset"; 2788 status = "okay"; 2789 supports-sd; 2790 bus-width = <0x04>; 2791 cap-mmc-highspeed; 2792 cap-sd-highspeed; 2793 disable-wp; 2794 sd-uhs-sdr104; 2795 vmmc-supply = <0xb4>; 2796 vqmmc-supply = <0x2c>; 2797 pinctrl-names = "default"; 2798 pinctrl-0 = <0xb5 0xb6 0xb7 0xb8>; 2799 }; 2800 2801 dwmmc@fe2c0000 { 2802 compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc"; 2803 reg = <0x00 0xfe2c0000 0x00 0x4000>; 2804 interrupts = <0x00 0x63 0x04>; 2805 max-frequency = <0x8f0d180>; 2806 clocks = <0x1f 0xb2 0x1f 0xb3 0x1f 0x18c 0x1f 0x18d>; 2807 clock-names = "biu\0ciu\0ciu-drive\0ciu-sample"; 2808 fifo-depth = <0x100>; 2809 resets = <0x1f 0xd6>; 2810 reset-names = "reset"; 2811 status = "disabled"; 2812 }; 2813 2814 sfc@fe300000 { 2815 compatible = "rockchip,sfc"; 2816 reg = <0x00 0xfe300000 0x00 0x4000>; 2817 interrupts = <0x00 0x65 0x04>; 2818 clocks = <0x1f 0x78 0x1f 0x76>; 2819 clock-names = "clk_sfc\0hclk_sfc"; 2820 assigned-clocks = <0x1f 0x78>; 2821 assigned-clock-rates = <0x5f5e100>; 2822 status = "okay"; 2823 }; 2824 2825 sdhci@fe310000 { 2826 compatible = "rockchip,dwcmshc-sdhci\0snps,dwcmshc-sdhci"; 2827 reg = <0x00 0xfe310000 0x00 0x10000>; 2828 interrupts = <0x00 0x13 0x04>; 2829 assigned-clocks = <0x1f 0x7b 0x1f 0x7d>; 2830 assigned-clock-rates = <0xbebc200 0x16e3600>; 2831 clocks = <0x1f 0x7c 0x1f 0x7a 0x1f 0x79 0x1f 0x7b 0x1f 0x7d>; 2832 clock-names = "core\0bus\0axi\0block\0timer"; 2833 status = "okay"; 2834 bus-width = <0x08>; 2835 supports-emmc; 2836 non-removable; 2837 max-frequency = <0xbebc200>; 2838 }; 2839 2840 nandc@fe330000 { 2841 compatible = "rockchip,rk-nandc-v9"; 2842 reg = <0x00 0xfe330000 0x00 0x4000>; 2843 interrupts = <0x00 0x46 0x04>; 2844 nandc_id = <0x00>; 2845 clocks = <0x1f 0x75 0x1f 0x74>; 2846 clock-names = "clk_nandc\0hclk_nandc"; 2847 status = "okay"; 2848 #address-cells = <0x01>; 2849 #size-cells = <0x00>; 2850 2851 nand@0 { 2852 reg = <0x00>; 2853 nand-bus-width = <0x08>; 2854 nand-ecc-mode = "hw"; 2855 nand-ecc-strength = <0x10>; 2856 nand-ecc-step-size = <0x400>; 2857 }; 2858 }; 2859 2860 crypto@fe380000 { 2861 compatible = "rockchip,rk3568-crypto"; 2862 reg = <0x00 0xfe380000 0x00 0x4000>; 2863 interrupts = <0x00 0x04 0x04>; 2864 clocks = <0x1f 0x6a 0x1f 0x6b 0x1f 0x6c 0x1f 0x6d>; 2865 clock-names = "aclk\0hclk\0sclk\0apb_pclk"; 2866 assigned-clocks = <0x1f 0x6c>; 2867 assigned-clock-rates = <0xbebc200>; 2868 resets = <0x1f 0x69>; 2869 reset-names = "crypto-rst"; 2870 status = "disabled"; 2871 }; 2872 2873 rng@fe388000 { 2874 compatible = "rockchip,cryptov2-rng"; 2875 reg = <0x00 0xfe388000 0x00 0x2000>; 2876 clocks = <0x1f 0x70 0x1f 0x6f>; 2877 clock-names = "clk_trng\0hclk_trng"; 2878 resets = <0x1f 0x6d>; 2879 reset-names = "reset"; 2880 status = "okay"; 2881 }; 2882 2883 otp@fe38c000 { 2884 compatible = "rockchip,rk3568-otp"; 2885 reg = <0x00 0xfe38c000 0x00 0x4000>; 2886 #address-cells = <0x01>; 2887 #size-cells = <0x01>; 2888 clocks = <0x1f 0x73 0x1f 0x72 0x1f 0x71 0x1f 0x181>; 2889 clock-names = "usr\0sbpi\0apb\0phy"; 2890 resets = <0x1f 0x1cf>; 2891 reset-names = "otp_phy"; 2892 2893 cpu-code@2 { 2894 reg = <0x02 0x02>; 2895 phandle = <0x0f>; 2896 }; 2897 2898 cpu-version@8 { 2899 reg = <0x08 0x01>; 2900 bits = <0x03 0x03>; 2901 phandle = <0x0e>; 2902 }; 2903 2904 mbist-vmin@9 { 2905 reg = <0x09 0x01>; 2906 bits = <0x00 0x04>; 2907 phandle = <0x08>; 2908 }; 2909 2910 id@a { 2911 reg = <0x0a 0x10>; 2912 phandle = <0x0d>; 2913 }; 2914 2915 cpu-leakage@1a { 2916 reg = <0x1a 0x01>; 2917 phandle = <0x06>; 2918 }; 2919 2920 log-leakage@1b { 2921 reg = <0x1b 0x01>; 2922 phandle = <0xa9>; 2923 }; 2924 2925 npu-leakage@1c { 2926 reg = <0x1c 0x01>; 2927 phandle = <0x63>; 2928 }; 2929 2930 gpu-leakage@1d { 2931 reg = <0x1d 0x01>; 2932 phandle = <0x68>; 2933 }; 2934 2935 core-pvtm@2a { 2936 reg = <0x2a 0x02>; 2937 phandle = <0x07>; 2938 }; 2939 }; 2940 2941 i2s@fe400000 { 2942 compatible = "rockchip,rk3568-i2s-tdm"; 2943 reg = <0x00 0xfe400000 0x00 0x1000>; 2944 interrupts = <0x00 0x34 0x04>; 2945 clocks = <0x1f 0x3f 0x1f 0x43 0x1f 0x39>; 2946 clock-names = "mclk_tx\0mclk_rx\0hclk"; 2947 dmas = <0xb9 0x00>; 2948 dma-names = "tx"; 2949 resets = <0x1f 0x50 0x1f 0x51>; 2950 reset-names = "tx-m\0rx-m"; 2951 rockchip,cru = <0x1f>; 2952 rockchip,grf = <0x33>; 2953 rockchip,playback-only; 2954 #sound-dai-cells = <0x00>; 2955 status = "okay"; 2956 phandle = <0x11f>; 2957 }; 2958 2959 i2s@fe410000 { 2960 compatible = "rockchip,rk3568-i2s-tdm"; 2961 reg = <0x00 0xfe410000 0x00 0x1000>; 2962 interrupts = <0x00 0x35 0x04>; 2963 clocks = <0x1f 0x47 0x1f 0x4b 0x1f 0x3a>; 2964 clock-names = "mclk_tx\0mclk_rx\0hclk"; 2965 dmas = <0xb9 0x02 0xb9 0x03>; 2966 dma-names = "tx\0rx"; 2967 resets = <0x1f 0x52 0x1f 0x53>; 2968 reset-names = "tx-m\0rx-m"; 2969 rockchip,cru = <0x1f>; 2970 rockchip,grf = <0x33>; 2971 #sound-dai-cells = <0x00>; 2972 pinctrl-names = "default"; 2973 pinctrl-0 = <0xba 0xbb 0xbc 0xbd>; 2974 status = "okay"; 2975 rockchip,clk-trcm = <0x01>; 2976 phandle = <0xcc>; 2977 }; 2978 2979 i2s@fe420000 { 2980 compatible = "rockchip,rk3568-i2s-tdm"; 2981 reg = <0x00 0xfe420000 0x00 0x1000>; 2982 interrupts = <0x00 0x36 0x04>; 2983 clocks = <0x1f 0x4f 0x1f 0x4f 0x1f 0x3b>; 2984 clock-names = "mclk_tx\0mclk_rx\0hclk"; 2985 dmas = <0xb9 0x04 0xb9 0x05>; 2986 dma-names = "tx\0rx"; 2987 rockchip,cru = <0x1f>; 2988 rockchip,grf = <0x33>; 2989 rockchip,clk-trcm = <0x01>; 2990 #sound-dai-cells = <0x00>; 2991 pinctrl-names = "default"; 2992 pinctrl-0 = <0xbe 0xbf 0xc0 0xc1>; 2993 status = "disabled"; 2994 }; 2995 2996 i2s@fe430000 { 2997 compatible = "rockchip,rk3568-i2s-tdm"; 2998 reg = <0x00 0xfe430000 0x00 0x1000>; 2999 interrupts = <0x00 0x37 0x04>; 3000 clocks = <0x1f 0x53 0x1f 0x57 0x1f 0x3c>; 3001 clock-names = "mclk_tx\0mclk_rx\0hclk"; 3002 dmas = <0xb9 0x06 0xb9 0x07>; 3003 dma-names = "tx\0rx"; 3004 resets = <0x1f 0x55 0x1f 0x56>; 3005 reset-names = "tx-m\0rx-m"; 3006 rockchip,cru = <0x1f>; 3007 rockchip,grf = <0x33>; 3008 rockchip,clk-trcm = <0x01>; 3009 #sound-dai-cells = <0x00>; 3010 pinctrl-names = "default"; 3011 pinctrl-0 = <0xc2 0xc3 0xc4 0xc5>; 3012 status = "disabled"; 3013 phandle = <0x11d>; 3014 }; 3015 3016 pdm@fe440000 { 3017 compatible = "rockchip,rk3568-pdm\0rockchip,pdm"; 3018 reg = <0x00 0xfe440000 0x00 0x1000>; 3019 clocks = <0x1f 0x5a 0x1f 0x59>; 3020 clock-names = "pdm_clk\0pdm_hclk"; 3021 dmas = <0xb9 0x09>; 3022 dma-names = "rx"; 3023 pinctrl-names = "default"; 3024 pinctrl-0 = <0xc6 0xc7 0xc8 0xc9 0xca 0xcb>; 3025 #sound-dai-cells = <0x00>; 3026 status = "disabled"; 3027 phandle = <0x121>; 3028 }; 3029 3030 vad@fe450000 { 3031 compatible = "rockchip,rk3568-vad"; 3032 reg = <0x00 0xfe450000 0x00 0x10000>; 3033 reg-names = "vad"; 3034 clocks = <0x1f 0x5b>; 3035 clock-names = "hclk"; 3036 interrupts = <0x00 0x89 0x04>; 3037 rockchip,audio-src = <0xcc>; 3038 rockchip,det-channel = <0x00>; 3039 rockchip,mode = <0x00>; 3040 #sound-dai-cells = <0x00>; 3041 status = "disabled"; 3042 rockchip,buffer-time-ms = <0x80>; 3043 phandle = <0x126>; 3044 }; 3045 3046 spdif@fe460000 { 3047 compatible = "rockchip,rk3568-spdif"; 3048 reg = <0x00 0xfe460000 0x00 0x1000>; 3049 interrupts = <0x00 0x66 0x04>; 3050 dmas = <0xb9 0x01>; 3051 dma-names = "tx"; 3052 clock-names = "mclk\0hclk"; 3053 clocks = <0x1f 0x5f 0x1f 0x5c>; 3054 #sound-dai-cells = <0x00>; 3055 pinctrl-names = "default"; 3056 pinctrl-0 = <0xcd>; 3057 status = "disabled"; 3058 phandle = <0x124>; 3059 }; 3060 3061 audpwm@fe470000 { 3062 compatible = "rockchip,rk3568-audio-pwm\0rockchip,audio-pwm-v1"; 3063 reg = <0x00 0xfe470000 0x00 0x1000>; 3064 clocks = <0x1f 0x63 0x1f 0x60>; 3065 clock-names = "clk\0hclk"; 3066 dmas = <0xb9 0x08>; 3067 dma-names = "tx"; 3068 #sound-dai-cells = <0x00>; 3069 rockchip,sample-width-bits = <0x0b>; 3070 rockchip,interpolat-points = <0x01>; 3071 status = "disabled"; 3072 }; 3073 3074 codec-digital@fe478000 { 3075 compatible = "rockchip,rk3568-codec-digital\0rockchip,codec-digital-v1"; 3076 reg = <0x00 0xfe478000 0x00 0x1000>; 3077 clocks = <0x1f 0x67 0x1f 0x66 0x1f 0x65 0x1f 0x64>; 3078 clock-names = "adc\0dac\0i2c\0pclk"; 3079 pinctrl-names = "default"; 3080 pinctrl-0 = <0xce>; 3081 resets = <0x1f 0x5f>; 3082 reset-names = "reset"; 3083 rockchip,grf = <0x33>; 3084 #sound-dai-cells = <0x00>; 3085 status = "disabled"; 3086 phandle = <0x11e>; 3087 }; 3088 3089 dmac@fe530000 { 3090 compatible = "arm,pl330\0arm,primecell"; 3091 reg = <0x00 0xfe530000 0x00 0x4000>; 3092 interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>; 3093 clocks = <0x1f 0x10d>; 3094 clock-names = "apb_pclk"; 3095 #dma-cells = <0x01>; 3096 arm,pl330-periph-burst; 3097 phandle = <0x40>; 3098 }; 3099 3100 dmac@fe550000 { 3101 compatible = "arm,pl330\0arm,primecell"; 3102 reg = <0x00 0xfe550000 0x00 0x4000>; 3103 interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>; 3104 clocks = <0x1f 0x10d>; 3105 clock-names = "apb_pclk"; 3106 #dma-cells = <0x01>; 3107 arm,pl330-periph-burst; 3108 phandle = <0xb9>; 3109 }; 3110 3111 rkscr@fe560000 { 3112 compatible = "rockchip-scr"; 3113 reg = <0x00 0xfe560000 0x00 0x10000>; 3114 interrupts = <0x00 0x61 0x04>; 3115 pinctrl-names = "default"; 3116 pinctrl-0 = <0xcf>; 3117 clocks = <0x1f 0x114>; 3118 clock-names = "g_pclk_sim_card"; 3119 status = "disabled"; 3120 }; 3121 3122 can@fe570000 { 3123 compatible = "rockchip,canfd-1.0"; 3124 reg = <0x00 0xfe570000 0x00 0x1000>; 3125 interrupts = <0x00 0x01 0x04>; 3126 clocks = <0x1f 0x141 0x1f 0x140>; 3127 clock-names = "baudclk\0apb_pclk"; 3128 resets = <0x1f 0x155 0x1f 0x154>; 3129 reset-names = "can\0can-apb"; 3130 tx-fifo-depth = <0x01>; 3131 rx-fifo-depth = <0x06>; 3132 status = "disabled"; 3133 assigned-clocks = <0x1f 0x141>; 3134 assigned-clock-rates = <0x8f0d180>; 3135 pinctrl-names = "default"; 3136 pinctrl-0 = <0xd0>; 3137 }; 3138 3139 can@fe580000 { 3140 compatible = "rockchip,canfd-1.0"; 3141 reg = <0x00 0xfe580000 0x00 0x1000>; 3142 interrupts = <0x00 0x02 0x04>; 3143 clocks = <0x1f 0x143 0x1f 0x142>; 3144 clock-names = "baudclk\0apb_pclk"; 3145 resets = <0x1f 0x157 0x1f 0x156>; 3146 reset-names = "can\0can-apb"; 3147 tx-fifo-depth = <0x01>; 3148 rx-fifo-depth = <0x06>; 3149 status = "disabled"; 3150 assigned-clocks = <0x1f 0x143>; 3151 assigned-clock-rates = <0x8f0d180>; 3152 pinctrl-names = "default"; 3153 pinctrl-0 = <0xd1>; 3154 }; 3155 3156 can@fe590000 { 3157 compatible = "rockchip,canfd-1.0"; 3158 reg = <0x00 0xfe590000 0x00 0x1000>; 3159 interrupts = <0x00 0x03 0x04>; 3160 clocks = <0x1f 0x145 0x1f 0x144>; 3161 clock-names = "baudclk\0apb_pclk"; 3162 resets = <0x1f 0x159 0x1f 0x158>; 3163 reset-names = "can\0can-apb"; 3164 tx-fifo-depth = <0x01>; 3165 rx-fifo-depth = <0x06>; 3166 status = "disabled"; 3167 assigned-clocks = <0x1f 0x145>; 3168 assigned-clock-rates = <0x8f0d180>; 3169 pinctrl-names = "default"; 3170 pinctrl-0 = <0xd2>; 3171 }; 3172 3173 i2c@fe5a0000 { 3174 compatible = "rockchip,rk3399-i2c"; 3175 reg = <0x00 0xfe5a0000 0x00 0x1000>; 3176 clocks = <0x1f 0x148 0x1f 0x147>; 3177 clock-names = "i2c\0pclk"; 3178 interrupts = <0x00 0x2f 0x04>; 3179 pinctrl-names = "default"; 3180 pinctrl-0 = <0xd3>; 3181 #address-cells = <0x01>; 3182 #size-cells = <0x00>; 3183 status = "okay"; 3184 3185 goodix_ts@5d { 3186 compatible = "goodix,gt9xx"; 3187 reg = <0x5d>; 3188 gtp_resolution_x = <0x780>; 3189 gtp_resolution_y = <0x4b0>; 3190 gtp_int_tarigger = <0x01>; 3191 gtp_change_x2y = <0x00>; 3192 gtp_overturn_x = <0x00>; 3193 gtp_overturn_y = <0x00>; 3194 gtp_send_cfg = <0x01>; 3195 gtp_touch_wakeup = <0x00>; 3196 pinctrl-names = "default"; 3197 pinctrl-0 = <0xd4>; 3198 goodix_rst_gpio = <0x37 0x0e 0x00>; 3199 goodix_irq_gpio = <0x37 0x0d 0x02>; 3200 goodix,cfg-group0 = [55 80 07 b0 04 0a 3d 00 01 08 28 05 50 32 03 05 00 00 00 00 00 00 00 18 1a 1e 14 8e 2f 99 17 15 31 0d 00 00 02 9b 03 1d 00 00 00 00 00 00 00 00 00 00 00 1e 78 94 c5 02 08 00 00 00 5b 22 00 4c 2d 00 41 3c 00 38 4f 00 32 69 00 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 04 05 06 07 08 09 0c 0d 0e 0f 10 11 14 15 16 17 ff ff 00 00 00 00 00 00 00 00 00 00 00 02 04 06 07 08 0a 0c 0d 0f 10 11 12 13 19 1b 1c 1e 1f 20 21 22 23 24 25 26 27 28 29 ff ff ff 00 00 00 00 00 00 00 00 00 00 6b 01]; 3201 goodix,cfg-group1 = [55 80 07 b0 04 0a 3d 00 01 08 28 05 50 32 03 05 00 00 00 00 00 00 00 18 1a 1e 14 8e 2f 99 17 15 31 0d 00 00 02 9b 03 1d 00 00 00 00 00 00 00 00 00 00 00 1e 78 94 c5 02 08 00 00 00 5b 22 00 4c 2d 00 41 3c 00 38 4f 00 32 69 00 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 04 05 06 07 08 09 0c 0d 0e 0f 10 11 14 15 16 17 ff ff 00 00 00 00 00 00 00 00 00 00 00 02 04 06 07 08 0a 0c 0d 0f 10 11 12 13 19 1b 1c 1e 1f 20 21 22 23 24 25 26 27 28 29 ff ff ff 00 00 00 00 00 00 00 00 00 00 6b 01]; 3202 }; 3203 }; 3204 3205 i2c@fe5b0000 { 3206 compatible = "rockchip,rk3399-i2c"; 3207 reg = <0x00 0xfe5b0000 0x00 0x1000>; 3208 clocks = <0x1f 0x14a 0x1f 0x149>; 3209 clock-names = "i2c\0pclk"; 3210 interrupts = <0x00 0x30 0x04>; 3211 pinctrl-names = "default"; 3212 pinctrl-0 = <0xd5>; 3213 #address-cells = <0x01>; 3214 #size-cells = <0x00>; 3215 status = "okay"; 3216 3217 gc2093@37 { 3218 compatible = "galaxycore,gc2093"; 3219 reg = <0x37>; 3220 clocks = <0x1f 0xd7>; 3221 clock-names = "xvclk"; 3222 power-domains = <0x21 0x08>; 3223 pinctrl-names = "default\0rockchip,camera_pwr"; 3224 pinctrl-0 = <0xd6>; 3225 pinctrl-1 = <0xd7>; 3226 pwdn-gpios = <0xd8 0x15 0x00>; 3227 reset-gpios = <0xd9 0x10 0x01>; 3228 avdd-supply = <0xda>; 3229 dovdd-supply = <0xda>; 3230 dvdd-supply = <0xda>; 3231 power-supply = <0xda>; 3232 rockchip,camera-module-index = <0x00>; 3233 rockchip,camera-module-facing = "front"; 3234 rockchip,camera-module-name = "YT-RV1109-2-V1"; 3235 rockchip,camera-module-lens-name = "40IR-2MP-F20"; 3236 3237 port { 3238 3239 endpoint { 3240 remote-endpoint = <0xdb>; 3241 data-lanes = <0x01 0x02>; 3242 phandle = <0x10a>; 3243 }; 3244 }; 3245 }; 3246 }; 3247 3248 i2c@fe5c0000 { 3249 compatible = "rockchip,rk3399-i2c"; 3250 reg = <0x00 0xfe5c0000 0x00 0x1000>; 3251 clocks = <0x1f 0x14c 0x1f 0x14b>; 3252 clock-names = "i2c\0pclk"; 3253 interrupts = <0x00 0x31 0x04>; 3254 pinctrl-names = "default"; 3255 pinctrl-0 = <0xdc>; 3256 #address-cells = <0x01>; 3257 #size-cells = <0x00>; 3258 status = "disabled"; 3259 3260 sht4x@44 { 3261 compatible = "sht4x"; 3262 reg = <0x44>; 3263 }; 3264 }; 3265 3266 i2c@fe5d0000 { 3267 compatible = "rockchip,rk3399-i2c"; 3268 reg = <0x00 0xfe5d0000 0x00 0x1000>; 3269 clocks = <0x1f 0x14e 0x1f 0x14d>; 3270 clock-names = "i2c\0pclk"; 3271 interrupts = <0x00 0x32 0x04>; 3272 pinctrl-names = "default"; 3273 pinctrl-0 = <0xdd>; 3274 #address-cells = <0x01>; 3275 #size-cells = <0x00>; 3276 status = "okay"; 3277 3278 hym8563@51 { 3279 status = "okay"; 3280 compatible = "haoyu,hym8563"; 3281 irq-gpios = <0xd8 0x0c 0x01>; 3282 reg = <0x51>; 3283 #clock-cells = <0x00>; 3284 clock-frequency = <0x8000>; 3285 clock-output-names = "hym8563-clkout"; 3286 }; 3287 }; 3288 3289 i2c@fe5e0000 { 3290 compatible = "rockchip,rk3399-i2c"; 3291 reg = <0x00 0xfe5e0000 0x00 0x1000>; 3292 clocks = <0x1f 0x150 0x1f 0x14f>; 3293 clock-names = "i2c\0pclk"; 3294 interrupts = <0x00 0x33 0x04>; 3295 pinctrl-names = "default"; 3296 pinctrl-0 = <0xde>; 3297 #address-cells = <0x01>; 3298 #size-cells = <0x00>; 3299 status = "disabled"; 3300 }; 3301 3302 timer@fe5f0000 { 3303 compatible = "rockchip,rk3568-timer\0rockchip,rk3288-timer"; 3304 reg = <0x00 0xfe5f0000 0x00 0x1000>; 3305 interrupts = <0x00 0x6d 0x04>; 3306 clocks = <0x1f 0x16c 0x1f 0x16d>; 3307 clock-names = "pclk\0timer"; 3308 }; 3309 3310 watchdog@fe600000 { 3311 compatible = "snps,dw-wdt"; 3312 reg = <0x00 0xfe600000 0x00 0x100>; 3313 clocks = <0x1f 0x116 0x1f 0x115>; 3314 clock-names = "tclk\0pclk"; 3315 interrupts = <0x00 0x95 0x04>; 3316 status = "okay"; 3317 }; 3318 3319 spi@fe610000 { 3320 compatible = "rockchip,rk3066-spi"; 3321 reg = <0x00 0xfe610000 0x00 0x1000>; 3322 interrupts = <0x00 0x67 0x04>; 3323 #address-cells = <0x01>; 3324 #size-cells = <0x00>; 3325 clocks = <0x1f 0x152 0x1f 0x151>; 3326 clock-names = "spiclk\0apb_pclk"; 3327 dmas = <0x40 0x14 0x40 0x15>; 3328 dma-names = "tx\0rx"; 3329 pinctrl-names = "default\0high_speed"; 3330 pinctrl-0 = <0xdf 0xe0 0xe1>; 3331 pinctrl-1 = <0xdf 0xe0 0xe2>; 3332 status = "disabled"; 3333 }; 3334 3335 spi@fe620000 { 3336 compatible = "rockchip,rk3066-spi"; 3337 reg = <0x00 0xfe620000 0x00 0x1000>; 3338 interrupts = <0x00 0x68 0x04>; 3339 #address-cells = <0x01>; 3340 #size-cells = <0x00>; 3341 clocks = <0x1f 0x154 0x1f 0x153>; 3342 clock-names = "spiclk\0apb_pclk"; 3343 dmas = <0x40 0x16 0x40 0x17>; 3344 dma-names = "tx\0rx"; 3345 pinctrl-names = "default\0high_speed"; 3346 pinctrl-0 = <0xe3 0xe4>; 3347 pinctrl-1 = <0xe3 0xe5>; 3348 status = "okay"; 3349 }; 3350 3351 spi@fe630000 { 3352 compatible = "rockchip,rk3066-spi"; 3353 reg = <0x00 0xfe630000 0x00 0x1000>; 3354 interrupts = <0x00 0x69 0x04>; 3355 #address-cells = <0x01>; 3356 #size-cells = <0x00>; 3357 clocks = <0x1f 0x156 0x1f 0x155>; 3358 clock-names = "spiclk\0apb_pclk"; 3359 dmas = <0x40 0x18 0x40 0x19>; 3360 dma-names = "tx\0rx"; 3361 pinctrl-names = "default\0high_speed"; 3362 pinctrl-0 = <0xe6 0xe7>; 3363 pinctrl-1 = <0xe6 0xe8>; 3364 status = "okay"; 3365 }; 3366 3367 spi@fe640000 { 3368 compatible = "rockchip,rk3066-spi"; 3369 reg = <0x00 0xfe640000 0x00 0x1000>; 3370 interrupts = <0x00 0x6a 0x04>; 3371 #address-cells = <0x01>; 3372 #size-cells = <0x00>; 3373 clocks = <0x1f 0x158 0x1f 0x157>; 3374 clock-names = "spiclk\0apb_pclk"; 3375 dmas = <0x40 0x1a 0x40 0x1b>; 3376 dma-names = "tx\0rx"; 3377 pinctrl-names = "default\0high_speed"; 3378 pinctrl-0 = <0xe9 0xea>; 3379 pinctrl-1 = <0xe9 0xeb>; 3380 status = "okay"; 3381 }; 3382 3383 serial@fe650000 { 3384 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3385 reg = <0x00 0xfe650000 0x00 0x100>; 3386 interrupts = <0x00 0x75 0x04>; 3387 clocks = <0x1f 0x11f 0x1f 0x11c>; 3388 clock-names = "baudclk\0apb_pclk"; 3389 reg-shift = <0x02>; 3390 reg-io-width = <0x04>; 3391 dmas = <0x40 0x02 0x40 0x03>; 3392 pinctrl-names = "default"; 3393 pinctrl-0 = <0xec 0xed>; 3394 status = "okay"; 3395 }; 3396 3397 serial@fe660000 { 3398 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3399 reg = <0x00 0xfe660000 0x00 0x100>; 3400 interrupts = <0x00 0x76 0x04>; 3401 clocks = <0x1f 0x123 0x1f 0x120>; 3402 clock-names = "baudclk\0apb_pclk"; 3403 reg-shift = <0x02>; 3404 reg-io-width = <0x04>; 3405 dmas = <0x40 0x04 0x40 0x05>; 3406 pinctrl-names = "default"; 3407 pinctrl-0 = <0xee>; 3408 status = "disabled"; 3409 }; 3410 3411 serial@fe670000 { 3412 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3413 reg = <0x00 0xfe670000 0x00 0x100>; 3414 interrupts = <0x00 0x77 0x04>; 3415 clocks = <0x1f 0x127 0x1f 0x124>; 3416 clock-names = "baudclk\0apb_pclk"; 3417 reg-shift = <0x02>; 3418 reg-io-width = <0x04>; 3419 dmas = <0x40 0x06 0x40 0x07>; 3420 pinctrl-names = "default"; 3421 pinctrl-0 = <0xef>; 3422 status = "okay"; 3423 }; 3424 3425 serial@fe680000 { 3426 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3427 reg = <0x00 0xfe680000 0x00 0x100>; 3428 interrupts = <0x00 0x78 0x04>; 3429 clocks = <0x1f 0x12b 0x1f 0x128>; 3430 clock-names = "baudclk\0apb_pclk"; 3431 reg-shift = <0x02>; 3432 reg-io-width = <0x04>; 3433 dmas = <0x40 0x08 0x40 0x09>; 3434 pinctrl-names = "default"; 3435 pinctrl-0 = <0xf0>; 3436 status = "disabled"; 3437 }; 3438 3439 serial@fe690000 { 3440 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3441 reg = <0x00 0xfe690000 0x00 0x100>; 3442 interrupts = <0x00 0x79 0x04>; 3443 clocks = <0x1f 0x12f 0x1f 0x12c>; 3444 clock-names = "baudclk\0apb_pclk"; 3445 reg-shift = <0x02>; 3446 reg-io-width = <0x04>; 3447 dmas = <0x40 0x0a 0x40 0x0b>; 3448 pinctrl-names = "default"; 3449 pinctrl-0 = <0xf1>; 3450 status = "disabled"; 3451 }; 3452 3453 serial@fe6a0000 { 3454 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3455 reg = <0x00 0xfe6a0000 0x00 0x100>; 3456 interrupts = <0x00 0x7a 0x04>; 3457 clocks = <0x1f 0x133 0x1f 0x130>; 3458 clock-names = "baudclk\0apb_pclk"; 3459 reg-shift = <0x02>; 3460 reg-io-width = <0x04>; 3461 dmas = <0x40 0x0c 0x40 0x0d>; 3462 pinctrl-names = "default"; 3463 pinctrl-0 = <0xf2>; 3464 status = "okay"; 3465 }; 3466 3467 serial@fe6b0000 { 3468 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3469 reg = <0x00 0xfe6b0000 0x00 0x100>; 3470 interrupts = <0x00 0x7b 0x04>; 3471 clocks = <0x1f 0x137 0x1f 0x134>; 3472 clock-names = "baudclk\0apb_pclk"; 3473 reg-shift = <0x02>; 3474 reg-io-width = <0x04>; 3475 dmas = <0x40 0x0e 0x40 0x0f>; 3476 pinctrl-names = "default"; 3477 pinctrl-0 = <0xf3>; 3478 status = "okay"; 3479 }; 3480 3481 serial@fe6c0000 { 3482 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3483 reg = <0x00 0xfe6c0000 0x00 0x100>; 3484 interrupts = <0x00 0x7c 0x04>; 3485 clocks = <0x1f 0x13b 0x1f 0x138>; 3486 clock-names = "baudclk\0apb_pclk"; 3487 reg-shift = <0x02>; 3488 reg-io-width = <0x04>; 3489 dmas = <0x40 0x10 0x40 0x11>; 3490 pinctrl-names = "default"; 3491 pinctrl-0 = <0xf4>; 3492 status = "disabled"; 3493 }; 3494 3495 serial@fe6d0000 { 3496 compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; 3497 reg = <0x00 0xfe6d0000 0x00 0x100>; 3498 interrupts = <0x00 0x7d 0x04>; 3499 clocks = <0x1f 0x13f 0x1f 0x13c>; 3500 clock-names = "baudclk\0apb_pclk"; 3501 reg-shift = <0x02>; 3502 reg-io-width = <0x04>; 3503 dmas = <0x40 0x12 0x40 0x13>; 3504 pinctrl-names = "default"; 3505 pinctrl-0 = <0xf5>; 3506 status = "okay"; 3507 }; 3508 3509 pwm@fe6e0000 { 3510 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3511 reg = <0x00 0xfe6e0000 0x00 0x10>; 3512 #pwm-cells = <0x03>; 3513 pinctrl-names = "active"; 3514 pinctrl-0 = <0xf6>; 3515 clocks = <0x1f 0x15a 0x1f 0x159>; 3516 clock-names = "pwm\0pclk"; 3517 status = "okay"; 3518 phandle = <0x132>; 3519 }; 3520 3521 pwm@fe6e0010 { 3522 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3523 reg = <0x00 0xfe6e0010 0x00 0x10>; 3524 #pwm-cells = <0x03>; 3525 pinctrl-names = "active"; 3526 pinctrl-0 = <0xf7>; 3527 clocks = <0x1f 0x15a 0x1f 0x159>; 3528 clock-names = "pwm\0pclk"; 3529 status = "okay"; 3530 }; 3531 3532 pwm@fe6e0020 { 3533 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3534 reg = <0x00 0xfe6e0020 0x00 0x10>; 3535 #pwm-cells = <0x03>; 3536 pinctrl-names = "active"; 3537 pinctrl-0 = <0xf8>; 3538 clocks = <0x1f 0x15a 0x1f 0x159>; 3539 clock-names = "pwm\0pclk"; 3540 status = "disabled"; 3541 }; 3542 3543 pwm@fe6e0030 { 3544 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3545 reg = <0x00 0xfe6e0030 0x00 0x10>; 3546 interrupts = <0x00 0x53 0x04 0x00 0x57 0x04>; 3547 #pwm-cells = <0x03>; 3548 pinctrl-names = "active"; 3549 pinctrl-0 = <0xf9>; 3550 clocks = <0x1f 0x15a 0x1f 0x159>; 3551 clock-names = "pwm\0pclk"; 3552 status = "okay"; 3553 }; 3554 3555 pwm@fe6f0000 { 3556 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3557 reg = <0x00 0xfe6f0000 0x00 0x10>; 3558 #pwm-cells = <0x03>; 3559 pinctrl-names = "active"; 3560 pinctrl-0 = <0xfa>; 3561 clocks = <0x1f 0x15d 0x1f 0x15c>; 3562 clock-names = "pwm\0pclk"; 3563 status = "disabled"; 3564 }; 3565 3566 pwm@fe6f0010 { 3567 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3568 reg = <0x00 0xfe6f0010 0x00 0x10>; 3569 #pwm-cells = <0x03>; 3570 pinctrl-names = "active"; 3571 pinctrl-0 = <0xfb>; 3572 clocks = <0x1f 0x15d 0x1f 0x15c>; 3573 clock-names = "pwm\0pclk"; 3574 status = "disabled"; 3575 }; 3576 3577 pwm@fe6f0020 { 3578 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3579 reg = <0x00 0xfe6f0020 0x00 0x10>; 3580 #pwm-cells = <0x03>; 3581 pinctrl-names = "active"; 3582 pinctrl-0 = <0xfc>; 3583 clocks = <0x1f 0x15d 0x1f 0x15c>; 3584 clock-names = "pwm\0pclk"; 3585 status = "disabled"; 3586 }; 3587 3588 pwm@fe6f0030 { 3589 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3590 reg = <0x00 0xfe6f0030 0x00 0x10>; 3591 interrupts = <0x00 0x54 0x04 0x00 0x58 0x04>; 3592 #pwm-cells = <0x03>; 3593 pinctrl-names = "active"; 3594 pinctrl-0 = <0xfd>; 3595 clocks = <0x1f 0x15d 0x1f 0x15c>; 3596 clock-names = "pwm\0pclk"; 3597 status = "disabled"; 3598 }; 3599 3600 pwm@fe700000 { 3601 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3602 reg = <0x00 0xfe700000 0x00 0x10>; 3603 #pwm-cells = <0x03>; 3604 pinctrl-names = "active"; 3605 pinctrl-0 = <0xfe>; 3606 clocks = <0x1f 0x160 0x1f 0x15f>; 3607 clock-names = "pwm\0pclk"; 3608 status = "okay"; 3609 }; 3610 3611 pwm@fe700010 { 3612 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3613 reg = <0x00 0xfe700010 0x00 0x10>; 3614 #pwm-cells = <0x03>; 3615 pinctrl-names = "active"; 3616 pinctrl-0 = <0xff>; 3617 clocks = <0x1f 0x160 0x1f 0x15f>; 3618 clock-names = "pwm\0pclk"; 3619 status = "disabled"; 3620 }; 3621 3622 pwm@fe700020 { 3623 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3624 reg = <0x00 0xfe700020 0x00 0x10>; 3625 #pwm-cells = <0x03>; 3626 pinctrl-names = "active"; 3627 pinctrl-0 = <0x100>; 3628 clocks = <0x1f 0x160 0x1f 0x15f>; 3629 clock-names = "pwm\0pclk"; 3630 status = "disabled"; 3631 }; 3632 3633 pwm@fe700030 { 3634 compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm"; 3635 reg = <0x00 0xfe700030 0x00 0x10>; 3636 interrupts = <0x00 0x55 0x04 0x00 0x59 0x04>; 3637 #pwm-cells = <0x03>; 3638 pinctrl-names = "active"; 3639 pinctrl-0 = <0x101>; 3640 clocks = <0x1f 0x160 0x1f 0x15f>; 3641 clock-names = "pwm\0pclk"; 3642 status = "disabled"; 3643 }; 3644 3645 tsadc@fe710000 { 3646 compatible = "rockchip,rk3568-tsadc"; 3647 reg = <0x00 0xfe710000 0x00 0x100>; 3648 interrupts = <0x00 0x73 0x04>; 3649 rockchip,grf = <0x33>; 3650 clocks = <0x1f 0x111 0x1f 0x10f>; 3651 clock-names = "tsadc\0apb_pclk"; 3652 assigned-clocks = <0x1f 0x110 0x1f 0x111>; 3653 assigned-clock-rates = <0x1036640 0xaae60>; 3654 resets = <0x1f 0x182 0x1f 0x181 0x1f 0x1d7>; 3655 reset-names = "tsadc\0tsadc-apb\0tsadc-phy"; 3656 #thermal-sensor-cells = <0x01>; 3657 rockchip,hw-tshut-temp = <0x1d4c0>; 3658 rockchip,hw-tshut-mode = <0x00>; 3659 rockchip,hw-tshut-polarity = <0x00>; 3660 pinctrl-names = "gpio\0otpout"; 3661 pinctrl-0 = <0x102>; 3662 pinctrl-1 = <0x103>; 3663 status = "okay"; 3664 phandle = <0x1b>; 3665 }; 3666 3667 saradc@fe720000 { 3668 compatible = "rockchip,rk3568-saradc\0rockchip,rk3399-saradc"; 3669 reg = <0x00 0xfe720000 0x00 0x100>; 3670 interrupts = <0x00 0x5d 0x04>; 3671 #io-channel-cells = <0x01>; 3672 clocks = <0x1f 0x113 0x1f 0x112>; 3673 clock-names = "saradc\0apb_pclk"; 3674 resets = <0x1f 0x180>; 3675 reset-names = "saradc-apb"; 3676 status = "okay"; 3677 vref-supply = <0x104>; 3678 phandle = <0x11b>; 3679 }; 3680 3681 mailbox@fe780000 { 3682 compatible = "rockchip,rk3568-mailbox\0rockchip,rk3368-mailbox"; 3683 reg = <0x00 0xfe780000 0x00 0x1000>; 3684 interrupts = <0x00 0xb7 0x04 0x00 0xb8 0x04 0x00 0xb9 0x04 0x00 0xba 0x04>; 3685 clocks = <0x1f 0x11b>; 3686 clock-names = "pclk_mailbox"; 3687 #mbox-cells = <0x01>; 3688 status = "disabled"; 3689 }; 3690 3691 phy@fe820000 { 3692 compatible = "rockchip,rk3568-naneng-combphy"; 3693 reg = <0x00 0xfe820000 0x00 0x100>; 3694 #phy-cells = <0x01>; 3695 clocks = <0x32 0x1f 0x1f 0x17c 0x1f 0x7f>; 3696 clock-names = "refclk\0apbclk\0pipe_clk"; 3697 assigned-clocks = <0x32 0x1f>; 3698 assigned-clock-rates = <0x5f5e100>; 3699 resets = <0x1f 0x1c4 0x1f 0x1c5>; 3700 reset-names = "combphy-apb\0combphy"; 3701 rockchip,pipe-grf = <0x105>; 3702 rockchip,pipe-phy-grf = <0x106>; 3703 status = "okay"; 3704 phandle = <0x20>; 3705 }; 3706 3707 phy@fe830000 { 3708 compatible = "rockchip,rk3568-naneng-combphy"; 3709 reg = <0x00 0xfe830000 0x00 0x100>; 3710 #phy-cells = <0x01>; 3711 clocks = <0x32 0x22 0x1f 0x17d 0x1f 0x7f>; 3712 clock-names = "refclk\0apbclk\0pipe_clk"; 3713 assigned-clocks = <0x32 0x22>; 3714 assigned-clock-rates = <0x5f5e100>; 3715 resets = <0x1f 0x1c6 0x1f 0x1c7>; 3716 reset-names = "combphy-apb\0combphy"; 3717 rockchip,pipe-grf = <0x105>; 3718 rockchip,pipe-phy-grf = <0x107>; 3719 status = "okay"; 3720 phandle = <0x22>; 3721 }; 3722 3723 phy@fe840000 { 3724 compatible = "rockchip,rk3568-naneng-combphy"; 3725 reg = <0x00 0xfe840000 0x00 0x100>; 3726 #phy-cells = <0x01>; 3727 clocks = <0x32 0x25 0x1f 0x17e 0x1f 0x7f>; 3728 clock-names = "refclk\0apbclk\0pipe_clk"; 3729 assigned-clocks = <0x32 0x25>; 3730 assigned-clock-rates = <0x5f5e100>; 3731 resets = <0x1f 0x1c8 0x1f 0x1c9>; 3732 reset-names = "combphy-apb\0combphy"; 3733 rockchip,pipe-grf = <0x105>; 3734 rockchip,pipe-phy-grf = <0x108>; 3735 status = "okay"; 3736 phandle = <0x23>; 3737 }; 3738 3739 phy@fe850000 { 3740 compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy"; 3741 reg = <0x00 0xfe850000 0x00 0x10000 0x00 0xfe060000 0x00 0x10000>; 3742 reg-names = "phy\0host"; 3743 clocks = <0x32 0x17 0x1f 0x17a 0x1f 0xe8>; 3744 clock-names = "ref\0pclk\0pclk_host"; 3745 #clock-cells = <0x00>; 3746 resets = <0x1f 0x1bb>; 3747 reset-names = "apb"; 3748 power-domains = <0x21 0x09>; 3749 #phy-cells = <0x00>; 3750 status = "okay"; 3751 phandle = <0x2f>; 3752 }; 3753 3754 phy@fe860000 { 3755 compatible = "rockchip,rk3568-dsi-dphy\0rockchip,rk3568-video-phy"; 3756 reg = <0x00 0xfe860000 0x00 0x10000 0x00 0xfe070000 0x00 0x10000>; 3757 reg-names = "phy\0host"; 3758 clocks = <0x32 0x19 0x1f 0x17b 0x1f 0xe9>; 3759 clock-names = "ref\0pclk\0pclk_host"; 3760 #clock-cells = <0x00>; 3761 resets = <0x1f 0x1bc>; 3762 reset-names = "apb"; 3763 power-domains = <0x21 0x09>; 3764 #phy-cells = <0x00>; 3765 status = "disabled"; 3766 phandle = <0x9a>; 3767 }; 3768 3769 csi2-dphy-hw@fe870000 { 3770 compatible = "rockchip,rk3568-csi2-dphy-hw"; 3771 reg = <0x00 0xfe870000 0x00 0x1000>; 3772 clocks = <0x1f 0x179>; 3773 clock-names = "pclk"; 3774 rockchip,grf = <0x33>; 3775 status = "okay"; 3776 phandle = <0x109>; 3777 }; 3778 3779 csi2-dphy0 { 3780 compatible = "rockchip,rk3568-csi2-dphy"; 3781 rockchip,hw = <0x109>; 3782 status = "okay"; 3783 3784 ports { 3785 #address-cells = <0x01>; 3786 #size-cells = <0x00>; 3787 3788 port@0 { 3789 reg = <0x00>; 3790 #address-cells = <0x01>; 3791 #size-cells = <0x00>; 3792 3793 endpoint@0 { 3794 reg = <0x00>; 3795 remote-endpoint = <0x10a>; 3796 data-lanes = <0x01>; 3797 phandle = <0xdb>; 3798 }; 3799 }; 3800 3801 port@1 { 3802 reg = <0x01>; 3803 #address-cells = <0x01>; 3804 #size-cells = <0x00>; 3805 3806 endpoint@0 { 3807 reg = <0x00>; 3808 remote-endpoint = <0x10b>; 3809 phandle = <0x79>; 3810 }; 3811 }; 3812 }; 3813 }; 3814 3815 csi2-dphy1 { 3816 compatible = "rockchip,rk3568-csi2-dphy"; 3817 rockchip,hw = <0x109>; 3818 status = "disabled"; 3819 }; 3820 3821 csi2-dphy2 { 3822 compatible = "rockchip,rk3568-csi2-dphy"; 3823 rockchip,hw = <0x109>; 3824 status = "disabled"; 3825 }; 3826 3827 usb2-phy@fe8a0000 { 3828 compatible = "rockchip,rk3568-usb2phy"; 3829 reg = <0x00 0xfe8a0000 0x00 0x10000>; 3830 interrupts = <0x00 0x87 0x04>; 3831 clocks = <0x32 0x13>; 3832 clock-names = "phyclk"; 3833 #clock-cells = <0x00>; 3834 assigned-clocks = <0x1f 0x0b>; 3835 assigned-clock-parents = <0x25>; 3836 clock-output-names = "usb480m_phy"; 3837 rockchip,usbgrf = <0x10c>; 3838 status = "okay"; 3839 phandle = <0x25>; 3840 3841 host-port { 3842 #phy-cells = <0x00>; 3843 status = "okay"; 3844 phy-supply = <0x10d>; 3845 phandle = <0x26>; 3846 }; 3847 3848 otg-port { 3849 #phy-cells = <0x00>; 3850 status = "okay"; 3851 vbus-supply = <0x10e>; 3852 phandle = <0x24>; 3853 }; 3854 }; 3855 3856 usb2-phy@fe8b0000 { 3857 compatible = "rockchip,rk3568-usb2phy"; 3858 reg = <0x00 0xfe8b0000 0x00 0x10000>; 3859 interrupts = <0x00 0x88 0x04>; 3860 clocks = <0x32 0x15>; 3861 clock-names = "phyclk"; 3862 #clock-cells = <0x00>; 3863 rockchip,usbgrf = <0x10f>; 3864 status = "okay"; 3865 phandle = <0x27>; 3866 3867 host-port { 3868 #phy-cells = <0x00>; 3869 status = "okay"; 3870 phy-supply = <0x10d>; 3871 phandle = <0x29>; 3872 }; 3873 3874 otg-port { 3875 #phy-cells = <0x00>; 3876 status = "okay"; 3877 phy-supply = <0x10d>; 3878 phandle = <0x28>; 3879 }; 3880 }; 3881 3882 phy@fe8c0000 { 3883 compatible = "rockchip,rk3568-pcie3-phy"; 3884 reg = <0x00 0xfe8c0000 0x00 0x20000>; 3885 #phy-cells = <0x00>; 3886 clocks = <0x32 0x26 0x32 0x27 0x1f 0x177>; 3887 clock-names = "refclk_m\0refclk_n\0pclk"; 3888 resets = <0x1f 0x1be>; 3889 reset-names = "phy"; 3890 rockchip,phy-grf = <0x110>; 3891 status = "disabled"; 3892 phandle = <0xaf>; 3893 }; 3894 3895 pinctrl { 3896 compatible = "rockchip,rk3568-pinctrl"; 3897 rockchip,grf = <0x33>; 3898 rockchip,pmu = <0x34>; 3899 #address-cells = <0x02>; 3900 #size-cells = <0x02>; 3901 ranges; 3902 3903 gpio0@fdd60000 { 3904 compatible = "rockchip,gpio-bank"; 3905 reg = <0x00 0xfdd60000 0x00 0x100>; 3906 interrupts = <0x00 0x21 0x04>; 3907 clocks = <0x32 0x2e 0x32 0x0c>; 3908 gpio-controller; 3909 #gpio-cells = <0x02>; 3910 interrupt-controller; 3911 #interrupt-cells = <0x02>; 3912 phandle = <0x37>; 3913 }; 3914 3915 gpio1@fe740000 { 3916 compatible = "rockchip,gpio-bank"; 3917 reg = <0x00 0xfe740000 0x00 0x100>; 3918 interrupts = <0x00 0x22 0x04>; 3919 clocks = <0x1f 0x163 0x1f 0x164>; 3920 gpio-controller; 3921 #gpio-cells = <0x02>; 3922 interrupt-controller; 3923 #interrupt-cells = <0x02>; 3924 phandle = <0xac>; 3925 }; 3926 3927 gpio2@fe750000 { 3928 compatible = "rockchip,gpio-bank"; 3929 reg = <0x00 0xfe750000 0x00 0x100>; 3930 interrupts = <0x00 0x23 0x04>; 3931 clocks = <0x1f 0x165 0x1f 0x166>; 3932 gpio-controller; 3933 #gpio-cells = <0x02>; 3934 interrupt-controller; 3935 #interrupt-cells = <0x02>; 3936 phandle = <0xd8>; 3937 }; 3938 3939 gpio3@fe760000 { 3940 compatible = "rockchip,gpio-bank"; 3941 reg = <0x00 0xfe760000 0x00 0x100>; 3942 interrupts = <0x00 0x24 0x04>; 3943 clocks = <0x1f 0x167 0x1f 0x168>; 3944 gpio-controller; 3945 #gpio-cells = <0x02>; 3946 interrupt-controller; 3947 #interrupt-cells = <0x02>; 3948 phandle = <0x7d>; 3949 }; 3950 3951 gpio4@fe770000 { 3952 compatible = "rockchip,gpio-bank"; 3953 reg = <0x00 0xfe770000 0x00 0x100>; 3954 interrupts = <0x00 0x25 0x04>; 3955 clocks = <0x1f 0x169 0x1f 0x16a>; 3956 gpio-controller; 3957 #gpio-cells = <0x02>; 3958 interrupt-controller; 3959 #interrupt-cells = <0x02>; 3960 phandle = <0xd9>; 3961 }; 3962 3963 pcfg-pull-up { 3964 bias-pull-up; 3965 phandle = <0x114>; 3966 }; 3967 3968 pcfg-pull-down { 3969 bias-pull-down; 3970 phandle = <0x112>; 3971 }; 3972 3973 pcfg-pull-none { 3974 bias-disable; 3975 phandle = <0x111>; 3976 }; 3977 3978 pcfg-pull-none-drv-level-1 { 3979 bias-disable; 3980 drive-strength = <0x01>; 3981 phandle = <0x116>; 3982 }; 3983 3984 pcfg-pull-none-drv-level-2 { 3985 bias-disable; 3986 drive-strength = <0x02>; 3987 phandle = <0x115>; 3988 }; 3989 3990 pcfg-pull-none-drv-level-3 { 3991 bias-disable; 3992 drive-strength = <0x03>; 3993 phandle = <0x11a>; 3994 }; 3995 3996 pcfg-pull-up-drv-level-1 { 3997 bias-pull-up; 3998 drive-strength = <0x01>; 3999 phandle = <0x119>; 4000 }; 4001 4002 pcfg-pull-up-drv-level-2 { 4003 bias-pull-up; 4004 drive-strength = <0x02>; 4005 phandle = <0x113>; 4006 }; 4007 4008 pcfg-pull-none-smt { 4009 bias-disable; 4010 input-schmitt-enable; 4011 phandle = <0x117>; 4012 }; 4013 4014 pcfg-output-low-pull-down { 4015 output-low; 4016 bias-pull-down; 4017 phandle = <0x118>; 4018 }; 4019 4020 acodec { 4021 4022 acodec-pins { 4023 rockchip,pins = <0x01 0x09 0x05 0x111 0x01 0x01 0x05 0x111 0x01 0x00 0x05 0x111 0x01 0x07 0x05 0x111 0x01 0x08 0x05 0x111 0x01 0x03 0x05 0x111 0x01 0x05 0x05 0x111>; 4024 phandle = <0xce>; 4025 }; 4026 }; 4027 4028 cam { 4029 4030 cam-clkout0 { 4031 rockchip,pins = <0x04 0x07 0x01 0x111>; 4032 phandle = <0xd6>; 4033 }; 4034 4035 cam-sleep { 4036 rockchip,pins = <0x04 0x07 0x00 0x111>; 4037 }; 4038 4039 camera-pwr { 4040 rockchip,pins = <0x00 0x11 0x00 0x111>; 4041 phandle = <0xd7>; 4042 }; 4043 4044 cam-reset { 4045 rockchip,pins = <0x04 0x10 0x00 0x112>; 4046 }; 4047 4048 cam-pwdn { 4049 rockchip,pins = <0x02 0x15 0x00 0x111>; 4050 }; 4051 }; 4052 4053 can0 { 4054 4055 can0m1-pins { 4056 rockchip,pins = <0x02 0x02 0x04 0x111 0x02 0x01 0x04 0x111>; 4057 phandle = <0xd0>; 4058 }; 4059 }; 4060 4061 can1 { 4062 4063 can1m1-pins { 4064 rockchip,pins = <0x04 0x12 0x03 0x111 0x04 0x13 0x03 0x111>; 4065 phandle = <0xd1>; 4066 }; 4067 }; 4068 4069 can2 { 4070 4071 can2m1-pins { 4072 rockchip,pins = <0x02 0x09 0x04 0x111 0x02 0x0a 0x04 0x111>; 4073 phandle = <0xd2>; 4074 }; 4075 }; 4076 4077 clk32k { 4078 4079 clk32k-out0 { 4080 rockchip,pins = <0x00 0x08 0x02 0x111>; 4081 phandle = <0x1e>; 4082 }; 4083 }; 4084 4085 ebc { 4086 4087 ebc-pins { 4088 rockchip,pins = <0x04 0x10 0x02 0x111 0x04 0x0b 0x02 0x111 0x04 0x0c 0x02 0x111 0x04 0x06 0x02 0x111 0x04 0x11 0x02 0x111 0x03 0x16 0x02 0x111 0x03 0x17 0x02 0x111 0x03 0x18 0x02 0x111 0x03 0x19 0x02 0x111 0x03 0x1a 0x02 0x111 0x03 0x1b 0x02 0x111 0x03 0x1c 0x02 0x111 0x03 0x1d 0x02 0x111 0x03 0x1e 0x02 0x111 0x03 0x1f 0x02 0x111 0x04 0x00 0x02 0x111 0x04 0x01 0x02 0x111 0x04 0x02 0x02 0x111 0x04 0x03 0x02 0x111 0x04 0x04 0x02 0x111 0x04 0x05 0x02 0x111 0x04 0x0e 0x02 0x111 0x04 0x0f 0x02 0x111>; 4089 phandle = <0x6b>; 4090 }; 4091 }; 4092 4093 eth1 { 4094 4095 eth1m0-pins { 4096 rockchip,pins = <0x03 0x08 0x03 0x111>; 4097 phandle = <0x85>; 4098 }; 4099 }; 4100 4101 gmac1 { 4102 4103 gmac1m0-miim { 4104 rockchip,pins = <0x03 0x14 0x03 0x111 0x03 0x15 0x03 0x111>; 4105 phandle = <0x7f>; 4106 }; 4107 4108 gmac1m0-clkinout { 4109 rockchip,pins = <0x03 0x10 0x03 0x111>; 4110 phandle = <0x84>; 4111 }; 4112 4113 gmac1m0-rx-bus2 { 4114 rockchip,pins = <0x03 0x09 0x03 0x111 0x03 0x0a 0x03 0x111 0x03 0x0b 0x03 0x111>; 4115 phandle = <0x81>; 4116 }; 4117 4118 gmac1m0-tx-bus2 { 4119 rockchip,pins = <0x03 0x0d 0x03 0x115 0x03 0x0e 0x03 0x115 0x03 0x0f 0x03 0x111>; 4120 phandle = <0x80>; 4121 }; 4122 4123 gmac1m0-rgmii-clk { 4124 rockchip,pins = <0x03 0x07 0x03 0x111 0x03 0x06 0x03 0x116>; 4125 phandle = <0x82>; 4126 }; 4127 4128 gmac1m0-rgmii-bus { 4129 rockchip,pins = <0x03 0x04 0x03 0x111 0x03 0x05 0x03 0x111 0x03 0x02 0x03 0x115 0x03 0x03 0x03 0x115>; 4130 phandle = <0x83>; 4131 }; 4132 }; 4133 4134 hdmitx { 4135 4136 hdmitxm0-cec { 4137 rockchip,pins = <0x04 0x19 0x01 0x111>; 4138 phandle = <0x9e>; 4139 }; 4140 4141 hdmitx-scl { 4142 rockchip,pins = <0x04 0x17 0x01 0x111>; 4143 phandle = <0x9c>; 4144 }; 4145 4146 hdmitx-sda { 4147 rockchip,pins = <0x04 0x18 0x01 0x111>; 4148 phandle = <0x9d>; 4149 }; 4150 }; 4151 4152 i2c0 { 4153 4154 i2c0-xfer { 4155 rockchip,pins = <0x00 0x09 0x01 0x117 0x00 0x0a 0x01 0x117>; 4156 phandle = <0x35>; 4157 }; 4158 }; 4159 4160 i2c1 { 4161 4162 i2c1-xfer { 4163 rockchip,pins = <0x00 0x0b 0x01 0x117 0x00 0x0c 0x01 0x117>; 4164 phandle = <0xd3>; 4165 }; 4166 }; 4167 4168 i2c2 { 4169 4170 i2c2m1-xfer { 4171 rockchip,pins = <0x04 0x0d 0x01 0x117 0x04 0x0c 0x01 0x117>; 4172 phandle = <0xd5>; 4173 }; 4174 }; 4175 4176 i2c3 { 4177 4178 i2c3m0-xfer { 4179 rockchip,pins = <0x01 0x01 0x01 0x117 0x01 0x00 0x01 0x117>; 4180 phandle = <0xdc>; 4181 }; 4182 }; 4183 4184 i2c4 { 4185 4186 i2c4m1-xfer { 4187 rockchip,pins = <0x02 0x0a 0x02 0x117 0x02 0x09 0x02 0x117>; 4188 phandle = <0xdd>; 4189 }; 4190 }; 4191 4192 i2c5 { 4193 4194 i2c5m0-xfer { 4195 rockchip,pins = <0x03 0x0b 0x04 0x117 0x03 0x0c 0x04 0x117>; 4196 phandle = <0xde>; 4197 }; 4198 }; 4199 4200 i2s1 { 4201 4202 i2s1m0-lrcktx { 4203 rockchip,pins = <0x01 0x05 0x01 0x111>; 4204 phandle = <0xbb>; 4205 }; 4206 4207 i2s1m0-mclk { 4208 rockchip,pins = <0x01 0x02 0x01 0x111>; 4209 phandle = <0x3f>; 4210 }; 4211 4212 i2s1m0-sclktx { 4213 rockchip,pins = <0x01 0x03 0x01 0x111>; 4214 phandle = <0xba>; 4215 }; 4216 4217 i2s1m0-sdi0 { 4218 rockchip,pins = <0x01 0x0b 0x01 0x111>; 4219 phandle = <0xbc>; 4220 }; 4221 4222 i2s1m0-sdo0 { 4223 rockchip,pins = <0x01 0x07 0x01 0x111>; 4224 phandle = <0xbd>; 4225 }; 4226 }; 4227 4228 i2s2 { 4229 4230 i2s2m0-lrcktx { 4231 rockchip,pins = <0x02 0x13 0x01 0x111>; 4232 phandle = <0xbf>; 4233 }; 4234 4235 i2s2m0-sclktx { 4236 rockchip,pins = <0x02 0x12 0x01 0x111>; 4237 phandle = <0xbe>; 4238 }; 4239 4240 i2s2m0-sdi { 4241 rockchip,pins = <0x02 0x15 0x01 0x111>; 4242 phandle = <0xc0>; 4243 }; 4244 4245 i2s2m0-sdo { 4246 rockchip,pins = <0x02 0x14 0x01 0x111>; 4247 phandle = <0xc1>; 4248 }; 4249 }; 4250 4251 i2s3 { 4252 4253 i2s3m0-lrck { 4254 rockchip,pins = <0x03 0x04 0x04 0x111>; 4255 phandle = <0xc3>; 4256 }; 4257 4258 i2s3m0-sclk { 4259 rockchip,pins = <0x03 0x03 0x04 0x111>; 4260 phandle = <0xc2>; 4261 }; 4262 4263 i2s3m0-sdi { 4264 rockchip,pins = <0x03 0x06 0x04 0x111>; 4265 phandle = <0xc4>; 4266 }; 4267 4268 i2s3m0-sdo { 4269 rockchip,pins = <0x03 0x05 0x04 0x111>; 4270 phandle = <0xc5>; 4271 }; 4272 }; 4273 4274 lcdc { 4275 4276 lcdc-ctl { 4277 rockchip,pins = <0x03 0x00 0x01 0x111 0x02 0x18 0x01 0x111 0x02 0x19 0x01 0x111 0x02 0x1a 0x01 0x111 0x02 0x1b 0x01 0x111 0x02 0x1c 0x01 0x111 0x02 0x1d 0x01 0x111 0x02 0x1e 0x01 0x111 0x02 0x1f 0x01 0x111 0x03 0x01 0x01 0x111 0x03 0x02 0x01 0x111 0x03 0x03 0x01 0x111 0x03 0x04 0x01 0x111 0x03 0x05 0x01 0x111 0x03 0x06 0x01 0x111 0x03 0x07 0x01 0x111 0x03 0x08 0x01 0x111 0x03 0x09 0x01 0x111 0x03 0x0a 0x01 0x111 0x03 0x0b 0x01 0x111 0x03 0x0c 0x01 0x111 0x03 0x0d 0x01 0x111 0x03 0x0e 0x01 0x111 0x03 0x0f 0x01 0x111 0x03 0x10 0x01 0x111 0x03 0x13 0x01 0x111 0x03 0x11 0x01 0x111 0x03 0x12 0x01 0x111>; 4278 phandle = <0x31>; 4279 }; 4280 }; 4281 4282 pdm { 4283 4284 pdmm0-clk { 4285 rockchip,pins = <0x01 0x06 0x03 0x111>; 4286 phandle = <0xc6>; 4287 }; 4288 4289 pdmm0-clk1 { 4290 rockchip,pins = <0x01 0x04 0x03 0x111>; 4291 phandle = <0xc7>; 4292 }; 4293 4294 pdmm0-sdi0 { 4295 rockchip,pins = <0x01 0x0b 0x02 0x111>; 4296 phandle = <0xc8>; 4297 }; 4298 4299 pdmm0-sdi1 { 4300 rockchip,pins = <0x01 0x0a 0x03 0x111>; 4301 phandle = <0xc9>; 4302 }; 4303 4304 pdmm0-sdi2 { 4305 rockchip,pins = <0x01 0x09 0x03 0x111>; 4306 phandle = <0xca>; 4307 }; 4308 4309 pdmm0-sdi3 { 4310 rockchip,pins = <0x01 0x08 0x03 0x111>; 4311 phandle = <0xcb>; 4312 }; 4313 }; 4314 4315 pmic { 4316 4317 pmic_int { 4318 rockchip,pins = <0x00 0x03 0x00 0x114>; 4319 phandle = <0x38>; 4320 }; 4321 4322 soc_slppin_gpio { 4323 rockchip,pins = <0x00 0x02 0x00 0x118>; 4324 phandle = <0x3b>; 4325 }; 4326 4327 soc_slppin_slp { 4328 rockchip,pins = <0x00 0x02 0x01 0x114>; 4329 phandle = <0x39>; 4330 }; 4331 4332 soc_slppin_rst { 4333 rockchip,pins = <0x00 0x02 0x02 0x111>; 4334 }; 4335 }; 4336 4337 pwm0 { 4338 4339 pwm0m0-pins { 4340 rockchip,pins = <0x00 0x0f 0x01 0x111>; 4341 phandle = <0x42>; 4342 }; 4343 }; 4344 4345 pwm1 { 4346 4347 pwm1m0-pins { 4348 rockchip,pins = <0x00 0x10 0x01 0x111>; 4349 phandle = <0x43>; 4350 }; 4351 }; 4352 4353 pwm2 { 4354 4355 pwm2m0-pins { 4356 rockchip,pins = <0x00 0x11 0x01 0x111>; 4357 phandle = <0x44>; 4358 }; 4359 }; 4360 4361 pwm3 { 4362 4363 pwm3-pins { 4364 rockchip,pins = <0x00 0x12 0x01 0x111>; 4365 phandle = <0x45>; 4366 }; 4367 }; 4368 4369 pwm4 { 4370 4371 pwm4-pins { 4372 rockchip,pins = <0x00 0x13 0x01 0x111>; 4373 phandle = <0xf6>; 4374 }; 4375 }; 4376 4377 pwm5 { 4378 4379 pwm5-pins { 4380 rockchip,pins = <0x00 0x14 0x01 0x111>; 4381 phandle = <0xf7>; 4382 }; 4383 }; 4384 4385 pwm6 { 4386 4387 pwm6-pins { 4388 rockchip,pins = <0x00 0x15 0x01 0x111>; 4389 phandle = <0xf8>; 4390 }; 4391 }; 4392 4393 pwm7 { 4394 4395 pwm7-pins { 4396 rockchip,pins = <0x00 0x16 0x01 0x111>; 4397 phandle = <0xf9>; 4398 }; 4399 }; 4400 4401 pwm8 { 4402 4403 pwm8m0-pins { 4404 rockchip,pins = <0x03 0x09 0x05 0x111>; 4405 phandle = <0xfa>; 4406 }; 4407 }; 4408 4409 pwm9 { 4410 4411 pwm9m0-pins { 4412 rockchip,pins = <0x03 0x0a 0x05 0x111>; 4413 phandle = <0xfb>; 4414 }; 4415 }; 4416 4417 pwm10 { 4418 4419 pwm10m0-pins { 4420 rockchip,pins = <0x03 0x0d 0x05 0x111>; 4421 phandle = <0xfc>; 4422 }; 4423 }; 4424 4425 pwm11 { 4426 4427 pwm11m0-pins { 4428 rockchip,pins = <0x03 0x0e 0x05 0x111>; 4429 phandle = <0xfd>; 4430 }; 4431 }; 4432 4433 pwm12 { 4434 4435 pwm12m0-pins { 4436 rockchip,pins = <0x03 0x0f 0x02 0x111>; 4437 phandle = <0xfe>; 4438 }; 4439 }; 4440 4441 pwm13 { 4442 4443 pwm13m0-pins { 4444 rockchip,pins = <0x03 0x10 0x02 0x111>; 4445 phandle = <0xff>; 4446 }; 4447 }; 4448 4449 pwm14 { 4450 4451 pwm14m0-pins { 4452 rockchip,pins = <0x03 0x14 0x01 0x111>; 4453 phandle = <0x100>; 4454 }; 4455 }; 4456 4457 pwm15 { 4458 4459 pwm15m0-pins { 4460 rockchip,pins = <0x03 0x15 0x01 0x111>; 4461 phandle = <0x101>; 4462 }; 4463 }; 4464 4465 scr { 4466 4467 scr-pins { 4468 rockchip,pins = <0x01 0x02 0x03 0x111 0x01 0x07 0x03 0x114 0x01 0x03 0x03 0x114 0x01 0x05 0x03 0x111>; 4469 phandle = <0xcf>; 4470 }; 4471 }; 4472 4473 sdmmc0 { 4474 4475 sdmmc0-bus4 { 4476 rockchip,pins = <0x01 0x1d 0x01 0x113 0x01 0x1e 0x01 0x113 0x01 0x1f 0x01 0x113 0x02 0x00 0x01 0x113>; 4477 phandle = <0xb5>; 4478 }; 4479 4480 sdmmc0-clk { 4481 rockchip,pins = <0x02 0x02 0x01 0x113>; 4482 phandle = <0xb6>; 4483 }; 4484 4485 sdmmc0-cmd { 4486 rockchip,pins = <0x02 0x01 0x01 0x113>; 4487 phandle = <0xb7>; 4488 }; 4489 4490 sdmmc0-det { 4491 rockchip,pins = <0x00 0x04 0x01 0x114>; 4492 phandle = <0xb8>; 4493 }; 4494 }; 4495 4496 sdmmc2 { 4497 4498 sdmmc2m0-bus4 { 4499 rockchip,pins = <0x03 0x16 0x03 0x113 0x03 0x17 0x03 0x113 0x03 0x18 0x03 0x113 0x03 0x19 0x03 0x113>; 4500 phandle = <0xa3>; 4501 }; 4502 4503 sdmmc2m0-clk { 4504 rockchip,pins = <0x03 0x1b 0x03 0x113>; 4505 phandle = <0xa5>; 4506 }; 4507 4508 sdmmc2m0-cmd { 4509 rockchip,pins = <0x03 0x1a 0x03 0x113>; 4510 phandle = <0xa4>; 4511 }; 4512 }; 4513 4514 spdif { 4515 4516 spdifm0-tx { 4517 rockchip,pins = <0x01 0x04 0x04 0x111>; 4518 phandle = <0xcd>; 4519 }; 4520 }; 4521 4522 spi0 { 4523 4524 spi0m0-pins { 4525 rockchip,pins = <0x00 0x0d 0x02 0x111 0x00 0x15 0x02 0x111 0x00 0x0e 0x02 0x111>; 4526 phandle = <0xe1>; 4527 }; 4528 4529 spi0m0-cs0 { 4530 rockchip,pins = <0x00 0x16 0x02 0x111>; 4531 phandle = <0xdf>; 4532 }; 4533 4534 spi0m0-cs1 { 4535 rockchip,pins = <0x00 0x14 0x02 0x111>; 4536 phandle = <0xe0>; 4537 }; 4538 }; 4539 4540 spi1 { 4541 4542 spi1m0-pins { 4543 rockchip,pins = <0x02 0x0d 0x03 0x111 0x02 0x0e 0x03 0x111 0x02 0x0f 0x04 0x111>; 4544 phandle = <0xe4>; 4545 }; 4546 4547 spi1m0-cs0 { 4548 rockchip,pins = <0x02 0x10 0x04 0x111>; 4549 phandle = <0xe3>; 4550 }; 4551 }; 4552 4553 spi2 { 4554 4555 spi2m0-pins { 4556 rockchip,pins = <0x02 0x11 0x04 0x111 0x02 0x12 0x04 0x111 0x02 0x13 0x04 0x111>; 4557 phandle = <0xe7>; 4558 }; 4559 4560 spi2m0-cs0 { 4561 rockchip,pins = <0x02 0x14 0x04 0x111>; 4562 phandle = <0xe6>; 4563 }; 4564 }; 4565 4566 spi3 { 4567 4568 spi3m1-pins { 4569 rockchip,pins = <0x04 0x12 0x02 0x111 0x04 0x15 0x02 0x111 0x04 0x13 0x02 0x111>; 4570 phandle = <0xea>; 4571 }; 4572 4573 spi3m1-cs0 { 4574 rockchip,pins = <0x04 0x16 0x02 0x111>; 4575 phandle = <0xe9>; 4576 }; 4577 }; 4578 4579 tsadc { 4580 4581 tsadc-shutorg { 4582 rockchip,pins = <0x00 0x01 0x02 0x111>; 4583 phandle = <0x103>; 4584 }; 4585 }; 4586 4587 uart0 { 4588 4589 uart0-xfer { 4590 rockchip,pins = <0x00 0x10 0x03 0x114 0x00 0x11 0x03 0x114>; 4591 phandle = <0x41>; 4592 }; 4593 }; 4594 4595 uart1 { 4596 4597 uart1m1-xfer { 4598 rockchip,pins = <0x03 0x1f 0x04 0x114 0x03 0x1e 0x04 0x114>; 4599 phandle = <0xec>; 4600 }; 4601 4602 uart1m1-ctsn { 4603 rockchip,pins = <0x04 0x11 0x04 0x111>; 4604 phandle = <0xed>; 4605 }; 4606 4607 uart1m1-rtsn { 4608 rockchip,pins = <0x04 0x0e 0x04 0x111>; 4609 phandle = <0x12e>; 4610 }; 4611 }; 4612 4613 uart2 { 4614 4615 uart2m0-xfer { 4616 rockchip,pins = <0x00 0x18 0x01 0x114 0x00 0x19 0x01 0x114>; 4617 phandle = <0xee>; 4618 }; 4619 }; 4620 4621 uart3 { 4622 4623 uart3m0-xfer { 4624 rockchip,pins = <0x01 0x00 0x02 0x114 0x01 0x01 0x02 0x114>; 4625 phandle = <0xef>; 4626 }; 4627 }; 4628 4629 uart4 { 4630 4631 uart4m0-xfer { 4632 rockchip,pins = <0x01 0x04 0x02 0x114 0x01 0x06 0x02 0x114>; 4633 phandle = <0xf0>; 4634 }; 4635 }; 4636 4637 uart5 { 4638 4639 uart5m0-xfer { 4640 rockchip,pins = <0x02 0x01 0x03 0x114 0x02 0x02 0x03 0x114>; 4641 phandle = <0xf1>; 4642 }; 4643 }; 4644 4645 uart6 { 4646 4647 uart6m0-xfer { 4648 rockchip,pins = <0x02 0x03 0x03 0x114 0x02 0x04 0x03 0x114>; 4649 phandle = <0xf2>; 4650 }; 4651 }; 4652 4653 uart7 { 4654 4655 uart7m0-xfer { 4656 rockchip,pins = <0x02 0x05 0x03 0x114 0x02 0x06 0x03 0x114>; 4657 phandle = <0xf3>; 4658 }; 4659 }; 4660 4661 uart8 { 4662 4663 uart8m0-xfer { 4664 rockchip,pins = <0x02 0x16 0x02 0x114 0x02 0x15 0x03 0x114>; 4665 phandle = <0xf4>; 4666 }; 4667 }; 4668 4669 uart9 { 4670 4671 uart9m0-xfer { 4672 rockchip,pins = <0x02 0x07 0x03 0x114 0x02 0x08 0x03 0x114>; 4673 phandle = <0xf5>; 4674 }; 4675 4676 rs485-pins { 4677 rockchip,pins = <0x04 0x04 0x04 0x111 0x04 0x05 0x04 0x111>; 4678 }; 4679 }; 4680 4681 spi0-hs { 4682 4683 spi0m0-pins { 4684 rockchip,pins = <0x00 0x0d 0x02 0x119 0x00 0x15 0x02 0x119 0x00 0x0e 0x02 0x119>; 4685 phandle = <0xe2>; 4686 }; 4687 }; 4688 4689 spi1-hs { 4690 4691 spi1m0-pins { 4692 rockchip,pins = <0x02 0x0d 0x03 0x119 0x02 0x0e 0x03 0x119 0x02 0x0f 0x04 0x119>; 4693 phandle = <0xe5>; 4694 }; 4695 }; 4696 4697 spi2-hs { 4698 4699 spi2m0-pins { 4700 rockchip,pins = <0x02 0x11 0x04 0x119 0x02 0x12 0x04 0x119 0x02 0x13 0x04 0x119>; 4701 phandle = <0xe8>; 4702 }; 4703 }; 4704 4705 spi3-hs { 4706 4707 spi3m1-pins { 4708 rockchip,pins = <0x04 0x12 0x02 0x119 0x04 0x15 0x02 0x119 0x04 0x13 0x02 0x119>; 4709 phandle = <0xeb>; 4710 }; 4711 }; 4712 4713 gpio-func { 4714 4715 tsadc-gpio-func { 4716 rockchip,pins = <0x00 0x01 0x00 0x111>; 4717 phandle = <0x102>; 4718 }; 4719 }; 4720 4721 mxc6655xa { 4722 4723 mxc6655xa_irq_gpio { 4724 rockchip,pins = <0x03 0x11 0x00 0x111>; 4725 }; 4726 }; 4727 4728 touch { 4729 4730 touch-gpio { 4731 rockchip,pins = <0x00 0x0d 0x00 0x114 0x00 0x0e 0x00 0x111>; 4732 }; 4733 }; 4734 4735 sdio-pwrseq { 4736 4737 wifi-enable-h { 4738 rockchip,pins = <0x03 0x1d 0x00 0x111>; 4739 phandle = <0x12c>; 4740 }; 4741 }; 4742 4743 usb { 4744 4745 vcc5v0-host-en { 4746 rockchip,pins = <0x00 0x06 0x00 0x111 0x00 0x08 0x00 0x114>; 4747 phandle = <0x129>; 4748 }; 4749 4750 vcc5v0-otg-en { 4751 rockchip,pins = <0x00 0x05 0x00 0x111>; 4752 phandle = <0x12a>; 4753 }; 4754 }; 4755 4756 wireless-bluetooth { 4757 4758 uart1-gpios { 4759 rockchip,pins = <0x04 0x0e 0x00 0x111>; 4760 phandle = <0x130>; 4761 }; 4762 4763 bt-gpios { 4764 rockchip,pins = <0x04 0x05 0x00 0x111 0x04 0x06 0x00 0x111 0x04 0x09 0x00 0x111>; 4765 phandle = <0x12f>; 4766 }; 4767 }; 4768 4769 headphone { 4770 4771 hp-det { 4772 rockchip,pins = <0x03 0x01 0x00 0x112>; 4773 phandle = <0x131>; 4774 }; 4775 }; 4776 4777 wireless-wlan { 4778 4779 wifi-host-wake-irq { 4780 rockchip,pins = <0x03 0x1c 0x00 0x112>; 4781 phandle = <0x12d>; 4782 }; 4783 }; 4784 4785 lcd0 { 4786 4787 lcd0-rst-gpio { 4788 rockchip,pins = <0x00 0x0f 0x00 0x111>; 4789 phandle = <0x97>; 4790 }; 4791 4792 tp-irq-gpio { 4793 rockchip,pins = <0x00 0x0d 0x00 0x111>; 4794 phandle = <0xd4>; 4795 }; 4796 }; 4797 4798 lcd1 { 4799 4800 lcd1-rst-gpio { 4801 rockchip,pins = <0x03 0x04 0x00 0x111>; 4802 }; 4803 }; 4804 4805 tp { 4806 4807 tp-enable-h { 4808 rockchip,pins = <0x00 0x1d 0x00 0x111>; 4809 }; 4810 }; 4811 4812 lcd { 4813 4814 lcd-enable-gpio { 4815 rockchip,pins = <0x00 0x17 0x00 0x111>; 4816 }; 4817 }; 4818 4819 fusb30x { 4820 4821 fusb0-int { 4822 rockchip,pins = <0x00 0x15 0x00 0x114>; 4823 }; 4824 }; 4825 4826 rotary { 4827 4828 rotary_gpio { 4829 rockchip,pins = <0x04 0x13 0x00 0x111 0x01 0x09 0x00 0x111>; 4830 }; 4831 }; 4832 4833 pwmled { 4834 4835 pwm_led { 4836 rockchip,pins = <0x00 0x0f 0x01 0x111 0x00 0x16 0x01 0x111 0x04 0x15 0x01 0x111>; 4837 }; 4838 }; 4839 4840 gpiokey { 4841 4842 gpio_key { 4843 rockchip,pins = <0x04 0x16 0x00 0x111>; 4844 }; 4845 }; 4846 4847 gmac { 4848 4849 rmii-pins { 4850 rockchip,pins = <0x03 0x09 0x03 0x111 0x03 0x0a 0x03 0x111 0x03 0x0b 0x03 0x111 0x03 0x0c 0x03 0x111 0x03 0x0d 0x03 0x115 0x03 0x0e 0x03 0x115 0x03 0x0f 0x03 0x111 0x03 0x10 0x03 0x111 0x03 0x14 0x03 0x111 0x03 0x15 0x03 0x111 0x04 0x12 0x00 0x111>; 4851 }; 4852 }; 4853 }; 4854 4855 chosen { 4856 bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=a2d37d82-51e0-420d-83f5-470db993dd35 hardware=rk3566 rw rootwait default_boot_device=fe310000.sdhci rw rootwait ohos.required_mount.system=/dev/block/platform/fe310000.sdhci/by-name/system@/usr@ext4@ro,barrier=1@wait,required ohos.required_mount.vendor=/dev/block/platform/fe310000.sdhci/by-name/vendor@/vendor@ext4@ro,barrier=1@wait,required ohos.required_mount.misc=/dev/block/platform/fe310000.sdhci/by-name/misc@none@none@none@wait,required"; 4857 }; 4858 4859 adc-keys { 4860 compatible = "adc-keys"; 4861 io-channels = <0x11b 0x00>; 4862 io-channel-names = "buttons"; 4863 keyup-threshold-microvolt = <0x1b7740>; 4864 poll-interval = <0x64>; 4865 4866 vol-up-key { 4867 label = "volume up"; 4868 linux,code = <0x73>; 4869 press-threshold-microvolt = <0x6d6>; 4870 }; 4871 4872 vol-down-key { 4873 label = "volume down"; 4874 linux,code = <0x72>; 4875 press-threshold-microvolt = <0x48a1c>; 4876 }; 4877 4878 menu-key { 4879 label = "menu"; 4880 linux,code = <0x8b>; 4881 press-threshold-microvolt = <0xef420>; 4882 }; 4883 4884 back-key { 4885 label = "back"; 4886 linux,code = <0x9e>; 4887 press-threshold-microvolt = <0x13eb9c>; 4888 }; 4889 }; 4890 4891 audiopwmout-diff { 4892 status = "disabled"; 4893 compatible = "simple-audio-card"; 4894 simple-audio-card,format = "i2s"; 4895 simple-audio-card,name = "rockchip,audiopwmout-diff"; 4896 simple-audio-card,mclk-fs = <0x100>; 4897 simple-audio-card,bitclock-master = <0x11c>; 4898 simple-audio-card,frame-master = <0x11c>; 4899 4900 simple-audio-card,cpu { 4901 sound-dai = <0x11d>; 4902 }; 4903 4904 simple-audio-card,codec { 4905 sound-dai = <0x11e>; 4906 phandle = <0x11c>; 4907 }; 4908 }; 4909 4910 dc-12v { 4911 compatible = "regulator-fixed"; 4912 regulator-name = "dc_12v"; 4913 regulator-always-on; 4914 regulator-boot-on; 4915 regulator-min-microvolt = <0xb71b00>; 4916 regulator-max-microvolt = <0xb71b00>; 4917 phandle = <0x127>; 4918 }; 4919 4920 hdmi-sound { 4921 compatible = "simple-audio-card"; 4922 simple-audio-card,format = "i2s"; 4923 simple-audio-card,mclk-fs = <0x80>; 4924 simple-audio-card,name = "rockchip,hdmi"; 4925 status = "okay"; 4926 4927 simple-audio-card,cpu { 4928 sound-dai = <0x11f>; 4929 }; 4930 4931 simple-audio-card,codec { 4932 sound-dai = <0x120>; 4933 }; 4934 }; 4935 4936 leds { 4937 compatible = "gpio-leds"; 4938 4939 work { 4940 gpios = <0x37 0x10 0x00>; 4941 linux,default-trigger = "heartbeat"; 4942 }; 4943 }; 4944 4945 dummy-codec { 4946 status = "disabled"; 4947 compatible = "rockchip,dummy-codec"; 4948 #sound-dai-cells = <0x00>; 4949 phandle = <0x122>; 4950 }; 4951 4952 pdm-mic-array { 4953 status = "disabled"; 4954 compatible = "simple-audio-card"; 4955 simple-audio-card,name = "rockchip,pdm-mic-array"; 4956 4957 simple-audio-card,cpu { 4958 sound-dai = <0x121>; 4959 }; 4960 4961 simple-audio-card,codec { 4962 sound-dai = <0x122>; 4963 }; 4964 }; 4965 4966 rk809-sound { 4967 status = "okay"; 4968 compatible = "simple-audio-card"; 4969 simple-audio-card,format = "i2s"; 4970 simple-audio-card,name = "rockchip,rk809-codec"; 4971 simple-audio-card,mclk-fs = <0x100>; 4972 4973 simple-audio-card,cpu { 4974 sound-dai = <0xcc>; 4975 }; 4976 4977 simple-audio-card,codec { 4978 sound-dai = <0x123>; 4979 }; 4980 }; 4981 4982 spdif-sound { 4983 status = "okay"; 4984 compatible = "simple-audio-card"; 4985 simple-audio-card,name = "ROCKCHIP,SPDIF"; 4986 4987 simple-audio-card,cpu { 4988 sound-dai = <0x124>; 4989 }; 4990 4991 simple-audio-card,codec { 4992 sound-dai = <0x125>; 4993 }; 4994 }; 4995 4996 spdif-out { 4997 status = "okay"; 4998 compatible = "linux,spdif-dit"; 4999 #sound-dai-cells = <0x00>; 5000 phandle = <0x125>; 5001 }; 5002 5003 vad-sound { 5004 status = "disabled"; 5005 compatible = "rockchip,multicodecs-card"; 5006 rockchip,card-name = "rockchip,rk3568-vad"; 5007 rockchip,cpu = <0xcc>; 5008 rockchip,codec = <0x123 0x126>; 5009 }; 5010 5011 vcc3v3-sys { 5012 compatible = "regulator-fixed"; 5013 regulator-name = "vcc3v3_sys"; 5014 regulator-always-on; 5015 regulator-boot-on; 5016 regulator-min-microvolt = <0x325aa0>; 5017 regulator-max-microvolt = <0x325aa0>; 5018 vin-supply = <0x127>; 5019 phandle = <0x3e>; 5020 }; 5021 5022 vcc5v0-sys { 5023 compatible = "regulator-fixed"; 5024 regulator-name = "vcc5v0_sys"; 5025 regulator-always-on; 5026 regulator-boot-on; 5027 regulator-min-microvolt = <0x4c4b40>; 5028 regulator-max-microvolt = <0x4c4b40>; 5029 vin-supply = <0x127>; 5030 phandle = <0x36>; 5031 }; 5032 5033 vcc5v0-usb { 5034 compatible = "regulator-fixed"; 5035 regulator-name = "vcc5v0_usb"; 5036 regulator-always-on; 5037 regulator-boot-on; 5038 regulator-min-microvolt = <0x4c4b40>; 5039 regulator-max-microvolt = <0x4c4b40>; 5040 vin-supply = <0x127>; 5041 phandle = <0x128>; 5042 }; 5043 5044 vcc5v0-host-regulator { 5045 compatible = "regulator-fixed"; 5046 regulator-name = "vcc5v0_host"; 5047 regulator-boot-on; 5048 regulator-always-on; 5049 regulator-min-microvolt = <0x4c4b40>; 5050 regulator-max-microvolt = <0x4c4b40>; 5051 enable-active-high; 5052 gpio = <0x37 0x06 0x00>; 5053 vin-supply = <0x128>; 5054 pinctrl-names = "default"; 5055 pinctrl-0 = <0x129>; 5056 phandle = <0x10d>; 5057 }; 5058 5059 vcc5v0-otg-regulator { 5060 compatible = "regulator-fixed"; 5061 regulator-name = "vcc5v0_otg"; 5062 regulator-min-microvolt = <0x4c4b40>; 5063 regulator-max-microvolt = <0x4c4b40>; 5064 enable-active-high; 5065 gpio = <0x37 0x05 0x00>; 5066 vin-supply = <0x128>; 5067 pinctrl-names = "default"; 5068 pinctrl-0 = <0x12a>; 5069 phandle = <0x10e>; 5070 }; 5071 5072 vcc3v3-lcd0-n { 5073 compatible = "regulator-fixed"; 5074 regulator-name = "vcc3v3_lcd0_n"; 5075 regulator-boot-on; 5076 regulator-min-microvolt = <0x325aa0>; 5077 regulator-max-microvolt = <0x325aa0>; 5078 enable-active-high; 5079 gpio = <0x37 0x10 0x00>; 5080 vin-supply = <0x3e>; 5081 phandle = <0x96>; 5082 5083 regulator-state-mem { 5084 regulator-off-in-suspend; 5085 }; 5086 }; 5087 5088 vcc3v3-lcd1-n { 5089 compatible = "regulator-fixed"; 5090 regulator-name = "vcc3v3_lcd1_n"; 5091 regulator-boot-on; 5092 regulator-min-microvolt = <0x325aa0>; 5093 regulator-max-microvolt = <0x325aa0>; 5094 enable-active-high; 5095 gpio = <0x37 0x15 0x00>; 5096 vin-supply = <0x3e>; 5097 5098 regulator-state-mem { 5099 regulator-off-in-suspend; 5100 }; 5101 }; 5102 5103 sdio-pwrseq { 5104 compatible = "mmc-pwrseq-simple"; 5105 clocks = <0x12b 0x01>; 5106 clock-names = "ext_clock"; 5107 pinctrl-names = "default"; 5108 pinctrl-0 = <0x12c>; 5109 post-power-on-delay-ms = <0xc8>; 5110 reset-gpios = <0x7d 0x1d 0x01>; 5111 phandle = <0xa2>; 5112 }; 5113 5114 wireless-wlan { 5115 compatible = "wlan-platdata"; 5116 rockchip,grf = <0x33>; 5117 pinctrl-names = "default"; 5118 pinctrl-0 = <0x12d>; 5119 wifi_chip_type = "ap6256"; 5120 WIFI,host_wake_irq = <0x7d 0x1c 0x00>; 5121 status = "okay"; 5122 }; 5123 5124 wireless-bluetooth { 5125 compatible = "bluetooth-platdata"; 5126 clocks = <0x12b 0x01>; 5127 clock-names = "ext_clock"; 5128 uart_rts_gpios = <0xd9 0x0e 0x01>; 5129 pinctrl-names = "default\0rts_gpio"; 5130 pinctrl-0 = <0x12e 0x12f>; 5131 pinctrl-1 = <0x130>; 5132 BT,reset_gpio = <0xd9 0x05 0x00>; 5133 BT,wake_gpio = <0xd9 0x06 0x00>; 5134 BT,wake_host_irq = <0xd9 0x09 0x00>; 5135 status = "okay"; 5136 }; 5137 5138 test-power { 5139 status = "okay"; 5140 }; 5141 5142 rk-headset { 5143 compatible = "rockchip_headset"; 5144 headset_gpio = <0x7d 0x01 0x00>; 5145 pa_fault_sd_gpio = <0xd9 0x14 0x00>; 5146 pa_mute_gpip = <0x37 0x00 0x01>; 5147 pinctrl-names = "default"; 5148 pinctrl-0 = <0x131>; 5149 }; 5150 5151 vcc-camera-regulator { 5152 compatible = "regulator-fixed"; 5153 gpio = <0x37 0x11 0x00>; 5154 pinctrl-names = "default"; 5155 pinctrl-0 = <0xd7>; 5156 regulator-name = "vcc_camera"; 5157 enable-active-high; 5158 regulator-always-on; 5159 regulator-boot-on; 5160 phandle = <0xda>; 5161 }; 5162 5163 gpio-regulator { 5164 compatible = "regulator-fixed"; 5165 regulator-name = "vcc3v3_pcie"; 5166 regulator-min-microvolt = <0x325aa0>; 5167 regulator-max-microvolt = <0x325aa0>; 5168 enable-active-high; 5169 gpio = <0x37 0x12 0x00>; 5170 startup-delay-us = <0x1388>; 5171 vin-supply = <0x127>; 5172 phandle = <0xad>; 5173 }; 5174 5175 fiq-debugger { 5176 compatible = "rockchip,fiq-debugger"; 5177 rockchip,serial-id = <0x02>; 5178 rockchip,wake-irq = <0x00>; 5179 rockchip,irq-mode-enable = <0x01>; 5180 rockchip,baudrate = <0x16e360>; 5181 interrupts = <0x00 0xfc 0x08>; 5182 pinctrl-names = "default"; 5183 pinctrl-0 = <0xee>; 5184 status = "okay"; 5185 }; 5186 5187 debug@fd904000 { 5188 compatible = "rockchip,debug"; 5189 reg = <0x00 0xfd904000 0x00 0x1000 0x00 0xfd905000 0x00 0x1000 0x00 0xfd906000 0x00 0x1000 0x00 0xfd907000 0x00 0x1000>; 5190 }; 5191 5192 cspmu@fd90c000 { 5193 compatible = "rockchip,cspmu"; 5194 reg = <0x00 0xfd90c000 0x00 0x1000 0x00 0xfd90d000 0x00 0x1000 0x00 0xfd90e000 0x00 0x1000 0x00 0xfd90f000 0x00 0x1000>; 5195 }; 5196 5197 charge-animation { 5198 compatible = "rockchip,uboot-charge"; 5199 rockchip,uboot-charge-on = <0x01>; 5200 rockchip,android-charge-on = <0x00>; 5201 rockchip,uboot-low-power-voltage = <0xd16>; 5202 rockchip,screen-on-voltage = <0xd48>; 5203 rockchip,auto-wakeup-interval = <0x3c>; 5204 status = "okay"; 5205 }; 5206 5207 backlight { 5208 compatible = "pwm-backlight"; 5209 pwms = <0x132 0x00 0x61a8 0x00>; 5210 brightness-levels = <0x00 0x14 0x14 0x15 0x15 0x16 0x16 0x17 0x17 0x18 0x18 0x19 0x19 0x1a 0x1a 0x1b 0x1b 0x1c 0x1c 0x1d 0x1d 0x1e 0x1e 0x1f 0x1f 0x20 0x20 0x21 0x21 0x22 0x22 0x23 0x23 0x24 0x24 0x25 0x25 0x26 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>; 5211 default-brightness-level = <0xc8>; 5212 phandle = <0x95>; 5213 }; 5214}; 5215
